Switching control circuit and power supply circuit

Abstract

To provide a switching control circuit reduced in a switching loss of a power supply circuit, and the power supply circuit.SOLUTION: Provided is a switching control circuit having an inductor applied with a rectification voltage corresponding to an AC voltage and a transistor for controlling an inductance current flowing in the inductor, and switching the transistor of a power supply circuit generating an output voltage of a target level from the AC voltage. The switching control circuit has: a signal outputting circuit which outputs a signal to turn on the transistor when the inductor current becomes a first prescribed value after the transistor is turned off, after a first period corresponding to a conduction period of conduction of a parasitic diode of the transistor has passed; and a driving circuit which turns on the transistor on the basis of the signal, and turns off the transistor on the basis of a return voltage corresponding to the output voltage.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present invention relates to a switching control circuit and a power supply circuit. [Background technology]

[0002] As a power supply circuit, a power factor correction circuit (hereinafter referred to as a PFC (Power Factor Correction) circuit as appropriate) is known, which turns on a transistor after a predetermined period according to the resonance period after the inductor current becomes zero (see, for example, Patent Documents 1 to 3). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-70192 [Patent Document 2] International Publication No. 2018 / 123115 [Patent Document 3] JP 2017-77171 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, when the input voltage to the power supply circuit is low, the parasitic diode of the transistor may become conductive after the inductor current becomes 0. In this case, a switching control circuit that turns on the transistor based on the resonance period may not be able to reduce switching loss appropriately.

[0005] The present invention has been made in view of the above-mentioned problems in the prior art, and an object of the present invention is to provide a switching control circuit and a power supply circuit that can reduce the switching loss of the power supply circuit. [Means for solving the problem]

[0006] In order to solve the above problem, a first aspect of the present invention provides a switching control circuit for switching on the transistor of a power supply circuit that generates an output voltage of a target level from the AC voltage, the switching control circuit comprising: an inductor to which a rectified voltage corresponding to an AC voltage is applied; and a transistor that controls an inductor current flowing through the inductor. The switching control circuit comprises: a signal output circuit that outputs a signal to turn on the transistor after a first period corresponding to a conduction period during which a parasitic diode of the transistor is conductive has elapsed when the inductor current reaches a first predetermined value after the transistor is turned off; and a drive circuit that turns on the transistor based on the signal and turns off the transistor based on a feedback voltage corresponding to the output voltage.

[0007] A second aspect of the present invention provides a power supply circuit that generates an output voltage of a target level from an AC voltage. The power supply circuit includes an inductor to which a rectified voltage corresponding to the AC voltage is applied, a transistor that controls an inductor current flowing through the inductor, and a switching control circuit that switches on and off the transistor. The switching control circuit includes a signal output circuit that outputs a signal to turn on the transistor after a first period corresponding to a conduction period during which a parasitic diode of the transistor is conductive has elapsed when the inductor current reaches a first predetermined value after the transistor is turned off, and a drive circuit that turns on the transistor based on the signal and turns off the transistor based on a feedback voltage corresponding to the output voltage. [Effects of the Invention]

[0008] It is possible to provide a switching control circuit and a power supply circuit that can reduce the switching loss of the power supply circuit.

[0009] The above summary of the invention does not list all of the necessary features of the present invention, and subcombinations of these features may also constitute inventions. [Brief explanation of the drawings]

[0010] [Figure 1] An example of a circuit diagram of a general AC-DC converter 10a is shown. [Figure 2] An example of a resonant current flowing through the AC-DC converter 10a via the inductor 21 and the parasitic capacitor 38 is shown. [Figure 3] 1 shows an example of main current and voltage waveforms of the AC-DC converter 10a when the rectified voltage Vr is higher than (1 / 2) times the output voltage Vout. [Figure 4] An example of a current flowing through a parasitic diode in the AC-DC converter 10a is shown. [Figure 5] 1 shows an example of waveforms of main currents and voltages of the AC-DC converter 10a when the rectified voltage Vr is lower than half the output voltage Vout. [Figure 6] 1 shows an example of a circuit diagram of an AC-DC converter 10b according to an embodiment. [Figure 7] An example of the configuration of the power factor correction IC 35a is shown. [Figure 8] An example of the processing performed by the calculation circuit 62a will be shown below. [Figure 9] 10 is an example of an operation flow of the power factor correction IC 35a. [Figure 10] 10 shows an example of main current and voltage waveforms of the AC-DC converter 10b when the rectified voltage Vr is higher than 1 / 2 times the output voltage Vout. [Figure 11] 10 shows an example of main current and voltage waveforms of the AC-DC converter 10b when the rectified voltage Vr is lower than 1 / 2 times the output voltage Vout. [Figure 12] An example of the configuration of the power factor correction IC 35b is shown. [Figure 13] An example of the processing performed by the calculation circuit 62b and the second control circuit 70 will be shown. [Figure 14] 10 is an example of an operation flow of the power factor correction IC 35b. [Figure 15] 1 shows an example of a circuit diagram of an AC-DC converter 10c according to an embodiment. [Figure 16] An example of the configuration of the power factor correction IC 35c is shown below. [Figure 17]An example of the process performed by the calculation circuit 62c is shown. [Figure 18] An example of the operation flow of the power factor improvement IC 35c is shown. [Figure 19] An example of the configuration of the power factor improvement IC 35d is shown. [Figure 20] An example of the processes performed by the calculation circuit 62d and the second control circuit 70 is shown. [Figure 21] An example of the operation flow of the power factor improvement IC 35d is shown.

Mode for Carrying Out the Invention

[0011] Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the claims. Also, not all combinations of features described in the embodiments are essential for the solution means of the invention.

[0012] In this specification, the term "connection" is used, but unless otherwise specified, "connection" means "electrically connected". In this specification, for a voltage or a signal, when the logic level is at a low level, it is referred to as the L level, and when the logic level is at a high level, it is referred to as the H level.

[0013] FIG. 1 shows an example of a circuit diagram of a general AC-DC converter 10a. The AC-DC converter 10a is a boost-type PFC circuit that generates an output voltage Vout at a target level from the AC voltage Vac of a commercial power supply. The output voltage Vout generated by the AC-DC converter 10a is used to drive the load 11

[0014] The load 11 is, for example, a DC-DC converter or an electronic device that operates with a DC voltage.

[0015] <<Configuration of the AC-DC Converter 10a>> The AC-DC converter 10a includes a full-wave rectifier circuit 30, capacitors 31 and 32, an inductor 33, a diode 34, a power factor correction IC 100, an NMOS transistor 36, and resistors 40 to 42. The NMOS transistor 36 of this embodiment also includes a body diode 37 and a parasitic capacitor 38 as parasitic elements.

[0016] ===Input to full-wave rectifier circuit 30=== The AC power supply 20 is a commercial AC power supply for supplying an AC voltage Vac to the full-wave rectifier circuit 30. The AC voltage Vac is, for example, a voltage of 100 to 277 V and a frequency of 50 to 60 Hz.

[0017] ===Configuration from full-wave rectifier circuit 30 to load 11=== The full-wave rectifier circuit 30 full-wave rectifies a predetermined input AC voltage Vac and outputs the rectified voltage Vr to the capacitor 31 and the inductor 33. The inductor 33 receives the rectified voltage Vr according to the AC voltage Vac.

[0018] The capacitor 31 smoothes the rectified voltage Vr supplied from the full-wave rectifier circuit 30 .

[0019] The capacitor 32, together with the inductor 33, the diode 34, and the NMOS transistor 36, constitutes a boost chopper circuit. As a result, the charging voltage of the capacitor 32 is boosted to a DC output voltage Vout and supplied to the load 11.

[0020] The power factor correction IC (Integrated Circuit; IC) 100 is an integrated circuit that controls the switching of the NMOS transistor 36 so that the level of the output voltage Vout becomes a target level (for example, 400 V) while correcting the power factor of the AC-DC converter 10a.

[0021] The power factor correction IC 100 has terminals FB, CS, and OUT. The power factor correction IC 100 is also provided with terminals other than the three terminals FB, CS, and OUT described above, but these are omitted here for convenience.

[0022] In this embodiment, the NMOS transistor 36 is used as a switching element (so-called power transistor) used for power conversion, but this is not limiting. For example, other transistors such as a P-type transistor or a bipolar transistor may also be used as the switching element.

[0023] The gate electrode of the NMOS transistor 36 is connected to the terminal OUT, and the terminal OUT is applied with the voltage Vdr from the power factor correction IC 100. As described above, the NMOS transistor 36 has the body diode 37 and the parasitic capacitor 38 as parasitic elements.

[0024] The body diode 37 is a diode formed by the pn junction between the drain and source of the NMOS transistor 36, and is a parasitic diode.

[0025] The parasitic capacitor 38 is a parasitic capacitance between the drain and source of the NMOS transistor 36. In the AC-DC converter 10a, when the NMOS transistor 36 is turned off, a parasitic capacitance exists in the circuit that causes resonance together with the inductance L of the inductor 33. The parasitic capacitor 38 is an example of a main parasitic capacitance that causes resonance together with the inductance L of the inductor 33.

[0026] However, the diode and capacitor connected to the NMOS transistor 36 are not limited to parasitic elements. Specifically, instead of the body diode 37, a diode whose anode and cathode are connected in anti-parallel to the drain and source of the NMOS transistor 36 may be used. Similarly, instead of the parasitic capacitor 38, a capacitor may be connected in parallel to the NMOS transistor 36.

[0027] In this case, the diode connected to the NMOS transistor 36 may be a diode that is turned on for the same period as the period Ta (described later) when the conduction phenomenon of the body diode 37 occurs.

[0028] Resistors 40 and 41 form a voltage dividing circuit that divides the output voltage Vout to generate the voltage Vfb. The voltage dividing circuit formed by resistors 40 and 41 applies the voltage Vfb as a feedback voltage to terminal FB of the power factor correction IC 100.

[0029] Resistor 42 is a resistor for detecting the inductor current IL1. A voltage Vcs corresponding to the inductor current IL1 occurs across resistor 42. One end of resistor 42 is connected to terminal CS of the power factor correction IC 100.

[0030] The power factor correction IC 100 is a general integrated circuit that controls the AC-DC converter 10a. After the inductor current IL becomes 0 based on the voltage Vcs, the power factor correction IC 100 turns on the NMOS transistor 36 when a predetermined period has elapsed. At this time, the on-period of the NMOS transistor 36 is determined based on the voltage Vfb applied to terminal FB.

[0031] <<Current when the NMOS transistor 36 turns off>> ==When the rectified voltage Vr is higher than (1 / 2) times the output voltage Vout== By the way, when the rectified voltage Vr is higher than (1 / 2) times the output voltage Vout, when the NMOS transistor 36 turns off, as shown in FIGS. 2 and 3, a resonance current corresponding to the inductor 33 and the parasitic capacitor 38 flows. [[ID=二十]]

[0032] FIG. 2 shows an example of the resonance current flowing through the AC-DC converter 10a via the inductor 21 and the parasitic capacitor 38.

[0033] ]>Details will be described in FIG. 3. Due to the influence of the resonance phenomenon, the drain-source voltage Vds of the NMOS transistor 36 vibrates sinusoidally with the voltage Vout as the maximum value. The amplitude of the vibration of the voltage Vds is determined as Vout - Vr based on the output voltage Vout and the rectified voltage Vr.

[0034] FIG. 3 shows an example of main current and voltage waveforms of AC-DC converter 10a when the resonant current of FIG. 2 flows (when rectified voltage Vr is higher than 1 / 2 times output voltage Vout).

[0035] At time t1, the power factor correction IC 100 applies an H-level voltage Vdr to the gate electrode of the NMOS transistor 36. Accordingly, the inductor current IL begins to increase.

[0036] In the figure, "positive inductor current IL1" refers to a current flowing from one end of inductor 33, where full-wave rectifier circuit 30 and inductor 33 are connected, to the other end of inductor 33, where inductor 33 and NMOS transistor 36 are connected. Also, "negative inductor current IL1" refers to a current flowing from the other end of inductor 33 to one end of inductor 33.

[0037] At time t2, the power factor correction IC 100 changes the voltage Vdr to the L level. As the NMOS transistor 36 turns off, the inductor current IL decreases and the voltage Vds increases to the voltage Vout.

[0038] At time t3, the inductor current becomes almost zero (hereinafter, "almost zero" will be referred to simply as "0" where appropriate). When the inductor current becomes small, the effect of resonance occurs due to the inductance L of the inductor 33 and the capacitance C connected in series to the inductor 33.

[0039] It should be noted that the "capacitance C" herein includes not only the capacitance of the parasitic capacitor 38 but also the capacitance of the wiring connected in series to the inductor 33, but for the sake of convenience, the following description will be made assuming that it is the capacitance of the parasitic capacitor 38.

[0040] Between time t3 and time t4, the inductor current IL reaches a minimum value and then returns to zero at time t4. Furthermore, due to resonance, the voltage Vds also oscillates with an amplitude twice that of Vout-Vr. Time t4 marks the time when a half cycle of resonance has elapsed since time t3.

[0041] At time t5, one resonance cycle has elapsed since time t4. Between time t4 and time t5, voltage Vds reaches a maximum value, and then reaches a minimum value (bottom) again at time t5. After this, the same operation as that from time t1 onwards is repeated.

[0042] In this way, when the rectified voltage Vr is higher than half the output voltage Vout, the voltage Vds of the NMOS transistor 36 fluctuates within a range of positive values. In this range, the body diode 37 of the NMOS transistor 36 does not turn on.

[0043] Resonant operation as shown in the figure occurs between the inductor 33 and the parasitic capacitor 38. In this case, if the inductance of the inductor 33 is L and the capacitance of the parasitic capacitor 38 is C, the resonance period is Tc=π×√(LC).

[0044] ==When the rectified voltage Vr is lower than (1 / 2) times the output voltage Vout== When the rectified voltage Vr is lower than half the output voltage Vout, when the NMOS transistor 36 is turned off, a resonant current flows and then the body diode 37 becomes conductive, as shown in FIGS.

[0045] 4 shows an example of the current flowing through the AC-DC converter 10a via a parasitic diode. When the rectified voltage Vr becomes lower than half the output voltage Vout, the voltage Vds of the NMOS transistor 36 becomes 0 or less due to the resonance phenomenon shown in FIG. 5, which will be described later.

[0046] 5 shows an example of the main current and voltage waveforms of the AC-DC converter 10a when the rectified voltage Vr is lower than half the output voltage Vout. The diagram shows the case where the rectified voltage Vr is lower than half the output voltage Vout.

[0047] Here, the operation of the AC-DC converter 10a in FIG. 5 from when the NMOS transistor 36 is turned on until the inductor current IL becomes zero (from time t11 to time t13) is the same as the operation from time t1 to t3 in FIG. 4.

[0048] However, Fig. 5 shows an example in which the rectified current Vr is lower than half the output voltage Vout, and the maximum value of the inductor current IL is also smaller than in the case of Fig. 4. Therefore, the magnitude of the inductor current IL at time t12 is smaller than the magnitude of the inductor current IL at time t2 in Fig. 4.

[0049] The period from when the NMOS transistor 36 is turned off at time t12 to when the inductor current IL reaches 0 at time t13 is defined as a period Tcrs. Because the maximum value of the inductor current IL is small, the period Tcrs is shorter than the period from time t2 when the NMOS transistor 36 is turned off to time t3 when the inductor current IL reaches 0 in FIG. 3 .

[0050] When the inductor current becomes nearly zero (for example, a few mA), the influence of resonance caused by the inductance L of the inductor 33 and the parasitic capacitor 38 appears, and between time t13 and time t14, the inductor current IL decreases, and the voltage Vds also decreases.

[0051] At time t14, the inductor current IL reaches a negative peak value Inp. Also at time t14, the voltage Vds also falls below 0 and falls below the forward voltage of the body diode 37. As a result, the voltage Vds does not fall below the forward voltage of the body diode 37. Note that because the absolute value of the forward voltage of the body diode 37 is smaller than the voltage Vout, for convenience, the voltage Vds at time t14 in the figure is shown as 0. When the body diode 37 becomes conductive, the inductor current IL rises from its peak Inp.

[0052] 3, the inductor current IL resonates with the inductance L of the inductor 33 and the parasitic capacitor 38. The voltage Vds of the NMOS transistor 36 rises from the forward voltage of the body diode 37 and performs a resonant operation with an amplitude Vout-Vr.

[0053] At time t16, which is one resonance period Tc after time t15, the inductor current IL indicates zero, and the voltage Vds also indicates zero.

[0054] The operation after time t16 is the same as the operation after time t11. In this way, when the rectified voltage Vr is lower than 1 / 2 the output voltage Vout, the body diode 37 of the NMOS transistor 36 is turned on.

[0055] Therefore, in the AC-DC converter 10a, the current that flows after the NMOS transistor 36 is turned off differs depending on whether the rectified voltage Vr is higher or lower than half the output voltage Vout, as shown in FIGS. 3 and 5.

[0056] A typical power factor correction IC 100 turns on the NMOS transistor 36 after a predetermined period corresponding to the resonance period has elapsed since the inductor current IL became 0. Therefore, such a power factor correction IC 100 has a problem in that it cannot turn on the NMOS transistor 36 at the desired timing when the rectified voltage Vr is lower than half the output voltage Vout and the body diode 37 is turned on.

[0057] Therefore, in order to turn on the NMOS transistor 36 at an appropriate timing, it is necessary to determine whether a resonance phenomenon as shown in Figures 2 and 3 occurs after the NMOS transistor 36 turns off, or whether a phenomenon in which the body diode 37 turns on (hereinafter referred to as "conduction phenomenon") as shown in Figures 4 and 5 occurs. The principle of determining these phenomena will be described below.

[0058] ===Judgment principle===

[0059] (Judgment principle 1) As described above, whether the voltage Vr is smaller than (1 / 2) times the voltage Vout, i.e., Vr<(1 / 2)×Vout (1) Whether resonance or conduction occurs can be determined by whether the following conditions are satisfied. Note that such determination can be realized, for example, by providing a terminal for detecting a voltage based on the rectified voltage Vr in the power factor correction IC (described later) in addition to the terminal FB.

[0060] (Judgment principle 2) Furthermore, when the period during which the NMOS transistor 36 is turned on is Ton, the periods Tcrs and Ton and the voltages Vout and Vr in FIG. 5 are expressed as follows: Vr×Ton=(Vout-Vr)×Tcrs...(2) This formula can be transformed into Vr / Vout=Tcrs / (Ton+Tcrs)...(3) Therefore, when formula (2) is true, formula (1) becomes: Tcrs / (Ton+Tcrs)<1 / 2 (4) becomes equivalent to

[0061] Therefore, it is possible to determine whether a resonance phenomenon or a conduction phenomenon occurs based on the period shown in equation (4). The power factor correction IC that performs such a determination will be described in detail later.

[0062] The period Ton corresponds to the "on period", and the value 1 / 2 in the formula (4) corresponds to the "second predetermined value".

[0063] (Judgment principle 3) Next, a description will be given of the equation that is satisfied by the conduction period Ta of the body diode 37 from when the body diode 37 becomes conductive until the inductor current IL becomes 0. First, the negative peak Inp of the inductor current IL is expressed as follows: Inp=√(C / L)×(Vout-Vr) (5) Meet the following.

[0064] Therefore, the period Ta is Ta = (Inp × L) / Vr (6) By substituting Eq. (1), Ta = √(LC) × [(Vout-Vr) / Vr] =(Tc / 2π)×[(Vout-Vr) / Vr]···(7) This will satisfy the following.

[0065] Therefore, when equation (1) is satisfied, the period from when the inductor current IL becomes negative until it indicates 0 becomes longer than Tc / 2π. (1 / 4)Tc+Ta>[(π+2) / 4π]×Tc...(8) Therefore, by continuing to calculate the period Ta, it is possible to determine whether the resonance phenomenon or the conduction phenomenon occurs based on the equation (7). The power factor correction IC that performs such a determination will be described in detail later.

[0066] Here, we have explained Determination Principles 1 to 3, but if a conduction phenomenon occurs after the NMOS transistor 36 is turned off, it is preferable to turn on the NMOS transistor 36 at a timing that takes into account the period Ta. Below, we will explain the calculation principle of the period Ta.

[0067] (Calculation principle 1) The period Ta in equation (7) can be calculated by providing the power factor correction circuit with terminals to which voltages corresponding to the output voltage Vout, the rectified voltage Vr, and the resonance period Tc are applied.

[0068] (Calculation principle 2) Calculation principle 2 explains that the period Ta can be calculated from the period Ton and the period Tcrs, which is the period from when the NMOS transistor 36 is turned off until the inductor current IL becomes 0, without directly measuring the voltage Vr. Here, the periods Ton, Tcrs, the voltage Vout, and the voltage Vr satisfy equation (2).

[0069] The period Ta is calculated by substituting equation (2) into equation (7): Ta = (Tc / 2π) × (Tcrs / Ton) ··· (9) is shown to satisfy

[0070] == An Example of the AC-DC Converter 10b According to the Embodiment == << Configuration of the AC-DC Converter 10b >> FIG. 6 shows an example of a circuit diagram of the AC-DC converter 10b according to the embodiment. The AC-DC converter 10a is a power supply circuit capable of corresponding to both the resonance phenomenon and the conduction phenomenon, and includes a full-wave rectifier circuit 30, capacitors 31 and 32, an inductor 33, a diode 34, a power factor correction IC 35a, an NMOS transistor 36, and resistors 40 to 45.

[0071] Here, the configurations denoted by the same reference numerals as those in FIG. 1 correspond to the same configurations. The AC-DC converter 10b is different from the AC-DC converter 10a in that it includes resistors 43 to 45 and the power factor correction IC 35a.

[0072] The power factor correction IC 35a is an integrated circuit capable of corresponding to both the resonance phenomenon and the conduction phenomenon, and includes terminals RT and VR in addition to terminals CS, FB, and OUT.

[0073] One end of the resistor 43 is connected to the terminal RT. The other end of the resistor 43 is grounded. The voltage Vrt generated in the resistor 43 is applied to the terminal RT. In the present embodiment, the resistor 43 has a resistance value of a magnitude corresponding to the resonance period Tc.

[0074] One end of the resistor 44 is connected to the node between the capacitor 31 and the inductor 33, and the other end is connected to the resistor 45. Thereby, the resistors 44 and 45 constitute a voltage dividing circuit for dividing the rectified voltage Vr. The voltage Vrdiv obtained by dividing the rectified voltage Vr is applied to the terminal VR.

[0075] Therefore, the rectified voltage Vr and the voltage corresponding to the resonance period Tc can be detected by these terminals RT and VR. The power factor correction IC 35a can calculate the conduction period of the body diode 37 based on the determination principle 1 and the calculation principle 1 as follows.

[0076] The AC-DC converter 10b corresponds to a "power supply circuit." The power factor correction IC 35a corresponds to a "switching control circuit."

[0077] ==Configuration of Power Factor Correction IC35a== 7 shows an example of the configuration of a power factor correction IC 35a. The power factor correction IC 35a includes analog-to-digital converters (ADCs) 51, 53, 55, and 58, an on-period setting circuit 52, a first control circuit 54, a signal output circuit 56a, a current source 57, a frequency detection circuit 59, and a drive circuit 60. Note that although terminals are depicted in different positions in FIG. 7 than in FIG. 6, the wiring, elements, etc. connected to each terminal are the same as in FIG. 6.

[0078] The ADCs 51, 53, 55, and 58 convert the voltages Vfb, Vr, Vcs, and Vrt applied to the terminals FB, VR, CS, and RT into digital values, respectively. Note that, for convenience, the digital values ​​output from the ADCs 51, 53, 55, and 58 will be described below as voltages Vfb, Vr, Vcs, and Vrt.

[0079] The on-period setting circuit 52 is a circuit equivalent to a so-called error amplifier circuit, and outputs data regarding the on-period Ton based on the error between the voltage Vfb and the reference voltage Vref to the drive circuit 60. For convenience of illustration, data regarding the period Ton is shown as Ton in the drawing.

[0080] The first control circuit 54 determines whether the voltage Vr is greater than ½ times the voltage Vout based on the voltages Vrdiv and Vfb, and controls whether the calculation circuit 62a (described later) operates in the first mode or the second mode. Specifically, when Vr<½Vout, the first control circuit 54 determines that conduction of the body diode 37 occurs and transmits a signal Smd1 to cause the calculation circuit 62a to operate in the first mode. When Vr≧½Vout, the first control circuit 54 determines that resonance occurs and transmits a signal Smd1 to cause the calculation circuit 62a to operate in the second mode. Note that whether the calculation circuit 62a operates in the first mode or the second mode when Vr=½×Vout is satisfied may be determined according to the design.

[0081] When the inductor current IL becomes equal to or less than a predetermined current value I0 (for example, several mA) that is slightly larger than zero, the signal output circuit 56 outputs a signal Von that turns on the NMOS transistor 36 after a predetermined period Tdelay. A specific configuration of the signal output circuit 56a will be described later.

[0082] A current source 57 supplies a predetermined constant current through a terminal RT to a resistor 43. By setting the resistance value of the resistor 43 to a value determined by the resonance period Tc of the inductor 33 and the parasitic capacitor 38, a voltage Vrt having a magnitude according to the resonance period Tc is generated at the terminal RT.

[0083] The frequency detection circuit 59 detects the switching frequency Freq of the NMOS transistor 36 based on the timing of a change in the level of the voltage Vdr output by the drive circuit 60. The frequency detection circuit 59 outputs data on the switching frequency Freq.

[0084] The drive circuit 60 changes the level of the voltage Vdr applied to the gate electrode of the NMOS transistor 36 based on the signal Von output by the output circuit 63 and the period Ton. Specifically, the drive circuit 60 determines the timing for changing the voltage Vdr to the H level based on the signal Von output by the signal output circuit 56, and turns on the NMOS transistor 36 for the period Ton.

[0085] ===Details of signal output circuit 56a=== The signal output circuit 56a includes a zero current detection circuit 61a, a calculation circuit 62a, and an output circuit 63a. The zero current detection circuit 61a detects that the inductor current IL is substantially zero based on the voltage Vcs when the inductor current IL becomes equal to or less than a predetermined current value I0 (e.g., several mA) that is slightly larger than zero, and outputs a signal Vdet.

[0086] The calculation circuit 62a calculates the period Tdelay until the output circuit 63a outputs the signal Von that turns on the NMOS transistor 36, depending on the first mode or the second mode specified by the first control circuit 54.

[0087] The calculation circuit 62a calculates the period Tdelay at predetermined intervals that are sufficiently shorter than the periods at which the inductor current IL, the rectified voltage Vr, the output voltage Vout, etc. Here, the "predetermined intervals" at which the calculation circuit 62a performs the calculation are set so that the calculation circuit 62a performs the calculation at intervals that are approximately the same as the switching interval (a interval corresponding to a threshold value fth for the switching frequency, which will be described later; for example, every 1 / fth).

[0088] However, the calculation circuit 62a may perform the calculation every time the zero current detection circuit 61a detects that the inductor current IL has become almost zero. In this case, the zero current detection circuit 61a also outputs the signal Vdet to the calculation circuit 62a.

[0089] The frequency with which the calculation circuit 62a calculates the period Tdelay may be sufficiently shorter than the cycles at which the rectified voltage Vr or the output voltage Vout changes. That is, when the changes in the rectified voltage Vr and the output voltage Vout are small, the calculation frequency may be every cycle longer than the period 1 / fth.

[0090] The output circuit 63a outputs a signal Von that turns on the NMOS transistor 36 in response to the signal Vdet at a timing based on the period Tdelay.

[0091] The zero current detection circuit 61a corresponds to the "detection circuit."

[0092] ===Processing performed by calculation circuit 62a=== 8 shows an example of the process performed by the calculation circuit 62a. Based on the signal Smd1 from the first control circuit 54, the mode in which the calculation circuit 62a operates is selected.

[0093] In the first mode, when the switching frequency Freq is equal to or lower than a predetermined threshold value fth (for example, 200 kHz), the calculation circuit 62a calculates the period Tdelay as period T1=(1 / 4)×Tc+(Tc / 2π)×[(Vout−Vr) / Vr]···(10).

[0094] On the other hand, when the switching frequency Freq is greater than the predetermined threshold value fth, the calculation circuit 62a sets the calculation result as T1+nTc (n is a natural number) as the period Tdelay.

[0095] As the switching frequency Freq increases, power loss due to switching increases. To reduce the switching loss, the period Tdelay is lengthened to reduce the switching frequency. The magnitude of the natural number n is set in advance so that the frequency Freq becomes equal to a predetermined threshold value fth. This allows the switching frequency Freq to be maintained at or below the predetermined threshold value fth.

[0096] Furthermore, in the second mode, when the switching frequency Freq is equal to or lower than a predetermined threshold value fth, the calculation circuit 62a calculates the period Tdelay as period T2=(1 / 2)×Tc (11).

[0097] Furthermore, when the switching frequency Freq exceeds a predetermined threshold value fth, the calculation circuit 62a sets the calculation result as T2+nTc (n is a natural number) as the period Tdelay. The magnitude of the natural number n is set in advance so that the frequency Freq becomes equal to the predetermined threshold value fth whether Tdelay is T1+nTc or T2+nTc. This lengthens the period Tdelay, making it possible to maintain the switching frequency Freq at or below the predetermined threshold value fth.

[0098] The threshold value fth corresponds to the "third predetermined value."

[0099] ===Power Factor Correction IC35a Operation Flow=== Fig. 9 shows an example of the operation flow of the power factor correction IC 35a. Fig. 10 shows an example of the main current and voltage waveforms of the AC-DC converter 10b when the rectified voltage Vr is higher than half the output voltage Vout. Fig. 11 shows an example of the main current and voltage waveforms of the AC-DC converter 10b when the rectified voltage Vr is lower than half the output voltage Vout.

[0100] First, the drive circuit 60 turns on the NMOS transistor 36, and then turns off the NMOS transistor 36 after each on-period Ton has elapsed based on the feedback voltage Vfb corresponding to the voltage Vout (times t11 to t12 in FIG. 10 (corresponding to the times indicated by the same symbols in FIG. 4, and the same applies below) and times t1 to t2 in FIG. 11 (corresponding to the times indicated by the same symbols in FIG. 5, and the same applies below)).

[0101] 10, when the NMOS transistor 36 is turned off, the inductor current IL decreases to almost zero and then decreases to a minimum value due to the resonance phenomenon (time t14). After that, the inductor current IL returns to 0 due to the resonance phenomenon or the conduction phenomenon in which the body diode 37 is turned on (time t15).

[0102] 11, when the NMOS transistor 36 is turned off, the inductor current IL decreases to almost zero (time t3). Thereafter, due to the resonance phenomenon, the inductor current IL flows as a negative current, and then increases to almost zero again (time t4). Hereinafter, which phenomenon occurs and at what timing the NMOS transistor 36 is turned on will be described according to the flow in FIG.

[0103] The frequency detection circuit 59 detects the switching frequency Freq based on the drive circuit Vdrv (S1), and outputs frequency data Freq based on the detection result to the calculation circuit 62a.

[0104] Next, the first control circuit 54 determines whether the voltage Vr is greater than 1 / 2 times the voltage Vout (S2). The first control circuit 54 outputs a signal Smd1 that controls the operation mode of the calculation circuit 62a according to the determination result.

[0105] If Vr<(1 / 2)×Vout (1) (S2: NO), as described above, the conduction phenomenon occurs in the case shown in Fig. 10. Therefore, the calculation circuit 62a calculates the period T1=(1 / 4)×Tc+(Tc / 2π)×[(Vout-Vr) / Vr] (10) in the first mode (S3).

[0106] After the inductor current reaches a minimum value, the body diode 37 becomes conductive (time t14) and the inductor current returns to zero (time t15). At time t15, the voltage Vds also reaches a minimum. The calculation circuit 62a can calculate the period T1 by adding the conduction period Ta of the body diode 37 (the period from time t14 to time t15 in FIG. 10) to (1 / 4)×Tc (the period from time t13 to time t14 in FIG. 10).

[0107] Furthermore, the calculation circuit 62a determines whether the switching frequency Freq is equal to or lower than a threshold value fth based on the frequency data Freq (S4).

[0108] If Freq≦fth is satisfied (S4: Yes), the calculation circuit 62a outputs the period Tdelay=T1 as the calculation result (S5), and if Freq>fth is satisfied (S4: No), the calculation circuit 62a outputs the period Tdelay=Tx=T1+nTc as the calculation result (S6) (Tx>T1). In the example of Fig. 10, in S6, the calculation circuit 62a calculates the period (the period from time t13 to t16) based on the period Tdelay=T1+Tc when n=1.

[0109] On the other hand, if Vr≧(½)×Vout (S2: Yes), as described above, a resonance phenomenon occurs as shown in Fig. 11. Therefore, the calculation circuit 62a calculates the period T2=(½)×Tc (11) (the period from time t3 to time t4 in Fig. 11) in the second mode (S7).

[0110] Furthermore, the calculation circuit 62a determines whether the switching frequency Freq is equal to or lower than a threshold value fth based on the frequency data Freq (S8).

[0111] If Freq≦fth is satisfied (S8: Yes), the calculation circuit 62a outputs the period Tdelay=T2 as the calculation result (S9), and if Freq>fth is satisfied (S8: No), the calculation circuit 62a outputs the period Tdelay=Ty=T2+nTc as the calculation result (S10) (Ty>T2). In the example of Fig. 11, in S10, the calculation circuit 62a calculates the period based on the period Tdelay=T2+Tc when n=1 (the period from time t3 to t5 in Fig. 11).

[0112] When it is detected that the inductor current IL has become 0, the output circuit 63a outputs the signal Von after a period Tdelay corresponding to the calculation result of the calculation circuit 62a has elapsed (S11). The output circuit 63a outputs the signal Von that turns on the NMOS transistor 36 at time t16 in the example of Fig. 10 and at time t5 in the example of Fig. 11.

[0113] As a result, when both the resonance phenomenon and the conduction phenomenon occur, the power factor correction IC 35a can drive the NMOS transistor 36 at the timing when the voltage Vdr becomes minimum, thereby reducing the switching loss in the AC-DC converter 10b.

[0114] The period T1 corresponds to a “first period,” and the period T2 corresponds to a “second period.” Furthermore, the inductor current IL, which is approximately zero (several mA), corresponds to a “first predetermined value.”

[0115] ===Configuration of power factor correction IC35b=== 12 shows an example of the configuration of a power factor correction IC 35b. The power factor correction IC 35b includes analog-to-digital converters (ADCs) 51, 53, 55, and 58, an on-period setting circuit 52, a signal output circuit 56b, a current source 57, a frequency detection circuit 59, a drive circuit 60, and a second control circuit 70. Components denoted by the same reference numerals as those in FIG. 7 correspond to the same components. The power factor correction IC 35b is configured to replace the power factor correction IC 35a in the AC-DC converter 10b of FIG. 6.

[0116] The following mainly describes the differences between the power factor correction IC 35b and the power factor correction IC 35a. The power factor correction IC 35b differs from the power factor correction IC 35a in that it does not include the first control circuit 54, but includes a signal output circuit 56b and a second control circuit 70.

[0117] The power factor correction IC35b is (1 / 4)Tc+Ta>[(π+2) / 4π]×Tc...(8) The power factor correction IC 35b determines whether a resonance phenomenon or a conduction phenomenon is occurring based on the determination principle 3. Then, based on the determination result, the power factor correction IC 35b controls whether the voltage Vdr to be applied to the gate electrode of the NMOS transistor 36 is changed at a timing corresponding to the period T1 or at a timing corresponding to the period T2.

[0118] The signal output circuit 56b is (Tc / 2π)×[(Vout-Vr) / Vr]···(7) Based on the calculation principle 1, when the inductor current IL becomes 0 after the NMOS transistor 36 is turned off, the signal output circuit 56b outputs the signal Von at a timing according to the period T1 or T2. The signal output circuit 56b includes a zero current detection circuit 61b, a calculation circuit 62b, and an output circuit 63b.

[0119] Similar to the zero current detection circuit 61a, the zero current detection circuit 61b outputs a signal Vdet when it detects that the inductor current IL has become substantially zero based on the voltage Vcs.

[0120] The second control circuit 70 is (1 / 4)Tc+Ta>[(π+2) / 4π]×Tc...(8) 13 and 14, the specific processing of the calculation circuit 62b will be described, and the relationship between the second control circuit 70 and the calculation circuit 62b will also be described.

[0121] ===Processing Performed by Calculation Circuit 62b and Second Control Circuit 70=== FIG. 13 shows an example of the processing performed by the calculation circuit 62b and the second control circuit .

[0122] The calculation circuit 62b continues to calculate the period T1=(1 / 4)×Ta+(Tc / 2π)×[(Vout-Vr) / Vr] (10), T2=(1 / 2)×Tc (11). Specifically, the calculation circuit 62b can calculate the period T1 based on data on the voltages Vrt, Vfb, and Vrdiv, and the frequency Freq. Furthermore, the calculation circuit 62b outputs the calculation result T1 to the output circuit 63b when the switching frequency Freq is equal to or less than a threshold fth (Freq≦fth), and outputs the calculation result T1+nTc when Freq>fth.

[0123] The calculation circuit 62b can calculate the period T2 based on data on the voltages Vrt, Vfb, and Vrdiv and the frequency Freq. If Freq≦fth, the calculation circuit 62b outputs the calculation result T2 to the output circuit 63b, and if Freq>fth, the calculation circuit 62b outputs the calculation result T2+nTc to the output circuit 63b.

[0124] The second control circuit 70 determines whether the condition of equation (8): (1 / 4)Tc+Ta>[(π+2) / 4π]×Tc of determination principle 3 is satisfied based on the calculation result of the calculation circuit 62b. As a result, the second control circuit 70 outputs a signal Smd2 that controls whether the timing at which the output circuit 63b turns on the NMOS transistor 36 is based on the period T1 or the period T2. Note that in this embodiment, the determination is based on the periods T1 and T2, but the period T1+nTc and the period T2+nTc may also be used for the determination.

[0125] When the periods T1 and T2 satisfy the condition of formula (8), the output circuit 63b outputs the signal Von based on the period T1 (first mode), and when the condition of formula (8) is not satisfied, the output circuit 63b outputs the signal Von based on the period T2 (second mode). In particular, when Freq≦fth is satisfied, the output circuit 63 outputs a signal at a timing based on the period T1 or T2, and when Freq>fth, the output circuit 63 outputs a signal at a timing based on the period T1+nTc or T2+nTc.

[0126] ===Power Factor Correction IC35b Operation Flow=== FIG. 14 shows an example of the operation flow of the power factor correction IC 35b.

[0127] First, the frequency detection circuit 59 detects the switching frequency Freq based on the drive circuit Vdrv (S21). The frequency detection circuit 59 outputs data of the frequency Freq based on the detection result to the calculation circuit 62b.

[0128] Next, the calculation circuit 62b calculates the period T1=(1 / 4)×Tc+(Tc / 2π)×[(Vout−Vr) / Vr]···(10) and the period T2=(1 / 2)×Tc···(11) (S22).

[0129] Next, the second control circuit 70 determines whether the periods T1 and T2 satisfy a predetermined condition (equation (8): (1 / 4)Tc+Ta>[(π+2) / 4π]×Tc) (S23). Depending on the determination result, the second control circuit 70 outputs a signal Smd2 that controls the timing at which the output circuit 63b outputs a signal that turns on the NMOS transistor 36.

[0130] Here, the calculation circuit 62b changes the calculation result to be sent to the output circuit 63 depending on whether Freq≦fth is satisfied. If the periods T1 and T2 satisfy the predetermined condition (S23: Yes), the calculation circuit 62b determines whether Freq≦fth is satisfied (S24).

[0131] If Freq≦fth (S24: Yes), the calculation result from the calculation circuit 62b is the period T1. The output circuit 63b outputs the signal Von based on the signal Smd2 and the calculation result from the calculation circuit 62b (S25).

[0132] On the other hand, if Freq>fth (S24: No), the calculation result from the calculation circuit 62b is period Tx=T1+nTc. The output circuit 63b outputs the signal Von based on the signal Smd2 and the calculation result from the calculation circuit 62b (S26).

[0133] If the periods T1 and T2 do not satisfy the predetermined condition (S23: Yes), the calculation circuit 62b determines whether Freq≦fth is satisfied (S27).

[0134] If Freq≦fth (S27: Yes), the calculation result from the calculation circuit 62b is the period T2. The output circuit 63b outputs the signal Von based on the signal Smd2 and the calculation result from the calculation circuit 62b (S28).

[0135] On the other hand, if Freq>fth (S24: No), the calculation result from the calculation circuit 62b is the period Ty=T2+nTc. The output circuit 63b outputs the signal Von based on the signal Smd2 and the calculation result from the calculation circuit 62b (S29).

[0136] As a result, the power factor correction IC 35b can also drive the NMOS transistor 36 at the timing when the voltage Vdr is at a minimum regardless of whether the resonance phenomenon or the conduction phenomenon occurs, thereby reducing the switching loss in the AC-DC converter 10b.

[0137] ==Configuration of AC-DC Converter 10c== Fig. 15 shows an example of a circuit diagram of an AC-DC converter 10c according to an embodiment. The AC-DC converter 10c includes a power factor correction IC 35c having terminals different from those of the power factor correction IC 35a of the AC-DC converter 10b shown in Fig. 6. Components denoted by the same reference numerals as those in Figs. 1 and 6 correspond to the same components.

[0138] The power factor correction IC 35c of this embodiment does not include a terminal VR to which a voltage obtained by dividing the rectified voltage Vr is applied.

[0139] The power factor correction IC35c is Tcrs / (Ton+Tcrs)<1 / 2 (4) Based on the determination principle 2, it is determined whether a resonance phenomenon or a conduction phenomenon is occurring. If a conduction phenomenon is occurring, the power factor correction IC 35c: Ta=(Tc / 2π)×(Tcrs / Ton)···(9) The conduction period is calculated based on calculation principle 2. Then, the power factor correction IC 35c controls the timing to turn on the NMOS transistor 36. This allows the power factor correction IC 35c to deal with the conduction phenomenon. The configuration of the power factor correction IC 35c will be described below.

[0140] ===Configuration of Power Factor Correction IC35c=== Fig. 16 shows an example of the configuration of a power factor correction IC 35c. The power factor correction IC 35b includes ADCs 51, 53, 55, and 58 (Analog-to-Digital Converters), an on-period setting circuit 52, a Tcrs detection circuit 81, a signal output circuit 56c, a current source 57, a frequency detection circuit 59, a drive circuit 60, and a first control circuit 82. Here, components denoted with the same reference numerals as those in Fig. 7 correspond to the same components.

[0141] The following mainly describes the differences between the power factor correction IC 35c and the power factor correction ICs 35a and 35b.

[0142] The Tcrs detection circuit 81 detects the period from when the NMOS transistor 36 is turned off until the inductor current IL becomes almost zero (for example, several mA). Specifically, the Tcrs detection circuit 81 detects the timing when the NMOS transistor 36 is turned off using the voltage Vdr, and detects the timing when the inductor current IL becomes almost zero using a signal Vdet output from a zero current detection circuit 61c (described later). The Tcrs detection circuit 81 detects the period Tcrs using the difference between these timings.

[0143] The first control circuit 82 determines, based on the periods Ton and Tcrs, Tcrs / (Ton+Tcrs)<1 / 2 (4) Based on the determination principle 2 that determines whether the resonance phenomenon or the conduction phenomenon occurs, the signal Smd1 according to the determination result is output.

[0144] When the inductor current IL becomes substantially zero, the signal output circuit 56c outputs, after a period Tdelay, a signal Von that turns on the NMOS transistor 36. The signal output circuit 56c includes a zero current detection circuit 61c, a calculation circuit 62c, and an output circuit 63c.

[0145] Similar to the zero current detection circuits 61a and 61b, the zero current detection circuit 61c outputs a signal Vdet when it detects that the inductor current IL has become substantially zero based on the voltage Vcs.

[0146] Calculation circuit 62c is described below with reference to FIG.

[0147] ===Processing performed by calculation circuit 62c=== 17 shows an example of the process performed by the calculation circuit 62c. Based on the signal Smd1 from the first control circuit 82, the mode in which the calculation circuit 62c operates is selected.

[0148] Similarly to the calculation circuit 62a, the calculation frequency of the calculation circuit 62c may be at a predetermined cycle that is sufficiently shorter than the cycles at which the inductor current IL, the rectified voltage Vr, the output voltage Vout, etc. Alternatively, the calculation circuit 62c may perform the calculation every time the zero current detection circuit 61c detects that the inductor current IL has become substantially zero.

[0149] In the first mode, when the switching frequency Freq is equal to or lower than a predetermined threshold value fth (for example, 200 kHz), the calculation circuit 62c calculates the period Tdelay as period T1=(1 / 4)×Tc+(Tc / 2π)×(Tcrs / Ton)···(12).

[0150] On the other hand, when the switching frequency Freq is greater than the predetermined threshold value fth, the calculation circuit 62c sets the calculation result as T1+nTc (n is a natural number) as the period Tdelay.

[0151] As the switching frequency Freq increases, power loss due to switching increases. To reduce the switching loss, the period Tdelay is lengthened to reduce the switching frequency. The magnitude of the natural number n is set in advance so that the frequency Freq becomes equal to a predetermined threshold value fth. This allows the switching frequency Freq to be maintained at or below the predetermined threshold value fth.

[0152] Furthermore, in the second mode, when the switching frequency Freq is equal to or lower than a predetermined threshold value fth, the calculation circuit 62c calculates the period Tdelay as period T2=(1 / 2)×Tc (11).

[0153] Furthermore, when the switching frequency Freq exceeds a predetermined threshold value fth, the calculation circuit 62c sets the calculation result as T2+nTc (n is a natural number) as the period Tdelay. The magnitude of the natural number n is set in advance so that the frequency Freq becomes equal to the predetermined threshold value fth whether Tdelay is T1+nTc or T2+nTc. This lengthens the period Tdelay, making it possible to maintain the switching frequency Freq at or below the predetermined threshold value fth.

[0154] In response to the signal Vdet indicating that the inductor current IL has become substantially zero, the output circuit 63c in FIG. 16 outputs a signal Von that turns on the NMOS transistor 36 at a timing based on the period Tdelay calculated by the calculation circuit 62c.

[0155] ===Power Factor Correction IC35c Operation Flow=== 18 shows an example of the operation flow of the power factor correction IC 35c. Note that the relationship between each step of the operation flow in FIG. 18 and the timing of the waveforms in FIGS. 10 and 11 is the same as in FIG.

[0156] The frequency detection circuit 59 detects the switching frequency Freq based on the drive circuit Vdrv (S31), and outputs frequency data Freq based on the detection result to the calculation circuit 62c.

[0157] Next, the first control circuit 54 determines whether the voltage Vr is greater than 1 / 2 times the voltage Vout (S32). The first control circuit 54 outputs a signal Smd1 that controls the operation mode of the calculation circuit 62c according to the determination result.

[0158] If Tcrs / (Ton+Tcrs)<1 / 2 (4) (S32: NO), conduction occurs in the body diode 37. Therefore, the calculation circuit 62c calculates the period T1=(1 / 4)×Tc+(Tc / 2π)×(Tcrs / Ton) (12) in the first mode (S33).

[0159] Furthermore, the calculation circuit 62c determines whether the switching frequency Freq is equal to or lower than a threshold value fth based on the frequency data Freq (S34).

[0160] If Freq≦fth is satisfied (S34: Yes), the calculation circuit 62c outputs the period Tdelay=T1 as the calculation result (S35), and if Freq>fth is satisfied (S34: No), the calculation circuit 62c outputs the period Tdelay=Tx=T1+nTc as the calculation result (S36) (Tx>T1).

[0161] On the other hand, if Tcrs / (Ton+Tcrs)≧½ (S32: Yes), a resonance phenomenon occurs. Therefore, the calculation circuit 62c calculates the period T2=(½)×Tc (11) in the second mode (S37).

[0162] Furthermore, the calculation circuit 62c determines whether the switching frequency Freq is equal to or lower than a threshold value fth based on the frequency data Freq (S38).

[0163] If Freq≦fth is satisfied (S38: Yes), the calculation circuit 62c outputs the period Tdelay=T2 as the calculation result (S39), and if Freq>fth is satisfied (S38: No), the calculation circuit 62c outputs the period Tdelay=Ty=T2+nTc as the calculation result (S40) (Ty>T2).

[0164] When it is detected that the inductor current IL has become 0, the output circuit 63c outputs the signal Von after the time period Tdelay according to the calculation result of the calculation circuit 62c has elapsed (S41).

[0165] As a result, the power factor correction IC 35c can also drive the NMOS transistor 36 at the timing when the voltage Vdr is at a minimum regardless of whether the resonance phenomenon or the conduction phenomenon occurs, thereby reducing the switching loss in the AC-DC converter 10c.

[0166] ===Configuration of power factor correction IC35d=== FIG. 19 shows an example of the configuration of the power factor correction IC 35d.

[0167] The power factor correction IC 35d includes ADCs 51, 55, and 58 (Analog-to-Digital Converters), an on-period setting circuit 52, a signal output circuit 56d, a current source 57, a frequency detection circuit 59, a drive circuit 60, and a second control circuit 70. Here, components denoted with the same reference numerals as those in Fig. 12 correspond to the same components. The power factor correction IC 35d is configured to replace the power factor correction IC 35c in the AC-DC converter 10c in Fig. 15.

[0168] The following mainly describes the differences between the power factor correction IC 35d and the power factor correction IC 35c. The power factor correction IC 35d does not include the first control circuit 54, but includes a signal output circuit 56d and a second control circuit 70.

[0169] The power factor correction IC35d is (1 / 4)Tc+Ta>[(π+2) / 4π]×Tc...(8) Based on the determination principle 3, the power factor correction IC 35d determines whether a resonance phenomenon or a conduction phenomenon is occurring. Based on the determination result, the power factor correction IC 35d controls whether the voltage Vdr applied to the gate electrode of the NMOS transistor 36 is changed at a timing corresponding to the period T1 or at a timing corresponding to the period T2.

[0170] The signal output circuit 56d is Ta=(Tc / 2π)×(Tcrs / Ton)···(9) Based on calculation principle 2, when the inductor current IL becomes 0 after the NMOS transistor 36 is turned off, the signal output circuit 56d outputs the signal Von at a timing according to the period T1 or T2. The signal output circuit 56d includes a zero current detection circuit 61d, a calculation circuit 62d, and an output circuit 63d.

[0171] The second control circuit 70 determines whether the condition of equation (8): (1 / 4)Tc+Ta>[(π+2) / 4π]×Tc of determination principle 3 is satisfied. A specific configuration of the calculation circuit 62d will be described below with reference to Figures 20 and 21, and the relationship between the second control circuit 70 and the calculation circuit 62d will also be described here.

[0172] ===Processing Performed by Calculation Circuit 62d and Second Control Circuit 70=== FIG. 20 shows an example of the processing performed by the calculation circuit 62d and the second control circuit .

[0173] The calculation circuit 62d continues to calculate the period T1=(1 / 4)×Ta+(Tc / 2π)×(Tcrs / Ton) (12), T2=(1 / 2)×Tc (11). Specifically, the calculation circuit 62d can calculate the period T1 based on data on the voltages Vrt, Tcrs, Ton, and the frequency Freq. Furthermore, the calculation circuit 62d outputs the calculation result T1 to the output circuit 63d when the switching frequency Freq is equal to or less than a threshold fth (Freq≦fth), and outputs the calculation result T1+nTc when Freq>fth.

[0174] The calculation circuit 62d can calculate the period T2 based on data on the voltages Vrt, Tcrs, and Ton, and the frequency Freq. If Freq≦fth, the calculation circuit 62d outputs the calculation result T2 to the output circuit 63b, and if Freq>fth, the calculation circuit 62d outputs the calculation result T2+nTc to the output circuit 63b.

[0175] The second control circuit 70 determines whether the condition of equation (8) of determination principle 3 is satisfied based on the calculation result of the calculation circuit 62d. As a result, the second control circuit 70 outputs a signal Smd2 that controls whether the output circuit 63d determines the timing to turn on the NMOS transistor 36 based on the period T1 or the period T2. Note that in this embodiment, the determination is made based on the periods T1 and T2, but the periods T1+nTc and T2+nTc may also be used for the determination.

[0176] If the periods T1 and T2 satisfy the condition of equation (8), the output circuit 63d outputs the signal Von based on the period T1 (first mode), and if the condition of equation (8) is not satisfied, the output circuit 63d outputs the signal Von based on the period T2 (second mode). In particular, if Freq≦fth is satisfied, the output circuit 63 outputs a signal at a timing based on the period T1 or T2, and if Freq>fth, the output circuit 63 outputs a signal at a timing based on the period T1+nTc or T2+nTc.

[0177] ===Power Factor Correction IC35d Operation Flow=== FIG. 21 shows an example of the operation flow of the power factor correction IC 35d.

[0178] First, the frequency detection circuit 59 detects the switching frequency Freq based on the drive circuit Vdrv (S51). The frequency detection circuit 59 outputs data of the frequency Freq based on the detection result to the calculation circuit 62d.

[0179] Next, the calculation circuit 62d calculates the period T1=(1 / 4)×Tc+(Tc / 2π)×[Tcrs / Ton]···(12) and the period T2=(1 / 2)×Tc···(11) (S52).

[0180] Next, the second control circuit 70 determines whether the periods T1 and T2 satisfy a predetermined condition (equation (8): (1 / 4)Tc+Ta>[(π+2) / 4π]×Tc) (S53). Depending on the determination result, the second control circuit 70 outputs a signal Smd2 that controls the timing at which the output circuit 63d outputs a signal that turns on the NMOS transistor 36.

[0181] Here, the calculation circuit 62d changes the calculation result to be sent to the output circuit 63 depending on whether Freq≦fth is satisfied.

[0182] If the periods T1 and T2 satisfy the predetermined condition (S53: Yes), the calculation circuit 62d determines whether Freq≦fth is satisfied (S54).

[0183] If Freq≦fth (S54: Yes), the calculation result from the calculation circuit 62d is the period T1. The output circuit 63d outputs the signal Von based on the signal Smd2 and the calculation result from the calculation circuit 62d (S55).

[0184] On the other hand, if Freq>fth (S54: No), the calculation result from the calculation circuit 62d is period Tx=T1+nTc. The output circuit 63d outputs the signal Von based on the signal Smd2 and the calculation result from the calculation circuit 62d (S56).

[0185] If the periods T1 and T2 do not satisfy the predetermined condition (S53: Yes), the calculation circuit 62d determines whether Freq≦fth is satisfied (S57).

[0186] If Freq≦fth (S57: Yes), the calculation result from the calculation circuit 62d is the period T2. The output circuit 63d outputs the signal Von based on the signal Smd2 and the calculation result from the calculation circuit 62d (S58).

[0187] On the other hand, if Freq>fth (S54: No), the calculation result from the calculation circuit 62d is period Ty=T2+nTc. The output circuit 63d outputs the signal Von based on the signal Smd2 and the calculation result from the calculation circuit 62d (S59).

[0188] As a result, the power factor correction IC 35d can also drive the NMOS transistor 36 at the timing when the voltage Vdr is at a minimum regardless of whether the resonance phenomenon or the conduction phenomenon occurs, thereby reducing the switching loss in the AC-DC converter 10c.

[0189] ===Summary=== The AC-DC converters 10b and 10c and the power factor correction ICs 35a to 35d of this embodiment have been described above.

[0190] In the power factor correction ICs 35a to 35d, in order to reduce the switching loss of the NMOS transistor 36, the NMOS transistor 36 is turned off, and then turned on after the conduction period of the body diode 37 has elapsed since the inductor current IL became substantially zero. With the above configuration, even if a conduction phenomenon occurs, the NMOS transistor 36 can be turned on at the timing when the drain-source voltage Vds of the NMOS transistor 36 becomes a minimum value. This reduces the switching loss of the NMOS transistor 36 in the AC-DC converter 10b.

[0191] The signal output circuit 56a of the power factor correction IC 35a includes a zero current detection circuit 61a that detects when the inductor current IL becomes substantially zero after the NMOS transistor 36 is turned off, a calculation circuit 62a that calculates the period T1 based on the feedback voltage Vfb, the voltage Vrdiv corresponding to the rectified voltage Vr, and the resonance period Tc of the inductor current, and an output circuit 63a that outputs a signal Von after the period T1 has elapsed since the inductor current IL became substantially zero.

[0192] As a result, the ON timing of the NMOS transistor 36 can be calculated based on the feedback voltage Vfb and the rectified voltage Vr, and on the conduction period of the body diode 37, thereby reducing switching loss.

[0193] The power factor correction IC 35a also includes a first control circuit 54 that causes the calculation circuit 62a to operate in the first mode or the second mode, and the calculation circuit 62a calculates the period T1 in the first mode and calculates the period T2 corresponding to the period Tc in the second mode. Furthermore, the output circuit 63a outputs the signal Von after the period Tdelay calculated by the calculation circuit 62a has elapsed since the inductor current IL became substantially zero.

[0194] As a result, the power factor correction IC 35a can turn on the NMOS transistor 36 at the timing when the voltage Vds reaches a minimum value based on the feedback voltage Vfb and the rectified voltage Vr, regardless of whether the body diode 37 is conductive or resonant. Therefore, the switching loss of the NMOS transistor 36 can be reduced.

[0195] In addition, the first control circuit 54 operates the calculation circuit 62a in the first mode when the rectified voltage Vr is lower than 1 / 2 the output voltage Vout, and operates the calculation circuit 62a in the second mode when the rectified voltage Vr is higher than 1 / 2 the output voltage Vout.

[0196] This allows the first control circuit 54 to determine whether the conduction phenomenon or the resonance phenomenon is occurring, based on the first determination principle.

[0197] In addition, the power factor correction IC 35b includes a second control circuit 70 that operates the output circuit 63c in the first mode or the second mode, and the calculation circuit 62c calculates the period T1 and the period T2. In the first mode, the output circuit 63 outputs the signal Von after the period T1 has elapsed since the inductor current becomes almost zero, and in the second mode, the output circuit 63 outputs the signal Von after the period T2 has elapsed since the inductor current IL becomes almost zero.

[0198] As a result, the power factor correction IC 35b can turn on the NMOS transistor 36 at the timing when the voltage Vds reaches a minimum value based on the conduction period of the body diode 37, based on Judgment Principle 3 and Calculation Principle 2. Therefore, the power factor correction IC 35c can reduce switching loss.

[0199] Furthermore, the second control circuit 70 operates the output circuit 63b in the first mode when the periods T1 and T2 satisfy equation (7) of determination principle 3, and operates the output circuit 63b in the second mode when the periods T1 and T2 do not satisfy equation (7).

[0200] This allows the second control circuit 70 to determine whether the conduction phenomenon or the resonance phenomenon is occurring, using the determination principle 3.

[0201] The signal output circuit 56c also includes a zero current detection circuit 61c that detects when the inductor current IL becomes substantially zero after the NMOS transistor 36 is turned off, a calculation circuit 62c that calculates a period T1 based on the period Ton from when the drive circuit 60 turns the NMOS transistor 36 on until it turns it off, the period Tcrs from when the NMOS transistor 36 is turned off until it becomes substantially zero, and the resonance period Tc of the inductor current IL, and an output circuit 63a that outputs a signal Von after the period T1 has elapsed since the inductor current IL became substantially zero.

[0202] As a result, the power factor correction IC 35c can turn on the NMOS transistor 36 at the timing when the voltage Vds reaches a minimum value, based on the conduction period of the body diode 37. Therefore, the power factor correction IC 35c can reduce switching loss.

[0203] The power factor correction IC 35c also includes a first control circuit 82 that causes the calculation circuit 62c to operate in the first mode or the second mode. The calculation circuit 62c calculates the period T1 in the first mode and calculates the period T2 in the second mode. The output circuit 63c outputs the signal Von after the period Tdelay calculated by the calculation circuit 62c has elapsed since the inductor current IL became approximately zero.

[0204] As a result, based on Calculation Principle 2, the NMOS transistor 36 can be turned on when the voltage Vds reaches a minimum value regardless of whether conduction or resonance occurs, without directly detecting the voltage Vrdiv based on the rectified voltage Vr. Therefore, the power factor correction IC 35c can reduce switching loss.

[0205] The first control circuit 82 operates the calculation circuit 62c in the first mode when the ratio based on the period Ton and the period Tcrs is smaller than 1 / 2, and operates the calculation circuit 62c in the second mode when the ratio is larger than 1 / 2.

[0206] As a result, based on determination principle 2, it is possible to determine whether the conduction phenomenon or the resonance phenomenon is occurring without directly detecting the voltage Vrdiv based on the rectified voltage Vr.

[0207] The power factor correction IC 35d includes a second control circuit 70 that causes the output circuit 63d to operate in the first mode or the second mode, and the calculation circuit 62d calculates the period T1 and the period T2. In the first mode, the output circuit 63d outputs the signal Von after the period T1 has elapsed since the inductor current IL became almost zero, and in the second mode, the output circuit 63d outputs the signal Von after the period T2 has elapsed since the inductor current IL became almost zero.

[0208] As a result, the power factor correction IC 35d can also reduce the switching loss of the NMOS transistor 36.

[0209] The power factor correction ICs 35a to 35d also include a frequency detection circuit 59 that detects the switching frequency Freq of the NMOS transistor 36, and the signal output circuits 56a to 56d output a signal Von after the elapse of periods T1+nTc and T2+nTc, which are longer than the periods T1 and T2, when the switching frequency Freq is higher than a threshold value fth.

[0210] By setting n to an appropriate value, the switching frequency Freq can be maintained at a constant value or less, and switching loss can be reduced.

[0211] Also provided are AC-DC converters 10b and 10c having power factor correction ICs 35a to 35d, thereby providing AC-DC converters 10b and 10c that are power supply circuits with reduced switching loss.

[0212] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that the technical scope of the present invention may include forms incorporating such modifications and improvements and their equivalents without departing from the spirit of the invention.

[0213] It should be noted that the execution order of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order. [Explanation of symbols]

[0214] 10a~10c AC-DC converter 11 Load 20 AC power supply 21 Inductor 22 Capacitor 30 Full wave rectifier circuit 31,32 Capacitor 33 Inductor 34 Diode 35 Power factor correction IC 36 NMOS transistors 37 Body diode 38 Parasitic Capacitor 40~45 Resistance 51, 53, 55, 58 ADC 52 ON period setting circuit 54 First control circuit 56a~56d Signal output circuit 57 Current source 59 Frequency detection circuit 60 Drive circuit 61a to 61d Zero current detection circuit 62a~62d Calculation circuit 63a~63d Output circuit 70 Second control circuit 81 Tcrs detection circuit 82 First control circuit 100 Power Factor Correction IC

Claims

1. 1. A switching control circuit for a power supply circuit that generates an output voltage of a target level from an AC voltage, the power supply circuit comprising: an inductor to which a rectified voltage corresponding to an AC voltage is applied; and a transistor that controls an inductor current flowing through the inductor, the switching control circuit switching the transistor, a signal output circuit that outputs a signal to turn on the transistor when the inductor current reaches a first predetermined value after the transistor is turned off and after a first period corresponding to a conduction period during which a parasitic diode of the transistor is conductive has elapsed; a drive circuit that turns on the transistor based on the signal and turns off the transistor based on a feedback voltage corresponding to the output voltage; Equipped with Switching control circuit.

2. 2. The switching control circuit according to claim 1, The signal output circuit a detection circuit that detects when the inductor current reaches the first predetermined value after the transistor is turned off; a calculation circuit that calculates the first period based on the feedback voltage, a voltage corresponding to the rectified voltage, and a resonance period of the inductor current; an output circuit that outputs the signal after the calculated first period has elapsed since the inductor current reached the first predetermined value; Including, Switching control circuit.

3. 3. The switching control circuit according to claim 2, a first control circuit that causes the calculation circuit to operate in a first mode or a second mode; The calculation circuit In the first mode, the first period is calculated, and in the second mode, the second period is calculated according to a resonance period of the inductor; The output circuit the signal is output after a period calculated by the calculation circuit has elapsed since the inductor current reached the first predetermined value. Switching control circuit.

4. 4. The switching control circuit according to claim 3, The first control circuit When the rectified voltage is lower than half the output voltage, the calculation circuit operates in the first mode, and when the rectified voltage is higher than half the output voltage, the calculation circuit operates in the second mode. Switching control circuit.

5. 3. The switching control circuit according to claim 2, a second control circuit that causes the output circuit to operate in a first mode or a second mode; The calculation circuit calculating the first period and a second period corresponding to a resonance period of the inductor; The output circuit In the first mode, the signal is output after the first period has elapsed since the inductor current reached the first predetermined value, and in the second mode, the signal is output after the second period has elapsed since the inductor current reached the first predetermined value. Switching control circuit.

6. 6. The switching control circuit according to claim 5, The second control circuit is When the first period and the second period satisfy a predetermined condition, the output circuit is operated in the first mode, and when the first period and the second period do not satisfy the predetermined condition, the output circuit is operated in the second mode. Switching control circuit.

7. 2. The switching control circuit according to claim 1, The signal output circuit a detection circuit that detects when the inductor current reaches the first predetermined value after the transistor is turned off; a calculation circuit that calculates the first period based on an on-period from when the drive circuit turns on the transistor until when it turns off, a period from when the drive circuit turns off the transistor until the inductor current reaches the first predetermined value, and a resonance period of the inductor current; an output circuit that outputs the signal after the calculated first period has elapsed since the inductor current reached the first predetermined value; Including, Switching control circuit.

8. 8. The switching control circuit according to claim 7, a first control circuit that causes the calculation circuit to operate in a first mode or a second mode; The calculation circuit In the first mode, the first period is calculated, and in the second mode, the second period is calculated according to a resonance period of the inductor; The output circuit the signal is output after a period calculated by the calculation circuit has elapsed since the inductor current reached the first predetermined value. Switching control circuit.

9. 9. A switching control circuit according to claim 8, The first control circuit When a ratio based on the on-period and a period from when the transistor is turned off until when the first predetermined value is reached is smaller than a second predetermined value, the calculation circuit is operated in the first mode, and when the ratio is larger than the second predetermined value, the calculation circuit is operated in the second mode. Switching control circuit.

10. 8. The switching control circuit according to claim 7, a second control circuit that causes the output circuit to operate in a first mode or a second mode; The calculation circuit calculating the first period and a second period corresponding to a resonance period of the inductor; The output circuit In the first mode, the signal is output after the first period has elapsed since the inductor current reached the first predetermined value, and in the second mode, the signal is output after the second period has elapsed since the inductor current reached the first predetermined value. Switching control circuit.

11. 11. The switching control circuit of claim 10, The second control circuit is When the first period and the second period satisfy a predetermined condition, the output circuit is operated in the first mode, and when the first period and the second period do not satisfy the predetermined condition, the output circuit is operated in the second mode. Switching control circuit.

12. 12. A switching control circuit according to claim 2, wherein: a frequency detection circuit for detecting a switching frequency of the transistor; The signal output circuit If the switching frequency is higher than a third predetermined value, the signal is output after a period longer than the calculated period has elapsed. Switching control circuit.

13. A power supply circuit that generates an output voltage of a target level from an AC voltage, an inductor to which a rectified voltage corresponding to the AC voltage is applied; a transistor for controlling an inductor current flowing through the inductor; a switching control circuit for switching the transistor; Equipped with The switching control circuit a signal output circuit that outputs a signal to turn on the transistor when the inductor current reaches a first predetermined value after the transistor is turned off and after a first period corresponding to a conduction period during which a parasitic diode of the transistor is conductive has elapsed; a drive circuit that turns on the transistor based on the signal and turns off the transistor based on a feedback voltage corresponding to the output voltage; Including, power circuit.

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