Wiring structure, manufacturing method thereof, and semiconductor package

Abstract

The present invention discloses a method, for manufacturing a wiring structure, comprising a step for forming wiring on an insulating resin layer. The step for forming wiring includes: forming a modified region containing pores on the surface of the insulating resin layer by treating the surface of the insulating resin layer via a treatment method that accompanies surface modification; using sputtering to form a seed layer on the surface of the insulating resin layer; and using electrolytic copper plating to form the wiring on the seed layer. The disclosed method may include, in this order, a step for forming a surface treating agent layer covering the surface of the wiring by treating the surface of the wiring with a surface treating agent for improving close adhesion; and a step for forming a modified region containing pores on the surface of a first insulating resin layer by treating the surface of the first insulating resin layer via a treatment method that accompanies surface modification.

Description

[Technical Field]

[0001] The present disclosure relates to a wiring structure, a method for manufacturing the same, and a semiconductor package. [Background technology]

[0002] In a packaging configuration in which semiconductor chips with different performance are mixed and mounted in one package, high-density interconnect technology between semiconductor chips is becoming increasingly important from the viewpoint of manufacturing costs (Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2003-318519 Summary of the Invention [Problem to be solved by the invention]

[0004] In the technology described in Patent Document 1, a seed layer is formed by electroless plating after treatment with a desmear treatment solution. A conductive portion is formed on the surface of the seed layer by supplying power to the seed layer. In the technology described in Patent Document 1, the surface of the insulating layer is roughened by wet desmear treatment. Roughening the surface of the insulating layer improves adhesion between the seed layer and the insulating layer due to an anchor effect.

[0005] However, according to the findings of the present inventors, when forming fine wiring on an insulating resin layer, roughening the surface of the insulating resin layer to obtain an anchor effect tends to cause defects such as the wiring collapsing or a part of the wiring peeling off from the insulating layer, resulting in a defect. This tendency is particularly pronounced when forming fine wiring with an L / S (line / space) of 10 / 10 μm or less.

[0006] Therefore, one aspect of the present disclosure relates to a method for manufacturing a wiring structure having fine wiring provided on an insulating resin layer while suppressing the occurrence of defects in the wiring.

[0007] When manufacturing a wiring structure having two or more insulating resin layers and wiring provided between adjacent insulating resin layers, the wiring may be treated with a surface treatment agent to form a surface treatment agent layer covering the surface of the wiring in order to improve adhesion to the insulating resin layer. However, this can result in insufficient adhesion between adjacent insulating resin layers. In particular, in the case of insulating resin layers compatible with high frequencies, the low polarity of the resin tends to result in insufficient adhesion between the insulating resin layers. Therefore, it is desirable to improve the adhesion between adjacent insulating resin layers while maintaining a sufficient surface treatment agent layer covering the wiring.

[0008] Another aspect of the present disclosure relates to a method for improving adhesion between adjacent insulating resin layers while leaving the surface treatment agent layer, in a case where a wiring structure having two or more insulating resin layers and wiring provided between adjacent insulating resin layers is manufactured by a method including forming a surface treatment agent layer on the surface of the wiring to improve adhesion. [Means for solving the problem]

[0009] One aspect of the present disclosure provides a method for manufacturing a wiring structure, comprising the steps of: treating a surface of the insulating resin layer with a treatment method involving surface modification to form a modified region containing voids on the surface of the insulating resin layer; forming a seed layer containing one or more metal layers on the surface of the insulating resin layer by sputtering; forming a resist on the seed layer having a pattern including openings through which the seed layer is exposed; forming the wiring on the seed layer exposed in the openings by electrolytic copper plating; removing the resist; and removing portions of the seed layer not covered by the wiring.

[0010] Another aspect of the present disclosure provides a wiring structure including an insulating resin layer, a seed layer including one or more metal layers provided on the insulating resin layer, and a copper wiring provided on the seed layer, wherein a modified region including pores is formed in a surface layer of the insulating resin layer facing the seed layer, and a portion of the metal forming the seed layer penetrates into the pores.

[0011] Yet another aspect of the present disclosure provides a semiconductor package including the wiring structure and a semiconductor chip connected to wiring of the wiring structure.

[0012] a resist having a pattern including an opening for forming wiring on the seed layer, the opening exposing the seed layer; forming wiring on the seed layer exposed in the opening by electrolytic copper plating; removing the resist; removing a portion of the seed layer not covered by the wiring to expose a portion of the surface of the first insulating resin layer not covered by the remaining seed layer; treating the surface of the wiring with a surface treatment agent for improving adhesion, thereby forming a surface treatment agent layer covering the surface of the wiring; treating the surface of the first insulating resin layer with a treatment method involving surface modification, thereby forming a modified region including voids on the surface of the first insulating resin layer; and forming a second insulating resin layer on the first insulating resin layer, the second insulating resin layer covering the wiring. [Effects of the Invention]

[0013] According to one aspect of the present disclosure, a wiring structure having fine wiring provided on an insulating resin layer can be manufactured while suppressing the occurrence of defects in the wiring.

[0014] According to one aspect of the present disclosure, it is possible to improve the adhesion of wiring while maintaining a relatively low surface roughness of the insulating resin layer, thereby reducing transmission loss due to the skin effect of the insulating resin layer.

[0015] According to one aspect of the present disclosure, when a wiring structure having two or more insulating resin layers and wiring provided between adjacent insulating resin layers is manufactured by a method including forming a surface treatment agent layer on the surface of the wiring to improve adhesion, it is possible to improve adhesion between adjacent insulating resin layers while leaving the surface treatment agent layer. [Brief explanation of the drawings]

[0016] [Figure 1] 1A to 1C are cross-sectional views schematically showing an example of a method for manufacturing a wiring structure. [Figure 2] 1A to 1C are cross-sectional views schematically showing an example of a method for manufacturing a wiring structure. [Figure 3] 1A to 1C are cross-sectional views schematically showing an example of a method for manufacturing a wiring structure. [Figure 4] 1A to 1C are cross-sectional views schematically showing an example of a method for manufacturing a wiring structure. [Figure 5] 1A to 1C are cross-sectional views schematically showing an example of a method for manufacturing a wiring structure. [Figure 6] 1A to 1C are cross-sectional views schematically showing an example of a method for manufacturing a wiring structure. [Figure 7] FIG. 1 is a schematic cross-sectional view showing an example of a semiconductor package. [Figure 8] 1 is a graph showing the unevenness of the surface of an insulating resin layer treated by ultraviolet irradiation. [Figure 9] 10 is a graph showing the unevenness of the surface of an insulating resin layer treated by a desmear treatment. [Figure 10] 1 is a graph showing the unevenness of the surface of an insulating resin layer treated by plasma treatment. DETAILED DESCRIPTION OF THE INVENTION

[0017] The present invention is not limited to the examples described below. In the following description, identical or equivalent parts are designated by the same reference numerals, and duplicated descriptions may be omitted. Positional relationships such as up, down, left, and right are based on the positional relationships shown in the drawings unless otherwise specified. Furthermore, the dimensional ratios of the drawings are not limited to those shown. Terms such as "left," "right," "front," "back," "top," "bottom," "upper," and "lower" do not necessarily mean that their relative positions do not change. The term "layer" encompasses not only a structure with a shape formed over the entire surface when observed in a plan view, but also a structure with a shape formed only in a portion.

[0018] 1, 2, and 3 are cross-sectional views schematically illustrating an example of a method for manufacturing a wiring structure. The method illustrated in FIGS. 1 to 3 includes the steps of: (I) forming a first insulating resin layer 21 having a pattern including openings 20 on a substrate 1; (II) forming wiring 5 on the insulating resin layer 21; and (III) forming two or more additional insulating resin layers 22, 23 stacked on the insulating resin layer 21 and additional wiring 5 provided between adjacent additional insulating resin layers 22, 23, thereby forming a multilayer wiring section 7 including three or more insulating resin layers 21, 22, 23 and two or more wiring layers 5. This method provides a wiring structure 60 including the substrate 1 and the multilayer wiring section 7 provided on the substrate 1.

[0019] 1 to 3 can be applied to semiconductor packages that require miniaturization and an increased number of pins, such as a semiconductor package having an interposer for mounting different types of semiconductor chips. More specifically, the wiring structure obtained by the method according to the present disclosure can constitute a semiconductor package having, for example, a pin spacing of 200 μm or less, or 30 to 100 μm, and the number of pins being 500 or more, or 1,000 to 10,000.

[0020] According to the method of the present disclosure, by forming a modified region on the surface of the insulating resin layer, it is possible to improve the adhesion between the seed layer and the insulating resin layer, and therefore, compared to methods including a desmear process, it is possible to manufacture a wiring structure having fine wiring for electrically connecting semiconductor chips with each other with a higher yield.

[0021] <Step (I) of forming a first insulating resin layer 21 having a pattern including openings 20 on the substrate 1> Step (I) includes preparing a plate-shaped substrate 1 having two main surfaces, providing an insulating resin layer 21 on one of the main surfaces of the substrate 1 ((a) of Figure 1), and forming a pattern in the insulating resin layer 21 that includes openings 20 for forming connecting portions through which the substrate 1 is exposed ((b) of Figure 1).

[0022] The base material 1 has an insulating substrate 11 and a conductive layer 12 provided on the insulating substrate 11. The insulating substrate 11 is not particularly limited, and may be, for example, a substrate including a silicon plate, a glass plate, a stainless steel plate, or a glass cloth. The conductive layer 12 that covers the entire main surface of the insulating substrate does not have to be provided. Instead of the conductive layer 12, wiring and / or pads may be provided on the insulating substrate 11. The base material 1 may be a semiconductor package having a semiconductor chip and an encapsulating resin layer that encapsulates the semiconductor chip.

[0023] The thickness of the substrate 1 may be 0.2 to 2.0 mm. If the thickness of the substrate 1 is less than 0.2 mm, handling tends to be difficult. If the thickness of the substrate 1 is greater than 2.0 mm, material costs tend to be high. The substrate 1 may be disk-shaped or panel-shaped. For example, the diameter of the disk-shaped substrate 1 may be 200 to 450 mm. The panel-shaped substrate 1 may have a rectangular main surface formed by sides with lengths of 300 to 700 mm.

[0024] The insulating resin layer 21 can be formed from, for example, a photosensitive resin composition. The insulating resin layer 21 formed from the photosensitive resin composition can easily have fine openings 20 formed therein by photolithography. The photosensitive resin composition can be, for example, in a liquid or film form. A film-like photosensitive resin composition is advantageous in terms of film thickness flatness and cost. The insulating resin layer 21 may also be formed from a thermosetting resin composition.

[0025] The insulating resin layer 21 may be provided by laminating a film-like photosensitive resin composition onto the substrate 1 at a relatively low temperature of 40 to 120° C. A film-like photosensitive resin composition that can be laminated at 40 to 120° C. tends to have appropriate tack and be able to suppress warping.

[0026] The insulating resin layer 21 may contain a filler having an average particle size of 500 nm or less, or 50 to 200 nm. A fine pattern is particularly easily formed in the insulating resin layer 21 containing the filler. The filler content may be 0 to 70 parts by mass, or 0 to 50 parts by mass, relative to 100 parts by mass of the total amount of the components of the insulating resin layer 21 other than the filler.

[0027] The thickness of the insulating resin layer 21 may be 10 μm or less, 5 μm or less, or 3 μm or less. A thin insulating resin layer 21 makes it easier to form fine openings 20. From the viewpoint of insulation reliability, the thickness of the insulating resin layer 21 may be 1 μm or more.

[0028] As shown in FIG. 1(b), a pattern including openings 20 exposing the substrate 1 is formed by removing a portion of the insulating resin layer 21 provided on the substrate 1. The openings 20 are recesses each having an inner wall extending in the thickness direction of the insulating resin layer 21 and a bottom surface which is the surface of the substrate 1 (or the conductive layer 12). The openings 20 for forming connecting portions may have a circular or elliptical shape when viewed from a direction perpendicular to the main surface of the insulating resin layer 21. The area of ​​the openings 20 when viewed from a direction perpendicular to the main surface of the insulating resin layer 21 may be an area corresponding to the area of ​​a circle having a diameter of 5 to 50 μm or 5 to 10 μm.

[0029] The openings 20 can be formed by, for example, laser ablation, photolithography, or imprinting. When the insulating resin layer 21 is formed of a photosensitive resin material, the openings 20 can be easily formed by photolithography, which includes exposure and development. The exposure method for photolithography may be, for example, a projection exposure method, a contact exposure method, or a direct writing exposure method. For development, an alkaline aqueous solution containing sodium carbonate or TMAH (tetramethylammonium hydroxide) may be used.

[0030] After the opening 20 is formed by photolithography, the insulating resin layer 21 may be further thermally cured. The heating temperature for thermal curing may be 100 to 200°C. The heating time for thermal curing may be 30 minutes to 3 hours. If there is residue of the insulating resin layer 21 on the bottom surface of the opening 20, the residue may be removed by oxygen plasma treatment, argon plasma treatment, or nitrogen plasma treatment.

[0031] The thermal expansion coefficient of the insulating resin layer 21 having a pattern including the openings 20 is 80×10 -6 / K or less, or 70 x 10 -6 / K or less. From the viewpoint of the stress relaxation property of the insulating resin layer 21 and easy formation of a high-definition pattern, the thermal expansion coefficient of the insulating resin layer 21 is set to 20×10 -6 / K or more.

[0032] <Step (II) of forming wiring 5 on insulating resin layer 21> Step (II) includes, in this order, treating the surface 21S, which is the main surface of the insulating resin layer 21 opposite the substrate 1, with a treatment method involving surface modification at least once to form a modified region 21A containing voids on the surface of the insulating resin layer 21 ((c) of Figure 1), forming a seed layer 3 on the surface 21S by sputtering ((d) and (e) of Figure 1), forming a resist 4 on the seed layer 3 having a pattern including openings 40 and 40a through which the seed layer 3 is exposed ((a) of Figure 2), forming wiring 5 and connecting portions 5a on the seed layer 3 exposed in the openings 40 and 40a by electrolytic copper plating ((b) of Figure 2), removing the resist 4 ((c) of Figure 2), and removing portions of the seed layer 3 that are not covered by the wiring 5 or connecting portions 5a ((d) of Figure 2).

[0033] By forming a modified region in the surface layer on the surface 21S side of the insulating resin layer 21, it is possible to improve the adhesion between the insulating resin layer 21 and the seed layer 3 formed by sputtering while maintaining a relatively low surface roughness of the surface 21S. The modified region 21A may include a plurality of fine pores that communicate with the surface 21S. It is believed that during the process of forming the seed layer 3 by sputtering, part of the metal forming the seed layer 3 enters the pores in the modified region 21A, resulting in improved adhesion between the seed layer 3 and the insulating resin layer 21. The formation of pores can be confirmed, for example, by observing a cross section of the insulating resin layer 21 with a scanning transmission electron microscope.

[0034] The treatment method for forming the modified region may be at least one treatment method selected from the group consisting of electron beam irradiation, ozone water treatment, and corona discharge treatment, or ultraviolet irradiation. Ultraviolet irradiation has the advantages of not requiring vacuum equipment and not generating waste liquid. The ultraviolet irradiation may be ultraviolet irradiation using an incoherent light source. Compared to coherent light sources such as laser light sources, an incoherent light source has the advantage of being able to efficiently irradiate ultraviolet rays over a wide area of ​​the insulating resin layer 21. Examples of incoherent light sources include high-pressure mercury lamps, low-pressure mercury lamps, and excimer lamps. The incoherent light source may be a low-pressure mercury lamp or an excimer lamp, which have a strong activation effect.

[0035] The treatment for forming the modified region 21A (e.g., ultraviolet irradiation) can be performed, for example, in the air or in an oxygen atmosphere. In the treatment for forming the modified region 21A, the temperature of the insulating resin layer 21 may be 25°C to 100°C, 40°C to 100°C, or 60°C to 100°C. The higher the temperature, the more efficiently the modified region 21A can be formed.

[0036] The surface 21S of the insulating resin layer 21 including the modified region 21A may have a surface roughness Ra of 70 nm or less. A small surface roughness Ra makes it difficult for defects to occur in the fine wiring 5. By forming the modified region 21A, it is possible to sufficiently increase the adhesion between the insulating resin layer 21 and the seed layer 3 even if the surface roughness Ra is small.

[0037] The modified region 21A may be formed to a depth of 50 nm or more from the surface 21S of the insulating resin layer 21. When the modified region 21A is formed deep, the effect of improving adhesion is more likely to be obtained. The depth of the modified region 21A from the surface 21S may be 200 nm or less.

[0038] After the modified region 21A is formed, the contact angle of the surface 21S of the insulating resin layer 21 with pure water may be 40 degrees or less, or 10 degrees or less.

[0039] After the modified region 21A is formed, an adhesion layer 31 and a power supply layer 32 are sequentially formed on the surface 21S by sputtering. The seed layer 3 is composed of the adhesion layer 31 and the power supply layer 32. The seed layer 3 including the adhesion layer 31 and the power supply layer 32 may be formed by electroless plating.

[0040] The adhesion layer 31 may be a metal layer containing, for example, titanium, chromium, tungsten, nickel, or an alloy containing two or more metals selected from these. The thickness of the adhesion layer 31 may be, for example, 20 to 200 nm, 40 to 200 nm, or 60 to 200 nm.

[0041] The power supply layer 32 functions as a power supply layer for electrolytic copper plating to form the wiring 5. The power supply layer 32 is typically a metal layer containing copper. The thickness of the power supply layer 32 may be, for example, 90 to 200 nm, 100 to 200 nm, or 150 to 300 nm.

[0042] After the formation of the seed layer 3, the insulating resin layer 21 and the seed layer 3 may be annealed to further increase the adhesive strength between the adhesive layer 31 and the insulating resin layer 21. The heating temperature for annealing may be 80 to 200° C., 120 to 200° C., or 120 to 180° C. The heating time for annealing may be 5 to 60 minutes, 10 to 60 minutes, or 20 to 60 minutes.

[0043] A resist 4 for forming wiring is formed on the seed layer 3, the resist 4 having a pattern including openings 40 for forming wiring and openings 40a for forming connecting portions. As shown in FIG. 2(a), the openings 40a for forming connecting portions are formed so that the openings 20 of the first insulating resin layer 21 are located inside the openings 40a. As a result, a recess is formed on the substrate 1, the recess being composed of the openings 20 having the seed layer 3 as their inner walls and the openings 40a communicating with the openings 20a.

[0044] The opening 40 for forming a wiring is formed at a position on the seed layer 3 other than the opening 20. The shape of the opening 40 for forming a wiring when viewed from a direction perpendicular to the main surface of the insulating resin layer 21 may include a linear portion. The width of the opening 40 (the width of the linear portion) may be 1 to 10 μm, or 1 to 5 μm. The width of the opening 40 corresponds to the width of the wiring 5 to be formed. If the width of the opening 40 is small, it is easier to provide a semiconductor device that achieves high density.

[0045] The opening 40a for forming a connecting portion may have a circular or elliptical shape when viewed from a direction perpendicular to the main surface of the insulating resin layer 21. The opening 40 when viewed from a direction perpendicular to the main surface of the insulating resin layer 21 may have an area equivalent to the area of ​​a circle with a diameter of 5 to 50 μm or 5 to 10 μm.

[0046] The resist 4 can be selected from those used in the art. For example, a negative photosensitive film resist (Photec RY-5107UT, manufactured by Hitachi Chemical Co., Ltd.) can be used. The recesses in the circuit-forming resist can be formed by first forming a film of the circuit-forming resist using a commercially available roll laminator, then adhering a patterned phototool to the film, exposing the film using an exposure device, and then spray-developing the film with an aqueous sodium carbonate solution. A positive photosensitive resist may be used instead of the negative resist.

[0047] Wiring 5 is formed by electrolytic copper plating on the seed layer 3 (power supply layer 32) exposed in the wiring formation opening 40. At the same time, connecting portions 5a filling the openings 40a and 20 are formed on the seed layer 3 (power supply layer 32) exposed in the connecting portion formation openings 40a and 20.

[0048] The wiring 5 may include linear portions having a width of 1 to 10 μm, or 1 to 5 μm. According to the method of the present disclosure, wiring 5 including linear portions having a minute width, i.e., having a pattern with a small L / S, can be easily manufactured while suppressing the occurrence of defects. The thickness of the wiring 5 may be 1 to 10 μm, 3 to 10 μm, or 5 to 10 μm.

[0049] After the wiring 5 is formed, the resist 4 is stripped from the seed layer 3. The resist 4 can be easily removed by using a commercially available stripping liquid.

[0050] Next, the portions of the seed layer 3 that are not covered by the wiring 5 or the connecting portion 5a are removed. The seed layer 3 can be easily removed by using a commercially available etching solution. Specific examples of commercially available etching solutions include WLC-C2 manufactured by Mitsubishi Gas Chemical Company, Inc., which is suitable for removing the power supply layer 32, and WLC-T manufactured by Mitsubishi Gas Chemical Company, Inc., which is suitable for removing the adhesion layer 31.

[0051] <Step (III) of forming multilayer wiring section 7> Step (III) may include repeating similar steps to form the first insulating resin layer 21 and the wiring 5 and the connecting portion 5a to form two or more additional insulating resin layers 22, 23 and one or more additional wirings 5. Specifically, step (III) may include, in this order, forming an additional insulating resin layer 22 on the first insulating resin layer 21, treating the surface of the additional insulating resin layer 22 by a treatment method involving surface modification to form a modified region including voids on the surface of the additional insulating resin layer 22, forming a seed layer including an adhesion layer and a power supply layer on the surface of the additional insulating resin layer 22 by sputtering, forming a resist on the seed layer having a pattern including openings for forming wiring through which the seed layer is exposed, forming additional wirings on the seed layer exposed in the openings for forming wiring in the resist by electrolytic copper plating, removing the resist, and removing portions of the seed layer that are not covered by the additional wirings. The treatment method for treating the surface of the additional insulating resin layer 22 may also be at least one treatment method selected from the group consisting of ultraviolet irradiation, electron beam irradiation, ozone water treatment, and corona discharge treatment.

[0052] The second insulating resin layer 22 to be added has a pattern including openings for forming connecting portions, through which the connecting portions 5a of the lower layer formed in the openings 20 of the first insulating resin layer 21 are exposed. The seed layer formed on the additional insulating resin layer 22 extends up to the connecting portions 5a of the lower layer exposed in the openings for forming connecting portions of the insulating resin layer 22. The resist pattern further includes openings for forming connecting portions, through which the seed layer formed in the openings for forming connecting portions of the additional insulating resin layer 22 is exposed. The connecting portions are formed together with additional wiring by electrolytic copper plating on the seed layer exposed in the openings for forming connecting portions. The second and subsequent insulating resin layers can have the same thickness as the first insulating resin layer.

[0053] Furthermore, by repeating the same steps except that no additional wiring is formed, the uppermost insulating resin layer 23 and the connecting portion 5a including the portion filling the opening of the insulating resin layer 23 are formed.

[0054] 4, 5, and 6 are cross-sectional views schematically showing another example of a method for manufacturing a wiring structure. The method shown in Figs. 4 to 6 includes the steps of forming a first insulating resin layer 21 having a pattern including openings 20 on a substrate 1, forming a seed layer 3 on a surface 21S of the first insulating resin layer 21, forming a resist 4 on the seed layer 3 having a pattern including openings 40 for forming wirings through which the seed layer 3 is exposed, forming wirings 5 ​​on the seed layer 3 exposed in the openings 40 by electrolytic copper plating, removing the resist 4, and treating the surface of the wirings 5 ​​with a surface treatment agent for improving adhesion to form a surface treatment agent layer 6 covering the surface of the wirings 5. The method includes, in this order, a step of forming a multilayer wiring section 7 including three insulating resin layers 21, 22, and 23, and two layers of wiring 5, by treating a surface 21S of the first insulating resin layer 21 with a treatment method involving surface modification to form a modified region 21B including voids on the surface of the first insulating resin layer 21, a step of forming a second insulating resin layer 22 on the first insulating resin layer 21 to cover the wiring 5, and a step of forming a second wiring 5 on the second insulating resin layer 22 and an additional third insulating resin layer 23 laminated on the second insulating resin layer 22. The step of forming the first insulating resin layer 21 having a pattern including openings 20 on the substrate 1 and the step of forming a seed layer 3 on the surface 21S of the first insulating resin layer 21 can be performed by a method similar to the example shown in FIG. 1. The seed layer 3 may be formed by electroless plating. can.

[0055] 4 to 6 can be applied to semiconductor packages that require miniaturization and an increased number of pins, such as a semiconductor package having an interposer for mounting different types of semiconductor chips. More specifically, the wiring structure obtained by the method according to the present disclosure can constitute a semiconductor package having, for example, a pin spacing of 200 μm or less, or 30 to 100 μm, and 500 or more, or 1,000 to 10,000 pins.

[0056] According to the method of the present disclosure, by forming a modified region on the surface of an insulating resin layer, it is possible to enhance the adhesion between insulating resin layers while maintaining the effect of the surface treatment agent in improving the adhesion of wiring, and therefore, compared to methods including a desmear treatment, it is possible to manufacture a wiring structure having fine wiring for electrically connecting semiconductor chips with each other with a better yield.

[0057] 1, the surface 21S, which is the main surface of the insulating resin layer 21 opposite the substrate 1, may be treated one or more times with a treatment method involving surface modification to form a modified region 21A containing voids in the surface layer of the insulating resin layer 21. The modified region 21A before the seed layer 3 is formed can be formed by a method similar to that used to form the modified region 21B after the seed layer 3 is removed and exposed, as described below. During the process of forming the seed layer 3 by sputtering, part of the metal forming the seed layer 3 enters the voids in the modified region 21A, which is thought to result in improved adhesion between the seed layer 3 and the insulating resin layer 21.

[0058] A resist 4 for forming interconnects is formed on the seed layer 3, the resist 4 having a pattern including openings 40 for forming interconnects and openings 40a for forming connecting portions. As shown in FIG. 4(a), the openings 40a for forming connecting portions are formed so that the openings 20 in the first insulating resin layer 21 are located inside the openings 40a. As a result, a recess is formed on the substrate 1, the recess being composed of the openings 20 having the seed layer 3 as their inner walls and the openings 40a communicating with the openings 20a.

[0059] The opening 40 for forming a wiring is formed at a position on the seed layer 3 other than the opening 20. The shape of the opening 40 for forming a wiring when viewed from a direction perpendicular to the main surface of the insulating resin layer 21 may include a linear portion. The width of the opening 40 (the width of the linear portion) may be 1 to 10 μm, or 1 to 5 μm. The width of the opening 40 corresponds to the width of the wiring 5 to be formed. If the width of the opening 40 is small, it is easier to provide a semiconductor device that achieves high density.

[0060] The opening 40a for forming a connecting portion may have a circular or elliptical shape when viewed from a direction perpendicular to the main surface of the insulating resin layer 21. The opening 40 when viewed from a direction perpendicular to the main surface of the insulating resin layer 21 may have an area equivalent to the area of ​​a circle with a diameter of 5 to 50 μm or 5 to 10 μm.

[0061] The resist 4 can be selected from those used in the art. For example, a negative photosensitive film resist (Photec RY-5107UT, manufactured by Hitachi Chemical Co., Ltd.) can be used. The recesses in the circuit-forming resist can be formed by first forming a film of the circuit-forming resist using a commercially available roll laminator, then adhering a patterned phototool to the film, exposing the film using an exposure device, and then spray-developing the film with an aqueous sodium carbonate solution. A positive photosensitive resist may be used instead of the negative resist.

[0062] Wiring 5 is formed by electrolytic copper plating on the seed layer 3 (power supply layer 32) exposed in the wiring formation opening 40. At the same time, connecting portions 5a filling the openings 40a and 20 are formed on the seed layer 3 (power supply layer 32) exposed in the connecting portion formation openings 40a and 20.

[0063] The wiring 5 may include linear portions having a width of 1 to 10 μm, or 1 to 5 μm. According to the method of the present disclosure, wiring 5 including linear portions having a minute width, i.e., having a pattern with a small L / S, can be easily manufactured while suppressing the occurrence of defects. The thickness of the wiring 5 may be 1 to 10 μm, 3 to 10 μm, or 5 to 10 μm.

[0064] After the wiring 5 is formed, the resist 4 is stripped from the seed layer 3. The resist 4 can be easily removed by using a commercially available stripping liquid.

[0065] Next, the portions of the seed layer 3 that are not covered by the wiring 5 or the connecting portion 5a are removed. The seed layer 3 can be easily removed by using a commercially available etching solution. Specific examples of commercially available etching solutions include WLC-C2 manufactured by Mitsubishi Gas Chemical Company, Inc., which is suitable for removing the power supply layer 32, and WLC-T manufactured by Mitsubishi Gas Chemical Company, Inc., which is suitable for removing the adhesion layer 31. The modified region 21A may also be removed together with the seed layer 3.

[0066] The surface of the wiring 5 is treated with a surface treatment agent. The surface treatment agent can be selected from those commonly used as surface treatment agents for improving adhesion between copper wiring and resin, and may be, for example, a surface treatment agent containing an organic component. Treatment with the surface treatment agent containing an organic component forms a surface treatment agent layer 6 that contains the organic component and covers the surface of the wiring 5. Examples of commercially available surface treatment agents containing organic components include "GliCAP" (trade name) manufactured by Shikoku Chemicals Corporation, "Novabond" (trade name) manufactured by Atotech Japan, Inc., and "CZ8401" and "CZ-8402" manufactured by MEC Co., Ltd. Prior to treatment with the surface treatment agent, the surface of the wiring 5 may be finely etched.

[0067] After treating the surface of the wiring 5 with a surface treatment agent, a modified region 21B containing pores is formed on the surface of the first insulating resin layer 21 on the surface 21S side by a surface modification treatment method. This prevents the loss of the surface treatment agent layer 6 and improves adhesion between the first insulating resin layer 21 and the second insulating resin layer 22 formed thereon. The modified region 21B may contain multiple fine pores that communicate with the surface 21S. During the formation of the second insulating resin layer 22, a portion of the resin forming the insulating resin layer 22 penetrates into the pores in the modified region 21B, which is thought to improve adhesion between the adjacent layer 3 and the insulating resin layers 21 and 22. The formation of pores can be confirmed, for example, by observing a cross section of the insulating resin layer 21 using a scanning transmission electron microscope. A similar modified region may also be formed on the surface of the surface treatment agent layer 6.

[0068] The treatment method for forming the modified region 21B may be at least one treatment method selected from the group consisting of ultraviolet irradiation, electron beam irradiation, ozone water treatment, and corona discharge treatment, or ultraviolet irradiation. Ultraviolet irradiation has the advantage of not requiring vacuum equipment and not generating waste liquid. Ultraviolet irradiation may be ultraviolet irradiation using an incoherent light source. Incoherent light sources are advantageous in that they can efficiently irradiate a wide area of ​​the insulating resin layer 21 with ultraviolet light, compared to coherent light sources such as laser light sources. Examples of incoherent light sources include high-pressure mercury lamps, low-pressure mercury lamps, and excimer lamps. The incoherent light source may be a low-pressure mercury lamp or an excimer lamp, which have a strong activation effect.

[0069] The treatment for forming the modified region 21B (e.g., ultraviolet irradiation) can be performed, for example, in the air or in an oxygen atmosphere. In the treatment for forming the modified region 21B, the temperature of the insulating resin layer 21 may be 25 to 100°C, 40 to 100°C, or 60 to 100°C. When the temperature is higher, the modified region 21A can be formed more efficiently.

[0070] After the modified region 21B is formed, the contact angle of the surface 21S of the insulating resin layer 21 with pure water may be 40 degrees or less, or 10 degrees or less.

[0071] After the modified region 21B is formed, a second insulating resin layer 22 covering the wiring 5 is formed on the first insulating resin layer 21. The second insulating resin layer 22 has a pattern including openings 22a that expose the surface treatment agent layer 6 covering the connecting portions 5a formed in the openings 20 of the first insulating resin layer 21. The second insulating resin layer 22 can be formed using a photosensitive resin composition or a thermosetting resin composition that is the same as or different from the photosensitive resin composition or the thermosetting resin composition used to form the first insulating resin layer 21. The second and subsequent insulating resin layers can have a thickness similar to that of the first insulating resin layer.

[0072] After the second insulating resin layer 22 is formed, the surface treatment agent layer 6 exposed in the opening 22a is removed. By removing the surface treatment agent layer 6, the first connecting portion 5a is exposed in the opening 22a. The surface treatment agent layer 6 can be removed by, for example, desmearing, copper etching solution treatment, oxygen plasma treatment, argon plasma treatment, nitrogen plasma treatment, fluorine plasma treatment, ultraviolet treatment, or a combination of these. From the viewpoint of removal efficiency, the surface treatment agent layer 6 may be removed by a combination of oxygen plasma and a sodium persulfate aqueous solution.

[0073] By forming a second layer of wiring 5 provided on the second layer of insulating resin layer 22 and an additional third layer of insulating resin layer 23 stacked on the second layer of insulating resin layer 22, a multilayer wiring section 7 including three layers of insulating resin layers 21, 22, 23 and two layers of wiring 5 is formed.

[0074] The process of forming the multilayer wiring portion 7 includes, for example, forming a seed layer including one or more metal layers on the surface of the second insulating resin layer 22 and extending onto the first-layer connecting portion 5a exposed in the connecting portion forming opening 22a; forming a resist on the seed layer having a pattern including an opening for forming a wiring through which the seed layer is exposed; forming the second-layer wiring 5 on the seed layer exposed in the opening for forming a wiring in the resist by electrolytic copper plating; removing the resist; removing the portion of the seed layer that is not covered by the second-layer wiring 5 to expose the portion of the surface of the second insulating resin layer 22 that is not covered by the remaining seed layer; treating the surface of the second-layer wiring 5 with a surface treatment agent to form a surface treatment agent layer; treating the surface of the second insulating resin layer 22 with a treatment method involving surface modification to form a modified region including voids on the surface of the second insulating resin layer 22; and forming a third insulating resin layer 23 on the second insulating resin layer 22 to cover the second-layer wiring 5. The surface of the second insulating resin layer 22 may also be treated by at least one treatment method selected from the group consisting of ultraviolet irradiation, electron beam irradiation, ozone water treatment, and corona discharge treatment.

[0075] The seed layer formed on the second insulating resin layer 22 extends up to above the underlying connecting portions 5a exposed in the connecting portion forming openings 22a of the insulating resin layer 22. The resist pattern formed on the seed layer further includes connecting portion forming openings that expose the seed layer formed in the connecting portion forming openings 22a of the second insulating resin layer 22. The second-layer connecting portions 5a are formed by electrolytic copper plating on the seed layer exposed in the connecting portion forming openings, together with the second-layer wiring 5. The third insulating resin layer 23 has a pattern that includes openings that expose the second-layer connecting portions 5a.

[0076] The step of forming the multilayer wiring section 7 may further include repeating the same steps to form a fourth or subsequent insulating resin layer and a third or subsequent wiring layer.

[0077] The wiring structure 60 formed by the above method includes a substrate 1 and a multilayer wiring section 7 provided on the substrate 1. The multilayer wiring section 7 includes an insulating layer 2 composed of a plurality of insulating resin layers 21, 22, and 23, a seed layer 3 provided on the insulating resin layers 21 and 22, and wiring 5 (copper wiring) provided on the seed layer 3. A clear interface does not necessarily have to be formed between adjacent insulating resin layers, and the boundary between the two may not be clear.

[0078] A modified region including pores may be formed in the surface layer of the insulating resin layers 21, 22 on the seed layer 3 side. A portion of the metal forming the seed layer 3 may penetrate into these pores. In other words, a portion of the metal forming the seed layer 3 may be dispersed throughout the modified region. The penetration of the metal of the seed layer into the modified region improves the adhesion between the insulating resin layer and the seed layer. The dispersion of the metal in the modified region can be confirmed, for example, by analyzing a cross section of the insulating resin layer using energy dispersive X-ray fluorescence spectroscopy (EDX).

[0079] The wiring structure can be used as a wiring substrate for mounting electronic components such as semiconductor chips. For example, it may be a rewiring layer of a semiconductor chip. FIG. 7 is a cross-sectional view showing an example of a semiconductor package including a wiring structure. The semiconductor package 100 shown in FIG. 7 includes a wiring structure 60 and a semiconductor chip 8 connected to the wiring 5 of the wiring structure 60. Solder balls 80 for connection are provided on the back surface of the semiconductor chip 8. The wiring structure 60 has connection pads 70 provided on a multilayer wiring section 7. The solder balls 80 and the connection pads 70 are bonded to each other, thereby electrically connecting the semiconductor chip 8 to the wiring structure 60. An underfill 9 is also provided to fill the space between the semiconductor chip 8 and the wiring structure 60. [Example]

[0080] The present invention is not limited to the following examples.

[0081] Consideration I 1. Fabrication of wiring structure Example 1 (1) Formation of insulating resin layer The following materials were mixed to prepare a solution containing a photosensitive resin composition for forming an insulating resin layer. Photoreactive resin: Acid-modified cresol novolac epoxy acrylate containing a carboxyl group and an ethylenically unsaturated group (CCR-1219H, product name, manufactured by Nippon Kayaku Co., Ltd.) Photoinitiator: 2,4,6-trimethylbenzoyl-diphenyl-phosphine oxide (Darocur TPO, product name, manufactured by Ciba Japan), and ethanone, 1-[9-ethyl-6-(2-methylbenzoyl)-9H-carbazol-3-yl]-, 1-(o-acetyloxime) (Irgacure OXE-02, product name, manufactured by Ciba Japan) ·Thermosetting component: Biphenol-type epoxy resin (YX-4000, product name, manufactured by Japan Epoxy Resin Co., Ltd.) Fila: Silica filler (average particle size 50 nm) surface-treated with vinylsilane

[0082] The dispersion state of the silica filler in the solution was measured using a dynamic light scattering nanotrack particle size distribution analyzer "UPA-EX150" (manufactured by Nikkiso Co., Ltd.) and a laser diffraction scattering microtrack particle size distribution analyzer "MT-3100" (manufactured by Nikkiso Co., Ltd.) It was confirmed that the silica filler was dispersed so that the maximum particle size was 1 μm or less.

[0083] The solution of the photosensitive resin composition was uniformly applied to a 16 μm-thick polyethylene terephthalate film (G2-16, product name, manufactured by Teijin Ltd.) and the coating was dried by heating at 100° C. for about 10 minutes to form a photosensitive resin layer with a thickness of 15 μm.

[0084] A substrate (200 mm × 200 mm square, 1.5 mm thick) was prepared, consisting of an insulating substrate containing glass cloth and a copper layer (20 μm thick) on the surface of the insulating substrate. A photosensitive resin layer was placed on the surface of the copper layer of the substrate, and the entire assembly was pressed using a press-type vacuum laminator (MVLP-500, manufactured by Meiki Seisakusho). The photosensitive resin layer was laminated onto the substrate by pressing. The pressing conditions were a press hot plate temperature of 80°C, a vacuum time of 20 seconds, a laminating press time of 60 seconds, an air pressure of 4 kPa or less, and a pressure of 0.4 MPa.

[0085] (2) Formation of an insulating resin layer with an opening A phototool having a pattern including openings was attached to the photosensitive resin layer on the substrate. The photosensitive resin layer was then exposed to 30 mJ / cm using an i-line stepper exposure machine (product name: S6CK type exposure machine, lens: ASC3(Ck), manufactured by Surma Precision Co., Ltd.). 2 The insulating resin layer was exposed to light with an energy amount of 2000 mJ / cm using a mask exposure machine (EXM-1201 exposure machine, manufactured by Oak Manufacturing Co., Ltd.) for 45 seconds after spray development using a 1% by mass aqueous solution of sodium carbonate at 30°C. This formed an insulating resin layer having a pattern including openings that exposed the surface of the substrate. 2After that, the insulating resin layer was thermally cured by heating in a clean oven at 170°C for 1 hour.

[0086] (3) Formation of modified areas The entire surface of the thermally cured insulating resin layer was irradiated with ultraviolet light using an ultraviolet irradiation device (SSP-16, manufactured by Sen Special Light Sources Co., Ltd.) equipped with an ultraviolet lamp. The distance from the ultraviolet lamp to the surface of the insulating resin layer was 40 mm, and the treatment time for ultraviolet light irradiation was 30, 45, 60, 120, 180, 300, or 600 seconds. The ultraviolet light irradiation formed a modified region containing micropores on the surface of the insulating resin layer.

[0087] (4) Seed layer formation A 150 nm thick Ti layer was formed as an adhesion layer on the surface of the insulating resin layer, including the modified region, using a sputtering system (ULVAC, SIV-500). A 200 nm thick Cu layer was formed as a power supply layer on the Ti layer using a sputtering system (ULVAC, SIV-500). The seed layer consisting of the Ti layer and the Cu layer and the insulating resin layer were annealed by heating at 180°C for 1 hour.

[0088] (5) Wiring formation A resist film for circuit formation (Hitachi Chemical, RY-5107UT) covered with a protective film was vacuum laminated onto the seed layer using a vacuum laminator (Nippon-Morton, V-160). The lamination temperature was 110°C, the lamination time was 60 seconds, and the lamination pressure was 0.5 MPa. After leaving it for one day, the resist film was exposed using an i-line stepper exposure machine (product name: S6CK type exposure machine, lens: ASC3(Ck), manufactured by Surma Precision). The exposure dose was 140 mJ / cm. 2The focus was -15 μm. After leaving the resist film for one day after exposure, the protective film was peeled off from the resist film, and the resist film was developed using a spray developer (Mikasa, AD-3000). The developer was a 1.0% aqueous sodium carbonate solution, the development temperature was 30°C, and the spray pressure was 0.14 MPa. By developing the resist film, a resist having a pattern including openings that exposed the seed layer was formed. The resist had a pattern including portions corresponding to wiring with an L / S of 10 μm / 10 μm, 7 μm / 7 μm, 5 μm / 5 μm, 3 μm / 3 μm, or 2 μm / 2 μm.

[0089] The structure consisting of the substrate, insulating resin layer, seed layer, and resist was immersed in a 100 mL / L aqueous solution of cleaner (manufactured by Okuno Chemical Industries, product name: ICP Clean S-135) at 50°C for 1 minute, in pure water at 50°C for 1 minute, in pure water at 25°C for 1 minute, and in a 10% aqueous sulfuric acid solution at 25°C for 1 minute, in that order. After immersion, the seed layer was then plated in a plating bath at 25°C with a current density of 1.5 A / dm 2 Copper wiring was formed by electroplating for 10 minutes under the conditions. The plating bath was prepared by adding 0.25 mL of hydrochloric acid, 10 mL of Top Lucina GT-3 (manufactured by Okuno Pharmaceutical Industries, Ltd., product name), and 1 mL of Top Lucina GT-2 (manufactured by Okuno Pharmaceutical Industries, Ltd., product name) to 7.3 L of an aqueous solution containing 120 g / L copper sulfate pentahydrate and 220 g / L 96% sulfuric acid. The structure after wiring formation was immersed in pure water at 25°C for 5 minutes and then dried on a hot plate at 80°C for 5 minutes.

[0090] The resist was stripped using a spray developer (Mikasa AD-3000) using a 2.38% TMAH aqueous solution as the stripping solution, at a stripping temperature of 40°C and a spray pressure of 0.2 MPa.

[0091] The Cu layer exposed by the resist stripping was removed by immersion in an etching solution (aqueous solution containing WLC-C2 (manufactured by Mitsubishi Gas Chemical Co., Inc.) at a concentration of 500 mL / L) at 25°C for 2 minutes. The structure was then immersed in pure water at 25°C for 5 minutes. The Ti layer was then removed by immersion in an etching solution (WLC-C2 concentration: 900 mL / L, 28% ammonia water concentration: 28 mL / L) at 30°C prepared by mixing WLC-T (manufactured by Mitsubishi Gas Chemical Co., Inc.) and 28% ammonia water for 1 minute. The structure from which the seed layer had been removed was immersed in pure water at 25°C for 5 minutes and then dried on a hot plate at 80°C for 5 minutes. Through these operations, a wiring structure having an insulating resin layer and wiring provided on the insulating resin layer was obtained.

[0092] (Comparative Example 1-1) An insulating resin layer having a pattern including openings was formed on a substrate using the same procedure as in Example 1. The substrate and the insulating resin layer were immersed in 40 mL / L of a swirler (Cleaner Securigant 902, manufactured by Atotech) at 70°C for 5 minutes to swell them. The substrate and the insulating resin layer were then immersed in pure water for 1 minute. The substrate and the insulating resin layer were then immersed in 40 mL / L of a desmear solution (Compact CP, manufactured by Atotech) at 70°C to roughen the surface of the insulating resin layer. The immersion time (treatment time) was 5, 10, 15, or 20 minutes. The substrate and the insulating resin layer were then immersed in pure water at 25°C for 5 minutes and dried on a hot plate at 80°C for 5 minutes. A wiring structure having an insulating resin layer and wiring provided on the insulating resin layer was then obtained using the same procedure as in Example 1.

[0093] (Comparative Example 1-2) An insulating resin layer having a pattern including openings was formed on a substrate using the same procedure as in Example 1. The surface of the insulating resin layer was treated by oxygen plasma using a plasma device (March, AP-1000). The plasma output was 300 W and the oxygen flow rate was 100 sccm. The oxygen plasma treatment time was 1 minute, 3 minutes, 5 minutes, or 10 minutes. Thereafter, a wiring structure having an insulating resin layer and wiring provided on the insulating resin layer was obtained.

[0094] 2. Analysis of the modified area 2-1.Surface roughness The surface roughness Ra of the insulating resin layer after the modified region was formed was measured using a laser microscope (OLS4000, manufactured by Olympus Corporation). The surface roughness was classified according to the Ra value according to the following criteria. A: 70nm or less B: Over 70nm and 100nm or less C: Over 100 nm 8, 9, and 10 are graphs showing the results of measuring surface roughness. Fig. 8 shows the unevenness of the insulating resin layer surface after treatment by Example 1 (ultraviolet irradiation), where (a) corresponds to a treatment time of 30 seconds and (b) corresponds to a treatment time of 600 seconds. Fig. 9 shows the unevenness of the insulating resin layer surface after treatment by Comparative Example 1-1 (desmear treatment) for 10 minutes. Fig. 10 shows the unevenness of the insulating resin layer surface after treatment by Comparative Example 1-2 (oxygen plasma treatment), where (a) corresponds to a treatment time of 3 minutes and (b) corresponds to a treatment time of 5 minutes.

[0095] 2-2. Depth of modified area The cross section of the insulating resin layer after surface modification was observed using a scanning transmission electron microscope (STEM, Hitachi, Ltd., HD-2700). The area where the presence of micropores formed by surface modification was recognized was considered to be the modified area, and its depth (thickness from the surface of the insulating resin layer) was measured. The depth of the modified area was classified according to the following criteria. A: 50nm or more B: 10nm or more and less than 50nm C: Less than 10 nm

[0096] 3.Wiring formability The state of wiring formation was observed, and wiring formability was judged according to the following criteria based on the number of defects due to peeling from the insulating resin layer among 10 wires contained in each section with an L / S of 10 μm / 10 μm, 7 μm / 7 μm, 5 μm / 5 μm, 3 μm / 3 μm, or 2 μm / 2 μm. A:0 pieces B: 1~2 pieces C: 3 or more

[0097] Table 1 shows the evaluation results of surface roughness, thickness of modified region, and wiring formability. In Example 1, in which the modified region was formed while suppressing an increase in surface roughness by ultraviolet irradiation, it was confirmed that fine wiring was stably formed without defects. In Comparative Examples 1-1 and 1-2, the surface of the insulating resin layer was roughened, but the formation of a modified region containing voids was not substantially observed.

[0098] [Table 1]

[0099] Study II 1. Fabrication of wiring structure Example 2 (1) Formation of the first insulating resin layer The following materials were mixed to prepare a solution containing a photosensitive resin composition for forming an insulating resin layer. Photoreactive resin: Acid-modified cresol novolac epoxy acrylate containing a carboxyl group and an ethylenically unsaturated group (CCR-1219H, product name, manufactured by Nippon Kayaku Co., Ltd.) Photoinitiator: 2,4,6-trimethylbenzoyl-diphenyl-phosphine oxide (Darocur TPO, product name, manufactured by Ciba Japan), and ethanone, 1-[9-ethyl-6-(2-methylbenzoyl)-9H-carbazol-3-yl]-, 1-(o-acetyloxime) (Irgacure OXE-02, product name, manufactured by Ciba Japan) ·Thermosetting component: Biphenol-type epoxy resin (YX-4000, product name, manufactured by Japan Epoxy Resin Co., Ltd.) Fila: Silica filler (average particle size 50 nm) surface-treated with vinylsilane

[0100] The dispersion state of the silica filler in the solution was measured using a dynamic light scattering nanotrack particle size distribution analyzer "UPA-EX150" (manufactured by Nikkiso Co., Ltd.) and a laser diffraction scattering microtrack particle size distribution analyzer "MT-3100" (manufactured by Nikkiso Co., Ltd.) It was confirmed that the silica filler was dispersed so that the maximum particle size was 1 μm or less.

[0101] The solution of the photosensitive resin composition was uniformly applied to a 16 μm-thick polyethylene terephthalate film (G2-16, product name, manufactured by Teijin Ltd.) and the coating was dried by heating at 100° C. for about 10 minutes to form a photosensitive resin layer with a thickness of 15 μm.

[0102] A substrate (200 mm × 200 mm square, 1.5 mm thick) was prepared, consisting of an insulating substrate containing glass cloth and a copper layer (20 μm thick) on the surface of the insulating substrate. A photosensitive resin layer was placed on the surface of the copper layer of the substrate, and the entire assembly was pressed using a press-type vacuum laminator (MVLP-500, manufactured by Meiki Seisakusho). The photosensitive resin layer was laminated onto the substrate by pressing. The pressing conditions were a press hot plate temperature of 80°C, a vacuum time of 20 seconds, a laminating press time of 60 seconds, an air pressure of 4 kPa or less, and a pressure of 0.4 MPa.

[0103] (2) Forming the first insulating resin layer with an opening A phototool having a pattern including openings was attached to the photosensitive resin layer on the substrate. The photosensitive resin layer was then exposed to 30 mJ / cm using an i-line stepper exposure machine (product name: S6CK type exposure machine, lens: ASC3(Ck), manufactured by Surma Precision Co., Ltd.). 2 The first insulating resin layer was exposed to light at an energy of 2000 mJ / cm using a mask exposure machine (EXM-1201 exposure machine, manufactured by Oak Manufacturing Co., Ltd.) for 45 seconds after spray development using a 1% by mass aqueous solution of sodium carbonate at 30°C. 2 After that, the insulating resin layer was thermally cured by heating in a clean oven at 170°C for 1 hour.

[0104] (3) Formation of modified areas After thermal curing, the entire surface of the insulating resin layer was irradiated with ultraviolet light using an ultraviolet light irradiation device (SSP-16, manufactured by Sen Special Light Sources Co., Ltd.) equipped with an ultraviolet lamp. The distance from the ultraviolet lamp to the surface of the insulating resin layer was 40 mm, and the treatment time for ultraviolet light irradiation was 45 seconds. The ultraviolet light irradiation formed a modified region containing minute voids on the surface of the insulating resin layer.

[0105] (4) Seed layer formation A 150 nm thick Ti layer was formed as an adhesion layer on the surface of the insulating resin layer, including the modified region, using a sputtering system (ULVAC, SIV-500). A 200 nm thick Cu layer was formed as a power supply layer on the Ti layer using a sputtering system (ULVAC, SIV-500). The seed layer consisting of the Ti and Cu layers and the insulating resin layer were annealed by heating at 180°C for 1 hour.

[0106] (5) Wiring formation A resist film for circuit formation (Hitachi Chemical, RY-5107UT) covered with a protective film was vacuum laminated onto the seed layer using a vacuum laminator (Nippon-Morton, V-160). The lamination temperature was 110°C, the lamination time was 60 seconds, and the lamination pressure was 0.5 MPa. After leaving it for one day, the resist film was exposed using an i-line stepper exposure machine (product name: S6CK type exposure machine, lens: ASC3(Ck), manufactured by Surma Precision). The exposure dose was 140 mJ / cm. 2 The focus was -15 μm. After leaving the resist film for one day after exposure, the protective film was peeled off from the resist film, and the resist film was developed using a spray developer (Mikasa AD-3000). The developer was a 1.0% aqueous sodium carbonate solution, the development temperature was 30°C, and the spray pressure was 0.14 MPa. By developing the resist film, a resist having a pattern that exposed the seed layer and included openings corresponding to the wiring and connecting parts was formed.

[0107] The structure consisting of the substrate, insulating resin layer, seed layer, and resist was immersed in a 100 mL / L aqueous solution of cleaner (manufactured by Okuno Chemical Industries, product name: ICP Clean S-135) at 50°C for 1 minute, in pure water at 50°C for 1 minute, in pure water at 25°C for 1 minute, and in a 10% aqueous sulfuric acid solution at 25°C for 1 minute, in that order. After immersion, the seed layer was then plated in a plating bath at 25°C with a current density of 1.5 A / dm 2 Copper wiring and connections were formed by electroplating for 10 minutes under the conditions. The plating bath was prepared by adding 0.25 mL of hydrochloric acid, 10 mL of Top Lucina GT-3 (manufactured by Okuno Pharmaceutical Industries, Ltd., product name), and 1 mL of Top Lucina GT-2 (manufactured by Okuno Pharmaceutical Industries, Ltd., product name) to 7.3 L of an aqueous solution containing 120 g / L copper sulfate pentahydrate and 220 g / L 96% sulfuric acid. The structure after wiring formation was immersed in pure water at 25°C for 5 minutes and then dried on a hot plate at 80°C for 5 minutes.

[0108] The resist was stripped using a spray developer (Mikasa AD-3000) using a 2.38% TMAH aqueous solution as the stripping solution, at a stripping temperature of 40°C and a spray pressure of 0.2 MPa.

[0109] The Cu layer exposed by the resist stripping was removed by immersion in an etching solution (aqueous solution containing WLC-C2 (manufactured by Mitsubishi Gas Chemical Co., Inc.) at a concentration of 500 mL / L) at 25°C for 2 minutes. The structure was then immersed in pure water at 25°C for 5 minutes. The Ti layer was then removed by immersion in an etching solution (WLC-C2 concentration: 900 mL / L, 28% ammonia water concentration: 28 mL / L) at 30°C prepared by mixing WLC-T (manufactured by Mitsubishi Gas Chemical Co., Inc.) and 28% ammonia water for 1 minute. The structure from which the seed layer had been removed was immersed in pure water at 25°C for 5 minutes and then dried on a hot plate at 80°C for 5 minutes.

[0110] (6) Formation of a surface treatment layer The wiring and connecting portions formed by copper plating were spray-cleaned with a 5% hydrochloric acid solution at 25°C for 30 seconds at a water pressure of 0.2 MPa. Next, the wiring and connecting portions were washed with pure water at 25°C for 1 minute. After washing, the wiring and connecting portions were spray-treated with a surface treatment agent (CZ-8401, MEC Co., Ltd.) at 25°C for 1 minute at a water pressure of 0.2 MPa. Next, the wiring and connecting portions were sequentially washed with running pure water at 25°C for 1 minute, spray-treated with a 10% sulfuric acid solution at 25°C for 20 seconds at a water pressure of 0.1 MPa, and then washed with running pure water at 25°C for 1 minute. The structure was then dried on a hot plate at 100°C for 5 minutes. This formed a surface treatment agent layer covering the exposed portions of the wiring and connecting portions.

[0111] (7) Formation of modified area The entire surfaces of the insulating resin layer and the surface treatment agent layer were irradiated with ultraviolet light using an ultraviolet irradiation device (SSP-16, manufactured by Sen Special Light Sources Co., Ltd.) equipped with an ultraviolet lamp. The distance from the ultraviolet lamp to the surface of the insulating resin layer was 40 mm, and the treatment time for ultraviolet light irradiation was 30 seconds, 45 seconds, 60 seconds, 90 seconds, 120 seconds, 180 seconds, 300 seconds, or 600 seconds. The ultraviolet light irradiation formed modified regions containing micropores on the surface layers of the insulating resin layer and the surface treatment agent layer.

[0112] (8) Formation of the second insulating resin layer A second insulating resin layer, in which the surface treatment agent layer on the connection portion is exposed, was formed on the first insulating resin layer using the same photosensitive resin composition as that used to form the first insulating resin layer. (9) Removal of the surface treatment layer To remove the surface treatment agent layer exposed in the opening, the surface treatment agent layer was first subjected to oxygen plasma treatment for 5 minutes using a plasma asher (March, AP-1000) at an oxygen flow rate of 1000 sccm and an output of 500 W. Next, the surface treatment agent layer was subjected to copper etching treatment with a 10 g / L aqueous solution of ammonium persulfate for 2 minutes, followed by running pure water at 25°C for 1 minute. The exposed connecting portion was then dried on a hot plate at 100°C for 5 minutes. Through these operations, a wiring structure for evaluation was obtained, which had two insulating resin layers, wiring, and a connecting portion.

[0113] (Comparative Example 2-1) A first insulating resin layer having a pattern including openings was formed on a substrate using the same procedure as in Example 2. The substrate and insulating resin layer were immersed in 40 mL / L of a swirler (Cleaner Securigant 902, manufactured by Atotech) at 70°C for 5 minutes to swell the insulating resin layer. The substrate and insulating resin layer were then immersed in pure water for 1 minute. The substrate and insulating resin layer were then immersed in 40 mL / L of a desmear solution (Compact CP, manufactured by Atotech) at 70°C to roughen the surface of the insulating resin layer. The immersion time (treatment time) was 5, 10, 15, or 20 minutes. The substrate and insulating resin layer were then immersed in pure water at 25°C for 5 minutes and dried on a hot plate at 80°C for 5 minutes. A seed layer, wiring, and a surface treatment agent layer were then formed in the same manner as in Example 2.

[0114] The structure on which the surface treatment agent layer was formed was immersed in 40 mL / L of a swirler (Cleaner Securigant 902, manufactured by Atotech) at 70°C for 5 minutes to swell the first insulating resin layer. The structure was then immersed in pure water for 1 minute. The structure was then immersed in 40 mL / L of a desmear solution (Compact CP, manufactured by Atotech) at 70°C to roughen the surface of the first insulating resin layer. The immersion times were the same as in the first treatment with the desmear solution: 5 minutes, 10 minutes, 15 minutes, and 20 minutes. The structure was then immersed in pure water for 1 minute and dried on a hot plate at 80°C for 5 minutes. A structure with an immersion time of 0 minutes, i.e., no roughening treatment with the desmear solution, was also prepared and subjected to the subsequent process of forming the second insulating resin layer.

[0115] Then, using the same photosensitive resin composition as that used to form the first insulating resin layer, a second insulating resin layer was formed on the first insulating resin layer, exposing the surface treatment agent layer on the connection portion. The surface treatment material layer exposed in the opening was removed in the same manner as in Example 2. By the above operations, a wiring structure for evaluation was obtained, which had two insulating resin layers, wiring, and a connection portion.

[0116] 2. Evaluation The cross section of the fabricated wiring structure was observed using a scanning electron microscope (Regulus-8230, manufactured by Hitachi High-Technologies Corporation) to check for the presence or absence of peeling between the first and second insulating resin layers, and the presence or absence of a surface treatment agent layer. As shown in Table 2, in the wiring structure of Example 2, the surface treatment agent layer that improves the adhesion of the wiring was maintained, and no peeling between the insulating resin layers was observed. In the structure of Example 2 in which the surface treatment agent layer was maintained, no peeling between the wiring and the insulating resin layer was observed. As shown in Table 3, in the case of Comparative Example 2-1, which was subjected to a desmear treatment, the surface treatment agent layer that improved the adhesion of the wiring disappeared.

[0117] [Table 2]

[0118] [Table 3] [Explanation of symbols]

[0119] 1...base material, 3...seed layer, 4...resist, 5...wiring (copper wiring), 5a...connecting portion, 6...surface treatment agent layer, 7...multilayer wiring portion, 8...semiconductor chip, 11...insulating substrate, 12...conductive layer, 20, 22a, 40, 40a...opening, 21, 22, 23...insulating resin layer, 21A, 21B...modified region, 21S...surface of insulating resin layer, 31...adhesion layer, 32...power supply layer, 60...wiring structure, 100...semiconductor package

Claims

1. A method for manufacturing a wiring structure, comprising a step of forming wiring on an insulating resin layer, The step of forming the wiring includes: treating the surface of the insulating resin layer by a treatment method involving surface modification to form a modified region including pores on the surface layer of the insulating resin layer; forming a seed layer including one or more metal layers on the surface of the insulating resin layer by sputtering so that a part of the metal forming the seed layer enters the pores; forming a resist having a pattern including an opening for forming wiring on the seed layer, through which the seed layer is exposed; forming the wiring on the seed layer exposed in the opening by electrolytic copper plating; removing the resist; removing a portion of the seed layer that is not covered by the wiring; in this order, the modified region is formed to a depth of 50 nm or more from the surface of the insulating resin layer. method.

2. the seed layer includes an adhesion layer in contact with the insulating resin layer and a power supply layer formed on the adhesion layer, the adhesion layer is a metal layer containing titanium, chromium, tungsten, nickel, or a combination thereof; The power supply layer is a metal layer containing copper. The method of claim 1.

3. The method according to claim 1 or 2, wherein the surface of the insulating resin layer including the modified region has a surface roughness Ra of 70 nm or less.

4. the method further comprises a step of forming, on a base material, the insulating resin layer having a pattern including openings for forming connecting portions through which the base material is exposed; the seed layer is formed to extend onto a surface of the substrate exposed in the opening for forming a connection portion; the resist pattern further includes openings for forming connecting portions, through which the seed layer formed in the openings for forming connecting portions of the insulating resin layer is exposed; a connecting portion filling the opening for forming the connecting portion together with the wiring is formed by electrolytic copper plating, and then a portion of the seed layer not covered by the wiring or the connecting portion is removed. The method according to any one of claims 1 to 3.

5. the method further comprises a step of forming two or more additional insulating resin layers stacked on the first insulating resin layer formed on the base material, and additional wiring provided between adjacent additional insulating resin layers, thereby forming a multilayer wiring section including three or more insulating resin layers and two or more wiring layers; The step of forming the multilayer wiring portion includes: forming an additional insulating resin layer on the first or additional insulating resin layer, the additional insulating resin layer having a pattern including openings for forming connecting portions, through which connecting portions of a lower layer formed in the openings of the first or additional insulating resin layer are exposed; treating a surface of the additional insulating resin layer by a treatment method involving surface modification to form a modified region including pores on the surface layer of the additional insulating resin layer; forming a seed layer including one or more metal layers on the surface of the additional insulating resin layer and extending onto the lower layer connecting portion exposed in the opening for forming the connecting portion by sputtering so that a part of the metal forming the seed layer enters the hole; forming a resist having a pattern including an opening for forming a wiring on the seed layer, the opening exposing the seed layer, the resist further including an opening for forming a connecting portion, the opening exposing the seed layer formed in the opening for forming a connecting portion of the additional insulating resin layer; forming additional wiring and connecting portions by electrolytic copper plating on the seed layer exposed in the openings of the resist for forming wiring or connecting portions; removing the resist; removing portions of the seed layer that are not covered by the additional wiring or the connecting portion; in this order, The method of claim 4.

6. an insulating resin layer; a seed layer including one or more metal layers provided on the insulating resin layer; a copper wiring provided on the seed layer; Equipped with a modified region including voids is formed in a surface layer of the insulating resin layer on the seed layer side, the modified region having a depth of 50 nm or more, and a part of the metal forming the seed layer entering the voids; Wiring structure.

7. the seed layer includes an adhesion layer in contact with the insulating resin layer and a power supply layer formed on the adhesion layer, the adhesion layer is a metal layer containing titanium, chromium, tungsten, nickel, or a combination thereof; The power supply layer is a metal layer containing copper. The wiring structure according to claim 6 .

8. 8. The wiring structure according to claim 6, wherein the wiring includes a linear portion having a width of 1 to 10 μm.

9. The wiring structure according to any one of claims 6 to 8, a semiconductor chip connected to the wiring of the wiring structure; A semiconductor package comprising:

10. The method according to any one of claims 1 to 5, wherein the treatment method is ultraviolet irradiation.

11. The method according to claim 10 , wherein the ultraviolet irradiation is ultraviolet irradiation irradiated by an incoherent light source.

12. The method according to any one of claims 1 to 5, wherein the wiring includes a linear portion having a width of 1 to 10 µm.

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