LAMINATE STRUCTURE AND METHOD FOR MANUFACTURING LAMINATE STRUCTURE

Abstract

To provide a method for manufacturing a laminated structure in which a Si film is laminated on a gallium oxide-based semiconductor substrate, and to provide a method for manufacturing a laminated structure in which the Si film can be accurately separated from the Si substrate by smart cutting, and a laminated structure manufactured by the method.SOLUTION: In one embodiment, a method for manufacturing a laminated structure 1 comprising an ion implantation process for ion implanting hydrogen ions at a predetermined depth from one main surface 121 of a Si substrate 12 to form a planar ion implantation region 122; a substrate bonding process for bonding one main surface 121 of the Si substrate 12 and one main surface 101 of a gallium oxide semiconductor substrate 10 having a (001) plane as a main surface; and a Si film formation process in which hydrogen embrittlement is caused in the ion implantation area 122 by applying heat treatment at a temperature of 350°C or higher and 450°C or lower to split the Si substrate 12 and leave a Si film 11 on one main surface 101 of the gallium oxide-based semiconductor substrate 10, is provided.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a laminated structure and a method for manufacturing the laminated structure. [Background technology]

[0002] Conventionally, a vertical power transistor has been known in which a Si substrate directly bonded to a Ga2O3 substrate is thinned, and the Ga2O3 substrate and the thinned Si substrate are used as the drift layer and channel layer, respectively (see Patent Document 1). According to the power transistor of Patent Document 1, the drift layer is thinned by using gallium oxide, which has a high dielectric breakdown field strength, and power loss in the on-state and during switching can be reduced. Furthermore, by using Si for the channel layer, the channel resistance can be reduced compared to when gallium oxide is used for the channel layer, and the on-resistance of the device can be reduced.

[0003] Generally, when growing an epitaxial film on a heterogeneous substrate, crystal defects occur in the epitaxial film due to the difference in crystal structure between the substrate and the epitaxial film. In particular, since the crystal structures of Ga2O3 and Si are significantly different, it is extremely difficult to even obtain a single-crystal film when growing a Si film epitaxially on a gallium oxide substrate.

[0004] According to the technology described in Patent Document 1, in which a Si film is formed by thinning a Si substrate directly bonded to a Ga2O3 substrate, there is no risk of crystal defects occurring in the Si film due to the difference in the crystal structures of Ga2O3 and Si, and the stacked Ga2O3 substrate and Si film can be applied to power devices that require high reliability. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent No. 6873516 Summary of the Invention [Problem to be solved by the invention]

[0006] Patent Document 1 lists Smart Cut (registered trademark) as one method for thinning a Si substrate bonded to a gallium oxide substrate. In Smart Cut, hydrogen ions are implanted and heat is applied to cause hydrogen embrittlement, splitting the substrate at the ion-implanted surface. In Smart Cut, heating to a certain temperature is required to split the substrate, but the higher the temperature, the more easily hydrogen ions diffuse and migrate from the ion-implanted surface, which may reduce the precision of the split.

[0007] An object of the present invention is to provide a method for manufacturing a laminated structure in which a Si film is stacked on a gallium oxide-based semiconductor substrate, which method is capable of separating the Si film from the Si substrate with high accuracy by smart cut, and a laminated structure manufactured by the manufacturing method. [Means for solving the problem]

[0008] In order to achieve the above object, one aspect of the present invention provides the following methods for producing a laminated structure (1) and (2), and a laminated structure (3).

[0009] [1] A method for manufacturing a stacked structure, comprising: an ion implantation step of implanting hydrogen ions into one main surface of a Si substrate at a predetermined depth to form a planar ion implanted region; a substrate bonding step of bonding the one main surface of the Si substrate to one main surface of a gallium oxide based semiconductor substrate having a (001) plane as a main surface; and a Si film formation step of performing heat treatment at a temperature of 350°C or higher and 450°C or lower to cause hydrogen embrittlement in the ion implanted region, thereby dividing the Si substrate and leaving a Si film on the one main surface of the gallium oxide based semiconductor substrate. [2] A method for manufacturing a stacked structure according to the above [1], comprising a recovery step of recovering damage to the Si film by performing a heat treatment at a temperature of 450°C or higher and 630°C or lower after the Si film formation step. [3] A laminated structure comprising a gallium oxide based semiconductor substrate having a (001) plane as a principal surface, and a Si film laminated on the gallium oxide based semiconductor substrate, wherein the full width at half maximum of an X-ray rocking curve of the (111) plane of the Si film is 150 arcsec or less. [Effects of the Invention]

[0010] According to the present invention, it is possible to provide a method for manufacturing a laminated structure in which a Si film is laminated on a gallium oxide-based semiconductor substrate, which method can accurately separate the Si film from the Si substrate by smart cut, and a laminated structure manufactured by the manufacturing method. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a vertical cross-sectional view of a laminated structure according to an embodiment of the present invention. [Figure 2] 2(a) to 2(c) are vertical cross-sectional views showing the manufacturing process of a laminated structure using Smart Cut according to an embodiment of the present invention. [Figure 3] FIG. 3 is an example of a transmission electron microscope (TEM) image of a cross section of the Si substrate immediately after the ion implantation step shown in FIG. 2(a). [Figure 4] FIG. 4 is a graph showing the relationship between the temperature of the heat treatment in the recovery step and the half-width of the X-ray rocking curve of the (111) plane of the Si film. [Figure 5] FIG. 5 is an atomic force microscope (AFM) observation image of the surface (peeled surface) of the Si film immediately after the Si film formation step (immediately before the recovery step). [Figure 6] FIG. 6 is a vertical cross-sectional view of a vertical power transistor, which is an example of a semiconductor device formed using the stacked structure according to the embodiment of the present invention. [Figure 7] FIG. 7(a) shows the forward and reverse current-voltage characteristics (logarithmic display) of the sample according to the example, and FIG. 7(b) shows the forward current-voltage characteristics (linear display). DETAILED DESCRIPTION OF THE INVENTION

[0012] [Embodiment] (Configuration of the laminated structure) FIG. 1 is a vertical cross-sectional view of a laminated structure 1 according to an embodiment of the present invention. The laminated structure 1 includes a gallium oxide-based semiconductor substrate 10 having a (001) plane as a main surface, and a Si film 11 laminated on the gallium oxide-based semiconductor substrate 10.

[0013] The gallium oxide-based semiconductor substrate 10 is made of a single crystal of a gallium oxide-based semiconductor. Here, the gallium oxide-based semiconductor refers to Ga2O3, or Ga2O3 to which elements such as Al and In are added. For example, the gallium oxide-based semiconductor is (Ga x Al y In (1-x-y) )2O3 (0 < x ≦ 1, 0 ≦ y ≦ 1, 0 < x + y ≦ 1). When Al is added to Ga2O3, the bandgap widens, and when In is added, the bandgap narrows.

[0014] The single crystal of the gallium oxide-based semiconductor constituting the gallium oxide-based semiconductor substrate 10 has a β-type crystal structure. Further, the gallium oxide-based semiconductor substrate 10 may contain dopants such as Si and Sn. The gallium oxide-based semiconductor substrate 10 is formed, for example, by slicing a bulk crystal of a Ga2O3-based single crystal grown by a melt growth method such as the FZ (Floating Zone) method or the EFG (Edge Defined Film Fed Growth) method and polishing the surface.

[0015] Note that the gallium oxide-based semiconductor substrate 10 may be a single substrate, or may be composed of a base substrate made of a single crystal of a gallium oxide-based semiconductor and an epitaxial film made of a single crystal of a gallium oxide-based semiconductor provided thereon. When the gallium oxide-based semiconductor substrate 10 is composed of a base substrate and an epitaxial film, the surface of the epitaxial film becomes a bonding surface 101 described later.

[0016] The Si film 11 is a film made of single-crystal Si and is formed by Smart Cut, which separates a thin film from a substrate. Smart Cut film formation avoids problems such as the occurrence of crystal defects due to differences in the crystal structure between the substrate and the epitaxial film in epitaxial growth, and uneven film thickness due to variations in the amount of polishing in the substrate when thinning the film by polishing it. This allows for the production of a thin film with few crystal defects and high film thickness uniformity. Smart Cut can produce a thin film with a uniform thickness of less than 1 μm. For example, it is not possible to obtain a thin film with a uniform thickness of less than 1 μm by grinding and polishing a substrate with a thickness of several hundred μm.

[0017] Furthermore, by setting the heat treatment temperature in the recovery step (described later) for recovering damage to the Si film 11 after separation from the substrate to 450° C. or higher and 630° C. or lower, the damage can be more effectively recovered and the full width at half maximum of the X-ray rocking curve of the (111) plane of the Si film 11 can be set to 150 arcsec or less. When the Si film 11 has high crystallinity such that the full width at half maximum of the X-ray rocking curve of the (111) plane is 150 arcsec or less, it is possible to manufacture a low-loss semiconductor device, for example, a low-loss power transistor in which degradation of channel mobility is suppressed.

[0018] (Method of manufacturing laminated structure) 2(a) to 2(c) are vertical cross-sectional views showing the manufacturing process of the laminated structure 1 using Smart Cut according to an embodiment of the present invention.

[0019] First, a gallium oxide based semiconductor substrate 10 and a Si substrate 12 are prepared, and one of the main surfaces (hereinafter referred to as bonding surfaces) 101, 121 of each substrate is subjected to a planarization process such as chemical mechanical polishing (CMP). The gallium oxide based semiconductor substrate 10 and the Si substrate 12 typically have a diameter of 4 to 8 inches, but it is believed that the laminated structure 1 can be manufactured even if the substrate has a larger diameter. Furthermore, the gallium oxide based semiconductor substrate 10 and the Si substrate 12 each have a thickness of, for example, 100 to 600 μm.

[0020] Next, as shown in FIG. 2(a), hydrogen ions are implanted into the Si substrate 12 at a predetermined depth from the bonding surface 121 to form a planar ion implanted region 122 (hereinafter referred to as an ion implantation step).

[0021] As will be described later, the Si substrate 12 is divided using the ion implantation region 122 as a dividing surface, and the film separated from the Si substrate 12 becomes the Si film 11 of the stacked structure 1. Therefore, the depth of the ion implantation region 122 from the bonding surface 121 of the Si substrate 12 is determined according to the desired thickness of the Si film 11.

[0022] The dose of hydrogen ions to be implanted is, for example, 2×10 16 ~8×10 16 / cm 2 The energy of the ion implantation is determined by the depth of the ion implantation region 122 from the junction surface 121. For example, when the ion implantation region 122 is formed at a depth of about 950 nm from the junction surface 121, hydrogen ions are implanted with an energy of about 110 keV.

[0023] Next, as shown in FIG. 2(b), the bonding surface 101 of the gallium oxide semiconductor substrate 10 and the bonding surface 121 of the Si substrate 12 are brought into contact with each other in a vacuum by a surface activated bonding method (hereinafter referred to as a substrate bonding step). -6 In an ultra-high vacuum chamber under a pressure of about 1 Pa, an Ar atomic beam accelerated with an energy of 1.5 keV is irradiated to remove the outermost surfaces of bonding surfaces 101 and 121, and the exposed newly formed surfaces are brought into contact with each other, thereby bonding bonding surfaces 101 and 121. After bonding bonding surfaces 101 and 121, gallium oxide based semiconductor substrate 10 and Si substrate 12 may be fixed with a jig or the like to prevent peeling.

[0024] Next, as shown in FIG. 2( c), the gallium oxide based semiconductor substrate 10 and the Si substrate 12, which have been bonded together through the substrate bonding step and whose bonding surfaces 101 and 121 have been bonded together, are subjected to a heat treatment to cause hydrogen embrittlement in the ion implantation region 122 of the Si substrate 12, thereby dividing the Si substrate 12 and leaving the Si film 11 on the bonding surface 101 of the gallium oxide based semiconductor substrate 10 (hereinafter referred to as the Si film formation step).

[0025] The temperature of the heat treatment in the Si film formation step is in the range of 350° C. to 450° C., and preferably in the range of 350° C. to 400° C. The heat treatment in the Si film formation step is carried out, for example, in an N2 or Ar atmosphere for 1 to 10 minutes. The heat treatment may be carried out in a vacuum chamber under reduced pressure, or in a furnace other than a vacuum chamber.

[0026] Fig. 3 is an example of a transmission electron microscope (TEM) image of the cross section of the Si substrate 12 immediately after the ion implantation step shown in Fig. 2(a). In the example shown in Fig. 3, an ion-implanted region 122 having a thickness of approximately 170 nm is formed at a position approximately 950 nm deep from the bonding surface 121 of the Si substrate 12. The Si substrate 12 shown in Fig. 3 is a p-type Si substrate manufactured by the CZ (Czochralski) method, with a diameter of 100 mm, a thickness of 510 to 540 µm, and a resistivity of 0.007 to 0.009 Ωm. The ion-implanted region 122 is formed by implanting 5 × 10 16 cm -2 The hydrogen ions are implanted to a dose of 1000 .mu.m.

[0027] 2(c) , by setting the temperature of the heat treatment to 350°C or higher and 450°C or lower, hydrogen embrittlement is sufficiently caused in the ion implantation region 122, and the diffusion and migration of hydrogen ions from the ion implantation region 122 is suppressed, thereby suppressing the spread of the region where hydrogen embrittlement occurs, and the Si substrate 12 can be divided accurately. Furthermore, by setting the temperature of the heat treatment in the Si film formation step to 400°C or lower, the diffusion and migration of Si from the ion implantation region 122 can be more effectively suppressed. Furthermore, by keeping the temperature of the heat treatment in the Si film formation step low, the cost and energy required to manufacture the stacked structure 1 can be reduced.

[0028] The reason why the Si substrate 12 can be divided by heat treatment at a relatively low temperature of 450°C or less in the Si film formation process is thought to be because there is a particularly large difference in the linear expansion coefficient between the

[0010] direction of the bonding surface 101, which is the (001) plane of the gallium oxide based semiconductor substrate 10, and the bonding surface 121 of the Si substrate 12 (for example, the linear expansion coefficients in the

[0010] direction of a Ga2O3 substrate, which is a typical example of a gallium oxide based semiconductor substrate 10, and that of the Si substrate 12 are 7.8 and 2.6, respectively), which generates a large stress near the bonding surface on the Si substrate 12 side. Note that, because the crystalline system of Si is cubic, the Si substrate 12 can be divided by heat treatment at the above temperature, regardless of the plane orientation of the bonding surface 121 of the Si substrate 12.

[0029] After the Si film forming step, another heat treatment is carried out to repair the damage to the Si film 11 that has occurred in the ion implantation step and the Si film forming step (hereinafter referred to as a repair step).

[0030] 4 is a graph showing the relationship between the temperature of the heat treatment in the recovery step and the half-width of the X-ray rocking curve of the (111) plane of the Si film 11. When the Si film 11 is used as a channel layer of a semiconductor device, it is preferable that the Si film 11 has crystallinity such that the half-width of the X-ray rocking curve of the (111) plane is approximately 150 arcsec or less.

[0031] 4, when the heat treatment temperature in the recovery step is approximately 450°C or higher and 630°C or lower, the half-width of the X-ray rocking curve of the (111) plane of the Si film 11 is approximately 150 arcsec or lower. When the heat treatment temperature in the recovery step is approximately 490°C or higher and 620°C or lower, the half-width of the X-ray rocking curve of the (111) plane of the Si film 11 is approximately 140 arcsec or lower. When the heat treatment temperature is approximately 530°C or higher and 610°C or lower, the half-width of the X-ray rocking curve of the (111) plane of the Si film 11 is approximately 130 arcsec or lower, further improving the crystallinity of the Si film 11. Therefore, the heat treatment temperature in the recovery step is preferably in the range of 450°C or higher and 630°C or lower, more preferably in the range of 490°C or higher and 620°C or lower, and even more preferably in the range of 530°C or higher and 610°C or lower. The heat treatment in the recovery step is carried out, for example, in an N2 or Ar atmosphere for 1 to 10 minutes. The heat treatment may be carried out in a vacuum chamber under reduced pressure, or in a furnace other than a vacuum chamber.

[0032] After the recovery step, the surface of the Si film 11 may be subjected to a polishing process such as chemical mechanical polishing (CMP) to be flattened.

[0033] 5 is an atomic force microscope (AFM) observation image of the surface (peeled surface) of the Si film 11 immediately after the Si film formation process (immediately before the recovery process). The average surface roughness (Ra) calculated from the measurement data related to the observation image of FIG. 5 is 4.3 nm, and the root mean square roughness (RMS) is 6 nm, which are sufficiently small, confirming that the Si substrate 12 was accurately divided in the Si film formation process. For example, in a manufacturing process of a semiconductor device using the stacked structure 1, if the Ra and RMS of the surface of the Si film 11 are both 10 nm or less, photolithography can be performed appropriately.

[0034] Thereafter, the Si substrate 12 separated from the gallium oxide-based semiconductor substrate 10 is used as the Si substrate 12 shown in FIG. 2(a), and by repeating the above steps, it is possible to form a plurality of Si films 11 of the stacked structures 1 from one Si substrate 12.

[0035] (Example of application of laminated structures) 6 is a vertical cross-sectional view of a vertical power transistor 2, which is an example of a semiconductor device formed using the stacked structure 1. The vertical power transistor 2 is a vertical MOSFET having a trench gate structure, and uses the stacked structure 1 as a semiconductor layer.

[0036] The gallium oxide based semiconductor substrate 10 of the laminated structure 1 is n + The Si film 11 includes an n-type drain layer 10a and a drift layer 10b. + The semiconductor substrate 11 includes a p-type source region 11a, a p-type Si bulk layer 11b, and a p-type block layer 11c.

[0037] In addition, the laminated structure 1 has n + A trench 21 is provided from the n-type source region 11a side to the drift layer 10b, a trench gate electrode 22 and a gate oxide film 23 are provided in the trench 21, a current isolation layer 24 into which nitrogen ions are implanted is provided below the trench 21, and a covering insulating film 25 is provided on the trench 21. + type source region 11a and n + A source electrode 26 and a drain electrode 27 are connected to the source and drain layers 10a, respectively.

[0038] The Si film 11 formed by smart cut does not contain crystal defects resulting from the difference in crystal structure between the gallium oxide based semiconductor substrate 10 and the Si film 11, and therefore the vertical power transistor 2 has high reliability.

[0039] (Effects of the embodiment) According to the above-described embodiment of the present invention, when the Si substrate 12 bonded to the gallium oxide based semiconductor substrate 10 is divided by Smart Cut, the Si substrate 12 is divided by heat treatment at a relatively low temperature of 450° C. or less, so that the diffusion and migration of hydrogen ions from the ion-implanted surface can be suppressed and the Si film 11 can be separated from the Si substrate 12 with high accuracy.

[0040] Furthermore, by performing a heat treatment at a temperature of 450° C. or higher and 630° C. or lower to repair the damage to the Si film 11 caused by smart cutting, it is possible to obtain a Si film 11 having particularly excellent crystallinity. [Example]

[0041] In order to confirm the rectification of the junction of the laminate of the gallium oxide based semiconductor substrate 10 and the Si film 11 according to the above embodiment, an n-type Ga2O3 substrate and a p-type Si substrate were directly bonded together, and the electrical characteristics of the junction were evaluated. The method and results are described below.

[0042] First, an n-type Ga2O3 substrate and a p-type Si substrate were prepared for evaluation in this example. Here, the Ga2O3 substrate was a rectangular substrate of 10 mm × 15 mm with the (001) plane as the main surface, and had a thickness of 1 to 5 × 10 17 cm -3 The Si substrate is a 22 mm x 22 mm square substrate manufactured using the CZ method, and has a resistivity of about 0.08 to 0.12 Ωcm and a thickness of about 295 to 345 μm.

[0043] Next, a mesa pattern was formed on the surface of the Si substrate. This mesa pattern consisted of square truncated pyramids, each with a square top surface of 2.2 mm × 2.2 mm and a height of approximately 10 μm, arranged in a matrix at 2.2 mm intervals.

[0044] Next, the surface of the Si substrate on which the mesa pattern was formed was directly bonded to the Ga2O3 substrate by surface activated bonding. -6 In an ultra-high vacuum chamber under a pressure of about 100 Pa, an Ar atomic beam accelerated at an energy of 1.5 keV was irradiated to remove the top surfaces of the bonding surfaces of the Ga2O3 substrate and the Si substrate (the surfaces on which the mesa pattern was formed), and the exposed newly formed surfaces were brought into contact with each other, thereby bonding the bonding surfaces together.

[0045] Next, an Al electrode that makes ohmic contact with the Si substrate was formed on the surface of the Si substrate opposite the Ga2O3 substrate, and a Ti / Au electrode that makes ohmic contact with the Ga2O3 substrate was formed on the surface of the Ga2O3 substrate opposite the Si substrate.

[0046] Next, a voltage was applied between the Al electrode and the Ti / Au electrode, and the current-voltage characteristics were measured.

[0047] Figure 7(a) shows the measured forward and reverse current-voltage characteristics (logarithmic display), and Figure 7(b) shows the measured forward current-voltage characteristics (linear display). The current-voltage characteristics shown in Figures 7(a) and (b) confirm that rectification was achieved.

[0048] Although the embodiments and examples of the present invention have been described above, the present invention is not limited to the above embodiments and examples, and various modifications are possible within the scope of the gist of the invention. Furthermore, the components of the above embodiments and examples can be combined in any manner without departing from the scope of the gist of the invention.

[0049] Furthermore, the above-described embodiments and examples do not limit the scope of the invention as claimed, and it should be noted that not all of the combinations of features described in the embodiments and examples are necessarily essential to the means for solving the problems of the invention. [Explanation of symbols]

[0050] 1...Laminated structure, 10...Gallium oxide based semiconductor substrate, 101...Bonding surface, 11...Si film, 12...Si substrate, 121...Bonding surface, 122...Ion implantation region

Claims

1. an ion implantation step of implanting hydrogen ions into one main surface of the Si substrate at a predetermined depth to form a planar ion implantation region; a substrate bonding step of bonding the one main surface of the Si substrate to one main surface of a gallium oxide based semiconductor substrate having a (001) plane as a main surface; a Si film forming step of performing a heat treatment at a temperature of 350° C. or higher and 450° C. or lower to cause hydrogen embrittlement in the ion implantation region, thereby dividing the Si substrate and leaving a Si film on the one main surface of the gallium oxide based semiconductor substrate; A method for manufacturing a laminated structure, comprising:

2. a recovery step of recovering damage to the Si film by performing a heat treatment at a temperature of 450° C. or higher and 630° C. or lower after the Si film forming step; A method for producing the laminated structure according to claim 1.

3. a gallium oxide-based semiconductor substrate having a (001) plane as a principal surface; a Si film laminated on the gallium oxide based semiconductor substrate; Equipped with the full width at half maximum of the X-ray rocking curve of the (111) plane of the Si film is 150 arcsec or less; Laminated structure.

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