Terminal structure, its manufacturing method and power device

Abstract

The present application provides a terminal structure, a manufacturing method and a power device, comprising: a first epitaxial layer; a buried layer located on one side of the first epitaxial layer; a first doping region penetrating the buried layer, the first doping region having a doping type opposite to that of the buried layer; a second epitaxial layer located on a side of the buried layer away from the first epitaxial layer, the second epitaxial layer having a main junction extension region and a field limiting ring in the second epitaxial layer; and an oxide layer located on a side of the second epitaxial layer away from the buried layer, the doping types of both the second epitaxial layer and the first epitaxial layer being opposite to that of the buried layer, the field limiting ring being located between the main junction extension region and the first doping region in a first direction, the first direction being perpendicular to a direction from the first epitaxial layer to the second epitaxial layer. The terminal structure, manufacturing method and power device provided by the technical solution of the present invention can improve the voltage resistance of the terminal structure, and further enhance the reliability and stability of the power device.

Description

cross reference

[0001] This application claims priority from a Chinese patent application filed with the China Patent Office on January 25, 2022, bearing application number 202210085312.1 and entitled "Terminal structure, manufacturing method and power device," the entire contents of which are incorporated herein by reference. This application claims priority from a Chinese patent application filed with the China Patent Office on January 25, 2022, bearing application number 202220207437.2 and entitled "Terminal Structure and Power Device," the entire contents of which are incorporated herein by reference. [Technical Field]

[0002] The present invention relates to the field of semiconductors, and more particularly to terminal structures, manufacturing methods and power devices. [Background technology]

[0003] Silicon carbide (SiC) has been rapidly developing as a wide bandgap semiconductor material over the past decade or so, and compared to other semiconductor materials, it has advantages such as a wide bandgap, high thermal conductivity, high carrier saturation mobility, and high power density. Since the 1990s, silicon carbide power devices have been widely used in switching regulators, high frequency heating, car electronics, power amplifiers, and other fields. Summary of the Invention [Problem to be solved by the invention]

[0004] Currently, in the design and manufacturing process of silicon carbide power devices, especially high-voltage power devices, the power device terminal structure is sensitive to the concentration of JTE and interface charge, resulting in problems such as low breakdown voltage and poor breakdown voltage capability, which affect the reliability and stability of the power device. Therefore, designing a more reliable and efficient power device terminal structure has become one of the urgent problems that those skilled in the art need to solve.

[0005] Therefore, the present application provides a terminal structure, a manufacturing method, and a power device that improve the pressure resistance capability of the terminal structure and further increase the reliability and stability of the power device. [Means for solving the problem]

[0006] To achieve the above objectives, the present invention provides the following technical solutions: A first aspect of the present application provides a terminal structure, the terminal structure comprising: a first epitaxial layer; and a buried layer located on one side of the first epitaxial layer; a first doped region penetrating the buried layer, the doping type of the first doped region being opposite to the doping type of the buried layer; a second epitaxial layer located on a side of the buried layer remote from the first epitaxial layer, the second epitaxial layer having a main junction extension region and a field limiting ring within the second epitaxial layer; an oxide layer located on the second epitaxial layer away from the buried layer; Including, The doping types of the second epitaxial layer and the first epitaxial layer are both opposite to the doping type of the buried layer, and the field limiting ring is located between the main junction extension region and the first doped region in a first direction, the first direction being perpendicular to a direction from the first epitaxial layer to the second epitaxial layer.

[0007] Preferably, the surface of the oxide layer facing away from the buried layer has a first trench extending into the second epitaxial layer and serving as an ion implantation window for the first doped region.

[0008] Preferably, the terminal structure includes a first protective layer located at the bottom of the first groove, the first protective layer being spaced apart from the first doping region.

[0009] Preferably, the terminal structure includes a second doping region and a third doping region penetrating the buried layer, the second doping region and the third doping region both being located between the field limiting ring and the first doping region, the doping type of the second doping region being opposite to that of the buried layer, the doping type of the third doping region being the same as that of the buried layer, and the doping concentration of the third doping region being greater than that of the buried layer.

[0010] Preferably, the surface of the oxide layer facing away from the buried layer has a second trench extending into the second epitaxial layer and serving as an ion implantation window for the second and third doping regions.

[0011] Preferably, the semiconductor device further includes a second protective layer located at the bottom of the second groove, the second doping region being spaced apart from the second protective layer, and the third doping region being in contact with the second protective layer.

[0012] Preferably, the semiconductor device has a plurality of third doped regions arranged at intervals in the first direction.

[0013] Preferably, the intervals between adjacent second grooves are equal, and the width of the second grooves gradually decreases along the direction from the main junction extension region toward the field limiting ring; or The second grooves have the same width, and the interval between adjacent second grooves gradually increases along the direction from the main junction extension region toward the field limiting ring.

[0014] Preferably, the optical fiber has a plurality of field-limiting rings arranged at intervals in the first direction.

[0015] Preferably, the spacing between adjacent field limiting rings is equal, and the width of the field limiting rings gradually decreases along the direction from the main junction extension region to the field limiting rings, or The field limiting rings have the same width, and the spacing between adjacent field limiting rings gradually increases along the direction from the main junction extension region toward the field limiting rings.

[0016] A second aspect of the present application provides a power device, the power device comprising: a terminal structure according to any of the paragraphs of the first aspect above; a device cell region located on the side of the main junction extension region away from the field limiting ring.

[0017] A third aspect of the present application provides a method of manufacturing, the method comprising: providing an epitaxial sheet, the epitaxial sheet including a first epitaxial layer, a buried layer located on one side of the first epitaxial layer, and a second epitaxial layer located on a side of the buried layer away from the first epitaxial layer, the second epitaxial layer and the first epitaxial layer both having doping types opposite to the doping type of the buried layer; forming an oxide layer on a surface of the second epitaxial layer away from the buried layer; forming a main junction extension region and a field limiting ring in the second epitaxial layer; forming a first doped region through the buried layer, the doping type of the first doped region being opposite to the doping type of the buried layer, and the field limiting ring being located between the main junction extension region and the first doped region in a first direction, the first direction being perpendicular to a direction from the first epitaxial layer to the second epitaxial layer.

[0018] Preferably, the method of forming the first doped region comprises: forming a first groove in a surface of the oxide layer facing away from the buried layer; performing ion implantation based on the first groove to form a first doping region; Includes:

[0019] Preferably, forming a second groove simultaneously with forming the first groove; Simultaneously with forming the first doped region, perform ion implantation based on the second groove to form a second doped region penetrating the buried layer; After forming the second doped region, perform ion implantation based on the second groove to form a third doped region penetrating the buried layer; further comprising The second doped region and the third doped region are both located between the field limiting ring and the first doped region. [Effects of the Invention]

[0020] As can be seen from the above description, the terminal structure, manufacturing method and power device provided by the technical solution of the present application use the buried layer to gently distribute the high electric field in the main junction extension region to the intermediate region of the entire terminal, i.e., the field limiting ring region, or the field limiting ring region and the third doping region, so that the multiple regions jointly share the avalanche breakdown energy, improving the avalanche withstand capability and breakdown voltage capability of the terminal structure, and further enhancing the reliability and stability of the power device. [Brief explanation of the drawings]

[0021] In order to more clearly explain the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. However, the drawings in the following description are only embodiments of the present application, and it is obvious to those skilled in the art that other drawings can be obtained based on the provided drawings on the premise that no work worth inventive step is required. The structures, proportions, dimensions, etc. shown in the drawings of this specification do not limit the operable conditions of this application, but are used to match the disclosure contents of the specification for the understanding and reading of those skilled in the art. Therefore, as long as they do not have any technical substantive meaning and do not affect the effects that can be realized and the purposes that can be achieved by this application, any structural modifications, changes in proportions, or adjustments in dimensions should still fall within the scope that can be covered by the technical contents disclosed in this application. [Figure 1] 1 is a cross-sectional schematic diagram of a traditional joint terminal expansion structure provided by an embodiment of the present application; [Figure 2] 1 is a cross-sectional schematic diagram of a traditional field limiting ring terminal structure provided by an embodiment of the present application; [Figure 3] 1 is a cross-sectional schematic diagram of a terminal structure according to an embodiment of the present application; [Figure 4] FIG. 10 is a cross-sectional schematic view of another terminal structure according to an embodiment of the present application. [Figure 5] 1 is a plan view of the structure of a power device according to an embodiment of the present application; [Figure 6] 1 is a cross-sectional flow chart of a manufacturing method according to an embodiment of the present application. [Figure 7] 1 is a cross-sectional flow chart of a manufacturing method according to an embodiment of the present application. [Figure 8] 1 is a cross-sectional flow chart of a manufacturing method according to an embodiment of the present application. [Figure 9] 1 is a cross-sectional flow chart of a manufacturing method according to an embodiment of the present application. [Figure 10] 1 is a cross-sectional flow chart of a manufacturing method according to an embodiment of the present application. [Figure 11] 1 is a cross-sectional flow chart of a manufacturing method according to an embodiment of the present application. [Figure 12] 1 is a cross-sectional flow chart of another manufacturing method according to an embodiment of the present application. [Figure 13] 1 is a cross-sectional flow chart of another manufacturing method according to an embodiment of the present application. [Figure 14] 1 is a cross-sectional flow chart of another manufacturing method according to an embodiment of the present application. [Figure 15] 1 is a cross-sectional flow chart of another manufacturing method according to an embodiment of the present application. [Figure 16] 1 is a cross-sectional flow chart of another manufacturing method according to an embodiment of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0022] The embodiments of the present application will be described below in a clear and complete manner in conjunction with the drawings of the embodiments of the present application, but it is clear that the described embodiments are not all of the embodiments of the present application, but only some of the embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by a person skilled in the art without any inventive effort fall within the scope of protection of the present application.

[0023] Currently, in the design and manufacturing process of silicon carbide and other power devices, especially high-voltage power devices, in order to reduce the electric field at the junction edge and improve the actual breakdown voltage capability of the device, the device needs to have a good terminal structure, such as a field plate (FP), a field limiting ring (FLR), a junction terminal extension (JTE), etc. The field limiting ring (FLR) and the junction terminal extension (JTE) are the main structures that are widely applied in conventional silicon carbide and other power device structures.

[0024] As shown in Figure 1, Figure 1 is a cross-sectional schematic diagram of a traditional joint terminal expansion structure provided in an embodiment of the present application. The joint terminal expansion structure includes: The semiconductor device includes a substrate 104, an epitaxial layer 18 located on one side of the substrate 104, an oxide layer 7 located on the side of the epitaxial layer 18 away from the substrate 104, a main junction extension region 2 located within the epitaxial layer 18, and a junction terminal extension region 19 also located within the epitaxial layer 18 on one side of the main junction extension region 2.

[0025] In this terminal structure, the junction terminal extension region 19 has a dominant concentration value, and the breakdown voltage of the device terminal is sensitive to the dominant concentration value of the junction terminal extension region 19, so the window is designed to be small. This terminal structure is very sensitive to surface charges, and the instability of the interface and the charge in the oxide layer 7 are likely to affect the surface electric field distribution of the device, which may further affect the breakdown voltage and reliability of the device. In addition, the manufacturing process of this terminal structure is complicated and not suitable for mass production.

[0026] Also, as shown in Figure 2, Figure 2 is a cross-sectional schematic diagram of a traditional field limiting ring structure provided in an embodiment of the present application, which includes: The device includes a substrate 104, an epitaxial layer 18 located on one side of the substrate 104, an oxide layer 7 located on the side of the epitaxial layer 18 away from the substrate 104, a main junction extension region 2 located within the epitaxial layer 18, and a field limiting ring 3 also located within the epitaxial layer 18 on one side of the main junction extension region 2.

[0027] Because devices such as silicon carbide have a high surface electric field in this terminal structure, in order to improve the breakdown voltage, the device design requires a greater number of field limiting rings 3 to reduce the peak surface electric field. Many design factors, such as the number of rings, ring width, and ring spacing, all affect the surface electric field distribution. The terminals of multiple field limiting rings 3 occupy a large chip area and do not contribute to improving current. Furthermore, this terminal structure is also very sensitive to surface charges, and the instability of the interface and charges in the oxide layer 7 can easily affect the surface electric field distribution of the device, further affecting the breakdown voltage and reliability of the device.

[0028] SUMMARY OF THE INVENTION The technical solution of the present application is based on the above-mentioned problems and provides a terminal structure, a manufacturing method and a power device that improve the pressure resistance of the terminal structure and further enhance the reliability and stability of the power device.

[0029] In order to make the above objects, features and advantages of the present application more clear and easily understandable, the present application will be further described in detail hereinafter in combination with drawings and specific embodiments.

[0030] Please refer to Fig. 3, which is a cross-sectional schematic diagram of a terminal structure according to an embodiment of the present application. a first epitaxial layer (101); a buried layer (102) located on one side of the first epitaxial layer (101); a first doping region (4) penetrating the buried layer (102), the first doping region (4) having a doping type opposite to that of the buried layer (102); a second epitaxial layer (103) located on the side of the buried layer (102) facing away from the first epitaxial layer (101), the second epitaxial layer (103) having a main junction extension region (2) and a field limiting ring (3) therein; and an oxide layer (7) located on the side of the second epitaxial layer (103) facing away from the buried layer (102).

[0031] The doping types of the second epitaxial layer 103 and the first epitaxial layer 101 are both opposite to the doping type of the buried layer 102, and in a first direction, the field limiting ring 3 is located between the main junction extension region 2 and the first doping region 4, and the first direction is perpendicular to the direction from the first epitaxial layer 101 to the second epitaxial layer 103.

[0032] Furthermore, the doping types of the main junction extension region 2 and the field limiting ring 3 are the same and opposite to that of the second epitaxial layer 103, i.e., the doping types of the main junction extension region 2 and the field limiting ring 3 are the same as that of the buried layer 102, and the main junction extension region 2 and the field limiting ring 3 are both highly doped, and generally, the doping concentrations of the main junction extension region 2 and the field limiting ring 3 are greater than that of the buried layer 102. For example, if the first epitaxial layer 101 and the second epitaxial layer 103 are N-type doped, the buried layer 102 is P-type doped, and the first doped region 4 is N-type doped, the N-type doping concentration of the first doped region 4 is greater than the P-type doping concentration of the buried layer 102, and the main junction extension region 2 and the field limiting ring 3 are both highly P-type doped. The main junction extension region serves to smoothly transition the electric field from the device cell region to the terminal structure in the power device.

[0033] Here, in this application, the doping types being the same means that the doping types of both or multiple targets are either N-type doping or P-type doping, and the doping concentrations are the same or different; correspondingly, the doping types being different means that at least one of the doping types of both or multiple targets is N-type doping and at least one target is P-type doping, and the corresponding doping concentrations may be the same or different.

[0034] In the present application, the first epitaxial layer 101, the buried layer 102 and the second epitaxial layer 103 are one or more of Si, SiC, Ga2O3.

[0035] Here, in this application, the doping concentration is not limited and defaults to a normal doping concentration between a low doping concentration and a high doping concentration. For example, N-type doping is between N-type low doping and N-type high doping. The following explanation about the doping concentration is also used similarly, so it will not be repeated in this application.

[0036] In this terminal structure, the presence of the buried layer 102 creates a leakage path along the buried layer 102, which can affect device reliability. Therefore, the first doping region 4 is used to block the electric field within the terminal structure and prevent leakage current from affecting other components. The first doping region 4 also terminates inversion layers formed on the device surface for various reasons, reducing the impact of surface contamination on the breakdown voltage and further improving device reliability. In addition, the buried layer 102 in this terminal structure distributes the high electric field in the main junction extension region 2 to the field limiting ring 3 in a relaxed manner. That is, the field limiting ring 3 performs a voltage division function, further improving the voltage resistance of the terminal structure and enhancing the reliability and stability of the device.

[0037] Preferably, the surface of the oxide layer 7 away from the buried layer 102 has a first groove 11 extending into the second epitaxial layer 103 to serve as an ion implantation window for the first doping region 4. The depth of the first groove 11 can be set according to needs, and its bottom may extend into the second epitaxial layer 103, be located within the oxide layer 7, or even be located at the interface between the oxide layer 7 and the second epitaxial layer 103. All of these are within the scope of protection of the present application. Accordingly, in actual processes, the formation of the first groove 11 does not require an additional process step; it can simply be modified from the conventional process. Furthermore, the formation of the first doping region 4 does not require the formation of the first groove 11; instead, the ion implantation window can be formed based on a patterned photoresist.

[0038] Preferably, the terminal structure includes a first protective layer 13 located at the bottom of the first groove 11, the first protective layer 13 being spaced apart from the first doping region 4. Ion implantation can also be performed based on the first groove 11 to form the first protective layer 13 below its bottom. The doping type of the first protective layer 13 is opposite to that of the first doping region 4, but is the same as, and lower than, the doping concentrations of the field limiting ring 3 and the main junction extension region 2. For example, if the field limiting ring 3 and the main junction extension region 2 are both highly P-doped, the first protective layer 13 can be P-doped or lightly P-doped. Typically, the first protective layer 13 is lightly P-doped. The first protective layer 13 reduces the influence of charges in the oxide layer 7 on the terminal structure and reduces the possibility of surface breakdown, improving device reliability and stability.

[0039] 4, which is a cross-sectional view of another terminal structure according to an embodiment of the present application. Based on the terminal structure shown in FIG. 3, the terminal structure is as follows: The semiconductor device further includes a second doping region 5 and a third doping region 6 penetrating the buried layer 102, both of which are located between the field limiting ring 3 and the first doping region 4. The doping type of the second doping region 5 is opposite to that of the buried layer 102, the doping type of the third doping region 6 is the same as that of the buried layer 102, and the doping concentration of the third doping region 6 is greater than that of the buried layer 102. In addition, the doping concentration of the second doping region 5 is generally greater than that of the buried layer 102. For example, if the buried layer 102 is P-doped, the second doping region 5 is highly N-doped and the third doping region 6 is highly P-doped.

[0040] This terminal structure uses the buried layer 102 to distribute the high electric field in the main junction extension region 2 to the intermediate region of the entire terminal, namely the field limiting ring 3 and the third doped region 6, in a relaxed manner, so that the multiple regions jointly share the avalanche breakdown energy of the device, thereby improving the avalanche resistance of the terminal structure, the breakdown voltage of the device, and the voltage resistance of the terminal structure, and further enhancing the reliability and stability of the power device.

[0041] Preferably, the surface of the oxide layer 7 away from the buried layer 102 has a second trench 12 extending into the second epitaxial layer 103 and serving as an ion implantation window for the second doping region 5 and the third doping region 6. Similar to the first trench 11, the depth of the second trench 12 can be set according to needs. Its bottom may extend into the second epitaxial layer 103, be located within the oxide layer 7, or even be located at the interface between the oxide layer 7 and the second epitaxial layer 103. All of these are within the scope of protection of the present application. Similarly, in actual processes, forming the second trench 12 does not require an additional process step; it can be achieved by simply modifying the design of a conventional process. Generally, the second trench 12 is formed simultaneously with the formation of the first trench 11. Furthermore, when forming the second doping region 5 or the third doping region 6, there is no need to form the second groove 12, and the ion implantation window can be formed based on the patterned photoresist.

[0042] Furthermore, the area of ​​the terminal structure can be reduced because the width of the second groove 12 is smaller than the width of the first groove 11. The width of the first groove 11 is large to ensure a better electric field blocking effect, and generally, the width of the first groove 11 is greater than 5 μm.

[0043] In actual processes, the main junction extension region 2 cannot reach an ideal state, and curved regions exist at the etching edges, which affect the breakdown voltage of the device. The first groove 11 and the second groove 12 reduce the ion concentration in the second epitaxial layer 103, weakening the electric field strength at the curved regions of the main junction extension region 2 and increasing the breakdown voltage. The first groove 11 and the second groove 12 also effectively improve the area utilization of the terminal structure, reducing the area of ​​the voltage dividing region and the chip area of ​​the terminal structure. This allows more devices to be manufactured from a silicon wafer with the same area, thereby reducing chip costs. However, in actual processes, the first groove 11 and the second groove 12 may not be formed depending on process or design needs.

[0044] The shape of the first groove 11 or the second groove 12 may be rectangular, trapezoidal, or U-shaped.

[0045] Preferably, the second groove 12 includes a second protective layer 14 located at the bottom thereof, the second doping region 5 being spaced apart from the second protective layer 14, and the third doping region 6 being in contact with the second protective layer 14. Similar to the first protective layer 13, the second protective layer 14 has a doping type opposite to that of the second doping region 5, a doping type identical to that of the third doping region 6, and a lower doping concentration than that of the third doping region 6. For example, if the second doping region 5 is N-doped, the third doping region 6 is P-doped, and the second protective layer 14 is lightly P-doped. The second protective layer 14 is located between the second groove 12 and the third doping region 6 and contacts the third doping region 6, reducing the influence of charges in the oxide layer 7 on the third doping region 6, thereby reducing the effect of surface breakdown, and improving the voltage dividing effect of the third doping region 6 and the breakdown voltage of the device, thereby enhancing the reliability and stability of the device.

[0046] Preferably, the terminal structure comprises a plurality of third doping regions 6 spaced apart in the first direction, which improves voltage division by the plurality of third doping regions 6, reduces the avalanche breakdown energy of the device shared by each third doping region 6, and improves the breakdown voltage and voltage resistance of the device.

[0047] Preferably, in the first embodiment, the intervals between adjacent second grooves 12 are equal, and the width of the second grooves 12 gradually decreases along the direction from the main junction expansion region 2 toward the field limiting ring 3; or In the second embodiment, the widths of the second grooves 12 are equal, and the intervals between adjacent second grooves 12 gradually increase along the direction from the main junction expansion region 2 toward the field limiting ring 3 .

[0048] In the present application, one second groove 12 and one corresponding second doping region 5 and one corresponding third doping region 6 constitute one trench ring. That is, in the first embodiment, the intervals between adjacent trench rings are equal, and the widths of the trench rings gradually decrease from the main junction extension region 2 to the field limiting ring 3. In the second embodiment, the widths of the trench rings are equal, and the intervals between adjacent trench rings gradually increase from the main junction extension region 2 to the field limiting ring 3.

[0049] Both of the above two aspects can optimize the electric field distribution in the terminal structure, reduce the sensitivity of the terminal structure to charge dose, and improve the reliability and stability of the power device. In actual processes, an appropriate form can be selected according to actual needs. Furthermore, the width and spacing of the trench rings can be flexibly configured according to different device specifications, and are not limited by this application.

[0050] Preferably, the terminal structure in the present application comprises a plurality of field limiting rings 3 arranged at intervals in the first direction, and the plurality of field limiting rings 3 improves voltage division, reduces the avalanche breakdown energy of the device shared by each field limiting ring 3, and further improves the breakdown voltage and withstand voltage of the device.

[0051] Preferably, in the first embodiment, the spacing between adjacent field limiting rings 3 is equal, and the width of the field limiting rings 3 gradually decreases along the direction from the main junction extension region 2 to the field limiting rings 3, or In the second configuration, the field limiting rings 3 have the same width, and the spacing between adjacent field limiting rings 3 gradually increases in the direction from the main junction extension region 2 toward the field limiting rings 3 .

[0052] Both of the above two aspects can optimize the electric field distribution in the terminal structure, reduce the sensitivity of the terminal structure to charge dose, and improve the reliability and stability of the power device. In actual processes, an appropriate form can be selected according to actual needs. Furthermore, the width and spacing of the field limiting rings 3 can be flexibly configured according to different device specifications, and are not limited by this application.

[0053] It should be noted that in this application, due to limitations in the drawings, the drawings do not show changes in the width of the field limiting rings 3 or the trench rings, and similarly do not show changes in the spacing between the field limiting rings 3 or the spacing between the trench rings, but this does not mean that the above changes are not included in this application.

[0054] Based on the above terminal structure, the embodiment of the present application further provides a power device, and the power device described below can be referred to correspondingly with the above terminal structure. Please refer to Figure 5, which is a plan view of the power device according to the embodiment of the present application. The power device includes: The device includes any one of the terminal structures described above and a device cell region 9 located on the side of the main junction extension region 2 away from the field limiting ring 3 .

[0055] 5 , the center of the entire power device is the device cell region 9, the region surrounding the device cell region 9 is the main junction extension region 2, the region surrounding the main junction extension region 2 is the field limiting ring region 20, which includes the field limiting ring 3, the region surrounding the field limiting ring region 20 is the trench ring region 21, which includes the second groove 12, the second doped region 5, and the third doped region 6, and the region surrounding the trench ring region 21 is the electric field shielding region 22, which includes the first groove 11 and the first doped region 4. In addition, between adjacent power devices, there are scribe lines 10 for dividing the silicon wafer to form single power devices.

[0056] The power devices include, but are not limited to, PIN, SBD, MOSFET, IGBT, or GTO, and wafer materials for manufacturing the power devices include, but are not limited to, silicon, silicon carbide, gallium arsenide, aluminum nitride, gallium nitride, gallium oxide, or diamond.

[0057] The power device provided by the present application has a high breakdown voltage, and therefore has good withstand voltage capability, as well as good reliability and stability.

[0058] Based on the above embodiments, the present application further provides a manufacturing method, and the manufacturing method described below can be referred to correspondingly with the above-mentioned terminal structure and power device. Please refer to Figures 6 to 11, which are cross-sectional flow charts of the manufacturing method provided by the embodiments of the present application. The manufacturing method includes the following steps: 6, provide an epitaxial sheet 1, which includes a first epitaxial layer 101, a buried layer 102 located on one side of the first epitaxial layer 101, and a second epitaxial layer 103 located on the side of the buried layer 102 away from the first epitaxial layer 101, wherein the doping types of the second epitaxial layer 103 and the first epitaxial layer 101 are opposite to that of the buried layer 102. For example, if the buried layer 102 is P-type doped, the first epitaxial layer 101 and the second epitaxial layer 103 are N-type doped.

[0059] The epitaxial sheet 1 further includes a substrate 104 located on the side of the first epitaxial layer 101 away from the buried layer 102 for supporting the first epitaxial layer 101 and improving the properties of the thin film. Preferably, the doping type of the substrate 104 is the same as that of the first epitaxial layer 101. The epitaxial layer may be directly obtained by custom procurement or may be manufactured and obtained based on a deposition process.

[0060] Step S102: An oxide layer 7 is formed on the surface of the second epitaxial layer 103 facing away from the buried layer 102. The oxide layer 7 serves the functions of protection and water vapor isolation, and particularly when ions are implanted, the oxide layer 7 is bombarded with ions to protect the film layer from damage, thereby reducing and even eliminating damage to the film layer caused by ion implantation.

[0061] In place of the oxide layer 7, a photoresist may be used as a protective layer to reduce damage to the film layer due to ion implantation. However, when manufacturing the terminal structure of a SiC power device (i.e., the second epitaxial layer 103 is SiC), Al ions are implanted to form the main junction extension region 2 and the field limiting ring 3. Because the relative atomic weight of Al is large, photoresist cannot block ion bombardment. Therefore, when implanting Al ions, the film layer structure 8 serves as a shielding layer for the ion implantation. The film layer structure 8 may be a single thick oxide medium layer or a multi-layer structure. Typically, the thickness of the oxide medium layer is 100 nm to 10 μm.

[0062] 7, the film layer structure 8 includes three layers: a first oxide layer 81 located on the surface of the second epitaxial layer 103 facing away from the buried layer 102; a polycrystalline silicon layer 82 located on the surface of the first oxide layer 81 facing away from the second epitaxial layer 103; and a second oxide layer 83 located on the surface of the polycrystalline silicon layer 82 facing away from the first oxide layer 81. The thickness of the first oxide layer is 50 to 500 nm, the thickness of the polycrystalline silicon layer is 100 to 2000 nm, and the thickness of the second oxide layer is 50 to 500 nm. Generally, the thickness of the first oxide layer is smaller than the thickness of the second oxide layer.

[0063] Step S103: Form the main junction extension region 2 and the field limiting ring 3 in the second epitaxial layer 103. The method for forming the main junction extension region 2 and the field limiting ring 3 is as follows. Step S103.1: Etching the oxide layer 7 based on a photolithography process to form an ion implantation window. Based on the patterned mask 17, the oxide layer 7 is subjected to processes such as photolithography and development to obtain the oxide layer 7 with an ion implantation window. An ion implantation window corresponding to the main junction extension region 2 and an ion implantation window corresponding to the field limiting ring 3 may be formed together. Step S103.2: Ion implantation is performed based on the ion implantation window to form the main junction extension region 2 and the field limiting ring 3.

[0064] 8, after photolithography and development, the second oxide layer 83 is first etched using a gas with good selectivity to the oxide layer and the polysilicon layer 82, such as CF4 or CHF3, and then the polysilicon layer 82 is etched using a gas with good selectivity to the polysilicon layer 82, such as HBr. Since some over-etching occurs during etching, the first oxide layer 81 is thin. The thin first oxide layer 81 is then used as a shielding layer for ion implantation to form the main junction extension region 2 and the field limiting ring 3. This improves the ion implantation distribution and effectively avoids the trench effect. After the ion implantation is completed, the film layer 8 is removed using a wet etching process.

[0065] It should be noted that in the present application, although the drawings do not show the thin first oxide layer 81, the first oxide layer 81 actually exists in the terminal structure.

[0066] Step S104: Referring to FIGS. 9 and 10, a first doping region 4 is formed penetrating the buried layer 102, the doping type of the first doping region 4 is opposite to that of the buried layer 102, and the field limiting ring 3 is located between the main junction extension region 2 and the first doping region 4 in a first direction, and the first direction is perpendicular to the direction from the first epitaxial layer 101 to the second epitaxial layer 103.

[0067] Based on the above, the method for forming the first doping region 4 includes the following steps. Step S104.1: As shown in Figure 9, a first groove 11 is formed on the surface of the oxide layer 7 away from the buried layer 102. The first groove 11 is formed based on a photolithography process. The first groove 11 extends into the second epitaxial layer 103 and serves as an ion implantation window for the first doping region 4. Step S104.2: As shown in Figure 10, ion implantation is performed based on the first groove 11 to form a first doped region 4. The first doped region 4 has a doping type opposite to that of the buried layer 102, a doping concentration greater than that of the buried layer 102, and serves to shield the buried layer 102.

[0068] 10, the manufacturing method may further include ion implantation based on the first groove 11 to form a first protective layer 13. The first protective layer 13 is located at the bottom of the first groove 11, and there is a gap between the first protective layer 13 and the first doping region 4. The doping type of the first protective layer 13 is the same as that of the buried layer 102, which reduces the influence of interface charges on the device.

[0069] Step S105: As shown in Figure 11, a medium with a high dielectric constant is filled into the first groove 11 to form a flat film layer. The medium is deposited by a CVD process to fill the first groove 11. The medium is typically SiO2, SiN x , Al2O3, AlN, HfO2, MgO, Sc2O3, Ga2O3, AlHFO x , HFSiON materials or any combination thereof.

[0070] Step S106: A cathode 16 is formed on the surface of the substrate 104 away from the first epitaxial layer 101, and an anode 15 is formed on the surface of the main junction extension region 2 away from the buried layer 102, and the anode 15 contacts the main junction extension region 2 to form the terminal structure shown in Figure 3. In addition, the anode 15 is generally made of a metal material.

[0071] 12 to 16, which are cross-sectional flow charts of another manufacturing method according to an embodiment of the present application. The present application further provides another manufacturing method, which, based on the above manufacturing method, further includes step S107 after step S104, Step S107 is as follows: A second doping region 5 and a third doping region 6 are formed through the buried layer 102, and the second doping region 5 and the third doping region 6 are both located between the field limiting ring 3 and the first doping region 4, the doping type of the second doping region 5 is opposite to that of the buried layer 102, the doping type of the third doping region 6 is the same as that of the buried layer 102, and the doping concentration of the third doping region 6 is greater than that of the buried layer 102.

[0072] In addition, the method for forming the second doping region 5 and the third doping region 6 includes the following steps. Step S107.1: As shown in Fig. 13, second grooves 12 are formed in the surface of the oxide layer 7 away from the buried layer 102. Similarly, the second grooves 12 are formed by a photolithography process, and the second grooves 12 extend into the second epitaxial layer 103 and serve as ion implantation windows for the second doping region 5 and the third doping region 6. The first grooves 11 and the second grooves 12 may have the same depth, and based on this, the second grooves 12 may be formed simultaneously with the formation of the first grooves 11. Step S107.2: As shown in Figure 14, based on the second groove 12, ion implantation is performed to form a second doping region 5 penetrating the buried layer 102. The second doping region 5 has a doping type opposite to that of the buried layer 102 and a doping concentration greater than that of the buried layer 102.

[0073] 14, ion implantation is performed based on the second groove 12 to form a second protective layer 14, which is located at the bottom of the second groove 12 and spaced apart from the second doping region 5. The doping type of the second protective layer 14 is the same as that of the buried layer 102 and is used to reduce the impact of interface charges on the device.

[0074] The doping type of the second doping region 5 is the same as that of the first doping region 4, and both doping concentrations are greater than that of the buried layer 102. Therefore, simultaneously with the formation of the first doping region 4, ion implantation is performed based on the second groove 12 to form the second doping region 5 penetrating the buried layer 102. Correspondingly, simultaneously with the formation of the first protective layer 13, the second protective layer 14 is formed.

[0075] Step S107.3: After the second doping region 5 is formed, ion implantation is performed based on the second groove 12 to form a third doping region 6 penetrating the buried layer 102, and the second doping region 5 and the third doping region 6 are both located between the field limiting ring 3 and the first doping region 4.

[0076] As shown in FIG. 15, the second groove 12 on the left side of the dashed line is the first window, and the second groove 12 on the right side of the dashed line is the second window. Ion implantation is performed based on the second window to form the third doping region 6, and the third doping region 6 contacts the above-mentioned second protective layer 14.

[0077] Furthermore, in this manufacturing method, after forming the second doping region 5 and the third doping region 6, step S105 is similarly performed to fill the first groove 11 and the second groove 12 at the same time (as shown in FIG. 16), and then step S106 is performed to form the terminal structure of FIG. 4.

[0078] As described above, in the terminal structure, manufacturing method, and power device provided by the technical solution of the present application, the implantation depth of the third doping region 6 is greater than that of the field limiting ring 3, creating a vertical step effect in the doping distribution in the device cell region 9, improving the device's breakdown voltage capability and reducing the chip area required for the terminal structure. At the same time, the terminal structure of the present application is insensitive to the concentration and surface charge of the JTE. Furthermore, in the present application, the buried layer 102 distributes the high electric field of the main junction extension region 2 to the intermediate region of the entire terminal, i.e., the field limiting ring 3 region, or the field limiting ring 3 region and the third doping region 6, so that the multiple regions share the avalanche breakdown energy, improving the avalanche withstand capability and breakdown voltage capability of the terminal structure and further enhancing the reliability and stability of the power device.

[0079] Each embodiment in this specification is described in a sequential, parallel, or combined sequential and parallel manner, and each embodiment mainly describes the differences from other embodiments, and references are made to the same or similar parts between the embodiments. Since the apparatus disclosed in the embodiment corresponds to the method disclosed in the embodiment, the description thereof will be brief, and reference is made to the method description for relevant parts.

[0080] In the description of this application, the orientations or positional relationships indicated by terms such as "upper," "lower," "top," "bottom," "inner," and "outer" are orientations or positional relationships based on those shown in the drawings, and do not indicate or imply that the referred-to devices or components must have a specific orientation or be constructed and operated in a specific orientation, but are merely for the convenience and simplification of the description of this application, and are not intended to limit the present application. When a component is considered to be "connected" to another component, it may be directly connected to the other component, or there may be components provided between them at the same time.

[0081] Additionally, in this specification, relational terms such as "first" and "second" are used solely to distinguish one entity or operation from another, without necessarily requiring or implying that such an actual relationship or order exists between those entities or operations. Additionally, the terms "comprise," "include," "comprises," or any other variation thereof are intended to include a non-exclusive inclusion, whereby an item or equipment containing a set of elements includes not only those elements but also other elements not expressly listed, or even the inherent elements of such item or equipment. Unless further limited, an element defined by the phrase "comprises one ____" does not exclude that the item or equipment containing that element also contains other identical elements.

[0082] The above description of the disclosed embodiments will enable those skilled in the art to make or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Thus, the present application is not limited to the embodiments herein but is accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A terminal structure comprising: a first epitaxial layer; and a buried layer located on one side of the first epitaxial layer; a first doped region penetrating the buried layer, the doping type of the first doped region being opposite to the doping type of the buried layer; a second epitaxial layer located on a side of the buried layer away from the first epitaxial layer, the second epitaxial layer having a main junction extension region and a field limiting ring therein and penetrating the second epitaxial layer; an oxide layer located on a side of the second epitaxial layer away from the buried layer; Including, doping types of the second epitaxial layer and the first epitaxial layer are opposite to a doping type of the buried layer, the field limiting ring is located between the main junction extension region and the first doped region in a first direction, the first direction is perpendicular to a direction from the first epitaxial layer to the second epitaxial layer; the doping type of the main junction extension region and the field limiting ring is the same as the doping type of the buried layer, and the doping concentration of the first doped region, the main junction extension region, and the field limiting ring is greater than the doping concentration of the buried layer; A terminal structure characterized by:

2. a surface of the oxide layer facing away from the buried layer having a first trench extending into the second epitaxial layer and serving as an ion implantation window for the first doped region; The terminal structure according to claim 1 .

3. a first protective layer located at a bottom of the first groove and spaced apart from the first doped region, the first protective layer having a doping type opposite to that of the first doped region and a doping concentration lower than that of the main junction extension region and the field limiting ring; 3. The terminal structure according to claim 2.

4. a second doped region penetrating the buried layer and a third doped region penetrating the buried layer and the second epitaxial layer; the second doping region and the third doping region are both located between the field limiting ring and the first doping region, the doping type of the second doping region is opposite to that of the buried layer, the doping type of the third doping region is the same as that of the buried layer, and the doping concentration of the third doping region is greater than that of the buried layer; The terminal structure according to claim 1 .

5. a surface of the oxide layer facing away from the buried layer having a second recessed groove extending into the second epitaxial layer and serving as an ion implantation window for the second doped region and the third doped region; 5. The terminal structure according to claim 4.

6. a second protective layer located at a bottom of the second groove and spaced apart from the second doped region, the third doped region being in contact with the second protective layer, the second protective layer having a doping type identical to that of the third doped region and a doping concentration lower than that of the third doped region; 6. The terminal structure according to claim 5.

7. a plurality of the third doped regions arranged at intervals in the first direction; 5. The terminal structure according to claim 4.

8. The intervals between adjacent second grooves are equal, and the width of the second grooves gradually decreases along the direction from the main junction extension region toward the field limiting ring, or the second grooves have the same width, and the interval between adjacent second grooves gradually increases along a direction from the main junction extension region toward the field limiting ring; 6. The terminal structure according to claim 5.

9. a plurality of the field limiting rings arranged at intervals in the first direction; The terminal structure according to claim 1 .

10. The spacing between adjacent field limiting rings is equal, and the width of the field limiting rings gradually decreases along a direction from the main junction extension region toward the field limiting rings; or the field limiting rings have the same width, and the spacing between adjacent field limiting rings gradually increases along a direction from the main junction extension region toward the field limiting rings; 10. The terminal structure according to claim 9.

11. A power device, The terminal structure according to any one of claims 1 to 10, a device cell region of the main junction extension region located away from the field limiting ring; A power device comprising:

12. A manufacturing method comprising: providing an epitaxial sheet, the epitaxial sheet including a first epitaxial layer, a buried layer located on one side of the first epitaxial layer, and a second epitaxial layer located on a side of the buried layer away from the first epitaxial layer, the second epitaxial layer and the first epitaxial layer both having doping types opposite to the doping type of the buried layer; forming an oxide layer on a surface of the second epitaxial layer away from the buried layer; etching the oxide layer according to a photolithography process to form an ion implantation window, and performing ion implantation according to the ion implantation window to form a main junction extension region and a field limiting ring in the second epitaxial layer and penetrating the second epitaxial layer, wherein the doping types of the main junction extension region and the field limiting ring are the same as the doping type of the buried layer, and the doping concentrations of the main junction extension region and the field limiting ring are greater than the doping concentration of the buried layer; forming a first doped region through the buried layer after forming the main junction extension region and the field limiting ring, the doping type of the first doped region being opposite to the doping type of the buried layer, the field limiting ring being located between the main junction extension region and the first doped region in a first direction, the first direction being perpendicular to a direction from the first epitaxial layer to the second epitaxial layer, and the doping concentration of the first doped region being greater than the doping concentration of the buried layer; A manufacturing method comprising:

13. The method for forming the first doped region includes: forming a first groove in a surface of the oxide layer facing away from the buried layer; performing ion implantation based on the first groove to form the first doped region; The method of claim 12, comprising:

14. forming the first groove and forming a second groove simultaneously; Simultaneously with forming the first doped region, performing ion implantation based on the second groove to form a second doped region penetrating the buried layer; After forming the second doped region, performing ion implantation based on the second groove to form a third doped region penetrating the buried layer and the second epitaxial layer; further comprising the second doped region and the third doped region are both located between the field limiting ring and the first doped region; The method of claim 13 .

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