Linear Voltage Regulator

Abstract

The linear voltage regulator (100) includes a voltage input (101) and a voltage output (102). The linear voltage regulator includes a buffer (114) having a voltage node, an input node (108), an output node, and a control node (114), and a power transistor (120) having a control node (116) coupled to the output node of the buffer (114), an input node (124) coupled to the voltage input, and an output node (128) coupled to the voltage output. The linear voltage regulator includes a dropout detection module (136) having a control node (140) coupled to the control node of the power transistor, a voltage input node (144) coupled to the voltage input (102), a voltage output node (148) coupled to the voltage output, and an output node (152). The linear voltage regulator includes a feedforward module (156) having an input node (160) coupled to the output node of the dropout detection module and an output node (164) coupled to the control node (114) of the buffer (112).

Description

[Technical Field]

[0001] This application relates generally to electronic circuitry, and more particularly to circuits for linear voltage regulators. [Background technology]

[0002] A linear voltage regulator is a system designed to automatically maintain a relatively constant output voltage level, even when the input voltage level contains frequency spurs, voltage flicker, etc. (e.g., noise). Linear voltage regulators may use a simple feedforward design or may include negative feedback. Linear voltage regulators may be used to regulate one or more alternating current (AC) or direct current (DC) voltages. Linear voltage regulators are found in devices such as computer power supplies, where the voltage regulator stabilizes the DC voltage used by the processor and other components.

[0003] A low dropout regulator (LDO regulator) is a DC linear voltage regulator that regulates the output voltage even when the supply voltage is very close to the output voltage. LDO regulators have no switching noise on the output voltage and have a relatively simple design that includes a reference voltage, an amplifier, and a pass element. Summary of the Invention

[0004] In a first example, a linear voltage regulator includes a voltage input and a voltage output. The linear voltage regulator also includes a buffer having a voltage node, an input node, an output node, and a control node, and a power transistor having a control node coupled to the output node of the buffer, an input node coupled to the voltage input, and an output node coupled to the voltage output. The linear voltage regulator further includes a dropout detection module having a control node coupled to the control node of the power transistor, a voltage input node coupled to the voltage input, a voltage output node coupled to the voltage output, and an output node. The linear voltage regulator also includes a feedforward module having an input node coupled to the output node of the dropout detection module and an output node coupled to the control node of the buffer.

[0005] In a second example, a linear voltage regulator includes a buffer configured to output a buffered voltage signal. The linear voltage regulator also includes a power transistor configured to receive the buffered voltage signal and provide an output voltage at an output node configured to be coupled to a load, the output voltage being based on the input voltage and the buffered voltage signal. The linear voltage regulator further includes a dropout detection module configured to assert a power supply rejection ratio signal when a voltage difference between a voltage level of the input voltage and a voltage level of the output voltage is less than a threshold voltage, and the power supply rejection ratio signal is deasserted when a voltage difference between a voltage level of the voltage input and a voltage level of the voltage output is equal to or greater than the threshold voltage. The linear voltage regulator further includes a feedforward circuit module configured to assert a noise rejection signal in response to assertion of the power supply rejection ratio signal and to deassert the noise rejection signal in response to deassertion of the power supply rejection ratio signal, the buffer injecting noise into the buffered voltage signal in response to the noise rejection signal, and the power transistor filtering noise in the input voltage in response to injecting noise into the buffered voltage signal.

[0006] In a third example, a system includes a linear voltage regulator. The linear voltage regulator includes a buffer configured to output a buffered voltage signal and a power transistor configured to receive the buffered voltage signal and provide an output voltage to an output node of the linear voltage regulator, the output voltage being based on the input voltage and the buffered voltage signal. The linear voltage regulator also includes a dropout detection module configured to assert a power supply rejection ratio signal when a voltage difference between a voltage level of the voltage input and a voltage level of the voltage output is less than a threshold voltage, and to deassert the power supply rejection ratio signal when the voltage difference between the voltage level of the voltage input and the voltage level of the voltage output is equal to or greater than the threshold voltage. The linear voltage regulator further includes a feedforward circuit module configured to assert a noise rejection signal in response to assertion of the power supply rejection ratio signal and to deassert the noise rejection signal in response to deassertion of the power supply rejection ratio signal, the buffer and the power transistor configured to filter noise from the input voltage in response to assertion of the noise rejection signal. The system includes a load coupled to an output node of a linear voltage regulator, where the current provided to the load varies as a function of time and the voltage provided to the load from the linear voltage regulator remains substantially constant. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a block diagram of an example of a linear voltage regulator.

[0008] [Figure 2] FIG. 1 is a circuit diagram of an example of a linear voltage regulator.

[0009] [Figure 3] FIG. 3 is a circuit diagram of a buffer for the linear voltage regulator of FIG. 2.

[0010] [Figure 4] FIG. 4 is a circuit diagram of a super source follower for the buffer of FIG. 3.

[0011] [Figure 5] FIG. 3 is a circuit diagram of a dropout detection module for the linear voltage regulator of FIG. 2.

[0012] [Figure 6] 3 is a graph plotting noise voltage gain as a function of frequency for the linear voltage regulator of FIG. 2;

[0013] [Figure 7] 3 is a plurality of graphs plotting noise voltage gain as a function of frequency for varying differences between input and output voltages for the linear voltage regulator of FIG. 2;

[0014] [Figure 8] 3 is a plurality of graphs plotting noise voltage gain as a function of frequency for varying load currents for the linear voltage regulator of FIG. 2;

[0015] [Figure 9] FIG. 2 is a circuit diagram of another example of a linear voltage regulator.

[0016] [Figure 10] FIG. 10 is a circuit diagram of a buffer for the linear voltage regulator of FIG.

[0017] [Figure 11] FIG. 10 is a circuit diagram of a dropout detection module for the linear voltage regulator of FIG.

[0018] [Figure 12] 10 is a graph plotting noise voltage gain as a function of frequency for the linear voltage regulator of FIG. 9.

[0019] [Figure 13] 1 shows a block diagram of a system providing an example application for a linear voltage regulator. DETAILED DESCRIPTION OF THE INVENTION

[0020] A linear voltage regulator (also called a linear regulator) is a circuit used to provide a regulated output voltage at a voltage output from a fluctuating / noisy input voltage provided at a voltage input. The power supply rejection ratio (PSRR) of a linear voltage regulator defines how well supply noise is rejected at the linear voltage regulator's output voltage. In this description, the linear voltage regulator uses a feedforward technique to selectively inject a portion of the supply voltage into a buffer, or more generally, into a driver within the linear voltage regulator, while tracking the load current to cancel out the supply noise at the output, thereby improving the linear voltage regulator's PSRR during time intervals when the difference between the input voltage and the output voltage is small (e.g., below a threshold voltage). Conversely, during time intervals when the difference between the input voltage and the output voltage is equal to or greater than the threshold voltage, the feedforward technique is disabled, maintaining the power efficiency of the linear voltage regulator.

[0021] More specifically, a linear voltage regulator produces a buffered voltage signal V at its output. BUFF The linear voltage regulator also includes a power transistor coupled to the output of the buffer. In this description, the term "couple" means indirect or direct connection. The power transistor provides an output voltage VOUT based on the buffer voltage and an input voltage VIN. The linear voltage regulator includes a dropout detection module that detects when a voltage difference between the voltage level at the voltage input and the voltage level at the voltage output exceeds a threshold voltage V THRESH The dropout detection module asserts a PSRR signal when the voltage difference between the voltage level at the voltage input and the voltage level at the voltage output is less than a threshold voltage V THRESHThe linear voltage regulator further includes a feedforward circuit module that generates a noise rejection signal V in response to the assertion of the PSRR signal. NOISE_REJ and asserts the noise rejection signal V in response to the deassertion of the PSRR signal. NOISE_REJ Deassert

[0022] Noise-removed signal V NOISE_REJ is injected into the control node of the buffer. Also, the noise cancellation signal V NOISE_REJ is the noise component of the input voltage VIN, that is, V IN_AC The noise-removed signal V NOISE_REJ In response to this, the buffer converts the noise into a buffered voltage signal V BUFF The buffer voltage signal V BUFF In response to noise being injected into the power transistor, the power transistor will inject noise V into the input voltage VOUT so that the output voltage VOUT remains approximately constant. IN_AC Unless otherwise stated, in this description, the word "about" or "approximately" preceding a value means + / - 10 percent of the stated value.

[0023] FIG. 1 is a block diagram of a linear voltage regulator 100. The linear voltage regulator 100 implements a power supply such as a low-dropout regulator (LDO). Accordingly, the linear voltage regulator 100 receives an input voltage V at a voltage input 101, a reference voltage V, and provides an output voltage V at a voltage output 102. The reference voltage V is a bandgap voltage reference that remains constant across power supply variations, temperature changes, or circuit loads from the linear voltage regulator 100. The linear voltage regulator 100 is configured so that the output voltage V remains constant even in situations where the input voltage V encounters noise, such as frequency spurs or voltage flicker. The linear voltage regulator 100 has a power supply rejection ratio (PSRR), which characterizes the ability of the linear voltage regulator 100 to suppress power supply variations that appear at the input voltage V from the output voltage V. An alternative method for increasing the PSRR of a voltage regulator circuit involves reducing the power efficiency of the regulator to increase available headroom. Instead of such an alternative technique, the linear voltage regulator 100 may use a noise-rejecting signal V NOISE_REJ to selectively assert to cancel noise present on the input voltage VIN.

[0024] Linear voltage regulator 100 includes an op-amp 103 (operational amplifier) ​​having a first input node 104 coupled to a reference voltage VREF and a second input node 106. In various examples, the first input node of op-amp 103 is a given one of the non-inverting or inverting input of op-amp 103, and the second input node 106 is the other of the non-inverting or inverting input of op-amp 103. An output node of op-amp 103 provides a voltage signal V that is provided to an input node 108 of buffer 112. X to provide.

[0025] The output of buffer 112 is output signal V which is coupled to control node 116 of power transistor 120. BUFF Buffer 112 provides an output signal V that is provided to a control node 116 of power transistor 120. BUFF, which is coupled to the second input node 106 of the operational amplifier 103. In some examples, the power transistor 120 is implemented as a field effect transistor (FET), such as an n-channel FET (NFET) or a p-channel FET (PFET). In other examples, the power transistor 120 is implemented as a bipolar junction transistor (BJT), such as an NPN BJT or a PNP BJT. In examples where the power transistor 120 is implemented as a FET (NFET or PFET), the control node 116 of the power transistor 120 is the gate. In examples where the power transistor 120 is implemented as a BJT (NPN or PNP), the control node 116 is the base. The power transistor 120 also includes an input node 124 coupled to an input voltage V at the voltage input 101 and an output node 128 providing an output voltage V at the voltage output 102 of the linear voltage regulator 100, which is also coupled to the second input node 106 of the operational amplifier 103. In an example where power transistor 120 is implemented as an NFET, input node 124 represents the drain and output node 128 represents the source. In an example where power transistor 120 is implemented as a PFET, input node 124 represents the source and output node 128 represents the drain. In an example where power transistor 120 is implemented as an NPN BJT, input node 124 represents the collector and output node 128 represents the emitter. In an example where power transistor 120 is implemented as a PNP BJT, input node 124 represents the emitter and output node 128 represents the collector.

[0026] In some examples, an auxiliary voltage is provided that is separate from the input voltage V. In other examples, the linear voltage regulator 100 operates with a single voltage source, such that the input voltage V provides power to the components of the linear voltage regulator 100. The buffer voltage V BUFFis also provided to dropout detection module 136 at control node 140 of dropout detection module 136. A voltage input node 144 of dropout detection module 136 is coupled to input voltage V at voltage input 101, and a voltage output node 148 is coupled to voltage output 102 of linear voltage regulator 100. An output node 152 of dropout detection module 136 provides PSRR signal V to feedforward module 156 at input node 160. PSRR The feedforward module 156 provides the noise-reduced signal V to the control node 114 of the buffer 112. NOISE_REJ and an output node 164 that provides:

[0027] The voltage output 102 is coupled to a load 168 which is coupled in parallel with an output capacitor 172. The load 168 and the output capacitor 172 are coupled to an electrically neutral node 176 (e.g., ground or virtual ground). The load current I LOAD is provided from voltage output 102 to load 168. Load current I LOAD varies as a function of time, while the voltage provided by linear voltage regulator 100 to load 168 remains approximately constant.

[0028] In operation, buffer 112 converts the voltage signal V output by operational amplifier 103 X , and a buffered voltage signal V BUFF It outputs a buffered voltage signal V BUFF In response to this, power transistor 120 generates a buffered voltage signal V BUFF The linear voltage regulator 100 provides an output voltage VOUT to a load 168 that varies as a function of VREF. If the output voltage VOUT rises too high relative to the reference voltage VREF, the linear voltage regulator 100 generates a buffered voltage signal V BUFF is adjusted and configured to control the power transistor 120 to maintain a constant output voltage VOUT.

[0029] The difference between the input voltage and the output voltage (VIN-VOUT) is the threshold voltage V THRESHIn the situation where the threshold voltage V is equal to or greater than V, the power transistor 120 operates in the saturation region, and the noise injected into the input voltage V is filtered by the buffer 112 and the operational amplifier 103. The noise injected into the input voltage V is represented as V IN_AC. The noise in the output voltage V OUT is represented as V OUT_AC. When the power transistor 120 operates in the saturation region, V OUT_AC is at least one order of magnitude smaller (1 / 10) than V IN_AC. For example, THRESH is equal to 1 V and the voltage VOUT is at least 1 V less than the input voltage V, the power transistor 120 operates in the saturation region and the noise V present in the input voltage V is filtered using the combination of the operational amplifier 103, the buffer 112, and the power transistor 120.

[0030] However, VOUT-VIN is the threshold voltage V THRESH In a situation approaching, for example, the load current I LOAD The dropout detection module 136 transitions from operating in the saturation region to the linear region in response to an increase in V. Thus, the dropout detection module 136 is configured with a delta voltage ΔV, which is experimentally determined, and a threshold voltage V THRESH is smaller than (e.g., ΔV <V THRESH ). The dropout detection module 136 detects the buffered voltage signal V BUFF , and the voltage difference between the voltage level VIN at the voltage input node 144 and the voltage level at the voltage output VOUT is a threshold voltage V THRESH If the PSRR signal V PSRR In other words, the dropout detection module 136 asserts VOUT-VIN <V THRESH In the case of PSRR signal V PSRR The dropout detection module 136 also asserts a threshold voltage V THRESH If it is equal to or greater than , the PSRR signal V PSRR Deassert

[0031] PSRR signal V PSRR In response to the assertion of NOISE_REJ (also called the feedforward signal). Conversely, the PSRR signal V PSRR In response to the deassertion of V, the feedforward module 156 generates the noise cancellation signal V NOISE_REJ In this manner, dropout detection module 136 and feedforward module 156 work in concert to selectively apply a PSRR boost to linear voltage regulator 100.

[0032] Noise-removed signal V NOISE_REJ In response to the injection of BUFF The buffer output V BUFF The noise at the buffer output V has the opposite polarity to the noise at the input voltage VIN_AC. BUFF In response to the noise in the input voltage, power transistor 120 cancels the noise in the input voltage, VIN_AC, resulting in a reduced noise in the output voltage, VOUT_AC.

[0033] Therefore, the dropout detection module 136 detects whether the voltage difference between the input voltage VIN and the voltage output VOUT exceeds the threshold voltage V THRESH for a time interval that is less than (for example, VOUT-VIN <V THRESH Similarly, the feedforward module 156 selectively activates the feedforward module 156 when the voltage difference between the input voltage VIN and the voltage output VOUT is greater than or equal to the threshold voltage V THRESH for a time interval equal to or greater than (for example, VOUT-VIN>V THRESHIn this manner, the dropout voltage of linear voltage regulator 100 and / or the size of power transistor 120 can be reduced without reducing the power efficiency of linear voltage regulator 100, as opposed to alternative techniques for reducing the dropout voltage.

[0034] 2 is a circuit diagram of a linear voltage regulator 200 that can be used to implement the linear voltage regulator 100 of FIG. 1. The linear voltage regulator 200 implements a linear voltage regulator, such as an LDO. Thus, the linear voltage regulator 200 receives an input voltage VIN and a reference voltage VREF, and outputs an output voltage VOUT to a load 202 and an output capacitor 203 (Cour) in parallel with the load 202. As an example, the output capacitor 203 has a capacitance of approximately 10 microfarads (μF). The output voltage VOUT is calculated based on the load current I LOAD The linear voltage regulator 200 induces a load current I LOAD varies as a function of time and the output voltage V remains approximately constant even in situations where the input voltage V experiences noise such as frequency spurs, voltage flicker, etc. Linear voltage regulator 200 also receives an auxiliary voltage source VHV that provides power to the components of linear voltage regulator 200.

[0035] The linear voltage regulator 200 has a power supply rejection ratio (PSRR) that characterizes the ability of the linear voltage regulator 200 to suppress power supply variations present in the input voltage VIN from the output voltage VOUT. The linear voltage regulator 200 includes an operational amplifier 204, where a reference voltage VREF is provided to a non-inverting input of the operational amplifier 204. The inverting input of the operational amplifier 204 is coupled to a voltage output 208 of the linear voltage regulator 200, which provides the output voltage VOUT. The output V Xis provided to the input of buffer 212. Buffer 212 and op amp 204 have a power supply node coupled to node 210, which is coupled to auxiliary voltage source VHV. Buffer 212 also receives noise-reduced signal VHV from feedforward module 220. NOISE_REJ The buffer 212 includes a control node 216 that receives the output voltage V BUFF to the power transistor 224.

[0036] FIG. 3 shows a circuit diagram of a buffer 300 for a linear voltage regulator, such as linear voltage regulator 200 of FIG. 2. Buffer 300 can be used to implement buffer 212 of FIG. 2. Accordingly, like reference numbers and names are used in FIGS. 2 and 3 to indicate like structures and signals. Buffer 300 includes a positive supply node 304 that is coupled to an auxiliary voltage source VHV. Buffer 300 receives a voltage VHV output from an operational amplifier, such as operational amplifier 204 of FIG. 1. X and an input node 308 receiving a buffer 300V. BUFF Buffer 300 also receives noise-reduced signal V from feedforward module 220 of FIG. NOISE_REJ Buffer 300 also includes a negative power supply node 320 that is coupled to an electrically neutral node (e.g., ground or virtual ground) of the linear voltage regulator.

[0037] Buffer 300 includes a first NFET 324 having a gate coupled to input node 308 and a source coupled to output node 312. Buffer 300 also includes a second NFET 328 having a source coupled to output node 312 of buffer 300. The gate of second NFET 328 is coupled to the output node of super source follower 330. Buffer 300 also includes a first PFET 332, a second PFET 336, and a third PFET 340, each having a source coupled to positive power supply node 304. The gate of first PFET 332 and the drain of first PFET 332 are also coupled together at node 342. The drain of first PFET 332 is coupled to the drain of first NFET 324. The gate of the second PFET 336 and the gate of the third PFET 340 are also coupled to node 342. Thus, the second PFET 336 and the third PFET 340 are arranged in a current mirror with the first PFET 332.

[0038] The drain of the second PFET 336 is coupled to the control node 316 of the buffer 300, the input node of the super source follower 330, and a first bias current source 344. The first bias current source 344 is also coupled to the negative power supply node 320. A second bias current source 348 is also coupled between the output node 312 and the negative power supply node 320. A coupling capacitor 352, CGPASS, is coupled in parallel with the second bias current source 348. The drain of the third PFET 340 is coupled to the positive power supply node 356 of the super source follower 330. In operation, the buffer 300 is connected to a voltage source 356 of the buffer 300V. BUFF The output voltage of the input voltage V X to the noise-removed signal V NOISE_REJ Therefore, V BUFF -V X +V NOISE_REJ is.

[0039] FIG. 4 shows a circuit diagram of a super source follower 400 that can be used as super source follower 330 of FIG. 3. As such, the same reference numbers and names are used in FIGS. 3 and 4 to indicate the same structures and signals. Super source follower 400 includes a control node 404 and an output node 408. Control node 404 receives an input voltage VIN, and output node 408 provides an output voltage VOUT. Super source follower 400 includes a positive power supply node 412 coupled to a drain voltage VDD and a negative power supply node 416 coupled to an electrically neutral node (e.g., ground or virtual ground).

[0040] Super source follower 400 includes a PFET 420 and an NFET 424. The source of PFET 420 and the drain of NFET 424 are coupled to an output node 408. A first current source 432 is also coupled to a positive power supply node 412 and provides a first current I1 that flows from the positive power supply node 412 to the output node 408. The gate of NFET 424 and the drain of PFET 420 are also coupled to a node 436. The source of NFET 424 is coupled to a negative power supply node 416 of super source follower 400. A second current source 440 is also coupled between node 436 and the negative power supply node 416.

[0041] In operation, super source follower 400 acts as a buffer such that the output voltage VOUT of super source follower 400 is approximately equal to the input voltage VIN. TIFF0007783271000001.tif412 Also, because the input voltage VIN is provided to the gate of PFET 420, super source follower 400 has a high input impedance (eg, 1 megaohm or greater).

[0042] 2, in linear voltage regulator 200, power transistor 224 is implemented as an NFET. Also, the output voltage V of buffer 212 BUFFis provided to a node 228 that is coupled to the gate (e.g., control node) of power transistor 224. The drain (input node) of power transistor 224 is coupled to a voltage input 232 of linear voltage regulator 200 that is coupled to input voltage V, and the source (output node) of power transistor 224 is coupled to a voltage output 208 of linear voltage regulator 200.

[0043] The output of buffer 212 is also provided to dropout detection module 240. Dropout detection module 240 includes a control node 242 coupled to node 228 and an output node 246 coupled to feedforward module 220. Dropout detection module 240 also includes a power input node 248 coupled to voltage input 232, which is coupled to input voltage V, and a power output node 250 coupled to voltage output 208, which provides output voltage V for linear voltage regulator 200.

[0044] Dropout detection module 240 includes a voltage source 252, a first NFET 254, and a second NFET 258. First NFET 254 is alternatively referred to as a sense transistor or sense NFET, and second NFET 258 is alternatively referred to as a boost transistor or boost NFET. First NFET 254 of dropout detection module 240 is a scaled-down version of power transistor 224. More specifically, power transistor 224 has a channel size that is approximately three orders of magnitude larger (1000 times larger) than the channel size of first NFET 254. A gate of first NFET 254 is coupled to control node 242 of dropout detection module 240, and consequently, the gate of first NFET 254 is also coupled to the gate of power transistor 224. Additionally, the source of the first NFET 254 is coupled to the power output node 250 of the dropout detection module 240 , and the drain of the first NFET 254 is coupled to the output node 246 of the dropout detection module 240 .

[0045] Figure 5 shows a circuit diagram of a dropout detection module 500 for a linear voltage regulator, such as linear voltage regulator 200 of Figure 2. Dropout detection module 500 can be used to implement dropout detection module 240 of Figure 2. Accordingly, like reference numbers and names are used in Figures 5 and 4 to indicate like structures and signals. Dropout detection module 500 includes a power input node 504 coupled to an input voltage V, such as input voltage V of Figure 1. Dropout detection module 500 also includes a power output node 508 coupled to the output node of the voltage regulator, such that an output voltage V is applied to power output node 508.

[0046] The dropout detection module 500 includes a control node 512 coupled to the output of a buffer (e.g., buffer 212 in FIG. 2) and configured to control the buffer output voltage V BUFF is applied to the control node 512. The dropout detection module 500 detects the PSRR signal V PSRR The dropout detection module 500 includes an output node 514 that provides a bias current I. The dropout detection module 500 includes a first NFET 516 and a second NFET 520. The first NFET 516 can be used to implement the first NFET 254 of the dropout detection module 240 of FIG. 2, and the second NFET 520 can be used to implement the second NFET 258 of the dropout detection module 240 of FIG. 2. The dropout detection module 500 includes a bias current I BIAS and a resistor 528. As an example, the bias current I BIAS is approximately 8 microamperes (μA).

[0047] The gate of first NFET 516 is coupled to control node 512. The source of first NFET 516 is also coupled to power output node 508, and the drain of first NFET 516 is coupled to output node 514 of dropout detection module 500. A current source 524 is coupled to power input node 504 and to the gate of second NFET 520 at node 532. A resistor 528 is also coupled to node 532. The drain of second NFET 520 is coupled to power input node 504. Current source 524 induces a voltage drop of delta voltage ΔV across resistor 528. Thus, the voltage level at the gate of second NFET 520 is greater than the voltage level at the gate of first NFET 516 by delta voltage ΔV. Thus, the combination of current source 524 and resistor 528 provides voltage source 252 of FIG. 2 .

[0048] 2, voltage source 252 provides a voltage drop equal to the delta voltage ΔV between the gate of first NFET 254 and the gate of second NFET 258. Thus, the positive terminal of voltage source 252 is coupled to the gate of second NFET 258, and the negative terminal of voltage source 252 is coupled to the gate of first NFET 254 and to control node 242 of dropout detection module 240. The source of second NFET 258 is coupled to output node 246 of dropout detection module 240, such that the source of second NFET 258 is coupled to the drain of first NFET 254. The drain of second NFET 258 is coupled to power input node 248 of dropout detection module 240, such that the drain of second NFET 258 is coupled to input voltage VIN.

[0049] The feedforward module 220 includes a control node 264 coupled to the output node 246 of the dropout detection module 240 and an output node 268 coupled to the control node 216 of the buffer 212. The feedforward module 220 also includes a positive power supply node 272 coupled to the auxiliary supply voltage VHV and a negative power supply node 274 coupled to an electrically neutral node (e.g., ground or virtual ground) of the linear voltage regulator 200.

[0050] The feed-forward module 220 includes a first current source 276 and a second current source 278, as well as a third NFET 280 and a fourth NFET 282. The first current source 276 provides a bias current I from the positive power supply node 272 to the drain and gate of the third NFET 280. BIAS , so that the drain and gate of the third NFET 280 are coupled together. The source of the third NFET 280 is coupled to the negative power supply node 274 of the feedforward module 220. A second current source 278 provides a bias current I from the positive power supply node 272 to the drain of the fourth NFET 282. BIAS The source of the fourth NFET 282 is coupled to the negative power supply node 274 of the feedforward module 220. As an example, I BIAS is about 8 μA.

[0051] The third NFET 280 and the fourth NFET 282 are connected as a current mirror, so that the drain current I BIAS equals the drain current on the third NFET 280. The gate of the third NFET 280 is connected to a power supply rejection resistor 284 (R PSRR ) is coupled to a first node of power supply rejection ratio resistor 284. By way of example, power supply rejection ratio resistor 284 has a resistance of approximately 2 megaohms (MΩ). A second node of power supply rejection ratio resistor 284 is coupled to node 286. Node 286 is coupled to the gate of fourth NFET 282 and power supply rejection ratio capacitor 288 (C PSRR ) to a first node of the power supply rejection ratio capacitor 288. By way of example, the power supply rejection ratio capacitor 288 has a capacitance of approximately 20 picofarads (pF). A second node of the power supply rejection ratio capacitor 288 is coupled to the control node 264 of the feedforward module 220.

[0052] In operation, buffer 212 converts the voltage signal V output by operational amplifier 204 X , and a buffered voltage signal V BUFFIt outputs a buffered voltage signal V BUFF In response to this, power transistor 224 generates a buffered voltage signal V BUFF The linear voltage regulator 100 provides an output voltage VOUT to a load 202 that varies as a function of VREF. If the output voltage VOUT rises too high relative to the reference voltage VREF, the linear voltage regulator 100 reduces the buffered voltage signal VREF. BUFF is configured to be regulated to control power transistor 120 to maintain a constant output voltage VOUT.

[0053] As shown, the drain-source voltage V of the power transistor 224 DS is the input voltage VIN of the linear voltage regulator 200 minus the output voltage VOUT (for example, V DS Therefore, the difference between the input voltage VIN and the output voltage (VIN-VOUT) is equal to the threshold voltage V THRESH In the situation where V is equal to or greater than V, the power transistor 224 operates in the saturation region, and as a result, noise injected into the input voltage V is filtered by the buffer 212. The input voltage V minus the output voltage V (V - V) is the drain-source voltage V of the power transistor 224. DS Therefore, in some instances, the threshold voltage V THRESH is set to a voltage level approximately equal to the overdrive voltage Vov of power transistor 224.

[0054] The noise injected into the input voltage VIN is represented as VIN_AC. The noise in the output voltage VOUT is represented as VOUT_AC. When the power transistor 224 operates in the saturation region, VOUT_AC is at least one order of magnitude smaller (1 / 10) than VIN_AC. For example, the threshold voltage V THRESHis equal to 1 V and the voltage VOUT is at least 1 V less than the input voltage VIN, the power transistor 224 operates in the saturation region, and the operational amplifier 204, the buffer 212, and the power transistor 224 work in concert to filter the noise VIN_AC present in the input voltage VIN. Also, during the interval when the power transistor 224 operates in the saturation region, V PSRR_AC The PSRR signal V PSRR The noise component of V is reduced to approximately 0 V. Specifically, when power transistor 224 operates in the saturation region, both first NFET 254 and second NFET 258 also operate in the saturation region, which reduces the PSRR signal V at output node 246 of dropout detection module 240. PSRR (Noise component V PSRR_AC ) to a level of approximately 0 volts. Thus, during these intervals when first NFET 254 and second NFET 258 are operating in the saturation region, the PSRR signal V PSRR is deasserted.

[0055] However, when VIN-VOUT is equal to the threshold voltage V THRESH , the power transistor 224 and the first NFET 254 of the dropout detection module 240 will LOAD , and transitions from operating in the saturation region to the linear region, such as by responding to an increase in V. As noted, first NFET 254 is a scaled-down version of power transistor 224, with the gate of first NFET 254 coupled to the gate of power transistor 224. Thus, as power transistor 224 transitions from the saturation region to the linear region, first NFET 254 also transitions from the saturation region to the linear region. Dropout detection module 240 also detects a threshold voltage V, which is experimentally determined. THRESH Smaller (e.g., AV <V THRESH) delta voltage ΔV. Due to the delta voltage ΔV, when the first NFET 254 transitions from the saturation region to the linear region, the second NFET 258 remains in the saturation region, and therefore the voltage at the output node 246 increases as the first NFET 254 transitions from the saturation region to the linear region. In this way, the PSRR signal V PSRR is asserted at the output node 246 of the dropout detection module 240. Thus, the second NFET 258 and the first NFET 254 of the dropout detection module 240 assert the buffered voltage signal V BUFF The voltage difference between the input voltage VIN and the output voltage VOUT reaches a threshold voltage V THRESH If the PSRR signal V PSRR (This is the noise component V PSRR_AC ) to transition the power transistor 224 into the linear region. In this situation, the noise V PSRR_AC is the noise in the input voltage, V IN_AC In other words, the dropout detection module 240 calculates the amplified version of VOUT-VIN <V THRESH If the PSRR signal V PSRR The dropout detection module 240 also asserts a threshold voltage V THRESH , indicating that the power transistor 224 is transitioning into the saturation region, the PSRR signal V PSRR Deassert

[0056] The feedforward module 220 outputs the (asserted) PSRR signal V PSRR , and the power supply rejection ratio capacitor 288 receives the PSRR signal V PSRR This blocks the direct current (DC) portion of the PSRR signal, V PSRR_ACis provided to node 286 and amplified by the fourth NFET 282 of the feedforward module 220. In particular, the drain of the fourth NFET 282, which is coupled to the output node 268 of the feedforward module 220, receives the noise-reducing signal V NOISE_REJ (alternatively called a feedforward signal), which is the PSRR signal V PSRR_AC is an amplified and inverted version of , which is the noise in the input voltage V IN_AC Conversely, the PSRR signal V PSRR In response to the deassertion of V, the feedforward module 220 generates the noise cancellation signal V NOISE_REJ In this manner, the dropout detection module 240 and the feedforward module 220 work in concert to selectively provide a PSRR boost.

[0057] Noise-removed signal V NOISE_REJ In response to the injection of V, the buffer 212 and the power transistor 224 operate in concert to filter noise in the input voltage V. More specifically, the noise-rejecting signal V NOISE_REJ The injection of noise at the input voltage causes an inverted version of VIN_AC to be injected into the output V of buffer 212. BUFF Therefore, the input voltage noise V IN_AC is included in the signal driving the gate of power transistor 224, so that power transistor 224, during operation in the linear region, amplifies the input voltage V, and thereby removes the noise component V from the input voltage. IN_AC As a result, the output voltage noise VOUT_AC is reduced.

[0058] Therefore, the dropout detection module 240 detects whether the voltage difference between the input voltage VIN and the voltage output VOUT exceeds the threshold voltage V THRESH for a time interval that is less than (for example, VOUT-VIN <V THRESH ), selectively activating the feedforward module 220. For example, the PSRR signal V PSRR is the load current I LOADThe voltage difference between the input voltage VIN and the output voltage VOUT is the threshold voltage V THRESH Similarly, the feedforward module 220 is configured to assert the voltage VOUT when the voltage difference between the input voltage VIN and the voltage output VOUT exceeds a threshold voltage V THRESH for a time interval equal to or greater than (for example, VIN-VOUT>V THRESH In this manner, the dropout voltage of linear voltage regulator 200 and / or the size of power transistor 224 can be reduced without reducing the power efficiency of linear voltage regulator 200, as opposed to alternative techniques for reducing the dropout voltage.

[0059] 6 shows a graph 600 including a plot of voltage gain Av in decibels (dB) of noise as a function of frequency in Hertz (Hz) using Equation 1. Graph 600 includes a first plot using PSRR boost with linear voltage regulator 200, where delta voltage ΔV is set to 200 millivolts (mV) and V for power transistor 224 is DS The V - V defining the linear voltage regulator is 400 mV. For comparison purposes, graph 600 also includes a second plot using an alternative voltage regulator circuit in which dropout detection module 240 and feedforward module 220 of FIG. 2 are omitted, resulting in a linear voltage regulator operating without PSRR boosting. Graph 600 plots noise gain (V / V ), so that a lower gain (A) (more negative) corresponds to improved performance for the linear voltage regulator. Equation 1: Av=20 log(VOUT_AC / VIN_AC)

[0060] As shown, the PSRR boost provided by the dropout detection module 240 and the feedforward module 220 of the linear voltage regulator 200 is approximately 1 kHz (10 3 Hz) to approximately 1MHz (10 6The MOSFET provides increased PSRR against noise at frequencies above 100 kHz (Hz).

[0061] 7 shows a graph 700 that plots voltage gain Av in decibels (dB) of noise as a function of frequency in Hertz (Hz) using Equation 1. Graph 700 shows that as V−V decreases for linear voltage regulator 200 of FIG. 2, PSRR increases. As noted, in linear voltage regulator 200, V−V is the voltage across power transistor 224 of linear voltage regulator 200. DS In graph 700, the delta voltage ΔV is set to 200 mV and the load current I LOAD is set to 5 amps (A). Each of the graphs 700 includes a first plot with PSRR boosting using linear voltage regulator 200 and a second plot with an alternative voltage regulator circuit, where dropout detection module 240 and feedforward module 220 of FIG. 2 are omitted, resulting in the linear voltage regulator operating without PSRR boosting. Graph 700 includes a first graph 710 with V - V of 1 V and a second graph 720 with V - V of 500 mV. Graph 700 also includes a third graph 730 with V - V of 400 mV and a fourth graph 740 with V - V of 300 mV.

[0062] As shown in graph 600 of FIG. 6 and graph 700 of FIG. 7, V DS As power transistor 224 transitions from the saturation region to the linear region (and V - V) decreases, the PSRR boost increases the PSRR provided by dropout detection module 240 and feedforward module 220 of linear voltage regulator 200. Also, as illustrated by first graph 710 of graph 700, power transistor 224 operates in the saturation region (e.g., V of power transistor 224 decreases). DSis greater than or equal to 1 V), the PSRR boost provides very little benefit. Therefore, as described above, the dropout detection module 240 adjusts the PSRR signal V PSRR . . . selectively assert or deassert.

[0063] 8 shows a graph 800 plotting voltage gain Av in decibels (dB) of noise as a function of frequency in Hertz (Hz) using Equation 1. Graph 800 shows the output current I for linear voltage regulator 200 of FIG. LOAD , which is the input voltage VIN minus the output voltage VOUT minus (VIN-VOUT), which also shows that the PSRR increases over the range of VOUT of the power transistor 224. DS , which remains constant at 400 mV. In graph 700, the delta voltage ΔV is set to 200 mV. Each of graphs 700 includes a first plot using linear voltage regulator 200 with PSRR boosting and a second plot using an alternative voltage regulator circuit, where dropout detection module 240 and feedforward module 220 of FIG. 2 are omitted, resulting in the linear voltage regulator operating without PSRR boosting. Graph 800 shows the results of a 0.2 A output current I LOAD and a first graph 810 with an output current I of 1 A. LOAD and a second graph 820 having an output current I of 5 A. LOAD As shown by graph 800, the performance of linear voltage regulator 200 with PSRR boost is consistent over a relatively wide range of output current I LOAD Improves against.

[0064] FIG. 9 shows another circuit diagram of a linear voltage regulator 900 that can be used to implement the linear voltage regulator 100 of FIG. 1. The linear voltage regulator 900 implements a linear voltage regulator circuit, such as an LDO. Thus, the linear voltage regulator 900 receives an input voltage VIN, a reference voltage VREF, and outputs an output voltage VOUT to a load 902 and an output capacitor 903 (Cour) in parallel with the load 902. By way of example, the output capacitor 903 has a capacitance of approximately 150 picofarads (pF). The output voltage VOUT is determined by the load current I at the load 902. LOAD The linear voltage regulator 900 induces a load current I LOAD The linear voltage regulator 900 is configured such that the output voltage V remains substantially constant even in situations where V varies as a function of time and the input voltage V experiences noise such as frequency spurs, voltage flicker, etc. In the illustrated example, the input voltage V powers the components of the linear voltage regulator 900, such that the linear voltage regulator 900 has a single voltage source, namely the input voltage V.

[0065] The linear voltage regulator 900 has a power supply rejection ratio (PSRR) that characterizes the ability of the linear voltage regulator 900 to suppress power supply variations present in the input voltage VIN from the output voltage VOUT. The linear voltage regulator 900 includes an operational amplifier 904, where a reference voltage VREF is provided to an inverting input of the operational amplifier 904. A non-inverting input of the operational amplifier 904 is coupled to a voltage output 908 of the linear voltage regulator 900, which provides the output voltage VOUT. The output V of the operational amplifier 904 is X is provided to the input of a buffer 912. The buffer 912 and the operational amplifier 904 have a power supply node coupled to a voltage input 910 that is coupled to a linear voltage regulator 900 that is coupled to an input voltage V. The buffer 912 also receives a noise-rejected signal V from a feedforward module 920. NOISE_REJ The buffer 912 includes a control node 916 that receives the output voltage V BUFF to power transistor 924.

[0066] FIG. 10 shows a circuit diagram of a buffer 1000 for a linear voltage regulator, such as linear voltage regulator 900 of FIG. 9. Buffer 1000 can be used to implement buffer 912 of FIG. 9. Accordingly, the same reference numbers and names are used in FIGS. 9 and 10 to indicate the same structures and signals. Buffer 1000 includes a positive power supply node 1004 that is coupled to an input voltage V. Buffer 1000 also includes a positive power supply node 1004 that is coupled to an input voltage V. The buffer ... output voltage V from an operational amplifier, such as operational amplifier 904 of FIG. 9. X an input node 1008 receiving a buffer 1000V BUFF Buffer 1000 also includes a control node 1016, which receives the noise-reduced signal V from feedforward module 920 of FIG. NOISE_REJ Buffer 1000 also includes a negative power supply node 1020 coupled to an electrically neutral node (e.g., ground or virtual ground) of the linear voltage regulator. A current source 1022 is coupled between negative power supply node 1020 and output node 1012. Current source 1022 provides a bias current I BIAS flows from the output node 1012 to the negative power supply node 1020. As an example, the bias current I BIAS is approximately 3 microamperes (μA).

[0067] Buffer 1000 includes an NFET 1024 having a gate coupled to input node 1008 and a source coupled to output node 1012. The drain of NFET 1024 is coupled to a control node 1016 of buffer 1000. Buffer 1000 also includes a PFET 1028 having a source coupled to positive power supply node 1004. The gate of PFET 1028 is coupled to control node 1016 and the drain of PFET 1028 is coupled to output node 1012. A resistor 1032 R BUFF is coupled between the positive power supply node 1004 and the control node 1016. In operation, the buffer 1000 outputs an output voltage V BUFF is the input voltage V X Plus noise-removing signal VNOISE_REJ Therefore, The file is TIFF0007783271000002.tif421.

[0068] 9, in linear voltage regulator 900, power transistor 924 is implemented as a PFET. Also, the output voltage V of buffer 912 BUFF is provided to a node 928 that is coupled to the gate (control node) of a power transistor 924. The source (input node) of power transistor 924 is coupled to a voltage input 910 that is coupled to an input voltage V, and the drain (output node) of power transistor 924 is coupled to a voltage output 908 of linear voltage regulator 900.

[0069] The output of buffer 912 is also provided to dropout detection module 940. Dropout detection module 940 includes a control node 942 coupled to node 928 and an output node 946 coupled to feedforward module 920. Dropout detection module 940 also includes a power input node 948 coupled to voltage input 910, which is coupled to input voltage V, and a power output node 950 coupled to voltage output 908, which provides output voltage V for linear voltage regulator 900.

[0070] Dropout detection module 940 includes a voltage source 952, a first PFET 954, and a second PFET 958. The first PFET 954 is alternatively referred to as a sense transistor or sense PFET, and the second PFET 958 is alternatively referred to as a boost transistor or boost PFET. The first PFET 954 of dropout detection module 940 is a scaled-down version of the power transistor 924. More specifically, the power transistor 924 has a channel size that is approximately three orders of magnitude larger (1000 times larger) than the channel size of the first PFET 954. A gate of the first PFET 954 is coupled to a control node 942 of dropout detection module 940, and consequently, the gate of the first PFET 954 is also coupled to the gate of the power transistor 924. Additionally, the source of the first PFET 954 is coupled to a power input node 948 of the dropout detection module 940 , and the drain of the first PFET 954 is coupled to an output node 946 of the dropout detection module 940 .

[0071] The voltage source 952 provides a voltage drop equal to the delta voltage ΔV between the gate of the first PFET 954 and the gate of the second PFET 958. Thus, the positive terminal of the voltage source 952 is coupled to the gate of the first PFET 954 and to the control node 942 of the dropout detection module 940, and the negative terminal of the voltage source 952 is coupled to the gate of the second PFET 958. The source of the second PFET 958 is coupled to the output node 946 of the dropout detection module 940, such that the source of the second PFET 958 is coupled to the drain of the first PFET 954. The drain of the second PFET 958 is coupled to the power output node 950 of the dropout detection module 940, such that the drain of the second PFET 958 is coupled to the output voltage VOUT.

[0072] Figure 11 shows a circuit diagram of a dropout detection module 1100 for a linear voltage regulator, such as linear voltage regulator 900 of Figure 9. Dropout detection module 1100 can be used to implement dropout detection module 940 of Figure 9. Accordingly, like reference numbers and names are used in Figures 9 and 11 to indicate like structures and signals. Dropout detection module 1100 includes a power input node 1104 that is coupled to an input voltage V, such as input voltage V of Figure 1. Dropout detection module 1100 also includes a power output node 1108 that is coupled to the output node of the voltage regulator, such that the output voltage V of the linear voltage regulator is applied to power output node 1108.

[0073] The dropout detection module 1100 includes a control node 1112 that is coupled to the output of a buffer (e.g., buffer 912 of FIG. 9 ) so that the buffer output voltage V BUFF is applied to the control node 1112. The dropout detection module 1100 detects the PSRR signal V PSRR The dropout detection module 1100 includes an output node 1114 that provides a bias current I. The dropout detection module 1100 includes a first PFET 1116 and a second PFET 1120. The first PFET 1116 can be used to implement the first PFET 954 of the dropout detection module 940 of FIG. 9, and the second PFET 1120 can be used to implement the second PFET 958 of the dropout detection module 940 of FIG. 9. The dropout detection module 1100 includes a bias current I BIASThe dropout detection module 1100 also includes a current source 1124 that provides a bias current I. The dropout detection module 1100 also includes a resistor 1128 coupled between the gate of the first PFET 1116 and the gate of the second PFET 1120. More specifically, a first node of the resistor 1128 is coupled to a control node 1112 of the dropout detection module 1100, which is coupled to the gate of the first PFET 1116. A second node of the resistor 1128 is coupled to a node 1129. The node 1129 is coupled to the current source 1124 and the gate of the second PFET 1120. The current source 1124 is also coupled to an electrically neutral node 1130 (e.g., ground or virtual ground). By way of example, a bias current I BIAS is about 3 μA.

[0074] Additionally, the source of a first PFET 1116 is coupled to the power input node 1104, and the drain of the first PFET 1116 is coupled to the output node 1114 of the dropout detection module 1100. The source of a second PFET 1120 is coupled to the output node 1114, and the drain of the second PFET 1120 is coupled to the power output node 1108, which provides the output voltage VOUT of the linear voltage regulator. A current source 1124 induces a voltage drop of a delta voltage ΔV across a resistor 1128. Thus, the voltage level at the gate of the second PFET 1120 is less than the voltage level at the gate of the first PFET 1116 by the delta voltage ΔV. Thus, the combination of the current source 1124 and the resistor 1128 provides the voltage source 952 of FIG. 9 .

[0075] 9, the feedforward module 920 includes a control node 964 coupled to the output node 946 of the dropout detection module 940 and an output node 968 coupled to the control node 916 of the buffer 912. The feedforward module 920 also includes a positive power supply node 972 coupled to the voltage input 910, which is coupled to the input voltage V, and a negative power supply node 974 coupled to an electrically neutral node of the linear voltage regulator 900 (e.g., ground or virtual ground).

[0076] The feed-forward module 920 includes a first current source 976 and a second current source 978, as well as a third PFET 980 and a fourth PFET 982. The first current source 976 supplies a bias current I 1 that flows from the drain and gate of the third PFET 980 to the negative power supply node 974. BIAS so that the drain and gate of the third PFET 980 are coupled together. The source of the third PFET 980 is coupled to the positive power supply node 972 of the feedforward module 920. A second current source 978 provides a bias current I from the positive power supply node 972 to the drain of the fourth PFET 982. BIAS The source of the fourth PFET 982 is coupled to the negative power supply node 974 of the feedforward module 920. As an example, I BIAS is about 3 μA.

[0077] The third PFET 980 and the fourth PFET 982 are coupled as a current mirror so that the current at the drain of the fourth PFET 982 is a current mirror of the drain current I for the third PFET 980. BIAS A gate of the third PFET 980 is coupled to a first node of a power supply rejection ratio resistor 984 (RPSRR). By way of example, the power supply rejection ratio resistor 984 has a resistance of approximately 2 megohms (MΩ). A second node of the power supply rejection ratio resistor 984 is coupled to a node 986. The node 986 is coupled to a gate of the fourth PFET 982 and to a first node of a power supply rejection ratio capacitor 988 (CPSRR). By way of example, the power supply rejection ratio capacitor 988 has a capacitance of approximately 10 picofarads (pF). A second node of the power supply rejection ratio capacitor 988 is coupled to the control node 964 of the feedforward module 920.

[0078] The feed-forward module 920 also includes a first NFET 990 and a second NFET 992. The gate and drain of the first NFET 990 are both coupled to the drain of the fourth PFET 982. The source of the first NFET 990 and the source of the second NFET 992 are coupled to the negative power supply node 974. The gate of the second NFET 992 is coupled to the gate of the first NFET 990, such that the second NFET 992 is arranged in a current mirror configuration with the first NFET 990.

[0079] A second current source 978 is coupled to the positive power supply node 972 and to the drain of a second NFET 992. The drain of the second NFET 992 is also coupled to the output node 968 of the feedforward module 920. Thus, the second current source 978 drives current from the positive power supply node 972 to the output node 968 and to the drain of the second NFET 992.

[0080] In operation, the buffer 912 receives the voltage signal V output by the operational amplifier 904. X , and a buffered voltage signal V BUFF It outputs a buffered voltage signal V BUFF In response to this, power transistor 924 regulates the output voltage VOUT to the buffered voltage signal V BUFF and provides a load 902 that varies as a function of the input voltage V. The linear voltage regulator 900 generates a buffered voltage signal V when the output voltage V is too high compared to the reference voltage V. BUFF is configured to be regulated to control power transistor 120 to maintain a constant output voltage VOUT.

[0081] As shown, the negative drain-source voltage, −V, of power transistor 924 DS is equal to the input voltage VIN minus the output voltage VOUT (VIN-VOUT) of the linear voltage regulator 900. Therefore, the difference between the input voltage VIN and the output voltage (VIN-VOUT) is the threshold voltage V THRESHIn the situation where V is equal to or greater than V, the power transistor 924 operates in the saturation region, so that noise injected into the input voltage V is filtered by the buffer 112. Thus, in some examples, the threshold voltage V THRESH is set to a voltage level approximately equal to the overdrive voltage Vov of power transistor 224.

[0082] The noise injected into the input voltage VIN is represented as VIN_AC. The noise in the output voltage VOUT is represented as VOUT_AC. When the power transistor 924 operates in the saturation region, VOUT_AC is at least one order of magnitude smaller (1 / 10) than VIN_AC. For example, the threshold voltage V THRESH is equal to 1 V and the voltage VOUT is at least 1 V less than the input voltage V, the power transistor 924 operates in the saturation region and filters the noise V_AC present in the input voltage V. Also, when the power transistor 224 operates in the saturation region, both the first PFET 954 and the second PFET 958 operate in the saturation region, thereby filtering the PSRR signal V at the output node 246 of the dropout detection module 940. PSRR (Noise component V PSRR_AC ) to a level of approximately 0 volts. Thus, during these intervals when first PFET 954 and second PFET 958 are operating in the saturation region, the PSRR signal V PSRR is deasserted.

[0083] However, VOUT-VIN (-V of power transistor 924) DS ) is the threshold voltage V THRESH In a situation approaching the load current I LOADThe first PFET 954 transitions from operating in the saturation region to the linear region, such as by responding to an increase in the voltage V. As described above, the first PFET 954 is a scaled-down version of the power transistor 924, and the gate of the first PFET 954 is coupled to the gate of the power transistor 924. Thus, when the power transistor 924 transitions from the saturation region to the linear region, the first PFET 954 also transitions from the saturation region to the linear region. The second PFET 958 remains in the saturation region when the first PFET 954 transitions from the saturation region to the linear region due to the delta voltage ΔV that causes the gate of the second PFET 958 to be ΔV lower than the gate of the first PFET 954. Thus, the voltage at the output node 946 of the dropout detection module 940 increases as the first PFET 954 transitions from the saturation region to the linear region. Thus, the PSRR signal V PSRR is asserted at the output node 946 of the dropout detection module 940. Thus, the second PFET 958 and the first PFET 954 of the dropout detection module 940 assert the buffered voltage signal V BUFF The difference between the voltage level at the input voltage VEST and the voltage level at the output voltage VOUT is equal to the threshold voltage V THRESH If the PSRR signal V PSRR (Noise component V PSRR_AC ) to transition power transistor 924 into the linear region. In this situation, the PSRR signal V PSRR_AC The noise in VIN_AC is an amplified version of the noise in the input voltage. In other words, the dropout detection module 940 <V THRESH When the PSRR signal V PSRR The dropout detection module 940 also asserts a threshold voltage V THRESH , indicating that the power transistor 924 is transitioning into the saturation region, the PSRR signal V PSRR Deassert

[0084] The feedforward module 920 generates the PSRR signal V PSRR , and the power supply rejection ratio capacitor 988 receives the PSRR signal V PSRR This blocks the direct current (DC) portion of the PSRR signal, V PSRR_AC is provided to node 986 and amplified by the fourth PFET 982. The noise component V of the PSRR signal PSRR_AC The amplified version of the noise-rejecting signal V is provided to a current mirror formed by a first NFET 990 and a second NFET 992 and coupled to an output node 968 of the feedforward module 920. NOISE_REJ (alternatively called the feedforward signal) is an amplified and inverted version of the PSRR signal, V PSRR_AC and it is the noise of the input voltage V IN_AC Conversely, the PSRR signal V PSRR In response to the deassertion of V, the feedforward module 920 generates the noise-removing signal V NOISE_REJ In this manner, the dropout detection module 940 and the feedforward module 920 work in concert to selectively provide a PSRR boost.

[0085] Noise-removed signal V NOISE_REJ In response to the injection of noise, the buffer 912 and the power transistor 924 operate in cooperation to filter noise from the input voltage V. More specifically, the noise-rejecting signal V NOISE_REJ The noise injection at the input voltage is buffered to an inverted version of VIN_AC. BUFF Thus, an inverted version of the input voltage noise V IN_AC is included in the signal driving the gate of power transistor 924, so that during amplification of input voltage V IN during linear region operation, power transistor 924 cancels the noise component V IN_AC from the input voltage.

[0086] Therefore, the dropout detection module 940 detects whether the voltage difference between the input voltage VIN and the voltage output VOUT exceeds the threshold voltage V THRESHfor a time interval that is less than (for example, VIN-VOUT <V THRESH ), selectively activating the feedforward module 920. For example, the PSRR signal V PSRR is the voltage difference between the input voltage VIN and the output voltage VOUT. THRESH Load current to a level less than I LOAD Similarly, the feedforward module 920 is configured to increase the voltage difference between the input voltage VIN and the voltage output VOUT by 1 / V. THRESH for a time interval equal to or greater than (for example, VIN-VOUT>V THRESH 900) is deactivated during a time interval where . In this way, the dropout voltage of linear voltage regulator 900 and / or the size of power transistor 924 can be reduced without reducing the power efficiency of linear voltage regulator 900, as opposed to alternative techniques for reducing the dropout voltage.

[0087] An alternative method for increasing the PSRR of a voltage regulator circuit involves reducing the power efficiency of the regulator to increase the available headroom. Instead of such an alternative technique, linear voltage regulator 900 reduces the power efficiency of the noise-rejecting signal V NOISE_REJ to selectively assert to cancel noise present on the input voltage VIN.

[0088] 1, linear voltage regulator 900 uses a PFET as power transistor 924. Using a PFET instead of an NFET as power transistor 924 allows for a single power source, i.e., input voltage V, to power the components of linear voltage regulator 900, at the expense of a larger size required for the PFET than would be required for an NFET with similar operating characteristics.

[0089] 12 shows a graph 1200 including a plot of voltage gain Av in decibels (dB) of noise as a function of frequency in Hertz (Hz) using Equation 1. Graph 1200 includes a first plot with PSRR boost using linear voltage regulator 200, where delta voltage ΔV is set to 120 millivolts (mV) and -V DS The VIN-VOUT ratio that defines the load current I LOAD is assumed to be approximately 1 milliamp (mA). For comparison purposes, graph 1200 also includes a second plot using an alternative voltage regulator circuit, in which dropout detection module 940 and feedforward module 920 of FIG. 9 are omitted, resulting in a linear voltage regulator operating without PSRR boosting. Graph 1200 plots the noise gain (VOUT_AC / VIN_AC), such that a lower (more negative) gain Av corresponds to improved performance of the linear voltage regulator.

[0090] As shown, the PSRR boost provided by the dropout detection module 940 and feedforward module 920 of the linear voltage regulator 900 provides increased PSRR against noise at frequencies between about 1.5 kHz and about 1.2 MHz. Thus, as described above, the dropout detection module 940 generates the PSRR signal V PSRR is selectively asserted and deasserted to avoid loss of power efficiency.

[0091] FIG. 13 shows a block diagram of a system 1300 providing an example application for a linear voltage regulator 1304. The linear voltage regulator 1304 is an LDO voltage regulator circuit that may be implemented with the linear voltage regulator 100 of FIG. 1, the linear voltage regulator 200 of FIG. 2, and / or the linear voltage regulator 900 of FIG. 9. The linear voltage regulator 1304 receives an input voltage V and provides an output voltage V in the manner described above. The linear voltage regulator 1304 also receives a reference voltage V. The linear voltage regulator 1304 limits power supply generated phase noise and clock jitter present on the output voltage V. Thus, the linear voltage regulator 1304 can be used to power high-performance serializers and deserializers (SerDes), analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and radio frequency (RF) components.

[0092] As an example of such RF components, system 1300 includes an in-phase, quadrature (IQ) modulator 1308 and an IQ demodulator 1312. IQ modulator 1308 and IQ demodulator 1312 are powered from an output voltage V provided by a linear voltage regulator 1304 at a positive power supply node VCC. However, system 1300 is only one example of such an application. There are many other applications that would benefit from the use of a linear voltage regulator 1304 to limit power supply generated phase noise and clock jitter present on the output voltage V.

[0093] Modifications in the described embodiments are possible, and other embodiments are possible, within the scope of the claims.

Claims

1. 1. A linear voltage regulator, comprising: a buffer having a first voltage input, a buffer input, a buffer output, and a first control input; a transistor having a second control input coupled to the buffer output, a second voltage input, and a first voltage output; a dropout detection module having a third control input coupled to the second control input, a third voltage input coupled to the second voltage input, a second voltage output coupled to the first voltage output, and a third voltage output; a feedforward module having a feedforward input coupled to the third voltage output and a feedforward output coupled to the first control input; a linear voltage regulator.

2. 2. The linear voltage regulator of claim 1, the dropout detection module: a sense transistor having a fourth control input coupled to the third control input and a fourth voltage input coupled to the third voltage output; a boost transistor having a fifth control input and a fifth voltage output coupled to the third voltage output; a delta voltage source coupled between the fourth and fifth control inputs, the delta voltage source configured to provide a delta voltage between the fourth and fifth control inputs; a linear voltage regulator.

3. 3. The linear voltage regulator of claim 2, the dropout detection module: providing a power supply rejection ratio signal at the third voltage output in response to a difference between the voltage of the second voltage input and the voltage of the second voltage output being less than a threshold; ceasing to provide the power supply rejection ratio signal in response to the difference being equal to or greater than the threshold value. A linear voltage regulator configured as follows:

4. 4. The linear voltage regulator of claim 3, A linear voltage regulator wherein the sense transistor is a scaled down version of the transistor.

5. 4. The linear voltage regulator of claim 3, The linear voltage regulator, wherein the feedforward module is configured to provide a noise rejection signal at the feedforward output in response to the power supply rejection ratio signal.

6. 4. The linear voltage regulator of claim 3, A linear voltage regulator, wherein the threshold is the voltage at which the transistor transitions from a saturated region of operation to a linear region of operation.

7. 7. The linear voltage regulator of claim 6, The linear voltage regulator, wherein the transistor, the sense transistor, and the boost transistor are n-channel field effect transistors (NFETs).

8. 2. The linear voltage regulator of claim 1, A linear voltage regulator, wherein the transistor is a p-channel field effect transistor (PFET).

9. 1. A linear voltage regulator, comprising: a buffer configured to provide a buffered voltage signal; a transistor configured to provide an output voltage based on an input voltage and the buffered voltage signal; a dropout detection module, providing a power supply rejection ratio signal in response to a difference between the input voltage and the output voltage being less than a threshold; ceasing to provide the power supply rejection ratio signal in response to the difference being equal to or greater than the threshold value. the dropout detection module configured to A feedforward circuit module, comprising: providing a noise rejection signal in response to the power supply rejection ratio signal; ceasing to provide the noise rejection signal in response to an absence of the power supply rejection ratio signal; The feedforward circuit module is configured as follows: Including, the buffer is further configured to add noise to the buffered voltage signal in response to the noise removal signal; The linear voltage regulator, wherein the transistor is further configured to filter noise from the input voltage in response to noise applied to the buffered voltage signal.

10. 10. The linear voltage regulator of claim 9, A linear voltage regulator, wherein the threshold is the voltage at which the transistor transitions from a saturated region of operation to a linear region of operation.

11. 11. The linear voltage regulator of claim 10, the transistor has a first channel size; The linear voltage regulator, wherein the dropout detection module includes a sense transistor having a second channel size, the first channel size being at least three orders of magnitude larger than the second channel size.

12. 12. The linear voltage regulator of claim 11, the dropout detection module further includes a boost transistor; The linear voltage regulator, wherein the transistor, the sense transistor, and the boost transistor are n-channel field effect transistors (NFETs).

13. 12. The linear voltage regulator of claim 11, The buffer is configured to provide the buffered voltage signal based on the input voltage.

14. 14. The linear voltage regulator of claim 13, the dropout detection module further includes a boost transistor; The linear voltage regulator, wherein the transistor, the sense transistor, and the boost transistor are p-channel field effect transistors (PFETs).

15. 1. A system comprising:

1. A linear voltage regulator, comprising: a buffer configured to provide a buffered voltage signal; a transistor configured to provide an output voltage based on an input voltage and the buffered voltage signal; a dropout detection module, providing a power supply rejection ratio signal in response to a difference between the input voltage and the output voltage being less than a threshold; ceasing to provide the power supply rejection ratio signal in response to the difference being equal to or greater than the threshold value. the dropout detection module configured to A feedforward circuit module, comprising: providing a noise rejection signal in response to the power supply rejection ratio signal; ceasing to provide the noise rejection signal in response to an absence of the power supply rejection ratio signal; The feedforward circuit module is configured as follows: Including, the linear voltage regulator, wherein the buffer and the transistor are configured to filter noise from the input voltage in response to the noise filtering signal; a load coupled to an output of the linear voltage regulator; Including, The system, wherein the linear voltage regulator is configured to provide a current to the load and to provide a voltage to the load, the current varying as a function of time while the voltage remains constant.

16. 16. The system of claim 15, the dropout detection module is further configured to provide the power supply rejection ratio signal during a time interval in which the current increases to a level where a difference between the input voltage and the output voltage is less than the threshold.

17. 16. The system of claim 15, the transistor is a first NFET; the dropout detection module includes a second NFET having a gate coupled to the gate of the first NFET and a source coupled to the source of the first NFET and to the load, the second NFET being a scaled down version of the first NFET.

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