High-speed single flux quantum pulse multiplier

Abstract

A method for generating an output signal based on a single flux quantum (SFQ) pulse comprises receiving an SFQ pulse and splitting it into a first path and a second path. The split SFQ pulse of the second path is stored in a latch. A second split of the split SFQ pulse of the first path is provided to provide a first output signal and a second output signal of the first path. The second output signal is delayed by a delayed Josephson transmission line (JTL). An output of the delayed JTL is provided to the latch as a clock input. A first output of the first path is recombined with an output of the latch to provide the output signal.

Description

[Technical Field]

[0001] The present disclosure relates generally to superconducting devices, and more particularly to multipliers that may be used in superconducting environments. [Background technology]

[0002] A single flux quantum (SFQ) pulse is formed when the superconducting phase difference across a resistively shunted Josephson junction (JJ) expands by 2π. From the second Josephson relation, the SFQ pulse is

number

[0003] As used herein, a rapid single flux quantum (RSFQ) circuit is a digital electronic circuit that uses superconducting devices such as JJs to process digital signals. In RSFQ logic, information is stored in the form of flux quanta and transmitted in the form of SFQ voltage pulses as described above. Summary of the Invention

[0004] According to various embodiments, circuits and methods are provided for generating an output signal based on a single flux quantum (SFQ) pulse. An SFQ pulse is received. The SFQ pulse is split into a first path and a second path. The split SFQ pulse of the second path is stored in a latch. A second split of the split SFQ pulse of the first path is provided to provide a first output signal and a second output signal of the first path. The second output signal is delayed by a delayed Josephson transmission line (JTL). The output of the delayed JTL is provided to the latch as a clock input. The first output of the first path is recombined with the output of the latch to provide the output signal.

[0005] In one embodiment, the latch is a D-latch, and the split SFQ pulse of the second path is stored in the latch as a circulating supercurrent.

[0006] In one embodiment, the recombination of the first output of the first path with the output of the latch is through a confluence buffer.

[0007] In one embodiment, the split SFQ pulses are passed to a first splitter through one or more Josephson transmission lines (JTLs), and the output of the latch is passed to a confluence buffer through one or more JTLs.

[0008] In one embodiment, the delay JTL has a serial chain of n JTL stages, each with a nominal current bias that results in a delay Δt, where Δt=n×Δt′, where Δt′ is the temporal pulse delay per JTL stage.

[0009] In one embodiment, the delay JTL has a serial chain of n JTL stages, resulting in a delay Δt=n×Δt′(I b ), where Δt'(I b ) is the bias current I b is the temporal pulse delay per JTL stage as a function of

[0010] In one embodiment, the delay JTL has a serial chain of n JTL stages, each stage contributing a delay

number

[0011] In one embodiment, the even order of frequency multiplication of the received SFQ pulses reduces the delay of the delay JTL by Δt / 2 n whereby the output train of pulses in the output signal is Δt / 2 n where Δt is the input pulse-to-pulse time interval and n is the number of pulse doubler stages in the serial chain of N cascaded stages. For each doubler stage n in the chain of N cascaded doublers, the inter-pulse interval is Δt / 2 n After N stages, the final inter-pulse spacing is Δt / 2 N is.

[0012] In one embodiment, odd orders of frequency multiplication of the received SFQ pulses are provided by providing at least two serially cascaded stages of the method, the first stage having a delay JTL set to 2Δt / 3 and a second delay JTL set to Δt / 3, where Δt is the spacing between input signal pulses.

[0013] These and other features will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings. [Brief explanation of the drawings]

[0014] The drawings are of exemplary embodiments. They do not depict all embodiments. Other embodiments may be used in addition or instead. Details that may be obvious or unnecessary may be omitted to save space or for a more effective illustration. Some embodiments may be practiced using additional components or steps and / or without all components or steps that are shown. When the same numeral appears in different drawings, it refers to the same or similar components or steps.

[0015] [Figure 1] FIG. 1 is a block diagram of a pulse doubler consistent with an illustrative embodiment.

[0016] [Figure 2A] 1 provides a circuit diagram of an example RSFQ pulse splitter consistent with exemplary embodiments.

[0017] [Figure 2B] FIG. 1 is a circuit diagram of an example RSFQ coalescing buffer consistent with exemplary embodiments.

[0018] [Figure 2C] FIG. 1 is a circuit diagram of an example Josephson transmission line consistent with illustrative embodiments.

[0019] [Figure 2D] FIG. 1 is a circuit diagram of an example D-latch circuit consistent with exemplary embodiments.

[0020] [Figure 3] FIG. 1 is a conceptual block diagram of pulse frequency doubling for even orders of multiplication, consistent with exemplary embodiments.

[0021] [Figure 4] FIG. 1 is a conceptual block diagram of pulse frequency multiplication to achieve odd order, consistent with exemplary embodiments.

[0022] [Figure 5] FIG. 10 is a conceptual block diagram of another pulse frequency multiplier achieving odd order consistent with exemplary embodiments.

[0023] [Figure 6] FIG. 1 is a conceptual block diagram of a pulse frequency multiplier capable of achieving any order of multiplication, both even or odd, consistent with exemplary embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0024] [overview] In the following detailed description, numerous specific details are set forth by way of example to provide a thorough understanding of the relevant teachings. However, it will be apparent that the present teachings may be practiced without such details. In other instances, well-known methods, procedures, components, and / or circuits have been described at a relatively high-level, without detailed description, in order to avoid unnecessarily obscuring aspects of the present teachings.

[0025] This disclosure relates generally to superconducting devices, and more particularly to RSFQ pulse multipliers that can be used in superconducting environments. RSFQ electronics have traditionally operated at very low voltages (e.g., multiples of tens of microvolts). Such low voltage operation has made it difficult to interface between RSFQ and complementary metal oxide semiconductor (CMOS) to combine the two technologies. Furthermore, measuring such small voltages is difficult and typically requires room temperature amplification. The cause of the small operating voltage is the quantum mechanical relationship between operating frequency and voltage: superconducting flux quantum Φ = 2.067 × 10 -15 W. In this regard, note that the frequency to voltage conversion is simply V = Φ*frequency. For example, with Φ a microwave circuit will only produce microvolts of DC voltage.

[0026] In various embodiments, the teachings herein provide a frequency multiplier that can provide even or odd multiples of the original input frequency of an SFQ signal. The SFQ pulse is split into separate paths, and the split SFQ pulse on the second path is stored in a latch, such as a D-latch. The split SFQ pulse on the first path is split again through a second splitter, with one pulse sent to the output and the other sent through a delay JTL to the CLK input of the latch. The first and second paths are then recombined through a confluence buffer. In one aspect, a variable level of multiplication can be selected by adjusting the delay via a current bias. If two cascaded stages have the same delay time and only a single pulse is added to the train, a factor of 1+n to 2^n can be achieved for N-stage multiplication, assuming all delay JTLs use the same number of stages. Each of these concepts is described in more detail below. Block Diagram Example

[0027] FIG. 1 is a block diagram of a pulse doubler 100 consistent with an example embodiment. The pulse doubler 100 includes a first splitter 102 having a first output O1 and a second output O2. There is a second splitter 106 coupled to the first output O1 of the first splitter 102. There is a delay element 108 coupled to a second output O2′ of the second splitter 106. In one embodiment, the delay element 108 is a Josephson transmission line (JTL) operable to provide a delay, as described in more detail below. There is a latch 110 having a data input coupled to the second output O2 of the first splitter 102 and a clock input coupled to the output of the delayed JTL 108. In one embodiment, the latch is a D-latch. There is a recombination circuit 120 configured to receive the first output O1′ of the second splitter 106 and the output of the latch 110 and provide a recombined output. In one embodiment, the recombination circuit 120 is a confluence buffer.

[0028] In one embodiment, there are one or more Josephson transmission lines (JTLs) coupled between the first output O1 of the first splitter 102 and the input of the second splitter 106. Similarly, there may be one or more JTLs coupled between the output of the latch 110 and the second input of the recombiner circuit 120.

[0029] A single SFQ pulse 130 enters a first splitter circuit 102, where two copies are generated and passed to a first (e.g., upper) and second (e.g., lower) track, respectively. The lower track pulse is provided to a latch (e.g., D latch) circuit 110 at its DATA input, where the signal is stored as a circulating supercurrent.

[0030] The upper track pulse is fed to a second splitter 106, where the first (upper track) split SFQ pulse is copied to provide two separate signals. The split SFQ signal at the second output O2′ of the second splitter 106 may be referred to herein as the upper track copy and is provided to a delay JTL 108. In various embodiments, the delay JTL 108 may have different configurations. For example, the delay JTL 108 may have a series chain of n JTL stages, each having a nominal current bias that results in a delay Δt=n×Δt′, where Δt′ is the temporal pulse delay per JTL stage.

[0031] In one embodiment, the delay JTL 108 comprises a serial chain of n JTL stages, with the resulting delay being Δt=n×Δt′(I b ), and configured to receive a controllable global bias current (e.g., by a user on a controller) such that Δt'(I b ) is the bias current I b is the temporal pulse delay per JTL stage as a function of

[0032] In one embodiment, the delay JTL 108 comprises a serial chain of n JTL stages, each of which introduces a delay of

number

[0033] The copy upper track at its output O2' of the second splitter 106, delayed by the delay JTL 108, is provided to the CLK input of the D latch, which triggers the second output O2 of the first splitter 102 to be released from the D latch 110 and passed to the confluence buffer 120 via the lower track JTL 112.

[0034] Both the upper track pulse provided at the output O1' of the second splitter 106 and the time-delayed lower track pulse provided at the output of the D latch 110 (possibly via JTL 112) are combined into a single track via a recombination circuit (e.g., a merging buffer) 120 resulting in two pulses 140 with a time separation Δt. Circuit Component Examples

[0035] 2A-2D provide examples of different building blocks of the pulse doubler 100 of FIG. 1 consistent with exemplary embodiments. More specifically, FIG. 2A provides a circuit diagram of an example RSFQ pulse splitter. A single input SFQ pulse arriving at input IN202 triggers junctions J1, J2, and J3 to generate output SFQ pulses at output terminals O1 (204) and O2 (206), each representing a copy of the input SFQ pulse.

[0036] FIG. 2B is a circuit diagram of an example RSFQ confluence buffer. A pulse arriving at input IN1 (222) triggers junctions J1, J4, and J5. Junction J5 switching provides an output pulse at O ​​(226), while the series of junctions J4 prevents backpropagation of the pulse from IN1 to IN2. A pulse arriving at IN2 (224) triggers junctions J2, J3, and J5. Junction J5 switching provides an output pulse at O ​​(226), while the series of junctions J3 prevents backpropagation of the pulse from IN2 to IN1. If pulses arriving at IN1 (222) and IN1 (224) are separated in time, two separate pulses will be received at output O (226). If pulses arriving at IN1 and IN2 are equivalent in time, only a single output pulse will be generated at O ​​(226). FIG. 2C is a circuit diagram of an example Josephson transmission line. An RSFQ pulse arriving at input IN (242) triggers junctions J1 and J2, sequentially generating a single SFQ pulse at output 244.

[0037] 2D is a circuit diagram of an example D-latch circuit. An SFQ pulse arriving at the DATA port 260 is stored as a circulating current in storage inductor 262, which forward-biases junction J1 (264). When a pulse arrives at the CLK port, the combination of the storage current and the pulse current triggers junction J1 (264), which generates an SFQ pulse at output O (268). If an SFQ pulse does not arrive at the DATA input 260 during a particular clock cycle, the CLK pulse drops across junction J2 (266), and no output 268 is generated. Explanation of even and odd frequency multiplication

[0038] Reference is now made to Figure 3, which is a conceptual block diagram 300 of pulse frequency doubling with even orders of multiplication, consistent with an exemplary embodiment. A pulse train 330 having an interval Δt between pulses is provided to a pulse doubler circuit 312. In the example of Figure 3, the delay between the upper and lower tracks is set to Δt / 2, such that the output train of pulses 340 now has an interval Δt / 2 between pulses, thereby effectively doubling the frequency of the input pulse train 330. Δt / 2 n Cascaded stages of pulse doublers with sequential upper and lower track delays of , where n indicates how many stages the pulse doubler has, can achieve a 2^N factor of multiplication of the initial pulse train frequency, where N is the total number of pulse doubler stages.

[0039] For example, exponential frequency multiplication is performed with a delay of Δt / 2 for each stage. n This can be achieved by cascading stages where n is the number of stages, and the total frequency multiplication will be 2^N, where N is the total number of stages.

[0040] The teachings herein also support odd orders of frequency multiplication. In this regard, FIG. 4 provides a conceptual block diagram 400 of pulse frequency multiplication to achieve odd orders consistent with exemplary embodiments. To achieve odd orders of multiplication in the initial pulse train 402 frequency, two cascaded minimum pulse doublers, represented by first and second doublers 412 and 424, respectively, are used.

[0041] In the example of FIG. 4, a pulse train 402 with an inter-pulse interval of Δt is applied to a first pulse doubler 412. Different patterns of pulses (e.g., dashed vs. solid) are used to better visually separate certain periods from others. The initial pulse train 402 is fed into the first pulse doubler circuit 412, and the delay between the upper and lower track pulses is designed to be 2Δt / 3. For example, to achieve a set delay for a known specific inter-pulse interval, the number of stages in the delay JTL can be determined via numerical modeling. For delay JTLs with bias current control, the delay can be dynamically controlled to accommodate different inter-pulse intervals. For two pulses 402 applied, a total of four pulses are generated, with the delay between the first, second, third, and fourth pulses being 2Δt / 3, and the delay between the second and third pulses being Δt / 3.

[0042] This train of pulses 416 is then passed to a second pulse doubler 422, where the delay time between the upper and lower tracks is set to Δt / 3. Because the delay of the second pulse doubler is equal to the interpulse spacing between the second and third pulses originating from the first stage doubler 412 in pulse train 416, the upper track pulse (3) and the delayed lower track pulse (2) arrive at the second stage pulse doubler 422 output merging buffer at the same time, resulting in a single output pulse (dotted waveform 423 in pulse train 424). Pulse doubler 422 has a merging buffer at its output. This alignment in time facilitates odd-order multiplication.

[0043] Other odd orders of multiplication are also contemplated by the teachings herein. For example, odd orders of multiplication can also be achieved by two pulse doublers with the same delay time. In this regard, reference is made to FIG. 5, which is a conceptual block diagram 500 of another pulse frequency multiplier achieving odd orders consistent with exemplary embodiments. In the embodiment of FIG. 5, an incoming SFQ signal 502 has a period of 3Δt. As each pulse reaches the first pulse doubler 512, a copy of each signal is formed and delayed by Δt (e.g., the doubler may introduce a delay via a delay JTL), resulting in two pairs of pulses separated by Δt, with a 2Δt separation between the pairs. These four pulses 516 are then passed to the second pulse doubler 522.

[0044] The second pulse doubler 522 then forms a total of eight pulses, but with synchronized timing, the output of the duplicated pulse resulting from the first (dashed) pulse in each pair aligns with the trailing (solid black) pulse, which, when combined accordingly in the confluence buffer described above, results in a single output pulse. The process is repeated for the second pair of pulses resulting from the first pulse doubler 512, ultimately resulting in a total of six pulses 524 (or a frequency multiplication of three). In this way, any odd order of multiplication (e.g., 5, 7, 9) can be achieved.

[0045] Reference is now made to FIG. 6, which is a conceptual block diagram 600 of a pulse frequency multiplier that can achieve any order of multiplication, both even and odd, consistent with an exemplary embodiment. The example pulse doubler / frequency multiplier 600 can achieve any order of multiplication (even or odd) by simply cascading identical copies of the pulse doubler circuit n-1 times for the multiplication factor. For example, if N=5, then after four cascaded stages with a delay Δt / 4, a frequency multiplication factor of 5 is achieved. For even-order exponential multiplication (i.e., a factor of 2̂n), a cascade of sequential pulse doublers, each with a decreasing delay Δt / 2̂n, can be used, where again, n is the number of pulse doubler stages. Thus, for a factor of 16, the approach would only require four stages with delays t / 2, t / 4, t / 8, t / 16 (as opposed to 15 stages with delay times of Δt / 16 each).

[0046] The teachings herein can be used not only for frequency multiplication, but also for voltage amplification. For example, the time-averaged DC voltage V measured across a switched JJ at frequency F is V = Φ*F. Therefore, if frequency F increases, the voltage increases proportionally. For a 5 GHz signal measured in this manner, the DC signal amplitude would be ∼10 uV. With 10x frequency multiplication, the measured time-averaged DC signal would be ∼100 uV. In various embodiments, frequency and / or voltage multiplication can be static or can be dynamically set. [Conclusion]

[0047] The description of various embodiments of the present teachings has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements over the art found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

[0048] While the above describes what is believed to be the best mode and / or alternative examples, it is understood that various modifications can be made therein, that the subject matter disclosed herein can be embodied in various forms and examples, and that the teachings can be applied to numerous applications, only some of which are described herein. It is intended that the following claims claim all such applications, modifications, and variations that are within the true scope of the present teachings.

[0049] The components, steps, features, objects, benefits, and advantages described herein are merely exemplary. None of these, nor any explanations related thereto, are intended to limit the scope of protection. While various advantages have been described herein, it will be understood that not all embodiments necessarily include all advantages. Unless otherwise specified, all measurements, values, ratings, positions, dimensions, sizes, and other specifications described herein, including the following claims, are approximate and not exact. They are intended to have a reasonable range consistent with the functions to which they relate and that which is customary in the technical field to which they pertain.

[0050] Numerous other embodiments are also contemplated, including embodiments having fewer, additional, and / or different components, steps, features, objects, benefits, and advantages. These also include embodiments in which components and / or steps are arranged and / or ordered differently. For example, any of the signals described herein may be scaled, buffered, scaled and buffered, converted to another state (e.g., voltage, current, charge, time, etc.), or converted to another state (e.g., HIGH to LOW and LOW to HIGH) without substantially changing the underlying control method.

[0051] While the foregoing has been described in conjunction with exemplary embodiments, it is understood that the term "exemplary" is intended to mean merely an example, not best or optimal. Except as noted immediately above, nothing described or illustrated is intended to, and should be construed as, providing the public with any component, step, feature, object, benefit, advantage, or equivalent, whether claimed or not.

[0052] It will be understood that the terms and expressions used herein have the ordinary meanings ascribed to such terms and expressions with respect to their respective fields of inquiry and study, unless a specific meaning is otherwise stated herein. Relative terms such as first and second may be used solely to distinguish one entity or action from another, without necessarily requiring or implying an actual relationship or order between the entities or actions. The terms "comprises," "comprising," or other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements does not include only those elements, but may also include other elements not inherent in or expressly listed in such process, method, article, or apparatus. The use of an element preceded by "a" or "an" does not, in the absence of further constraints, exclude the presence of additional identical elements in the process, method, article, or apparatus that includes that element.

[0053] An Abstract of the Disclosure is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, the foregoing Detailed Description recognizes that various features are grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Accordingly, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as separately claimed subject matter.

Claims

1. 1. A method for generating an output signal based on single flux quantum (SFQ) pulses, the method comprising: receiving the SFQ pulse; splitting the SFQ pulse into a first path and a second path; storing the divided SFQ pulses of the second path in a latch; providing a second division of the divided SFQ pulse in the first path to provide a first output signal and a second output signal in the first path; delaying the second output signal by a delay Josephson transmission line (JTL); providing the output of the delay JTL as a clock input to the latch; and recombining a first output of the first path with an output of the latch to provide an output signal. A method comprising:

2. the latch is a D latch; and the split SFQ pulse of the second path is stored in the latch as a circulating supercurrent; The method of claim 1.

3. 3. The method of claim 1, wherein the recombination of the first output of the first path with the output of the latch is through a confluence buffer.

4. passing the split SFQ pulses to a second splitter through one or more Josephson transmission lines (JTL); and passing the output of the latch to a confluence buffer through one or more JTL. The method of claim 1 , further comprising:

5. 5. The method of claim 1, wherein the delay JTL comprises a serial chain of n JTL stages, each having a nominal current bias that results in a delay Δt, where Δt=n×Δt′, where Δt′ is the temporal pulse delay per JTL stage.

6. The delay JTL comprises a serial chain of n JTL stages, resulting in a delay Δt=n×Δt′(I ｂ ), where Δt′(I ｂ ) is the bias current I ｂ 6. The method of claim 1, wherein the time pulse delay per JTL stage is a function of

7. The delay JTL comprises a serial chain of n JTL stages, each of which provides a delay [Equation 1] where Δt ｉ (I ｂ，ｉ 6. The method according to claim 1, wherein I b,i is the delay of the ith JTL stage as a function of its bias current I b,i.

8. The output train of the pulses of the output signal is Δt / 2 Ｎ The delay of each successive delay JTL stage is set to Δt / 2 so as to have an inter-pulse interval of ｎ 8. The method of claim 1, further comprising providing exponential frequency multiplication of the received SFQ pulse train by setting n=n=n+n=n+n=n+n=n+n=n, where n is the number of the delay JTL stages in the N cascaded linear chain.

9. A method according to any one of claims 1 to 8, further comprising the step of providing an odd order of frequency multiplication of the received SFQ pulse by providing at least two cascade connections, wherein the delay between the upper and lower tracks of the pulse for the first doubler stage is 2Δt / 3 and the delay between the upper and lower tracks of the pulse for the second doubler stage is Δt / 3.

10. a first splitter having a first output and a second output and configured to receive a single flux quantum (SFQ) pulse; a second splitter having a first' output and a second' output, the second splitter being coupled to the first output of the first splitter; a delayed Josephson transmission line (JTL) coupled to the second' output of the second splitter; a latch having a data input coupled to the second output of the first splitter and a clock input coupled to the output of the delay JTL; and a recombination circuit configured to receive the first' output of the second splitter and the output of the latch and provide a recombined output; A circuit comprising:

11. the latch is a D latch; and The latch is configured to store the split SFQ pulse of the second path as a circulating supercurrent. The circuit of claim 10.

12. 12. The circuit of claim 10 or 11, wherein the recombination circuit is a confluence buffer.

13. 13. The circuit of claim 10, further comprising one or more JTLs coupled between the first splitter and the second splitter.

14. The circuit of claim 10 , further comprising one or more JTLs coupled between the latch and the decoupling circuit.

15. 15. The circuit of claim 10, wherein the delay JTL comprises a serial chain of n JTL stages, each having a nominal current bias that results in a delay Δt, where Δt=n×Δt′, where Δt′ is the temporal pulse delay per JTL stage.

16. The delay JTL comprises a serial chain of n JTL stages, resulting in a delay Δt=n×Δt′(I ｂ ), where Δt′(I ｂ ) is the bias current I ｂ 16. The circuit of claim 10, wherein the time pulse delay per JTL stage is a function of

17. The delay JTL comprises a serial chain of n JTL stages, each of which introduces a delay of [Equation 2] where Δt ｉ (I ｂ，ｉ 16. The circuit of claim 10, wherein I b,i is the delay of the ith JTL stage as a function of its bias current I b,i.

18. 18. The circuit of claim 10, wherein the recombination circuit is a confluence buffer.

19. The delay of the delay JTL is Δt / 2 ｎ where n is set to Δt / 2 Ｎ 19. The circuit of claim 10, wherein the circuit is a pulse doubler stage in a chain of N serially connected pulse doublers that provides an output train of pulses of an output signal having an inter-pulse spacing of N, thereby facilitating even frequency multiplication of the received SFQ pulses.

20. 20. The circuit of claim 10, wherein the circuit is part of a cascade of at least two pulse doubler stages configured to cause the delay of each delay JTL to be 2Δt / 3, thereby facilitating odd frequency multiplication of the received SFQ pulses.

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