Method and apparatus for metal filling in metal gate stacks

Abstract

1. A method of filling a feature in a semiconductor structure, comprising: forming a barrier layer in the feature by one of atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD), where the barrier layer is one of cobalt (Co), molybdenum (Mo), molybdenum nitride (MoN)+Mo, titanium (Ti), titanium aluminum carbide (TiAlC), or titanium nitride (TiN); and forming a metal layer in the feature and over the barrier layer by either ALD or CVD, where the metal layer is one of aluminum (Al), Co, Mo, ruthenium (Ru), or tungsten (W).

Description

[Technical Field]

[0001] TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate generally to thin film manufacturing technology. [Background technology]

[0002]

[0002] At previous (i.e., larger) nodes, the industry used physical vapor deposition (PVD) of titanium (Ti) followed by chemical vapor deposition (CVD) of aluminum (Al) to achieve metal fill for metal gate stack applications. However, the inventors have observed that the aforementioned processes can no longer meet gap-fill requirements due to challenges posed by new applications and structures, such as three-dimensional (3D) FinFET or gate-all-around (GAA) structures, as devices scale to smaller feature sizes (e.g., smaller nodes).

[0003] To illustrate the above, FIG. 1 schematically illustrates a substrate 100 having a base layer 102 on which a feature 104 is formed. A barrier layer 106 is formed on the top surface of the base layer 102, including on the surface of the feature 104 (e.g., along the sidewalls and bottom of the feature 104). A metal layer 108 is then formed on the barrier layer 106. After the feature is filled with the barrier layer 106 and the metal layer 108, a seam 110 is observed within the feature 104. The presence of such a seam is undesirable because it adversely affects subsequent processes, such as chemical mechanical planarization (CMP) and etching processes. For example, etchants or CMP polishing slurries may undesirably diffuse through the seam into the feature. Furthermore, the inventors have observed that such seams may undesirably contribute to an increased stack resistance.

[0004]

[0004] Accordingly, the inventors have provided embodiments of a method and apparatus for filling features that can be extended to more challenging 3D structures such as FinFET and GAA structures. Summary of the Invention

[0005]

[0005] Embodiments of methods and apparatus for filling features are provided herein. In particular, embodiments of the present disclosure advantageously provide methods and apparatus for achieving different gap-fill schemes that are friendly to FinFET / GAA structures. The disclosed processes described herein can be used for smaller structures as well as more complex structures, such as 3D structures, particularly for FinFET and GAA applications.

[0006] Additionally, embodiments of the methods and apparatus provided herein can also be used to fill features with reduced or eliminated seams. In particular, embodiments of the present disclosure advantageously provide methods and apparatus for minimizing, reducing, or eliminating the formation of seams when filling features. Metal films have been demonstrated to provide good gap filling with minimal impact on electrical performance. Furthermore, because the underlying TiN material properties are preserved, the process can be easily integrated into multi-chamber processing tools, as described below.

[0007]

[0007] In some embodiments, a method for filling a feature in a semiconductor structure includes forming a barrier layer in the feature by one of atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD), where the barrier layer is one of cobalt (Co), molybdenum (Mo), molybdenum nitride (MoN)+Mo, titanium (Ti), titanium aluminum carbide (TiAlC), or titanium nitride (TiN), and forming a metal layer in the feature and on the barrier layer by either ALD or CVD, where the metal layer is one of aluminum (Al), Co, Mo, ruthenium (Ru), or tungsten (W).

[0008]

[0008] In some embodiments, gap filling within a feature of a semiconductor structure includes a barrier layer within the feature, the barrier layer being either molybdenum (Mo), molybdenum nitride (MoN) and Mo, titanium (Ti), titanium aluminum carbide (TiAlC), or titanium nitride (TiN), each formed by atomic layer deposition (ALD), or cobalt (Co) or Ti, each formed by chemical vapor deposition (CVD), and a metal layer within the feature and over the barrier layer, the metal layer being either Mo or tungsten (W), each formed by ALD, or aluminum (Al), Co, or ruthenium (Ru), each formed by CVD, wherein the metal layer is seamless.

[0009]

[0009] In some embodiments, a system for forming a gap fill in a feature of a semiconductor structure includes an apparatus configured to form a barrier layer in the feature by either atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD), the barrier layer being one of cobalt (Co), molybdenum (Mo), molybdenum nitride (MoN) and Mo, titanium (Ti), titanium aluminum carbide (TiAlC), or titanium nitride (TiN), and an apparatus to form a metal layer in the feature and over the barrier layer by either ALD or CVD, the metal layer being one of aluminum (Al), Co, Mo, ruthenium (Ru), or tungsten (W), wherein the barrier layer and the metal layer are gap fill, and the gap fill is seamless.

[0010]

[0010] Other further embodiments of the present disclosure are described below.

[0011]

[0011] Embodiments of the present disclosure, briefly summarized above and discussed in more detail below, can be understood by reference to exemplary embodiments thereof as illustrated in the accompanying drawings. However, the accompanying drawings depict only typical embodiments of the present disclosure and therefore should not be considered as limiting in scope, as the present disclosure may admit of other equally effective embodiments. [Brief explanation of the drawings]

[0012] [Figure 1]

[0012] FIG. 1 is a schematic diagram of a prior art feature filled in a substrate and including a seam. [Figure 2A]

[0013] FIG. 2A illustrates a non-limiting exemplary structure that can be fabricated using methods and apparatus according to the present disclosure. [Figure 2B-2C] 2B and 2C each show non-limiting exemplary structures that can be fabricated using methods and apparatus according to the present disclosure. [Figures 2D-2F] 2D-F each show non-limiting exemplary structures that can be fabricated using methods and apparatus according to the present disclosure. [Figure 3]

[0014] FIG. 3 is a flowchart of a method for forming a semiconductor structure having gap fill within features according to an embodiment of the present disclosure. [Figures 4A-4C]

[0015] 4A-4C illustrate cross-sectional views of forming a semiconductor structure having gap fill within a feature according to an embodiment of the present disclosure. [Figure 4D-4E] 4D and 4E show cross-sectional views of forming a semiconductor structure with gap filling within a feature according to an embodiment of the present disclosure. [Figure 5]

[0016] FIG. 5 shows a schematic top view of an exemplary multi-chamber processing system according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0013]

[0017] For ease of understanding, where possible, identical reference numerals have been used to designate identical elements common to multiple figures. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

[0014]

[0018] Embodiments of methods and apparatuses for filling features are provided herein. In particular, embodiments of the present disclosure advantageously provide methods and apparatuses for achieving different gap-filling schemes that are friendly to FinFET / GAA structures. The disclosed processes described herein can be used for smaller structures as well as more complex structures, such as 3D structures, particularly for FinFET and GAA applications. The gap-filling may be seam-free or essentially seam-free.

[0015]

[0019] As used herein, the terms "seamless," "seamless," and the like are intended to mean "seamless" and / or "essentially seamless."

[0016]

[0020] As used herein, terms such as "essentially seam-free" are intended to include structures in which seams are detectable by transmission electron microscopy (TEM), but the width of the seam is about 3 Angstroms or less over the entire length of the feature.

[0017]

[0021] Alternatively or additionally, as used herein, terms such as "essentially seam-free" are intended to mean that there are seams detectable by transmission electron microscopy, but that have minimal, if any, impact on the electrical performance of the semiconductor having the filled features.

[0018]

[0022] As used herein, terms such as "minimal impact on electrical performance" mean that, when filling a feature in the semiconductor, the semiconductor experiences a change in flat band voltage (Vfb) of about 0% to about 5% or less (e.g., about 0% to about 5%) and / or a change in equivalent oxide thickness (EOT) of 5% or less (e.g., about 0% to about 5%).

[0019]

[0023] 2A-2F each illustrate an exemplary structure that can be fabricated using methods and apparatus according to the present disclosure. In embodiments, according to embodiments of the present disclosure, gap fill within a feature of a semiconductor structure can include a barrier layer and a metal contact layer thereon. The gap fill can be seamless.

[0020]

[0024] 2A schematically illustrates a substrate 200A having a base layer 202 in which a feature 204 is formed according to an embodiment of the present disclosure. The base layer 202 may be a layer of a single material or compound. Alternatively, the base layer 202 may include multiple layers (e.g., film stacks) that may be present during the fabrication of a device such as a transistor (e.g., part of a FinFET structure, a GAA structure, a PMOS stack, an NMOS stack, etc.). The feature 204 may generally be the space between adjacent sidewalls 204a of the base layer 202, which may extend vertically to the bottom 204b of the feature. For example, the feature 204 may be a trench, a via, etc.

[0021]

[0025] In embodiments, the barrier layer 206 may be formed on the top surface 202a of the base layer 202 and on other surfaces of the feature 204 (e.g., on and along the sidewalls 204a and bottom 204b of the feature 204). The barrier layer 206 may be deposited to generally form a conformal layer on top of the base layer 202 and within the feature 204. The barrier layer 206 may be one layer of a single material or compound. Alternatively, the barrier layer 206 may include multiple layers.

[0022]

[0026] In embodiments, barrier layer 206 can be titanium (Ti) deposited by atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD), titanium nitride (TiN) deposited by ALD, titanium aluminum carbide (TiAlC) deposited by ALD, cobalt (Co) deposited by CVD, molybdenum (Mo) deposited by ALD, or molybdenum nitride (MoN) deposited by ALD with ALD-deposited Mo thereon. In embodiments, barrier layer 206 can be a combination of one or more of the foregoing.

[0023]

[0027] In embodiments, the barrier layer 206 may have a total volume within the feature 204 that is between about 5% and about 95% of the total volume of the unfilled feature 204. In embodiments, the barrier layer 206 may have a thickness 206a within the feature 204 that is between about 5% and about 95% of the width / diameter (i.e., critical dimension) 204c of the feature 204.

[0024]

[0028] In embodiments, a metal layer or contact layer 208 may then be formed on the barrier layer 206. The metal layer 208 may extend into and over the feature 204 and over the top surface 202a of the base layer 202. This allows the metal layer 208 to function as an electrical contact layer. The metal layer 208 may be one of aluminum (Al) deposited by CVD, cobalt (Co) deposited by CVD, molybdenum (Mo) deposited by ALD, ruthenium (Ru) deposited by CVD, or tungsten (W) deposited by ALD. In embodiments, the metal layer 208 may be a combination of one or more of the foregoing. The metal layer 208 may be seamless, and therefore the gap fill (i.e., the combined barrier layer and metal layers 206, 208) may also be seamless.

[0025]

[0029] In embodiments, metal layer 208 may have a total volume within the feature that is between about 5% and about 95% of the total volume of the unfilled feature 204. In embodiments, metal layer 208 may have a thickness 208a in feature 204 that is between about 5% and about 95% of the width / diameter (i.e., critical dimension) 204c of feature 204.

[0026]

[0030] In an embodiment, the particular metal layer 208 used may depend on the particular barrier layer 206 used. For example, the following table shows exemplary combinations of barrier layers 206 and metal layers 208 to form gap fills. TIFF0007784427000001.tif84170

[0027]

[0031] In embodiments where the metal layer 208 is an Al layer, the Al layer can be deposited by chemical vapor deposition (CVD). For example, an Al film can be deposited on the barrier layer 206 using a CVD process at a temperature of about 100-300°C, e.g., about 120-180°C, a pressure of about 1-50 Torr, and a reaction time of about 20 seconds. Suitable precursors for Al deposition include triethylaluminum (TEA), dimethylaluminum hydride (DMAH), and trimethylaluminum (TMA).

[0028]

[0032] In embodiments in which barrier layer 206 is a TiAlC or TiN layer and metal layer 208 is a TiCl+Al layer, metal layer 208 can be formed by a cyclic process that includes exposing the substrate to TiCl at a temperature of about 100 to about 450° C. and a pressure of about 1 to about 50 Torr. This can be followed by Al CVD deposition using the CVD process described above for Al metal layer 208. The cyclic process can be repeated as necessary to fill feature 204.

[0029]

[0033] In embodiments in which the barrier layer 206 or the metal layer 208 is a Co layer, the Co layer may be deposited by CVD or plasma-enhanced CVD (PECVD). For example, a Co film may be deposited on the base layer 202 (to form the barrier layer 206) or on the barrier layer 206 (to form the metal layer 208) using a CVD or PECVD process at a temperature between about 100 degrees Celsius and about 300 degrees Celsius and a pressure between about 1 and about 50 Torr. Suitable precursors for Co deposition include dicobalt hexacarbonyl tert-butylacetylene (CCTBA).

[0030]

[0034] In embodiments in which the barrier layer 206 is a Mo layer or a MoN+Mo layer, or in which the metal layer 208 is a Mo layer, the Mo or MoN+Mo layer can be deposited using atomic layer deposition (ALD). For example, a Mo or MoN film can be deposited on the barrier layer 206 using an ALD process in which the substrate is exposed to a molybdenum precursor and a reactant to form a bulk molybdenum film. In some embodiments, the ALD process can be performed at a temperature of about 350-600°C, e.g., about 400-600°C, at a pressure of about 1-50 Torr, for a reaction time appropriate to form a film to a desired thickness. A Mo film can then be deposited on the MoN film as described above.

[0031]

[0035] For example, only a Mo film can be deposited on the barrier layer 206 using an ALD process at a temperature between about 350 degrees Celsius and about 600 degrees Celsius, such as between about 400 degrees Celsius and about 600 degrees Celsius, at a pressure between about 1 and about 50 Torr.

[0032]

[0036] In another example, a MoN film can be deposited on the barrier layer 206 using an ALD process at a temperature of about 350 to about 600° C., e.g., about 400 to about 600° C., and a pressure of about 1 to about 50 Torr. A Mo film can then be deposited on the MoN film as described above.

[0033]

[0037] Suitable precursors for Mo or MoN+Mo deposition include any suitable molybdenum-containing compound capable of reacting (i.e., adsorbing or chemisorbing) with the substrate surface to leave behind a molybdenum-containing species on the substrate surface. In one or more embodiments, the molybdenum precursor includes one or more of molybdenum chloride (MoCl), molybdenum fluoride (MoF), molybdenum iodide (MoI), molybdenum bromide (MoBr), molybdenum hexacarbonyl (Mo(CO)), molybdenum dioxide (MoOCl), molybdenum oxytetrachloride (MoOCl), tetrakis(dimethylamino)molybdenum(IV), and bis(tert-butylimido)-bis(dimethylamido)molybdenum. Suitable reactants for Mo or MoN+Mo deposition include hydrogen gas (H) or 1-methyl-3,6-bis(trimethylsilyl)-1,4-cyclohexadiene (CHD).

[0034]

[0038] In embodiments where metal layer 208 is a ruthenium (Ru) layer, the Ru layer may be deposited by CVD. For example, a Ru film may be deposited on barrier layer 206 using a CVD process employing a ruthenium precursor and a catalyst at about 200 to about 500° C., e.g., about 250 to about 350° C., and about 1 to about 50 Torr.

[0035]

[0039] Suitable Ru precursors include Ru-containing gases with dienes, such as p-cymene Ru hexadiene or p-cymene Ru cyclohexadiene. Suitable catalysts include alkyl halides, such as alkyl iodides and alkyl bromides. The inventors have observed that using the process described herein, seamless gap filling can be achieved by improving the nucleation of deposited Ru films and reducing film roughness.

[0036]

[0040] In some embodiments, the Ru deposition process (Ru precursor soak time, catalyst soak time, deposition temperature) is optimized to minimize roughness.

[0037]

[0041] In some embodiments, the Ru deposition process includes pre-soaking the liner with a catalyst at a high pressure, such as at least about 20 Torr, for about 10 seconds to about 60 seconds. In some embodiments, one cycle of catalyst pre-soak followed by Ru deposition can be repeated, for example, up to five cycles.

[0038]

[0042] In some embodiments, there is no vacuum break between the barrier layer and the Ru deposition process to avoid or minimize the risk of oxygen contamination of the barrier layer.

[0039]

[0043] In some embodiments, where oxygen is present on the barrier layer surface, for example due to a vacuum break, the amount of O on the barrier layer surface may be increased by increasing the barrier layer surface to nitrogen (N * ) or hydrogen (H * ) can be removed or reduced by pretreatment using radicals or direct exposure to plasma. For example, the barrier layer can be exposed to an inductively coupled plasma containing H or an H / N mixture and a biased substrate support to react O from the barrier layer surface. For example, a plasma power of about 400 to 900 W can be provided to generate the plasma, and a bias power of about 50 to about 300 W can be provided to the substrate support.

[0040]

[0044] In some embodiments, the deposited film is annealed to promote grain growth, which can repair seams between two surfaces with very small gaps. Annealing can be performed at temperatures below 450°C for about 5 to about 30 minutes.

[0041]

[0045] In some embodiments where the metal layer 208 is a tungsten (W) layer, the W layer may be deposited by ALD. For example, a W film may be deposited on the barrier layer 206 using an ALD process at about 350 degrees Celsius to about 500 degrees Celsius and about 1 Torr to about 50 Torr. Suitable precursors include WF6, WCl5, and WCl6.

[0042]

[0046] In embodiments in which the barrier layer 206 is a Ti or TiN layer, the Ti layer can be deposited by a suitable ALD, CVD, or PVD process, and the TiN layer can be formed by a suitable ALD process. Suitable ALD processes can be performed, for example, at temperatures between about 100°C and about 400°C and pressures between about 1 Torr and about 50 Torr. Suitable Ti precursors include TiCl4, and suitable reactants include CHD. Suitable TiN precursors include TiCl4 and TDMAT, and suitable reactants include NH3 and N2H4.

[0043]

[0047] Suitable plasma-enhanced CVD processes can be carried out, for example, at temperatures between about 300°C and about 700°C and pressures between about 1 Torr and about 200 Torr. The plasma can be formed and / or maintained using RF energy between about 100 and about 1000 W at a frequency between about 350 kHz and about 2 MHz. Suitable process gases include TiCl4 and H2.

[0044]

[0048] Suitable PVD processes can be carried out, for example, at temperatures between about 30° C. and about 400° C. and pressures between about 1 mTorr and about 1000 mTorr. Suitable process gases include N2.

[0045]

[0049] In embodiments in which the barrier layer 206 is a TiAlC layer, the TiAlC layer can be deposited by a suitable ALD process at a temperature between about 300° C. and about 450° C. and a pressure between about 1 Torr and about 50 Torr. Suitable Ti precursors include TiCl4 and TDMAT. Suitable Al precursors include TEA, TMA, and DMAH.

[0046]

[0050] Optionally, after deposition of the Co or Ru film, an annealing process can be performed in a hydrogen gas (H) environment maintained at about 1 to about 50 Torr at a temperature greater than about 400° C. for about 1 to about 30 minutes. The annealing process can be performed in the same processing chamber or in a separate chamber configured to perform the annealing process.

[0047]

[0051] Exemplary treatments and treatment conditions are outlined in the table below. TIFF0007784427000002.tif90170

[0048]

[0052] In some embodiments, the deposition of the metal layer 208 and the barrier layer 206 films can be performed in separate processing chambers. Alternatively, and advantageously, the deposition of the metal layer 208 and the barrier layer 206 films can be integrated into a multi-chamber processing system (e.g., a cluster tool), such as, for example, the ENDURA® line of processing tools available from Applied Materials, Inc. of Santa Clara, California.

[0049]

[0053] FIG. 2A illustrates gap filling in a general semiconductor structure according to the present disclosure, while FIGS. 2B-2F illustrate more specific exemplary embodiments of semiconductor structures according to the present disclosure.

[0050]

[0054] 2B and 2C illustrate exemplary FinFET structures 200B, 200C in which processes according to the present disclosure can be used for the gate fill portion of the fabrication of the FinFET structures.

[0051]

[0055] FIG. 2D shows a portion of a gate-all-around (GAA) structure 200D, where processing according to the present disclosure can be used for the metal gate fill portion of the fabrication of the GAA structure.

[0052]

[0056] 2E and 2F show a p-type metal oxide semiconductor (PMOS) stack 200E and an n-type metal oxide semiconductor (NMOS) stack 200F, respectively, and processes according to the present disclosure can be used to fabricate PMOS and / or NMOS stacks.

[0053]

[0057] 3 is a flow diagram of a method 300 that can be used to fabricate semiconductor device structures on a substrate according to embodiments of the present disclosure, such as the embodiments shown in FIGS. 2A-2F. Method 300 may correspond to the manufacturing stages shown in FIGS. 4A-4E. For illustrative purposes, the method of FIG. 3 is generally provided with reference to CVD, ALD, or PVD-deposited barrier layers and / or metal contact layers.

[0054]

[0058] The method 300 may begin at block 310 by providing a substrate, such as the substrate 402 shown in Figure 4A, in a processing chamber. The substrate 402 shown in Figure 4A includes a semiconductor device structure 408 (e.g., a gate structure or other structure configured to form a contact structure) formed thereon.

[0055]

[0059] A silicon layer 404 can be formed on the substrate 402 with features 406 formed thereon. The features 406 (which can be contact openings, contact vias, contact trenches, contact channels, etc.) can be formed in the device structure 408 and can have sidewalls 412 and a bottom 414 that form an open channel to expose the underlying silicon layer 404. The silicon layer 404 can include any suitable layer, such as a single silicon layer or a multilayer film stack formed with at least one silicon layer. In an embodiment in which the silicon layer 404 is in the form of a single layer, the silicon layer 404 can be a silicon oxide layer, an oxide layer, a silicon nitride layer, a nitride layer, a silicon oxynitride layer, a titanium nitride layer, a polysilicon layer, a microcrystalline silicon layer, single crystal silicon, a doped polysilicon layer, a doped microcrystalline silicon layer, or doped single crystal silicon.

[0056]

[0060] In embodiments in which the silicon layer 404 is a film stack, the stack may include multiple oxide and nitride layers, at least one or more oxide layers sandwiching a nitride layer, and combinations thereof. Suitable dopants for doping the silicon layer 404 may include p-type and n-type dopants, such as boron (B)-containing dopants or phosphine (P)-containing dopants.

[0057]

[0061] In embodiments where the silicon layer 404 is in the form of a multiple film stack having at least one silicon-containing layer, the silicon layer 404 may include a repeating pair of layers including a silicon layer and a dielectric layer. In embodiments, the silicon layer 404 may include a polysilicon layer and / or other metallic materials and / or dielectric layers disposed therein. Suitable examples of dielectric layers may be selected from the group consisting of an oxide layer, a silicon oxide layer, a silicon nitride layer, a nitride layer, a titanium nitride layer, a composite of an oxide layer and a nitride layer, at least one or more oxide layers sandwiching a nitride layer, and combinations thereof, among others.

[0058]

[0062] Prior to transferring the substrate 402 into the processing chamber in block 310, a pre-cleaning process may optionally be performed in block 320 to treat the substrate surface 411, sidewalls 412, and bottom 414 of the openings / features 406 to remove native oxides or other contaminants. Removing native oxides or other contaminants from the substrate 402 may provide a low contact resistance surface, forming a good contact surface for forming a barrier layer.

[0059]

[0063] The pre-cleaning process may include supplying a pre-cleaning gas mixture into a pre-cleaning chamber at block 320. The pre-cleaning chamber may be a pre-clean PCII, PCXT, or Siconi™ chamber available from Applied Materials, Inc., Santa Clara, California. The pre-cleaning process may include supplying a cleaning gas mixture into the pre-cleaning chamber and forming a plasma from the pre-cleaning gas mixture to remove native oxide. In an embodiment, the pre-cleaning gas mixture may be a mixture of ammonia gas and nitrogen trifluoride gas. The amount of each gas introduced into the processing chamber may be varied and adjusted to accommodate, for example, the thickness of the native oxide layer to be removed, the geometry of the substrate to be cleaned, the volumetric capacity of the plasma, the volumetric capacity of the chamber body, and the capacity of a vacuum system coupled to the chamber body.

[0060]

[0064] Also, in block 320, a pretreatment process can optionally be performed to prepare the substrate surface 411, thereby forming a treated surface region 410 on the substrate surface 411, the sidewalls 412, and the bottom 414 of the feature 406 in the silicon layer 404, as shown in FIG. 4B. The pretreatment process in block 320 can be performed to modify the surface bonding structure of the silicon layer 404, thereby providing a surface with good absorption capability that promotes adhesion of metal atoms resulting from a subsequent barrier layer deposition process. The pretreatment gas mixture can include at least a hydrogen-containing gas, such as H, HO, or HO. An inert gas, such as Ar, He, or Kr, can also be provided to the pretreatment gas mixture.

[0061]

[0065] In block 330, as shown in FIG. 4C, a barrier layer deposition process can be performed to deposit a barrier layer 416 on the substrate and / or the processed surface region 410. The barrier layer 416 can prevent the contact metal layer from diffusing into the bonding material, typically silicon or silicon germanium compounds, on the substrate. The barrier layer 416 can be deposited by atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), or physical vapor deposition (PVD). In embodiments, the barrier layer 416 can have a thickness in a range from about 2 Å to about 100 Å, or from about 3 Å to about 80 Å, or from about 4 Å to about 50 Å.

[0062]

[0066] 4D, an optional wetting layer deposition may be performed to deposit a wetting layer 418 on the substrate 402. The wetting layer 418 may be deposited on the barrier layer 416. The wetting layer may be deposited by a process selected from PVD Co, CVD TiN, PVD TiN, CVD Ru, PVD Ru, PVD Ti nitridation, or a combination thereof.

[0063]

[0067] In embodiments in which a CVD process is used to deposit the wetting layer 418, the desired precursor gases may be supplied to the chamber and further supplied in the presence of a carrier gas.

[0064]

[0068] In embodiments in which the wetting layer 418 is deposited using a PVD process, a target containing the desired material to be deposited is provided, and a PVD process is performed to deposit the PVD wetting layer. In some embodiments, the wetting layer comprises PVD TiN. In such embodiments, a Ti target is provided and bombarded with ions to sputter Ti and deposit the wetting layer 418 on the barrier layer 416. A nitridation process using a nitrogen-containing precursor, such as NH3, in the presence of a plasma is performed on the PVD Ti layer to form the TiN wetting layer 418. In some embodiments, the wetting layer 418 comprises a nitrided Ti layer, where only the top few angstroms of titanium are converted to the TiN compound.

[0065]

[0069] In some embodiments, the wetting layer 418 is PVD Co. In such embodiments, a Co target is provided and bombarded with ions to sputter Co and deposit the wetting layer 418 on the barrier layer 416. In embodiments using PVD Co, RF power is provided at a frequency between about 5000 W and about 6000 W. The power for the PVD Co process is provided between about 400 W and about 600 W, and the chamber pressure during the PVD Co process is between about 50 mTorr and about 150 mTorr.

[0066]

[0070] At block 340, an optional annealing process may be performed on the wetting layer 418. The annealing process may reduce the surface roughness of the wetting layer 418, increase the grain size of the crystalline structure, and reduce impurities such as carbon that may be present in the wetting layer 418. The annealing process may be performed at a temperature between about 200° C. and about 500° C. In embodiments, the annealing process may be performed for a period between about 10 seconds and about 1000 seconds.

[0067]

[0071] 4E, a contact metal deposition process can be performed in a processing chamber to deposit a metal contact layer 420. The metal contact layer 420 can be deposited using a cyclic deposition process, which allows the metal contact layer 420 to fill the feature 406 without seams.

[0068]

[0072] The metal contact layer 420 may be deposited using a multi-step deposition process that includes multiple cycles of performing a cyclical metal deposition process to deposit the metal contact layer 420. In embodiments, the thickness of the metal contact layer 420 may be less than 50% of the feature diameter (critical dimension) of the smallest feature to be filled. In embodiments, the metal contact layer 420 may have a thickness in the range of about 20 Å to about 200 Å.

[0069]

[0073] In embodiments, a cyclical metal deposition process may be performed to partially fill the feature to less than half the feature diameter, followed by an optional annealing process at block 350. The cyclical deposition process followed by optional annealing may then be repeated to deposit the metal contact layer 420 until it reaches a predetermined thickness. In some embodiments, the metal contact layer 420 may be deposited to completely fill the feature in a single, non-cyclical deposition process. In such embodiments, the metal contact layer 420 may then be optionally annealed.

[0070]

[0074] In such an embodiment, the metal contact layer 420 may then be optionally annealed. The plasma treatment process may involve providing a process gas, such as H, to the chamber and applying an RF current to convert the process gas into a plasma. In one embodiment, the RF current has a frequency between about 200 W and about 800 W. The plasma treatment step may be performed for a period of about 1 second to about 60 seconds. In one embodiment, the substrate 402 may be heated to a temperature between about 100° C. and about 200° C. to further reduce the surface roughness of the metal contact layer 420 and reduce the proportion of impurities that may be present in the metal contact layer 420.

[0071]

[0075] In block 370, an annealing process can optionally be performed on the metal contact layer 420. The annealing process can reduce the surface roughness of the metal contact layer 420 and reduce impurities, such as carbon, that may be present in the metal contact layer 420. Additionally, the annealing process can increase the grain size, which in turn reduces resistivity and results in improved integrated circuit performance. The annealing process can be performed at a temperature between about 200°C and about 500°C. The annealing process can be performed in a chamber environment where an inert gas, such as argon, and a process gas, such as H2, are provided in the chamber. In one embodiment, the annealing process can be performed for a time period between about 30 seconds and about 90 seconds.

[0072]

[0076] 5 shows a schematic top view of an exemplary multi-chamber processing system 500 that can be adapted to perform processes as disclosed above. The multi-chamber processing system 500 includes multiple processing chambers configured to perform different processes integrated into the multi-chamber processing system 500.

[0073]

[0077] The multichamber processing system 500 includes one or more load lock chambers 502, 504 for transferring substrates to and from the multichamber processing system 500. Typically, the multichamber processing system 500 is under reduced pressure, so the load lock chambers 502, 504 can "pump down" substrates introduced into the multichamber processing system 500. A first robot 510 disposed in a first transfer chamber can transfer substrates between the load lock chambers 502, 504 and a first set of one or more substrate processing chambers, such as processing chambers 511, 512, 513, and 514. Each processing chamber 511, 512, 513, and 514 is configured to perform at least one substrate processing operation, such as an etch process, a treatment process, a deposition process (such as ALD, CVD, PECVD, PVD, etc.), degassing, pre-cleaning, alignment, and other substrate processing, including processes of the present disclosure.

[0074]

[0078] In some embodiments, the first robot 510 can also transfer substrates to / from one or more pass-through chambers 522, 524. The pass-through chambers 522, 524 can be used to maintain ultra-high vacuum conditions while allowing substrates to be transferred to a second transfer chamber within the multi-chamber processing system 500. The second robot 530 is disposed within the second transfer chamber and can transfer substrates between the pass-through chambers 522, 524 and a second set of one or more processing chambers. The processing chambers 532, 534, 536, 538 are configured to perform one or more specific substrate processes, including the processes described herein, as well as other suitable processes that may be performed before or after the processes disclosed herein. For example, according to the methods described herein, at least one processing chamber 532, 534, 536, 538 is configured to perform a substrate processing operation, such as a deposition process.

[0075]

[0079] Any of the processing chambers 511 , 512 , 513 , 514 , 532 , 534 , 536 , 538 may be removed from the multichamber processing system 500 if they are not required for the processes performed by the multichamber processing system 500 .

[0076]

[0080] In some embodiments, the multi-chamber processing system 500 includes at least one first deposition chamber configured to deposit a first layer on and within features formed in the substrate, such as the barrier layer 206 described above. In some embodiments, the multi-chamber processing system 500 further includes at least one second deposition chamber configured to deposit a metal fill layer, such as the metal fill layer 208 described above. For example, the first and second deposition chambers may be one of an ALD chamber, a CVD chamber, a PECVD chamber, a PVD chamber, etc., specifically configured to deposit one or more of the materials described above. In some embodiments, for example, when a Ru or Co film is used, one or more processing chambers of the multi-chamber processing system 500 may be an annealing chamber configured to perform the annealing process described above on the deposited Co and Ru films.

[0077]

[0081] A microprocessor controller 540 may be provided and coupled to the various components of the multi-chamber processing system 500 to control its operation. The controller 540 includes a central processing unit (CPU), memory, and support circuits. The controller 540 may control the multi-chamber processing system 500 directly or through other computers (or controllers) associated with particular process chambers and / or support system components. The controller 540 may be one of any type of general-purpose computer processor that can be used in an industrial environment to control the various chambers and sub-processors. The memory, or computer-readable medium, of the controller 540 may be one or more readily available memory devices, such as random access memory (RAM), read-only memory (ROM), floppy disks, hard disks, optical storage media (e.g., compact discs or digital video discs), flash drives, or other forms of digital storage (local or remote). Support circuits are coupled to the CPU for supporting the processor in a conventional manner. These circuits may include flash, power supplies, clock circuits, input / output circuits and subsystems, and the like. The inventive methods described herein may be stored in the memory as software routines that can be executed or called to control the operation of the multi-chamber processing system 500, or individual processing chambers connected thereto, in the manner described herein. The software routines may be stored and / or executed by a second CPU (not shown) located remotely from the hardware being controlled by the CPU.

[0078]

[0082] While the forgoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof.

Claims

1. 1. A method of filling features in a semiconductor structure, comprising: forming a barrier layer in the feature by one of atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD), the barrier layer being one of molybdenum (Mo), molybdenum nitride (MoN)+Mo, or titanium aluminum carbide (TiAlC); forming a metal layer in the feature and on the barrier layer by either ALD or CVD, the metal layer being one of aluminum (Al), Co, Mo, ruthenium (Ru), or tungsten (W); annealing the metal layer; Including, The method of forming the metal layer and annealing the metal layer is repeated multiple times.

2. The method of claim 1 , wherein forming the barrier layer is performed by ALD.

3. 3. The method of claim 1, wherein forming the metal layer is performed by ALD, and the metal layer is one of Mo or W.

4. 3. The method of claim 1, wherein forming the metal layer is performed by CVD, and the metal layer is one of Al, Co, or Ru.

5. 1. A method of filling features in a semiconductor structure, comprising: forming a barrier layer in the feature by one of atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD), the barrier layer being one of cobalt (Co), molybdenum nitride (MoN)+Mo, titanium (Ti), titanium aluminum carbide (TiAlC), or titanium nitride (TiN); forming a metal layer, the metal layer being molybdenum (Mo), in the feature and on the barrier layer by either ALD or CVD; annealing the metal layer; Including, The method of forming the metal layer and annealing the metal layer is repeated multiple times.

6. 6. The method of claim 5, wherein forming the barrier layer is by ALD, and the barrier layer is one of MoN+Mo, Ti, TiAlC, or TiN.

7. 6. The method of claim 5, wherein forming the barrier layer is performed by CVD, and the barrier layer is one of Co or Ti.

8. 6. The method of claim 5, wherein forming the barrier layer is by PVD, and the barrier layer is Ti.

9. 9. The method of claim 5, wherein forming the metal layer is performed by ALD.

10. A method for filling features in a semiconductor structure, comprising: forming a barrier layer in the feature by one of atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD), wherein the barrier layer is titanium aluminum carbide (TiAlC) or titanium nitride (TiN); exposing the barrier layer to TiCl 4 ; forming a metal layer, which is aluminum (Al), in the feature and on the barrier layer by either ALD or CVD after exposing the barrier layer to TiCl 4 ; Including, The method of exposing the barrier layer to TiCl 4 and forming the metal layer is repeated multiple times.

11. The method described in claim 10, wherein forming the barrier layer is performed by ALD.

12. The method of claim 10, wherein exposing the barrier layer to TiCl 4 is carried out at a temperature of 100 to 450° C. and a pressure of 1 to 50 Torr.

13. The method of claim 10, wherein forming the metal layer is performed by CVD at a temperature of 100 to 300° C. and a pressure of 1 to 50 Torr.

14. A method described in any one of claims 1 to 13, further comprising forming a wetting layer after forming the barrier layer and before forming the metal layer.

15. The method of claim 1, further comprising exposing the metal layer to a plasma treatment process.

16. 16. The method of any one of claims 1 to 15, wherein the semiconductor structure is one of a fin field effect transistor (FINFET), a gate-all-around transistor (GAA), a p-type metal oxide semiconductor (PMOS), or an n-type metal oxide semiconductor (NMOS).

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