Memory Device-Based Accelerated Deep Learning System

Abstract

The data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to be coupled to the host device. The controller is further configured to receive a plurality of commands, generate a logical block address (LBA) to physical block address (PBA) (L2P) mapping for each of the plurality of commands, and store data of the plurality of commands in the respective PBAs according to the generated L2P mapping. Each of the L2P mappings is generated based on a result of a deep learning (DL) training model using a neural network (NN) structure. The controller includes a NN command interpretation unit and an L2P mapping generator coupled to the NN command interpretation unit. The controller is configured to fetch the training data and the NN parameters from the memory device.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application incorporates by reference herein the entire contents of U.S. Non-Provisional Application No. 17 / 592,953, entitled "MEMORY DEVICE BASED ACCELERATED DEEP-LEARNING SYSTEM," filed February 4, 2022, for all purposes.

[0002] FIELD OF THE INVENTION Embodiments of the present disclosure relate generally to data storage devices such as solid-state drives (SSDs), and more particularly to utilizing deep learning training models stored in non-volatile memory to improve the read and write performance of data storage devices. [Background technology]

[0003] Deep Learning (DL) systems are an evolving technology with capabilities in a variety of fields. However, due to the increase in capabilities of DL systems, the corresponding hardware resource consumption for DL ​​systems increases as well. Due to the size of datasets and DL models, DL systems may require very large amounts of high-speed memory. Such memory may be random access memory (RAM). However, non-volatile memory, such as NAND memory devices, may be interlaced in DL hardware computations.

[0004] Typically, DL models are held in dynamic RAM (DRAM) of a data storage device. As the size of the DL model increases, more DRAM may be required, thus increasing the cost of the data storage device. However, non-volatile memory such as NAND memory may not have as high a cost per capacity as DRAM. However, NAND memory may not have the same performance output as DRAM. For example, a dataset may be approximately 100 GB or larger in size. A dataset is a collection of data samples and labels used to train a DL model.

[0005] Therefore, there is a need in the art for improved DL systems that use non-volatile memory for training DL models. Summary of the Invention

[0006] The present disclosure generally relates to data storage devices such as solid-state drives (SSDs), and more particularly to improving read and write performance of the data storage device by utilizing a deep learning training model stored in non-volatile memory. The data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to be coupled to a host device. The controller is further configured to receive a plurality of commands, generate a logical block address (LBA) to physical block address (PBA) (L2P) mapping for each of the plurality of commands, and store data of the plurality of commands in the respective PBAs according to the generated L2P mapping. Each of the L2P mappings is generated based on the result of a deep learning (DL) training model that uses a neural network (NN) structure. The controller includes an NN command interpretation unit and an L2P mapping generator coupled to the NN command interpretation unit. The controller is configured to fetch training data and NN parameters from the memory device.

[0007] In one embodiment, the data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to be coupled to a host device. The controller is further configured to receive a plurality of commands, generate a logical block address (LBA) to physical block address (PBA) (L2P) mapping for each of the plurality of commands, and store data of the plurality of commands in the respective PBAs according to the generated L2P mapping. Each of the L2P mappings is generated based on results of a deep learning (DL) training model using a neural network (NN) structure.

[0008] In another embodiment, a data storage device includes a memory device and a controller coupled to the memory device, the controller including a neural network (NN) command interpretation unit and a logical block address (LBA) to physical block address (PBA) (L2P) mapping generator coupled to the NN command interpretation unit, the controller configured to fetch training data and NN parameters from the memory device.

[0009] In another embodiment, a data storage device includes non-volatile memory means and a controller coupled to the non-volatile memory means, the controller configured to store neural network (NN) parameters and one or more hyperparameter values ​​in the non-volatile memory means, execute a fully autonomous deep learning (DL) training model or execute a semi-autonomous DL training model, and store data according to the executed DL training model. [Brief explanation of the drawings]

[0010] So that the above-mentioned features of the present disclosure can be understood in detail, a more particular description of the present disclosure briefly summarized above can be had by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only typical embodiments of the present disclosure and therefore should not be considered as limiting its scope, as the present disclosure may admit of other equally effective embodiments. [Figure 1] 1 is a schematic block diagram illustrating a storage system in which a data storage device can function as a storage device for a host device, according to certain embodiments. [Figure 2] FIG. 1 is an exemplary diagram of a deep neural network, according to certain embodiments. [Figure 3] FIG. 1 is a schematic block diagram illustrating an LBA / PBA addressing system, according to a particular embodiment. [Figure 4] FIG. 1 is a schematic block diagram illustrating an LBA / PBA addressing system, according to a particular embodiment. [Figure 5] 1 is a flow diagram illustrating a method for fully autonomous data storage device operation during deep learning training, according to certain embodiments. [Figure 6] 1 is a flow diagram illustrating a method of semi-autonomous data storage device operation during deep learning training, according to certain embodiments.

[0011] To facilitate understanding, the same reference numbers have been used, whenever possible, to designate identical elements common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific mention thereof. DETAILED DESCRIPTION OF THE INVENTION

[0012] Reference will be made below to embodiments of the present disclosure. However, it should be understood that the present disclosure is not limited to the specifically described embodiments. Instead, any combination of the following features and elements, whether associated with different embodiments or not, is contemplated to implement and practice the present disclosure. Furthermore, although embodiments of the present disclosure may achieve advantages over other possible solutions and / or over the prior art, whether or not a particular advantage is achieved by a given embodiment does not limit the present disclosure. Accordingly, the following aspects, features, embodiments, and advantages are merely exemplary and are not considered elements or limitations of the appended claims unless expressly recited in the claim(s). Similarly, references to "the present disclosure" should not be construed as a generalization of any inventive subject matter disclosed herein, and should not be considered elements or limitations of the appended claims unless expressly recited in the claims.

[0013] The present disclosure generally relates to data storage devices such as solid-state drives (SSDs), and more particularly to improving read and write performance of the data storage device by utilizing a deep learning training model stored in non-volatile memory. The data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to be coupled to a host device. The controller is further configured to receive a plurality of commands, generate a logical block address (LBA) to physical block address (PBA) (L2P) mapping for each of the plurality of commands, and store data of the plurality of commands in the respective PBAs according to the generated L2P mapping. Each of the L2P mappings is generated based on the result of a deep learning (DL) training model that uses a neural network (NN) structure. The controller includes an NN command interpretation unit and an L2P mapping generator coupled to the NN command interpretation unit. The controller is configured to fetch training data and NN parameters from the memory device.

[0014] 1 is a schematic block diagram illustrating a storage system 100 in which a host device 104 communicates with a data storage device 106, according to certain embodiments. For example, the host device 104 may store and retrieve data using non-volatile memory (NVM) 110 included in the data storage device 106. The host device 104 includes a host DRAM 138. In some implementations, the storage system 100 may include multiple storage devices, such as the data storage device 106, that may operate as a storage array. For example, the storage system 100 may include multiple data storage devices 106 configured as a redundant array of inexpensive / independent disks (RAID) that collectively function as a mass storage device for the host device 104.

[0015] Host device 104 may store and / or retrieve data to and / or from one or more storage devices, such as data storage device 106. As illustrated in Figure 1, host device 104 may communicate with data storage device 106 via interface 114. Host device 104 may comprise any of a wide range of devices, including a computer server, a network-attached storage (NAS) unit, a desktop computer, a notebook (i.e., laptop) computer, a tablet computer, a set-top box, a telephone such as a so-called "smart" phone, a so-called "smart" pad, a television, a camera, a display device, a digital media player, a video game console, a video streaming device, or any other device capable of transmitting or receiving data from a data storage device.

[0016] Data storage device 106 includes controller 108, NVM 110, power supply 111, volatile memory 112, interface 114, and write buffer 116. In some embodiments, data storage device 106 may include additional components not shown in FIG. 1 for clarity. For example, data storage device 106 may include a printed circuit board (PCB) to which components such as data storage device 106 are mechanically attached and which includes conductive traces that electrically interconnect the components of data storage device 106. In some embodiments, the physical dimensions and connector configuration of data storage device 106 may conform to one or more standard form factors. Some exemplary standard form factors include, but are not limited to, a 3.5" data storage device (e.g., HDD or SSD), a 2.5" data storage device, a 1.8" data storage device, a Peripheral Component Interconnect (PCI), a PCI Expansion (PCI-X), a PCI Express (PCIe) (e.g., PCIe x1, x4, x8, x16, PCIe Mini Card, Mini PCI, etc.). In some embodiments, the data storage device 106 may be directly coupled to the motherboard of the host device 104 (e.g., soldered or plugged directly into a connector).

[0017] The interface 114 may include one or both of a data bus for exchanging data with the host device 104 and a control bus for exchanging commands with the host device 104. The interface 114 may operate according to any suitable protocol. For example, the interface 114 may operate according to one or more of the following protocols: Advanced Technology Attachment (ATA) (e.g., Serial ATA (SATA) and Parallel ATA (PATA)), Fibre Channel Protocol (FCP), Serial Attached SCSI (SAS), PCI and PCIe, Small Computer System Interface (SCSI), Non-Volatile Memory Express (NVMe), OpenCAPI, GenZ, Cache Coherent Interface Accelerator (CCIX), Open Channel SSD (OCSSD), etc. The interface 114 (e.g., the data bus, the control bus, or both) is electrically connected to the controller 108 and provides an electrical connection between the host device 104 and the controller 108, enabling data to be exchanged between the host device 104 and the controller 108. In some embodiments, the electrical connection of interface 114 may also allow data storage device 106 to receive power from host device 104. For example, as illustrated in FIG. 1, power supply 111 may receive power from host device 104 via interface 114.

[0018] NVM 110 may include multiple memory devices or memory units. NVM 110 may be configured to store and / or retrieve data. For example, a memory unit of NVM 110 may receive data and a message from controller 108 instructing the memory unit to store data. Similarly, a memory unit may receive a message from controller 108 instructing the memory unit to retrieve data. In some embodiments, each of the memory units may be referred to as a die. In some embodiments, NVM 110 may include multiple dies (i.e., multiple memory units). In some embodiments, each memory unit may be configured to store a relatively large amount of data (e.g., 128 MB, 256 MB, 512 MB, 1 GB, 2 GB, 4 GB, 8 GB, 16 GB, 32 GB, 64 GB, 128 GB, 256 GB, 512 GB, 1 TB, etc.).

[0019] In some embodiments, each memory unit may include any type of non-volatile memory device, such as a flash memory device, a phase change memory (PCM) device, a resistive random access memory (ReRAM) device, a magnetoresistive random access memory (MRAM) device, a ferroelectric random access memory (F-RAM), a holographic memory device, and any other type of non-volatile memory device.

[0020] The NVM 110 may include multiple flash memory devices or memory units. The NVM flash memory devices may include NAND- or NOR-based flash memory devices and may store data based on the charge contained in the floating gate of the transistor of each flash memory cell. In an NVM flash memory device, the flash memory device may be divided into multiple dies, each of which may include multiple physical or logical blocks, and the multiple physical or logical blocks may be further divided into multiple pages. Each of the multiple blocks within a particular memory device may include multiple NVM cells. Rows of NVM cells may be electrically connected using word lines to define each of multiple pages. Each cell in each of the multiple pages may be electrically connected to a respective bit line. Furthermore, the NVM flash memory device may be a 2D or 3D device and may be a single-level cell (SLC), multi-level cell (MLC), triple-level cell (TLC), or quad-level cell (QLC) device. The controller 108 may write data to and read data from the NVM flash memory device at the page level and erase data from the NVM flash memory device at the block level.

[0021] The power supply 111 may provide power to one or more components of the data storage device 106. When operating in a standard mode, the power supply 111 may provide power to one or more components using power provided by an external device, such as the host device 104. For example, the power supply 111 may provide power to one or more components using power received from the host device 104 via the interface 114. In some embodiments, the power supply 111 may include one or more power storage components configured to provide power to one or more components when operating in a shutdown mode, such as when the power supply 111 stops receiving power from an external device. In this manner, the power supply 111 may function as an on-board power source. Some examples of the one or more power storage components include, but are not limited to, capacitors, supercapacitors, batteries, etc. In some embodiments, the amount of power that can be stored by the one or more power storage components may be a function of the cost and / or size (e.g., area / volume) of the one or more power storage components. In other words, as the amount of power stored by the one or more power storage components increases, the cost and / or size of the one or more power storage components also increase.

[0022] Volatile memory 112 may be used by controller 108 to store information. Volatile memory 112 may include one or more volatile memory devices. In some embodiments, controller 108 may use volatile memory 112 as a cache. For example, controller 108 may store cached information in volatile memory 112 until the cached information is written to NVM 110. As illustrated in FIG. 1 , volatile memory 112 may consume power received from power supply 111. Examples of volatile memory 112 include, but are not limited to, random access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, etc.)).

[0023] The controller 108 may manage one or more operations of the data storage device 106. For example, the controller 108 may manage reading data from and / or writing data to the NVM 110. In some embodiments, when the data storage device 106 receives a write command from the host device 104, the controller 108 may initiate the data storage command, store the data in the NVM 110, and monitor the progress of the data storage command. The controller 108 may determine at least one operating characteristic of the storage system 100 and store the at least one operating characteristic in the NVM 110. In some embodiments, when the data storage device 106 receives a write command from the host device 104, the controller 108 temporarily stores data associated with the write command in an internal memory or write buffer 116 before sending the data to the NVM 110.

[0024] 2 is an exemplary diagram of a deep neural network (DNN) 200 according to certain embodiments. The DNN 200 includes an input layer 202, a first hidden layer 204a, a second hidden layer 204b, a third hidden layer 204c, and an output layer 206. The number of hidden layers shown is not intended to be limiting but rather to provide examples of possible embodiments. Furthermore, the input layer 202, the first hidden layer 204a, the second hidden layer 204b, the third hidden layer 204c, and the output layer 206 each include multiple nodes. Each node in the input layer 202 may be an input node for data input. Each node in the first hidden layer 204a, the second hidden layer 204b, and the third hidden layer 204c combines an input from data with a set of coefficients or weights that amplify or attenuate the input, thereby assigning significance to the input with respect to the task the algorithm is attempting to learn. The results of the third hidden layer 204c are passed to the nodes of the output layer 206.

[0025] The basic forward computational operation (e.g., feedforward) of a single node activation in DNN 200 may be represented by the following equation:

[0026]

number

[0027]

number

[0028] The backpropagation equations (BP1, BP2, BP3, and BP4) indicate that there is a fixed input (z) that does not change and can be processed in static memory (e.g., NVM 110 of FIG. 1 ), and that there are adjustable values ​​(C, δ, and w) that can be temporarily adjusted or calculated and processed in dynamic memory (e.g., DRAM). Another memory consumer is the DL model itself (i.e., the NN parameters, which can be the “weights” or C, δ, and w). As the power of the DNN 200 increases, the size of the DL model also increases. While a fully connected NN architecture is illustrated, it should be understood that the embodiments described herein may be applicable to other NN architectures.

[0029] 3 is a schematic block diagram illustrating a logical block address (LBA) / physical block address (PBA) addressing system 300, according to a particular embodiment. The LBA / PBA addressing system 300 includes a host device 302 coupled to a data storage device 308. The data storage device 308 is coupled to an NVM storage system that includes multiple NVMs 316a-316n. It should be understood that the multiple NVMs 316a-316n may be disposed within the data storage device 308. In some examples, the multiple NVMs 316a-316n are NAND devices. The host device 302 includes a CPU / GPU unit 304 and a block-based command generator unit 306. The block-based command generator unit 306 generates commands to be programmed into blocks of NVMs among the multiple NVMs 316a-316n. The host device 302 recognizes the LBA where the data is stored, and the data storage device 308 recognizes the PBA where the data is stored in the plurality of NVMs 316a-316n.

[0030] The data storage device 308 includes a command interpretation unit 310, a block-based flash translation layer (FTL) translation unit 312, and a flash interface unit 314, all of which may be disposed within a controller, such as the controller 108 of FIG. 1 . The command interpretation unit 310 may be configured to receive or retrieve commands from the block-based command generator unit 306. The command interpretation unit 310 may process the commands and generate associated control information for the processed commands. The commands are then passed to the block-based FTL translation unit 312, which translates the commands from an LBA to a PBA. The flash interface unit 314 passes the read / write commands to an associated NVM among the plurality of NVMs 316a-316n based on the PBA. In other words, a translation layer between the LBA and the PBA is stored in the data storage device 308 such that each time a command is passed from the host device 302 to the data storage device 308, a corresponding PBA for the LBA associated with the command is extracted from the translation layer.

[0031] FIG. 4 is a schematic block diagram illustrating an LBA / PBA addressing system 400, according to certain embodiments. The LBA / PBA addressing system 400 includes a host device 402 coupled to a data storage device 408. The data storage device 408 is coupled to an NVM storage system including multiple NVMs 416a-416n. It should be understood that the multiple NVMs 416a-416n may be located within the data storage device 408. The host device 402 includes a CPU / GPU unit 404 and an NN interface command generator unit 406. The NN interface command generator unit 406 generates commands to be programmed into blocks of NVMs among the multiple NVMs 416a-416n. In some examples, the multiple NVMs 416a-416n are NAND devices. The commands may include a NN structure and one or more hyperparameter values. The NN structure and one or more hyperparameter values ​​are stored in one or more NVMs among the multiple NVMs 416a-416n. The one or more hyperparameter values ​​may define a training procedure for the DL model. The host device 402 knows the LBAs where data is stored, and the data storage device 408 knows the PBAs where data is stored in the multiple NVMs 416a-416n.

[0032] The data storage device 408 includes an NN interface command interpretation unit 410, a schedule-based FTL transformation unit 412, and a flash interface unit 414, all of which may be located within a controller, such as the controller 108 of FIG. 1. The NN interface command interpretation unit 410 may be configured to receive or retrieve commands from the NN interface command generator unit 406. The NN interface command interpretation unit 410 may process the commands and generate associated control information for the processed commands. In some embodiments, the data storage device may hold some or all of the NN structure and hyperparameter values ​​to reduce overhead and improve storage utilization for both dynamic parameters (e.g., “weights” and cost calculations) and static parameters, such as data stored in one of the plurality of NVMs 416a-416n.

[0033] The command is then passed to a schedule-based FTL translation unit 412, where the command is translated from an LBA to a PBA based on a schedule (e.g., a DL model) passed from the host device 402 to the data storage device 408. The flash interface unit 414 passes the read / write command to an associated NVM among the plurality of NVMs 416a-416n based on the PBA. In other words, a translation layer between the LBA and the PBA is stored in the data storage device 408 such that each time a command is passed from the host device 402 to the data storage device 408, a corresponding PBA for the LBA associated with the command is extracted from the translation layer.

[0034] FIG. 5 is a flow diagram illustrating a method 500 of fully autonomous data storage device operation during deep learning training, according to certain embodiments. Method 500 may be implemented by data storage device 408 of FIG. 4 or controller 108 of FIG. 1. For illustrative purposes, aspects of LBA / PBA addressing system 400 may be referenced herein. Fully autonomous data storage device operation may omit explicit transfer of NN parameters for certain read and write commands from CPU / GPU unit 404 to data storage device 408. If a GPU is utilized in addition to a CPU, dual read / write direct storage access may be enabled between the GPU and multiple NVMs 416a-416n.

[0035] Rather, the data storage device 408 may hold the NN structure and hyperparameter values. The NN interface command interpretation unit 410 may receive the NN structure and / or hyperparameter values ​​prior to the training process, or may select the NN structure and / or hyperparameter values ​​stored in a static configuration (i.e., stored offline). Thus, the training process and placement of data in the buffer (i.e., placement of data in one of the plurality of NVMs 416a-416n based on the L2P mapping) may be completed in a “fully autonomous” manner, e.g., without requiring feedback from the host device 402.

[0036] In block 502, the host device 402 selects a NN structure from a predetermined configuration or explicitly passes a NN structure. The predetermined configuration may be a previously trained NN structure or a default NN structure. In block 504, the host device 402 begins the training process by passing data locations through a dedicated interface. For example, the training process may be initiated by placing values ​​or data locations in nodes of the input layer 202 of FIG. 2. In block 506, the data storage device 408, or more specifically, the controller 108, reads and writes according to a predetermined schedule. The predetermined schedule may be passed from the host device 402 to the data storage device 408 before the training process, or the NN structure and / or hyperparameter values ​​maintained in the data storage device 408 in an offline location (e.g., one of the NVMs 416a-416n). In block 508, the host device 402 performs computations by reading and placing data in a buffer directed to the data storage device 408.

[0037] Method 500 can implement either block 506 or block 508 independently, or both block 506 and block 508 together. For example, the controller 108 may execute block 506 without executing block 508. In some examples, the results of block 506 may be passed to the host device 402 for implementation in block 508, and / or the results of block 508 may be passed to the data storage device 408 for implementation in block 506. As the need for random reads and writes decreases, data may be addressed in either full or partial block sizes. Thus, NN parameters may be addressed in a predetermined schedule via a starting point and offset. At block 510, DL model training terminates when a threshold number of iterations is reached (i.e., the predetermined training schedule has ended) or by the host device 402 terminating the training process, such as because cost calculations remain constant.

[0038] An alternative addressing scheme can use a key-value (KV) pair interface rather than a PBA to LBA mapping. Each data instance (e.g., value) can be addressed by using a key. NN parameters can be addressed in a structure related to an iteration or part of an iteration. For example, all NN parameters belonging to the first iteration (e.g., nodes 1 through 100 from a list of greater than 100 nodes) can be addressed via a single key.

[0039] To reduce model overfitting (e.g., redundant calculations, unnecessary shifts, etc.), DL model training may use dropout. Dropout disables one or some of the hidden layer nodes in each iteration of the algorithm, improving the robustness of the DL model and therefore the performance of the algorithm. However, dropout introduces a certain degree of uncertainty. Because network connections effectively change in each iteration, NN parameters may be used differently. If dropout can be applied before the training process, the modified NN connections may already be reflected in the NN hyperparameters. For example, the controller 108 or the data storage device 408 can apply dropout to specific nodes by analyzing the NN structure iteration for each iteration or by indicating which nodes are skipped in each iteration. In some examples, the data storage device 408 or the controller 108 can randomize the nodes excluded in each iteration according to a predetermined randomization setting.

[0040] FIG. 6 is a flow diagram illustrating a method 600 of semi-autonomous data storage device operation during deep learning training, according to certain embodiments. Method 600 may be implemented by data storage device 408 of FIG. 4 or controller 108 of FIG. 1. For illustrative purposes, aspects of LBA / PBA addressing system 400 may be referenced herein. When data storage device 408 is operating in semi-autonomous mode, CPU / GPU unit 404 may indicate which NN parameters to read in each iteration. Thus, challenges of synchronizing reads / writes and handling dropouts may be reduced when storing data in multiple NVMs 416a-416n based on L2P mapping.

[0041] The data storage device 408 or the controller 108 can take advantage of the unique characteristics of the DL model training workload and update the NN parameters after each read and loss calculation in a predetermined deterministic manner. Thus, the data storage device 408 or the controller 108 can update the “weights” by semi-autonomously implementing write commands. In other words, each update or write to the NN parameters or “weights” is completed to the same address as the previous read. Therefore, it may not be necessary to send a specific write command. Rather, the CPU / GPU unit 404 transfers a list of NN parameter “weights” to update to the data storage device 408 after each iteration.

[0042] In block 602, the host device 402 selects a NN structure from a predetermined configuration or explicitly passes a NN structure for one iteration. The predetermined configuration may be a previously trained NN structure or a default NN structure. In block 604, the host device 402 begins the training process by passing data locations through a dedicated interface. For example, the training process may be initiated by placing values ​​or data locations in nodes of the input layer 202 of FIG. 2. In block 606, the data storage device 408, or more specifically, the controller 108, reads and writes according to a predetermined schedule for one training iteration. The predetermined schedule may be passed from the host device 402 to the data storage device 408 before the training process, or the NN structure and / or hyperparameter values ​​maintained in the data storage device 408 in an offline location (e.g., one of the NVMs 416a-416n). In block 608, the host device 402 performs computations by reading and placing data in a buffer directed to the data storage device 408.

[0043] Method 600 may implement either block 606 or block 608 independently, or both block 606 and block 608 together. For example, the controller 108 may execute block 606 without executing block 608. In some examples, the results of block 606 may be passed to the host device 402 for implementation in block 608, and / or the results of block 608 may be passed to the data storage device 408 for implementation in block 606. As the need for random reads and writes decreases, data may be addressed in either full or partial block sizes. Thus, NN parameters may be addressed in a predetermined schedule via a starting point and an offset. In block 610, the data storage device 408 or the controller 108 determines whether the DL model training has ended. For example, training has ended when a threshold number of iterations has been reached (i.e., the predetermined training schedule has ended) or when the host device 402 has terminated the training process, such as because cost calculations have remained constant. If training is not complete at block 610, then method 600 returns to block 602. However, if training is complete at block 610, then method 600 ends at block 612.

[0044] By reducing the overhead of command transfer and interpretation between a host device running a machine learning application and the flash memory of a data storage device, power consumption may be reduced and throughput may be improved.

[0045] In one embodiment, the data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to be coupled to a host device. The controller is further configured to receive a plurality of commands, generate a logical block address (LBA) to physical block address (PBA) (L2P) mapping for each of the plurality of commands, and store data of the plurality of commands in the respective PBAs according to the generated L2P mapping. Each of the L2P mappings is generated based on results of a deep learning (DL) training model using a neural network (NN) structure.

[0046] The controller is further configured to receive the NN structure and one or more hyperparameter values ​​and store the NN structure and the hyperparameter values ​​in a memory device. The NN structure is received from a host device. The memory device is a non-volatile memory device. The one or more hyperparameter values ​​define a training procedure for the DL training model. The NN structure and the one or more hyperparameter values ​​are provided to the DL training model at the start of the training procedure. The DL training model uses predetermined hyperparameter values ​​of one or more predetermined parameter sets. The DL training model is updated after generating each of the L2P mappings. The controller is further configured to read the weights according to the NN structure. The weights are updated after generating each of the L2P mappings. The controller is further configured to arrange data for the multiple commands into a specified buffer. The arrangement is completed without the involvement of the host device.

[0047] In another embodiment, a data storage device includes a memory device and a controller coupled to the memory device, the controller including a neural network (NN) command interpretation unit and a logical block address (LBA) to physical block address (PBA) (L2P) mapping generator coupled to the NN command interpretation unit, the controller configured to fetch training data and NN parameters from the memory device.

[0048] The NN command interpretation unit is configured to interface with an NN interface command generator located in a host device. The NN parameters are KV pair data. The training data and the NN parameters are utilized in a deep learning (DL) training model. One or more portions of the DL training model are invalidated. The controller is configured to perform autonomous fetching of the training data and the NN parameters from a memory device. The controller is further configured to update one or more weights associated with the deep learning (DL) training model. The update is to the same address as a previous read of the one or more weights.

[0049] In another embodiment, a data storage device includes non-volatile memory means and a controller coupled to the non-volatile memory means, the controller configured to store neural network (NN) parameters and one or more hyperparameter values ​​in the non-volatile memory means, execute a fully autonomous deep learning (DL) training model or execute a semi-autonomous DL training model, and store data according to the executed DL training model.

[0050] The non-volatile memory means is a NAND-based memory means. Executing includes reading and writing according to a predetermined training schedule.

[0051] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope thereof, which scope is determined by the following claims.

Claims

1. 1. A data storage device comprising: a memory device that stores a neural network (NN) structure and one or more hyperparameter values; a controller coupled to the memory device, wherein the one or more hyperparameter values ​​define a training procedure for a deep learning (DL) training model that uses the NN structure, the controller configured to be coupled to a host device, the controller comprising: receiving the NN structure and the hyperparameter values; storing the NN structure and the hyperparameter values ​​in the memory device; configured to execute the DL training model according to the NN structure and the hyperparameter values ​​stored in the memory device; Receives multiple commands generating a logical block address (LBA) to physical block address (PBA) (L2P) mapping for each of the plurality of commands, each of the L2P mappings being generated based on results of the DL training model using the NN structure; The data storage device is further configured to store data of the plurality of commands in respective PBAs according to the generated L2P mapping.

2. The data storage device of claim 1 , wherein the NN structure is received from a host device.

3. The data storage device of claim 1 , wherein the memory device is a non-volatile memory device.

4. The data storage device of claim 1 , wherein the NN structure and the one or more hyperparameter values ​​are provided to the DL training model at the start of the training procedure.

5. The data storage device of claim 1 , wherein the DL training model uses predetermined hyperparameter values ​​of one or more predetermined parameter sets.

6. The data storage device of claim 1 , wherein the DL training model is updated after generating each of the L2P mappings.

7. 2. The data storage device of claim 1, wherein the controller is further configured to read one or more weights associated with the DL training model from the memory device, the weights being updated after generating each of the L2P mappings.

8. 10. The data storage device of claim 1, wherein the controller is further configured to place the data for the plurality of commands in designated buffers, the placement being completed without the involvement of a host device.

9. 1. A data storage device comprising: a non-volatile memory means for storing neural network (NN) parameters and one or more hyperparameter values; a controller coupled to said non-volatile memory means; the one or more hyperparameter values ​​define a training procedure for a deep learning (DL) training model; The controller: receiving the NN parameters and the hyperparameter values; storing the NN parameters and the one or more hyperparameter values ​​in the non-volatile memory means; Executing a fully autonomous deep learning (DL) training model or a semi-autonomous DL training model according to the NN parameters and the hyperparameter values ​​stored in the non-volatile memory means; wherein the semi-autonomous DL training model executes the DL training model according to specific NN parameters read from the non-volatile memory means for each training iteration under the direction of a host device; upon receiving a plurality of commands, generating a logical block address (LBA) to physical block address (PBA) (L2P) mapping for each of the plurality of commands, each of the L2P mappings being generated based on results of the DL training model; The data storage device is configured to store data for the plurality of commands in respective PBAs according to the generated L2P mapping.

10. 10. The data storage device of claim 9, wherein said non-volatile memory means is a NAND-based memory means.

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