Power semiconductor element test equipment

Abstract

To solve the problem of a conventional semiconductor element testing device that the connection state of a semiconductor element cannot be checked.SOLUTION: Switch circuits Ssb and Ssd are turned on and Switch circuits Ssc and Ssa are turned off. On voltage is applied to a transistor 117s and off voltage is applied to a transistor 117m. When the transistor 117s is connected normally, current Ia is detected by a clamp meter 128 with a current sensor 129. The connection of the transistor 117m is checked by turning off the switch circuits Ssb, Ssd, and Ssa and turning on the switch circuit Ssc. On voltage is applied to the transistor 117m and off voltage is applied to the transistor 117s. In the connection failure, Ia is not detected. In the case of normal connection, a power source device 132 feeds test current Id from the next cycle.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an electric element testing apparatus and method for testing semiconductor elements and electric elements, as well as to an electric element / semiconductor element evaluation method, evaluation test apparatus, and configuration of an electric element / semiconductor element. [Background technology]

[0002] Life tests for electrical elements such as semiconductor elements are conducted by turning the current on and off. The current from the semiconductor elements that supplies the inverter circuit and power circuit is large, at tens of amperes or more. There are many types of tests for electrical elements, and it is necessary to change the connection of the connecting wiring depending on the type of test.

[0003] For electrical element testing, it is necessary to check the connections before starting the test, and then start the test after checking. In addition, when testing semiconductor elements, it is necessary to conduct tests that are compatible with the circuit configuration that will actually be used. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2017-17822 Summary of the Invention [Problem to be solved by the invention]

[0005] Because circuit operations such as inverter circuits are complex, semiconductor device test equipment must also change its operation to suit the circuit operations, etc. However, conventional semiconductor device test equipment was unable to perform reliability tests on semiconductor devices in a way that suited actual use conditions.

[0006] When testing transistors, etc., a large current is applied. Therefore, when starting the test, it is necessary to check that the transistor terminals and the test circuit are securely connected. If the test is started with a poor connection, surge voltages and inrush currents will occur, destroying the transistors, etc. Conventional semiconductor device testing equipment is unable to check the connection state of the semiconductor device, and the semiconductor device may be destroyed at the start of the test.

[0007] Many of the devices driven by inverter circuits have large inductances, such as motors. When current flows through an inductance, large surge voltages and transient phenomena occur. Therefore, it is necessary to conduct tests on transistors and other devices that drive inverter circuits, taking into account the surge voltages and transient phenomena that may occur. However, surge voltages and transient phenomena are so diverse that it is not easy to carry out tests that address all of these assumptions.

[0008] Because the current applied to test semiconductor elements such as transistors is several hundred amperes or more, the connecting wires must be thick and low-resistance. Thick connecting wires are hard and inflexible. Changing the connections of thick connecting wires to match the test items takes a long time. [Means for solving the problem]

[0009] The power supply device 132 outputs a current Ia (not shown) when checking the connection. The current Ia is sufficiently smaller than the test current for checking the connection. An example is Ia<0.1Id. If the current Ia flows, it is determined that the connections of the switches, etc. and the test device, etc. are complete, and the device enters a test mode in which a test current flows. If the current Ia cannot be measured, it is determined that the connections of the switches, etc. and the test device, etc. are faulty, and the device does not enter test mode.

[0010] Switch circuits Ssb and Ssd are turned on, and switch circuit Ssc is turned off. An on voltage is applied to transistor 117s, and an off voltage is applied to transistor 117m. If transistor 117s is connected properly, current Ia is detected by clamp meter 128 via current sensor 129; if the connection is faulty, Ia is not detected. If the connection is normal, power supply device 132 will pass test current Id from the next cycle.

[0011] To check the connection of transistor 117m, switch circuits Ssb and Ssd are turned off, and switch circuit Ssc is turned on. An on voltage is applied to transistor 117m, and an off voltage is applied to transistor 117s. If transistor 117m is connected properly, current Ia is detected by clamp meter 128 via current sensor 129; if the connection is faulty, Ia is not detected. If the connection is normal, power supply device 132 will pass test current Id from the next cycle. [Effects of the Invention]

[0012] In the semiconductor test, the normal test current Id is applied after checking the connections of the semiconductor elements to be tested, so the semiconductor elements to be tested are not destroyed. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a block diagram and an explanatory diagram of a semiconductor device testing apparatus according to an embodiment of the present invention; [Figure 2] 1 is a configuration diagram of a semiconductor device testing device according to the present invention; [Figure 3] 1 is a block diagram and an explanatory diagram of a semiconductor device testing apparatus according to the present invention; [Figure 4] 1 is a block diagram and an explanatory diagram of a semiconductor device testing apparatus according to the present invention; [Figure 5] 1 is a block diagram and an explanatory diagram of a semiconductor device testing apparatus according to the present invention; [Figure 6] 1 is a block diagram and an explanatory diagram of a semiconductor device testing apparatus according to the present invention; [Figure 7]1A and 1B are explanatory and configuration diagrams of a semiconductor device testing device according to the present invention; [Figure 8] 1A and 1B are explanatory and configuration diagrams of a semiconductor device testing device according to the present invention; [Figure 9] 1A and 1B are explanatory and structural diagrams of a semiconductor element mounting portion of a semiconductor element testing apparatus according to the present invention; [Figure 10] 1A and 1B are explanatory and structural diagrams of a semiconductor element mounting portion of a semiconductor element testing apparatus according to the present invention; [Figure 11] 1A and 1B are explanatory and structural diagrams of a connection structure of a semiconductor element testing apparatus according to the present invention; [Figure 12] 1A and 1B are explanatory and structural diagrams of a connection structure of a semiconductor element testing apparatus according to the present invention; [Figure 13] 1A and 1B are explanatory and structural diagrams of a heat pipe portion of a semiconductor element testing apparatus according to the present invention; [Figure 14] 1A and 1B are explanatory and structural diagrams of a heat pipe portion of a semiconductor element testing apparatus according to the present invention; [Figure 15] 1A and 1B are explanatory and structural diagrams of a mounting fixture for a semiconductor device testing apparatus according to the present invention; [Figure 16] 1A and 1B are explanatory and structural diagrams of a mounting fixture for a semiconductor device testing apparatus according to the present invention; [Figure 17] 1 is an explanatory diagram of a test method for a semiconductor device according to an embodiment of the present invention; [Figure 18] 1 is an explanatory diagram of a test method for a semiconductor device according to an embodiment of the present invention; [Figure 19] 1 is a block diagram and an explanatory diagram of a semiconductor device testing apparatus according to an embodiment of the present invention; [Figure 20] 1 is an explanatory diagram of a test method for a semiconductor device according to an embodiment of the present invention; [Figure 21] 1 is an explanatory diagram of a test method for a semiconductor device according to an embodiment of the present invention; [Figure 22] 4 is a timing chart of a test method for a semiconductor device according to an embodiment of the present invention; [Figure 23] 4 is a timing chart of a test method for a semiconductor device according to an embodiment of the present invention; [Figure 24]4 is a timing chart of a test method for a semiconductor device according to an embodiment of the present invention; [Figure 25] 4 is a timing chart of a test method for a semiconductor device according to an embodiment of the present invention; [Figure 26] 4 is a timing chart of a test method for a semiconductor device according to an embodiment of the present invention; [Figure 27] 4 is a timing chart of a test method for a semiconductor device according to an embodiment of the present invention; [Figure 28] 1A and 1B are explanatory diagrams and an equivalent circuit diagram of a semiconductor element to be tested; [Figure 29] FIG. 1 is an explanatory diagram illustrating driving a three-phase motor using semiconductor elements. [Figure 30] FIG. 2 is an explanatory diagram of three-phase current waveforms. [Figure 31] FIG. 1 is an explanatory diagram of a method for generating a sine wave current using a PWM signal. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, a testing apparatus and a testing method for an electric element according to an embodiment of the present invention will be described with reference to the accompanying drawings. In the embodiments described in the specification, the IGBT will be mainly used as an example of a power semiconductor element as an electric element.

[0015] The present invention is not limited to IGBTs, but can be applied to various semiconductor elements such as reverse conducting IGBTs (RC-IGBTs), SiC transistors, MOSFETs, JFETs, thyristors, diodes, thermistors, and posistors.

[0016] Furthermore, it goes without saying that the present invention is not limited to semiconductor elements, but can also be applied to electrical elements other than semiconductor elements, such as resistor elements, capacitors, coils, crystal elements, varistors, and ZNR. The embodiments of the present invention described in the specification and drawings can be combined in part or in whole with each other, and can be combined with modifications.

[0017] Fig. 2 is a diagram illustrating the configuration and explanation of the semiconductor device testing apparatus of the present invention. As shown in Fig. 2, the semiconductor device testing apparatus of the present invention has a housing 210, a chiller (cooling / heating device) 136, a heating / cooling plate 134, and a circulating water pipe 135 that circulates water between the heating / cooling plate 134 and the chiller 136.

[0018] The transistor 117 to be tested and the like are placed in close contact with the heating / cooling plate 134. To achieve close contact, a heat transfer sheet may be placed and silicone grease may be applied.

[0019] 10, the partition wall 217 has an opening 216 for inserting a connection structure 218, which will be described in Figures 7, 8, 9, etc. The partition wall 215 has a hole for inserting a power supply wiring 212.

[0020] 2 includes a power supply device 132 that supplies a test current and a test voltage to the semiconductor element 117, and a control circuit 133 that controls the semiconductor element 117 or sets test conditions. The power supply device 132 includes, for example, a power supply device 132a and a power supply device 132b. The power supply device 132a outputs a forward current Id (positive polarity), and the power supply device 132b outputs or generates a current Id (reverse polarity) in the opposite direction to the power supply device 132a.

[0021] Although the current Id is described as a constant current, it is not limited to a constant current. It may be a variable current that changes depending on the test state of the semiconductor device being tested. Furthermore, what is supplied to the semiconductor device being tested is not limited to the current Id, and may be a voltage.

[0022] The control circuit 133 sets test conditions by varying the current Id, the gate drive voltage Vg, and the channel voltage Vce of the transistor 117 so that the temperature information Tj of the semiconductor element 117 becomes a predetermined value, and then performs the test.

[0023] The temperature information Tj includes the temperature of a test element such as a transistor, the terminal voltage due to the current flowing through the element to be tested such as a transistor or diode, a change in the terminal voltage, temperature-related information obtained from the terminal voltage, a value calculated from the terminal voltage, heat obtained by measuring the test element, etc. Although the temperature information Tj is used in this specification, it goes without saying that the temperature information is not limited to Tj. A control circuit 133 shown in FIG. 2 controls the power supply 132, which supplies a test voltage or current to the semiconductor device 117 under test.

[0024] If the temperature information Tj changes or changes to a predetermined value, it is determined that the semiconductor element 117 being tested has deteriorated or its characteristics have changed, and the test of the semiconductor element 117 is stopped or the test method or control method is changed.

[0025] The temperature of the semiconductor element 117 is maintained at a specified or predetermined value by heating or cooling the circulating water of the chiller 136. In addition, the temperature of the semiconductor element etc. is periodically changed in accordance with the test conditions, and the element is cooled or heated at a constant temperature.

[0026] The semiconductor element testing apparatus and semiconductor element testing method of the present invention can be applied to a wide variety of semiconductor elements 117 and semiconductor modules 117. As an example, the semiconductor element 117 in Fig. 28 has terminals P electrode terminal, O electrode terminal, and N electrode terminal to which a large current is applied or output, gate terminals g (gate terminal gm, gate terminal gs) to which a gate voltage is applied, collector terminals c (collector terminal cm, collector terminal cs), and emitter terminals e (emitter terminal em, emitter terminal es).

[0027] 28A and 28B are a schematic view and an equivalent circuit diagram of a semiconductor device, respectively. 28A and 28B show a configuration including a transistor 117 (transistor 117m, transistor 117s) and a diode Di (diode Dim, diode Dis).

[0028] Figures 28(b1) and (b2) show a configuration in which multiple transistors are connected together to perform testing by connecting the terminals of a semiconductor element having a transistor 117 (transistor 117m or transistor 117s) and a diode Di (diode Dim or diode Dis).

[0029] 28(c1) and (c2) show a configuration having a transistor 117 (transistor 117m or transistor 117s) and diodes Ds and Dm. Diodes Ds and Dm are diodes that detect the temperature of the transistor 117 or evaluate temperature changes. Diodes Ds and Dm are arranged and formed independently from the three terminals of the transistor (gate terminal, collector terminal, emitter terminal).

[0030] In the following embodiments, the semiconductor element 117 shown in Fig. 28 will be mainly used as an example. It goes without saying that the present invention is not limited to IGBTs, but may also be applied to other transistors having three terminals, such as SiC, bipolar transistors, MOS transistors, and FETs. It goes without saying that the present invention is not limited to these, and that the embodiments of the present invention can also be applied to electrical elements other than semiconductor elements, such as resistor elements.

[0031] Furthermore, as shown in FIG. 28, it is not limited to a configuration in which multiple transistors are connected, but it goes without saying that it can also be applied to testing a single transistor, semiconductor, or electrical element.

[0032] Fig. 1 is a block diagram and an explanatory diagram of a semiconductor device testing apparatus according to the present invention. Fig. 1 shows an example of a semiconductor device 117 to be tested, as shown in Fig. 28(a). However, it goes without saying that the present invention is not limited to Fig. 28(a).

[0033] The power supply device 132 of the semiconductor device testing device includes a power supply device 132a that generates a constant current in the forward direction and a power supply device 132b that generates a constant current in the reverse direction. When applying a test current to transistors 117s and 117m, the constant current is supplied from power supply device 132a. When applying a test current to diodes Dis and Dim, the constant current is supplied from power supply device 132b. Note that the test is not limited to a constant current, and a constant voltage may also be used. Furthermore, the voltage or current may be varied for a predetermined time or at a predetermined cycle.

[0034] The current flowing out of, or into, the power supply device 132 is detected or picked up by the current sensor 129, and the current is detected or measured by the clamp meter 128.

[0035] Clamp meter 128 measures or samples the current flowing through power supply wiring 212 in synchronization with a gate control signal (on / off signal) applied to transistor 117 under test. Note that the current measuring device is not limited to clamp meter 128, and may be, for example, a device that detects magnetism or electromagnetic waves from power supply wiring 212.

[0036] The current flowing into the power supply device 132 is placed on the power supply wiring 212a (ground wiring) like the current sensor 129a in Fig. 1. The current flowing out from the power supply device 132 is placed or installed on the power supply wiring 212b (power supply wiring) like the current sensor 129b in Fig. 1.

[0037] Clamp meter 128 measures or samples the current flowing through power supply wiring 212 in synchronization with a gate control signal (on / off signal) applied to transistor 117 under test. Note that the current measuring device is not limited to clamp meter 128, and may be, for example, a device that detects magnetism or electromagnetic waves from power supply wiring 212.

[0038] The connection to the switch circuit 124 for changing the connection is made using a fork plug 205. Connection and change of connection are made by inserting the fork plug 205 through an opening provided in the partition wall of the housing and making electrical contact with the switch circuit 124.

[0039] The power supply device 132 outputs a large constant current for testing the transistor 117. The power supply device 132 supplies power (current, voltage) in synchronization with a control signal from the control circuit board (controller) 111. The power supply device 132 can set the maximum voltage value to be output.

[0040] The power supply device 132 includes a power supply device 132a that outputs a forward current Id and a power supply device 132b that outputs a reverse current Id. The power supply devices 132a and 132b are controlled by the controller 111.

[0041] The switch circuit 122a (SWa) has a function of turning on (supply, application) and off (shutoff, open) the supply of the constant current output by the power supply device 132a. The switch circuit 122b (SWb) has a function of turning on (supply, application) and off (shutoff, open) the supply of the constant current output by the power supply device 132b.

[0042] The switch circuit 124c mainly functions to short-circuit the channel (emitter terminal-collector terminal) of the transistor 117s, or to connect the ground wiring and the collector terminal of the transistor 117m.

[0043] The switch circuit 124d mainly has a function of short-circuiting the channel (emitter terminal-collector terminal) of the transistor 117m, or a function of connecting the power supply wiring 212 and the emitter terminal of the transistor 117s.

[0044] 1, a connector 202m is connected to the terminals (emitter terminal em, gate terminal gm, collector terminal cm) of a transistor 117m, and a connector 202s is connected to the terminals (emitter terminal es, gate terminal gs, collector terminal cs) of a transistor 117s.

[0045] 3, 6, etc., fork plug 205e is connected to the P electrode terminal (element terminal 226a), fork plug 205h is connected to the O electrode terminal (element terminal 226c), and fork plug 205c is connected to the N electrode terminal (element terminal 226b). By attaching or detaching fork plug 205, switch circuit 124 and the terminals (P terminal, O terminal, N terminal) of semiconductor element 117 are connected to each other.

[0046] A predetermined constant current Ic is applied to the diode Di (diode Dim, diode Dis) of the semiconductor element 117 (semiconductor element 117s, semiconductor element 117m) to be tested during a period when the test current Id is not being applied. The equivalent resistance value of the diode changes with temperature, and the terminal voltage of the diode Di changes when a predetermined constant current is applied. Temperature information Tj is obtained from information on this terminal voltage Vi. FIG. 3 is an explanatory diagram and block diagram for explaining the sample connection circuit 203, focusing on the sample connection circuit 203 in FIG.

[0047] The sample connection circuit 203 is connected to the collector terminal, gate terminal, and emitter terminal of the transistor 117m and the transistor 117s. The sample connection circuit 203 is connected to the device control circuit board 209 and the control circuit board 111 and is controlled by them.

[0048] 3, a short circuit 137m is formed or placed between the gate terminal gm and the emitter terminal em of the transistor 117m, and a short circuit 137s is formed or placed between the gate terminal gs and the emitter terminal es of the transistor 117s.

[0049] The short circuit 137 is not limited to a switch and may be, for example, a short connector. It is preferable that the operation of the short circuit 137 be configured so that it can be controlled by the control circuit board 111 or the like. For example, the short circuit 137 is configured by an analog switch or the like.

[0050] When the short circuit 137s is turned on, the gate terminal gs and the emitter terminal es of the transistor 117s are short-circuited, and the transistor 117s is diode-connected.

[0051] When the short circuit 137m is turned on, the gate terminal gm and the emitter terminal em of the transistor 117m are short-circuited, and the transistor 117m is diode-connected.

[0052] 3, a constant current circuit 118m is configured to pass a constant current Icm through a diode Dim of a transistor 117m, and the voltage across the diode Dim is measured by the voltage across the collector terminal cm and emitter terminal em of the transistor 117m. Also, a constant current circuit 118s is configured to pass a constant current Ics through a diode Dis of a transistor 117s, and the voltage across the diode Dis is measured by the voltage across the collector terminal cs and emitter terminal es of the transistor 117s.

[0053] When a constant current is to flow through the diode Di, the transistor 117 is turned off. The constant current Icm to the diode Dim is fed as a sink current from the transistor Tm. The constant current Ics to the diode Dis is fed as a sink current from the transistor Ts.

[0054] The voltage across the diode Dim is measured or obtained by a voltage detection circuit 116m connected to the collector terminal cm and emitter terminal em of a transistor 117m. The voltage across the diode Dis is measured or obtained by a voltage detection circuit 116s connected to the collector terminal cs and emitter terminal es of a transistor 117s.

[0055] In the sample connection circuit 203, a gate signal control circuit 112, a gate driver circuit 113, a drive element circuit 127a, a short circuit 137, a constant current circuit 118, a voltage detection circuit 116, a temperature measurement circuit 115, etc. are formed and arranged.

[0056] The terminals of each circuit are connected to connection pins 206 of connector 202 and connection pins 206 of connector 208. The connection positions with connection pins 206 can be changed or varied using socket pins (not shown) or the like. The connection can also be changed to any or predetermined connection pins 206 using analog switches (not shown) or the like. Therefore, the semiconductor element testing apparatus of the present invention can change the connection between the internal wiring of sample connection circuit 203 and connection pins 206 depending on the terminal positions of semiconductor element 117 to be tested, the test conditions, and the test method.

[0057] 7, the sample connection circuit 203 is placed near the semiconductor element 117 to be tested, etc. This is to shorten the length of the signal wiring 222 that connects the semiconductor element 117 and the sample connection circuit 203. The signal wiring 222 transmits gate on / off signals and the like for the transistor 117. If noise or the like is multiplexed on the gate on / off signal, the noise may turn on the transistor 117 under test, which could result in destruction.

[0058] In the present invention, the sample connection circuit 203 is placed near the transistor 117. The wiring connection of the sample connection circuit 203 for the transistor 117 needs to be changed depending on the signal to be tested. In the present invention, the internal wiring of the sample connection circuit 203 is configured so that it can be easily changed, so that various tests can be performed without moving the position of the sample connection circuit 203.

[0059] In the embodiment of FIG. 3, the transistor 117 is configured to be tested as shown in FIG. 28(a) or FIG. 28(b). In the embodiment of FIG. 4, the transistor 117 is configured to be tested as shown in FIG. 28(c).

[0060] 3 and 4, different configurations of the transistor 117 to be tested result in different wiring states of the connection pins 206 of the connector 202. As shown in FIGS. 3 and 4, the wiring states can be easily changed within the sample connection circuit 203 of the present invention.

[0061] 4, one terminal of the constant current circuit 118 is connected to the P2 terminal of the connector 202, and in FIG. 3, one terminal of the constant current circuit 118 is connected to the P4 terminal of the connector 202. The connection can be changed manually or by settings from the controller circuit 111 using an analog switch circuit or the like. As shown in FIG. 1, a connector 202m is connected to the transistor 117m, and a connector 202s is connected to the transistor 117s.

[0062] A predetermined constant current Ic (Ics, Icm) for temperature monitoring is applied to at least one of the diodes Dm and Ds. The equivalent resistance value of the diode changes depending on the temperature of the semiconductor element 117, and application of the predetermined constant current changes the terminal voltage of the diode D (diode Dm, diode Ds). From information on this terminal voltage Vi, the temperature measurement circuits (temperature measurement circuits 115s, 115m) calculate temperature information Tj (temperature information Tjs, temperature information Tjm).

[0063] 3 and 4, a short circuit 137m is formed between the gate terminal gm and the emitter terminal em of the transistor 117m. A short circuit 137s is formed between the gate terminal gs and the emitter terminal es of the transistor 117s. The short circuit 137 is, for example, a switching transistor or an analog switch. The short circuit 137 is not limited to an element such as a transistor, but may be a mechanical short circuit using, for example, a connector or a short pin.

[0064] When short circuit 137 (short circuit 137m, short circuit 137s) is turned on, the emitter terminal and gate terminal of transistor 117m or transistor 117s are shorted. When the emitter terminal and gate terminal of transistor 117m or transistor 117s are shorted, transistor 117m or transistor 117s are diode-connected. Note that short circuit 137 (short circuit 137s, short circuit 137m) may be disposed or configured within sample connection circuit 203 (sample connection circuit 203s, sample connection circuit 203m).

[0065] The sample connection circuit 203 includes a gate driver circuit 113, a gate signal control circuit 112, a voltage detection circuit 116 that measures the terminal voltage of the diode, a constant current circuit 118 (constant current circuit 118s, constant current circuit 118m) that generates a constant current to be applied to the diode, and a drive element circuit 127a (drive element circuit 127as, drive element circuit 127am).

[0066] The gate driver circuit 113 can vary the output voltage Vsg. The gate driver circuit 113 can change or set the on-voltage and off-voltage. For example, as shown in FIG. 22, the off-voltage can be changed from 0V to a Vt voltage lower than 0V in accordance with the drive timing. It can also be set to a voltage equal to or higher than 0V. Furthermore, the gate driver circuit 113 changes the on-voltage Vg shown in FIG. 22 in accordance with the drive timing.

[0067] For example, during periods tn2 and tn1, a current Ic is supplied to a diode D (diode Dis, diode Dim), and when temperature information of the transistor 117 to be tested is obtained, a Vt voltage is applied to the gate terminal of the transistor 117, and when a test current Id is passed, a Vg voltage of the transistor 117 is applied.

[0068] When Vg2>Vg1, and current Ic is passed through transistor 117 to acquire temperature information, a high voltage Vg2 is applied to the gate terminal of transistor 117 to reduce the resistance between the channels of transistor 117. By reducing the resistance between the channels of transistor 117, heat generation between the channels of transistor 117 is significantly reduced, allowing the temperature of transistor 117 (temperature information Tj) to be acquired with high accuracy. During testing, a test voltage Vg1 is applied to the gate terminal of transistor 117 to perform the test. With the constant current Ic flowing, the intended temperature information Tj can be set and a power cycle test can be carried out.

[0069] The temperature information Tj is acquired periodically or for a fixed period. Therefore, Vg2 and Vg1 change or are changed periodically or for a fixed period. Vg2 and Vg1 can be set to any voltage value.

[0070] As described above, by changing or setting the gate terminal voltage during temperature measurement (temperature information Tj) and during testing, it is possible to obtain good temperature information and perform testing. Note that the voltage changes of Vg2 and Vg1 are configured to be synchronized with the cycle tc (tc1, tc2, ...) in Figure 23.

[0071] 3, the temperature of the semiconductor element 117 under test is measured by applying a constant current to the diode Di (diode Dim, diode Dis) and measuring the terminal voltage of the diode Di. However, this is not limiting. Instead of the diode Di, a parasitic diode additionally formed during the formation of the transistor 117 may be used to measure the temperature. It goes without saying that a diode made up of a separate chip may be incorporated into the package of the transistor 117, and the temperature and temperature characteristics of the transistor 117 may be measured using this diode.

[0072] Alternatively, a body diode may be formed on the transistor chip and used. Alternatively, a thermocouple, a temperature sensor, or the like may be used. The means for measuring the temperature may be built into the semiconductor element 117, or may be attached in close proximity to the semiconductor element 117.

[0073] Furthermore, the temperature of the transistor 117 may be measured by a thermocouple or the like attached to the package of the transistor 117. The above matters are also applicable to other semiconductor elements of the present invention.

[0074] 4, the temperature of the semiconductor element 117 under test is measured by applying a constant current Ic to the diode Ds or the diode Dm and measuring the terminal voltage of the diode Ds or the diode Dm. However, this is not limited to this. Instead of the diode Ds or the like, the temperature may be measured using a body diode additionally formed when the transistor 117 is formed. Alternatively, a thermocouple, a temperature sensor, or the like may be used. The means for measuring the temperature may be built into the semiconductor element 117 or may be attached in close proximity to the semiconductor element 117.

[0075] 1, 7, and 8, the sample connection circuit 203 is arranged near the transistor 117 (semiconductor element 117) so as to shorten the length of the signal wiring 222 connected to the transistor 117. Nearby means approximately 50 mm or less.

[0076] The transistor 117 in Fig. 3 does not form an independent diode. Therefore, the output current of the constant current circuit 118 is applied between P1 and P4 of the connector 202. The transistor 117 in Fig. 4 does form an independent diode. Therefore, the output current of the constant current circuit 118 is applied between P1 and P2 of the connector 202.

[0077] 3 and 4, it is necessary to change the magnitude of the current output by the constant current circuit 118, the timing of current application, and the pin position of the connecting connector 202. Also, it is necessary to change the settings of the resistance value of the drive element circuit 127a according to the use of the transistor 117 to be tested. It may also be necessary to change the control of the short circuit 137 and the position of the connecting pin 206.

[0078] The present invention basically shares the sample connection circuit 203, and can switch the connection state according to the test conditions, test method, and specifications of the tested transistor 117. Although not shown in Figures 3 and 4, an analog switch circuit or relay circuit is disposed within the sample connection circuit 203, and settings are changed using these circuits.

[0079] The sample connection circuit 203 includes a gate driver circuit 113m that generates a gate signal waveform to be applied to the gate terminal gm of the transistor 117m, a drive element circuit 127am that adjusts or sets the rising and falling waveforms of the gate signal, a short circuit 137m, and the like.

[0080] The sample connection circuit 203 also includes a constant current circuit 118m that generates a constant current Icm to be applied to the diode Dm of the transistor 117m, and a voltage detection circuit 116m that measures or detects the terminal voltage of the diode Dm.

[0081] The sample connection circuit 203 also includes a gate driver circuit 113s that generates a gate signal waveform to be applied to the gate terminal gs of the transistor 117s, a drive element circuit 127as that adjusts or sets the rising and falling waveforms of the gate signal, a short circuit 137s, and the like.

[0082] The sample connection circuit 203 also includes a constant current circuit 118s that generates a constant current Ics to be applied to the diode Ds of the transistor 117s, and a voltage detection circuit 116s that measures or detects the terminal voltage of the diode Ds.

[0083] 3 and 4, the drive element circuit 127a is connected to the input impedance of the gate terminal g of the transistor 117. However, the setting of the drive waveform of the transistor 117 is not limited to changing or setting the resistance value. In the present invention, a drive variable circuit 126 shown in FIG. 5 is formed or configured to change the signal waveform applied to the gate terminal etc., set the signal waveform, and change the test state.

[0084] The drive variable circuit 126 contains a plurality of drive element circuits 127. The drive variable circuit 126 is controlled by the control circuit 111, and one or more drive element circuits 127 are selected and electrically connected to the gate terminal of the transistor 117 to be tested. In addition, the resistance values ​​(Vr, R1, R2) of the resistor elements of the drive element circuit 127 are varied and set to predetermined values.

[0085] The resistance value Vr of the drive element circuit 127a of the drive variable circuit 126 can be set to any value between 0 (Ω) and 500 (Ω). It is also configured so that it can be set to a constant voltage or can be changed over time. For example, an electronic volume can be used.

[0086] The drive variable circuit 126 can set the slope of the rising waveform (rise time Tr) and the slope of the falling waveform (fall time Td) of the gate voltage signal applied to the gate terminal g of the transistor 117.

[0087] 3 and 4, the resistance value Vr of the drive element circuit 127a of the drive variable circuit 126 is variable, but this is not limiting. For example, the drive variable circuit 126 may be an external resistor.

[0088] 5 is an explanatory diagram and block diagram focusing on the variable drive circuit 126 of the semiconductor device testing apparatus of the present invention. The variable drive circuit 126 is a circuit that mainly sets the impedance of the gate terminal of a semiconductor device such as transistor 117, and the rising (turn-on) waveform and falling (turn-off) time waveform of the signal waveform applied to the gate terminal.

[0089] 5, a plurality of drive element circuits 127 are arranged in a drive variable circuit 126. The drive variable circuit 126 is arranged to correspond to the transistors 117s and 117m. The resistance element of the drive element circuit 127a is configured so that the resistance value can be varied within a range from 0Ω to 300Ω.

[0090] The switch circuit S1 (switch circuit S1s, switch circuit S1m), switch circuit S2 (switch circuit S2s, switch circuit S2m), switch circuit S3 (switch circuit S3s, switch circuit S3m), and switch circuit S4 (switch circuit S4s, switch circuit S4m) are configured so that they can be independently set to on or off (open or close). Therefore, multiple driver element circuits 127 can be selected simultaneously.

[0091] To maintain a low on-state voltage, IGBTs and bipolar transistors require a large base current. On the other hand, because power MOSFETs are voltage-controlled elements, they can be driven with only a small amount of power, just enough to charge the gate. The input capacitance of power MOSFETs is relatively large, so a low-impedance signal source must quickly charge the input capacitance, especially when switching at high speeds. A low impedance drive is required to shorten the turn-on time, but increasing the gate-source voltage conversely lengthens the turn-off time.

[0092] As described above, it is necessary to appropriately set the input impedance to the gate terminal in accordance with the characteristics of the semiconductor element 117 to be tested. In the present invention, the input impedance can be easily set by providing the driver element circuit 127 within the drive variable circuit 126. In other words, the switching time can be changed by changing the gate resistance value of the semiconductor element to be tested.

[0093] In the present invention, if it is desired to change the switching performance on the ON and OFF sides, this can be done by selecting any drive element circuit 127 in the drive variable circuit 126 and changing the resistance value of the drive element circuit 127a.

[0094] As described above, it is necessary to appropriately set the input impedance to the gate terminal in accordance with the characteristics of the semiconductor element 117 to be tested. In the present invention, the input impedance can be easily set by providing the driver element circuit 127 within the drive variable circuit 126. In other words, the switching time can be changed by changing the gate resistance value of the semiconductor element to be tested.

[0095] In the present invention, if it is desired to change the switching performance on the ON and OFF sides, this can be done by selecting any drive element circuit 127 in the drive variable circuit 126 and changing the resistance value of the drive element circuit 127a.

[0096] For example, in the case of drive element circuit 127b, the gate resistance when on is R1 and when off is R2. In the case of drive element circuit 127c, the gate resistance when on is R1 and R2 in parallel and when off is R2. In the case of drive element circuit 127d, the gate resistance when on is R2 and when off is R1 and R2 in parallel. The selection of drive element circuit 127 is performed by controller 111.

[0097] As described above, the semiconductor device testing apparatus of the present invention can test semiconductor devices under actual use conditions using the drive variable circuit 126. In addition, it can easily perform a wide variety of tests, such as overload drive tests, surge withstand voltage tests, and avalanche tests.

[0098] The potential of the emitter terminal e is used as a reference for the gate drive signal Vsg applied to the gate terminal g of the transistor 117. As shown in Figure 22(a), if the voltage that turns on the transistor 117 is Vg, when the Vg voltage is applied from the emitter potential, the transistor 117 turns on.

[0099] In the present invention, the 0 (V) potential is a voltage that turns off the transistor 117. The Vt voltage in FIG. 22(a) is a voltage with a more negative polarity than the 0 (V) potential. By applying the negative voltage Vt before applying the on voltage, the rising voltage curve from the negative voltage Vt to the on voltage (Vg) becomes steeper. Furthermore, depending on the type of transistor 117, the off characteristics of the transistor 117 can be improved.

[0100] The Vt voltage is applied during the tn2 and tn1 periods, and the tn2 and tn1 periods can be set as desired. The ton period is a period during which the Vg voltage (the on-voltage of the transistor 117) is applied. The Vt voltage can be varied and set as desired.

[0101] 5, the voltage waveform of the gate drive signal Vsg can be changed by selecting the drive element circuit 127 of the drive variable circuit 126. In Fig. 22(a), as an example, the waveform of the gate drive signal Vsg that is changed by selecting the drive element circuit 127 is shown by a solid line, a dotted line, etc.

[0102] As the waveform of the gate drive signal Vsg changes, the current Id flowing through the channel of the transistor 117 changes as shown by the solid line, dotted line, etc. in FIG. 22(b). The current Ia can be varied. Therefore, surge voltages and currents, transient voltages, transient currents, etc. that occur when the current Id rises and falls can be generated according to the test.

[0103] In FIG. 22, as an example, Vg is the on voltage, and 0 (V) or Vt voltage is the off voltage. As shown in FIG. 22(a), a negative voltage may be applied before the on voltage Vg is applied, and after it changes from the on voltage to the off voltage, it may be set to 0 (V). As shown in FIG. 22(a), the application period of the Vt voltage may be eliminated, and a 0 (V) voltage may be applied. In the present invention, the values ​​or control of the on voltage and off voltage are appropriately set according to each case.

[0104] 22(a), the transistor 117 is controlled to be turned on and off. The gate driver circuit 113 is controlled by a device control circuit board 209. The current source 121 outputs a constant current Id, which is supplied as Id to the transistor 117 .

[0105] The transistor 117 is turned on and off by the Vsg signal voltage output from the gate driver circuit 113, and a current Id flows between the channels of the transistor 117 while the transistor 117 is on.

[0106] As shown in Fig. 5, a variable drive circuit 126 is arranged on the output side of the gate driver circuit 113, and the variable drive circuit 126 has a drive element circuit 127a. Alternatively, as shown in Figs. 3 and 4, a variable resistance circuit 125 is arranged. The value of the variable resistance circuit 125 or the drive element circuit 127a is configured so that it can be set to a predetermined value or in steps between 0 (Ω) and 500 (Ω). The value of the drive element circuit 127a may be set by a control signal from the controller circuit board 111 (controller 111) while observing the waveform of the gate terminal g.

[0107] 5, drive element circuit 127a corresponds to drive element circuit 127a in Figures 3 and 4. In the semiconductor element testing apparatus of the present invention, a drive variable circuit 126 is arranged or configured as shown in Figure 5 in order to adapt the signal waveform applied to the gate terminal to the test conditions or to accommodate a wide variety of signal waveforms.

[0108] A resistor R (not shown) may be disposed between the gate terminal g and the emitter terminal e or the collector terminal c of the transistor 117 (transistor 117s, transistor 117m). By adjusting the value of the resistor R, the slope angles of the rising and falling voltage waveforms of the gate signal can be adjusted.

[0109] When the value of the drive element circuit 127a is large, the slope of the rising / falling waveform of the gate signal of the transistor 117 applied to the gate terminal of the transistor 117 becomes gentler.

[0110] On the other hand, if the resistance value of the drive element circuit 127a is small, the slope of the rising / falling waveform of the gate signal becomes steep. By changing the resistance value of the drive element circuit 127a or setting it to a predetermined value, the on time of the transistor 117 (transistor 117m, transistor 117s) can be adjusted.

[0111] Furthermore, by selecting the driver element circuits 127b to 127d that have diodes, it is possible to set, change or control the slope of the rising / falling waveform of the gate signal.

[0112] The gate driver circuit 113 can set the slope of the rising waveform (rise time Tr) and the slope of the falling waveform (fall time Td) of the gate voltage applied to the gate terminal g of the transistor 117. By separately adjusting the rise time Tr and the fall time Td, it is possible to arbitrarily adjust the on time of the transistor 117 (transistor 117m, transistor 117s).

[0113] The selection of the drive element circuit 127, such as the resistance value of the drive element circuit 127a, is set by the controller circuit board 111 (controller 111). The setting is not limited to a fixed value. The slope of the rising waveform (rise time Tr) and the slope of the falling waveform (fall time Td) of the gate driver circuit 113 may be changed. The resistance value at the rising edge and the resistance value at the falling edge of the gate signal may also be changed. Furthermore, the resistance value may be variably controlled in real time. By variably controlling the drive element circuit 127a, the on time of the transistor 117 (transistor 117m, transistor 117s) is stabilized.

[0114] If the resistance value at the rising edge of the gate signal is reduced, the waveform of the on-voltage applied to the gate terminal g of the transistor 117 (transistor 117m, transistor 117s) becomes steeper, and the transistor 117 (transistor 117m, transistor 117s) turns on quickly. If the resistance value at the rising edge of the gate signal is increased, the waveform of the on-voltage applied to the gate terminal of the transistor 117 becomes gentler, and the transistor 117 turns on gently.

[0115] When the resistance value at the falling edge of the gate signal is reduced, the waveform of the on-voltage applied to the gate terminal g of the transistor 117 (transistor 117m, transistor 117s) becomes steeper, quickly turning off the transistor 117. When the resistance value at the falling edge of the gate signal is increased, the waveform of the on-voltage applied to the gate terminal g of the transistor 117 becomes gentler, and the transistor 117 turns off gently.

[0116] As described above, the gate waveform Vsg can be set by controlling, adjusting, or setting the value of the drive element circuit 127a connected to the gate terminal of the transistor 117 (transistor 117m, transistor 117s), the selection of the drive element circuit 127, or the rise time / fall time of the gate driver circuit 113.

[0117] Therefore, the gate driver circuit 113 has the function of changing or modifying the inrush current Is and surge voltage Vs generated in the transistor 117 (transistor 117m, transistor 117s).

[0118] It goes without saying that the operation of the transistor 117 (transistor 117m, transistor 117s) can not only control the on-voltage of the gate terminal g of the transistor 117 (transistor 117m, transistor 117s), but also change or set the value of the constant current Id or voltage Vm supplied to the transistor 117 (transistor 117m, transistor 117s) by the current power supply 121. The drive element circuit 127 a on the output side of the gate driver circuit 113 is controlled by the controller circuit board 111 .

[0119] The current Id flowing through the channel of the transistor 117 varies depending on the gate waveform Vsg applied to the gate terminal g, and the temperature information Tj shown in Figure 22(c) varies depending on the current Id. In Figure 22(c), the variation in the temperature information Tj is indicated by solid lines, dotted lines, etc.

[0120] 3, 4, etc., the Vi voltage (Vis, Vim) is measured or acquired by a differential amplifier (subtractor) circuit. Therefore, an overvoltage is not applied to the transistor 117 and the diode Di, and the Vi voltage (Vis, Vim) can be acquired stably.

[0121] The differential amplifier (subtractor) circuit is not limited to an analog circuit that uses an operational amplifier circuit or the like. For example, it goes without saying that the terminal voltage of the diode Di and the terminal voltage of the drive element circuit 127a may be analog-to-digital converted and the Vi voltage (Vis, Vim) may be obtained by digital circuit processing or the like. The same applies to the voltage detection circuit 116 (voltage detection circuit 116m, voltage detection circuit 116s) and its peripheral circuitry.

[0122] A terminal of the transistor 117m is connected to a connection pin 206 of a connector 202m, and a terminal of the transistor 117s is connected to a connection pin 206 of a connector 202s. The connector 202 is configured so that it can be easily attached to and detached from the terminal of the transistor 117m.

[0123] In the sample connection circuit 203 (sample connection circuit 203s1, sample connection circuit 203s2, sample connection circuit 203m1, sample connection circuit 203m2) in FIG. 1, a gate driver circuit 113, a drive element circuit 127a, and a constant current circuit 118 are arranged or formed.

[0124] As shown in FIG. 7, the sample connection circuit 203 is located separately from the device control circuit board 209 so that it can be located close to the transistor 117 under test.

[0125] It is preferable to provide one sample connection circuit 203 for each transistor 117 to be tested, or each transistor 117m, or each transistor 117s, etc. However, this is not limitative, and one sample connection circuit 203 including multiple signal circuits may be provided for multiple transistors 117, etc.

[0126] 7, the sample connection circuit 203 is connected to the transistor 117 via a connection pin 206 of the connector 202. The gate driver circuit 113 and the gate terminals g (gate terminals gm, gs) of the transistors 117 (transistors 117m, 117s) are arranged so as to be a short distance of 30 mm or less.

[0127] If the distance between the gate driver circuit 113 and the gate terminal g of the transistor 117 is long, noise or the like is superimposed on the gate terminal g, causing the transistor 117 to malfunction and directly leading to the destruction of the transistor 117.

[0128] As shown in FIG. 2, the sample connection circuits 203s (sample connection circuits 203s1 and 203s2) are connected to a device control circuit board 209s via a connector 208s.

[0129] The sample connection circuit 203m (sample connection circuit 203m1, sample connection circuit 203m2) is connected to the device control circuit board 209m via a connector 208m.

[0130] The control circuit board 111 (controller 111) controls the device control circuit board 209 (device control circuit board 209s, device control circuit board 209m), the sample connection circuit 203s (sample connection circuit 203s1, sample connection circuit 203s2), and the short circuit 137 (short circuit 137m, short circuit 137s), and transmits and receives various data, voltages, and current values ​​as necessary.

[0131] 7, the device control circuit board 209 is placed in room B of the housing 210 of the semiconductor device testing apparatus. The housing 210 is a frame or the main body of the apparatus in which the power supply unit 132, the drive circuit, and the heating / cooling plate 134 of the semiconductor device testing apparatus are incorporated. The sample connection circuit 203 is placed in the C1 chamber of the housing 210 of the semiconductor device testing apparatus in order to be located close to the transistor 117 to be tested.

[0132] The sample connection circuits 203 (sample connection circuits 203m1, 203m2, 203s1, and 203s2) are connected to a connector 208 arranged on the side of the housing 210. Wiring connected to connection pins 206 of the connector 208 is connected to a device control circuit board 209 in Room B.

[0133] In the embodiment of the present invention, a fork plug will be described as an example of the connection plug 205. Fork plugs 205 are connected to one end of each connection wiring 211 and each power supply wiring 212, such as fork plug 205e connected to the collector terminal of transistor 117 and fork plug 205d connected to one terminal of power supply device 132, and are then connected to conductor plate 204.

[0134] Although the present specification and drawings describe the conductor plate 204, it is not limited to a plate shape and may be rod-shaped. It may be composed of multiple structures. It may have any shape as long as it can be joined to a structure such as the fork plug 205. For example, it may be a structure such as a socket or connector. Furthermore, the conductor plate 204 may be in the shape of a fork plug, and the fork plug 205 may be connected to the fork plug.

[0135] The present invention may be configured in any way as long as a fork plug 205 or the like is formed or placed on at least one terminal of the transistor 117 to be tested, and an electrical connection is made between the fork plug 205 and a connection object such as a conductor plate 204.

[0136] The fork plug 205 will be described as being inserted into a component or structure that separates spaces, such as the partition wall 214. However, this is not limiting. For example, the fork plug 205c may be connected to the conductive plate 204b, inserted through the partition wall 214, and electrically connected to one terminal (emitter terminal e) of the transistor 117.

[0137] The partitions 214, 215, and 217 of the semiconductor device testing apparatus of the present invention shown in Fig. 7 and other figures may be of any shape as long as they divide or separate spaces or regions. A wide variety of configurations or structures are applicable, such as wall-like, plate-like, mesh-like, film-like, and foil-like shapes.

[0138] The fork plug 205 may have any configuration, structure, form, style, or method that allows it to be electrically connected to an object such as the conductive plate 204 by press-fitting, pressure welding, insertion, crimping, clamping, fitting, or the like.

[0139] The test current Id to be passed through the transistor 117 is supplied by operating the power supply device 132. The power supply device 132 is controlled to operate / not operate (on / off) by a signal from the control circuit board (controller) 111. The power supply device 132 also switches between outputting and not outputting the current Id. The device control circuit board 209 is controlled by the control circuit board (controller) 111.

[0140] 1, 3, 6, etc., the transistor 117 to be tested will be described as having a diode Di (diode Dim, diode Dis) as shown in FIG. 28(a). The emitter terminal em of the transistor 117m will be described as being grounded. The gate terminal g (gate terminal gm, gate terminal gs) of the transistor 117 (transistor 117m, transistor 117s) is connected to the gate driver circuit 113 (gate driver circuit 113m, gate driver circuit 113s).

[0141] In the sample connection circuit 203 (sample connection circuit 203m, sample connection circuit 203s), a gate driver circuit 113, a drive element circuit 127a, a constant current circuit 118, and a voltage detection circuit 116 are arranged or formed.

[0142] The sample connection circuit 203 is connected to the transistor 117 via a connection pin 206 of the connector 202. The gate driver circuit 113 and the gate terminal g of the transistor 117 are arranged so that the distance between them is short, 30 mm or less. If the distance between the gate driver circuit 113 and the gate terminal g of the transistor 117 is long, noise etc. will be superimposed on the gate terminal g, causing the transistor 117 to malfunction.

[0143] 1 and 3, a test signal is applied from the gate driver circuit 113 to the gate terminal g of the transistor 117. The gate driver circuit 113 has an operational amplifier circuit.

[0144] 7, the device control circuit board 209 is placed in room B of a housing 210 of the semiconductor device tester. The housing 210 incorporates a power supply unit 132, a drive circuit system, a heating / cooling plate 134, and the like.

[0145] The sample connection circuit 203 is placed in the C1 chamber of the housing 210 of the semiconductor device testing device in order to be located close to the transistor 117 to be tested. The sample connection circuit 203 is connected to a connector 208 placed on the side of the housing 210. Wiring connected to the connection pin 206 of the connector 208 is connected to a device control circuit board 209 in the B chamber.

[0146] The sample connection circuit 203 is connected to a device control circuit board 209 by connection pins 206 of a connector 208. The sample connection circuits 203 are individually arranged corresponding to the transistors 117 to be tested, and the sample connection circuits 203 are configured so as to be easily detachable by connectors 202, etc.

[0147] A constant current circuit 118 supplies a constant current Ic to a diode Di arranged or formed between the channels of the transistor 117. A voltage detection circuit 116 buffers the terminal voltage of the diode Di (to reduce the output impedance) and outputs it as a voltage Vi. The voltage Vi is converted from analog to digital by a temperature measurement circuit 115.

[0148] The temperature measurement circuit 115 obtains temperature information Tj of the transistor 117 from the terminal voltage Vi and transfers it to the control circuit board 111. The temperature information is output from the connector 213 of the device control circuit board 209 to the mother board 207 and sent to the control circuit board 111. The gate driver circuit 113 applies a set on-voltage to the gate terminal of the transistor 117 at a set frequency (on-off cycle).

[0149] The transistor 117 is activated / deactivated (on / off) by the Vg signal voltage output from the gate driver circuit 113, and a current Id flows between the channels of the transistor 117 while the transistor 117 is on. The resistance value Vr of the drive element circuit 127a is configured so that it can be set to a constant voltage or a voltage that changes over time between 0 (Ω) and 500 (Ω).

[0150] The drive element circuit 127a can set the slope of the rising waveform (rise time Tr) and the slope of the falling waveform (fall time Td) of the gate voltage signal applied to the gate terminal g of the transistor 117 by varying or controlling the resistance value Vr.

[0151] 3 and other figures, the resistance value Vr of the drive element circuit 127a is variable, but this is not limiting. For example, the drive element circuit 127a may be an external resistor.

[0152] A constant current circuit 118 supplies a predetermined constant current Ic. The constant current Ic is applied to a diode Di. By monitoring the terminal voltage of the diode Di, the temperature change of the transistor 117 can be measured or observed.

[0153] In order to prevent the transistor 117 from generating heat due to the constant current Ic, the constant current Ic is set to a current value that is sufficiently smaller than the constant current Id that flows through the channel of the transistor 117 .

[0154] Specifically, the constant current Ic is set to 1 / 1000 or less of the current Id that is passed through the transistor 117 during testing. Preferably, the current Ic that is passed through the transistor 117 is set to 1×10 of the current Id. 6 1 or more of 1 x 10 4 The constant current Ic should be between 0.1mA and 100mA.

[0155] The channel current Id is changed, and the diode Di voltage (the voltage between the collector and emitter terminals of the transistor 117) is measured to determine the temperature coefficient K. The determined temperature coefficient K is stored in the temperature measurement circuit 115.

[0156] The temperature coefficient K is determined by heating the transistor 117 to a predetermined temperature using the heating / cooling plate 134, passing a constant current Ic through the diode Di, and measuring the terminal voltage. By varying the predetermined temperature and measuring the terminal voltage of the diode Di, the terminal voltage of the diode Di relative to the temperature of the transistor 117 can be obtained. Therefore, the temperature coefficient K of the transistor 117 can be determined from the terminal voltage of the diode Di relative to the temperature.

[0157] The constant current Ic flows through the diode Di when the channel current Id is not flowing. In other words, when the transistor 117 is not turned on, the constant current Ic flows and the voltage across the diode Di is measured. The voltage detection circuit 116 outputs the terminal voltage Vi (terminal c-terminal e) of the diode Di.

[0158] The voltage detection circuit 116 is not limited to one configured with an operational amplifier element, but may be any circuit having an output impedance lower than the input impedance.

[0159] The obtained temperature information Tj is sent to a control circuit board (controller) 111. When the temperature information Tj becomes equal to or greater than a predetermined set value, the control circuit board (controller) 111 determines that the transistor 117 is in a predetermined stress state or a deteriorated state, and changes the control of the test or stops the test.

[0160] In the embodiments such as FIG. 1(a), the switch circuit 124 uses the symbol for the switch circuit. Examples of the switch circuit 124 include a transistor, a mechanical relay, a phototransistor, a photodiode switch, a photoMOS relay, and a MOSFET. As shown in FIG. 1(b), the switch circuit 124 is preferably a MOSFET. A MOSFET is preferable because it has a small inter-channel voltage (Vsd). In the following embodiments, the switch circuit 124 will be described as a power MOSFET 124.

[0161] It is preferable to select a channel voltage (Vsda) of the power MOSFET 124a when it is on that is equal to or lower than the channel voltage (Vsdb) of the power MOSFET 124b when it is on. The channel voltage (Vsda) of the power MOSFET 124a when it is on is set to be smaller than the channel voltage (Vsdb) of the power MOSFET 124b when it is on. This is to ensure that the current Im flows stably when the switch circuit 124a is turned on and the terminals of the power supply device 132 are short-circuited.

[0162] The switch circuit 124 is mounted or formed on the switch circuit board 201. The switch circuit 124 is connected to a conductor plate 204. The conductor plate 204 is, for example, a copper plate having a thickness of 5 mm and a width of 50 mm. The length of the conductor plate 204 is, for example, 250 mm. 6, 7, and 11 show the fork plug 205 and the connection (contact) state between the fork plug 205 and the conductive plate 204. FIG.

[0163] Fig. 11(a) is a diagram showing a state in which a conductor plate 204 is attached to a switch circuit board (printed circuit board) 201 on which a switch circuit and the like are formed, and a fork plug 205 is connected to the conductor plate 204, as viewed from above. Fig. 11(b) is an explanatory diagram showing a state in which the fork plug 205 is clamped at one end of the conductor plate 204.

[0164] 6, 7, 8, etc., two conductive plates 204 are attached to the switch circuit board 201. The conductive plates 204 and the switch circuit board 201 are tightly attached and fixed together with screws or the like.

[0165] Electrical connection is achieved by mechanically fitting fork plug 205 and conductive plate 204. When the U-shaped portion of fork plug 205 is inserted into conductive plate 204, fork plug 205 and conductive plate 204 are joined well. 11, a connection bolt 219 is attached to the fork plug 205. A connection wire 211 is connected to the connection bolt 219.

[0166] A cross section taken along line AA' in Figure 11(a) is shown in Figure 11(b). The conductive plate 204 and the fork plug 205 come into contact with each other at contact parts 220a and 220b formed on the fork plug 205. The contact parts 220 are made of phosphor bronze and nickel alloy, and have spring properties. The surface of the contact parts 220 is gold-plated or silver-plated. The plating improves the electrical stability of the contact parts 220.

[0167] As shown in FIGS. 7 and 8, the fork plug 205 and the conductor plate 204 are electrically connected by inserting the fork plug 205 through an opening 216 in the partition wall 214 .

[0168] 7 shows the arrangement of each component of the semiconductor device testing apparatus of the present invention. The housing 210 of the semiconductor device testing apparatus has multiple sections. The lower part of the housing is separated into chambers A and B. The power supply unit 132 is placed in chamber A. Chambers A and B are separated by a partition wall 215. Chambers C1 and C2 are separated by a partition wall 217.

[0169] The power supply device 132, switch circuit board 201, and transistor 117 generate large noises due to repeated operation / non-operation. The noise can cause malfunctions of the circuit boards, etc. Malfunctions can be prevented by providing electrostatic and electromagnetic shields to the partition walls of each chamber.

[0170] Electrostatic shielding and electromagnetic shielding are realized by attaching or forming conductive plates, metal plates, metal films, or wire mesh around the periphery of each chamber or on the surface or inside of the partition wall.

[0171] In the C1 chamber, the heating / cooling plate 134, the circulating water pipe 135, etc. shown in FIG. 2 are arranged, and the transistor 117 to be tested is arranged in close contact with the heating / cooling plate 134.

[0172] Water leak sensors (not shown) are installed around the heating and cooling plate in chamber C1. If the circulating water (cooling medium) leaks, the water leak sensors will activate and stop the semiconductor device testing equipment or issue an alarm.

[0173] A drainage groove (not shown) is formed around the periphery of the heating / cooling plate 134. When circulating water (cooling medium) leaks from the heating / cooling plate, the circulating water (cooling medium) flows into the drainage groove and is discharged outside the semiconductor device testing apparatus. The heating / cooling plate 134 is mounted on a tray (not shown), and the tray is configured to be detachable from the partition wall 214 . As described above, the partition wall 214 is configured so that even if the circulating water pipe 135 or the like is damaged, the circulating water (cooling medium) or the like will not leak into the lower chambers A and B.

[0174] A partition wall 215 is formed between chamber A, in which the power supply unit 132 is disposed, and chamber B, in which the drive circuit system is disposed. An electrostatic shield plate or an electromagnetic shield plate is disposed on the partition wall 215, which blocks noise from the power supply unit 132 and prevents the noise from being applied to the drive circuit system in chamber B.

[0175] In this embodiment of the present invention, a fork plug 205 is inserted from chamber C2 and connected to the conductive plate 204 in chamber B. An opening 216 into which the fork plug 205 is inserted is formed in the partition wall 214.

[0176] In this embodiment of the present invention, the fork plug 205 is inserted from the top to the bottom. However, the present invention is not limited to this. For example, the conductor plate 204 may be placed in the C2 chamber, and the fork plug 205 may be inserted from the B chamber to electrically connect the fork plug 205 and the conductor plate 204.

[0177] 11(c), a connector 213 is attached to a motherboard 207. A control circuit board 111, a device control circuit board 209, and a switch circuit board 201 are attached to the connector 213 of the motherboard 207. The number of switch circuit boards 201 is prepared according to the number of transistors 117 to be tested. The number of switch circuit boards 201 can be easily changed by changing the number of switch circuit boards 201 attached to the motherboard 207.

[0178] Temperature information Tj, voltage Vi, a control signal for the drive element circuit 127a, a control signal for the constant current circuit 118, etc. are transmitted to the motherboard 207. In addition, power supply wiring and ground wiring for each circuit are formed and supplied to each circuit board via a connector 213.

[0179] 11(c), the conductive plate 204 is disposed so as to protrude from the switch circuit board 201. A fork plug 205 is connected to this protruding portion.

[0180] The fork plug 205a is connected to the conductor plate 204a of the switch circuit board 201a. The power supply wiring 212 is connected to the switch circuit board 201a through an opening 216 in the partition wall 215.

[0181] 7 and 8, fork plug 205d is connected to conductor plate 204c of switch circuit board 201b. Power supply wiring 212 is connected to switch circuit board 201b through opening 216 in partition wall 215. Fork plug 205b is connected to conductor plate 204b of switch circuit board 201a. Power supply wiring 212 is connected to switch circuit board 201a through opening 216 in partition wall 215.

[0182] 6, a switch circuit 124b is disposed between the conductor plates 204d and 204c of the switch circuit board 201b, and electrically shorts the conductor plates 204d and 204c. By shorting the conductor plates 204d and 204c, the current Id output by the power supply device 132 is supplied to the transistor 117 as the test current Id.

[0183] 6, switch circuit 124a is disposed between conductor plate 204i and conductor plate 204j of switch circuit board 201a. When switch circuit 124a is turned on, conductor plate 204i and conductor plate 204j are short-circuited. When this short-circuit occurs, current Id output by power supply device 132 flows to ground as discharge current Im. Alternatively, the charge stored in power supply device 132 is discharged. Therefore, transient voltages and the like are not applied across the channels of transistor 117, and transient currents and the like do not flow through transistor 117, preventing breakdown of electrical elements such as transistor 117.

[0184] A fork plug 205c is connected to the conductive plate 204b. A fork plug 205f is connected to the conductive plate 204a. A fork plug 205e is connected to the conductive plate 204d. A fork plug 205d is connected to the conductive plate 204c.

[0185] The fork plug 205 is made of a metal such as aluminum. The fork plug 205 has a nickel-plated base and a silver-plated surface. The fork plug 205 is formed with a thread so that the connection wiring 211 can be attached to the fork plug 205 with a connection bolt 219 .

[0186] 8 shows two switch circuit boards 201a and 201b. The switch circuit board 201 is connected to a connector 213 on the mother board 207.

[0187] 7 and 8, for example, fork plug 205c is inserted through opening 216 in partition wall 214 provided between chamber C2 and chamber B and connected to conductive plate 204b. Fork plug 205e is inserted through opening 216 in partition wall 214 provided between chamber C2 and chamber B and connected to conductive plate 204d.

[0188] The current flowing through the transistor 117 to be tested is large, at several hundred amperes, so the thickness of the connection wiring 211 used is also large. Therefore, the large connection wiring 211 and power supply wiring 212 are hard. Therefore, it is not easy to change the connection of the connection wiring 211 and power supply wiring 212.

[0189] In the semiconductor device testing apparatus of the present invention, a fork plug 205 is inserted from the C2 chamber into any opening 216 in the partition wall 214. By changing the position of the opening 216 into which the fork plug 205 is inserted, connection to any switch circuit board 201 is possible. Therefore, changing the connection with the switch circuit board 201 to be used depending on the test conditions of the transistor 117 does not require changing the wiring of the connection wiring 211, but only requires changing the position of the opening 216 into which the fork plug 205 is inserted. Also, as shown in FIG. 11(c), the switch circuit board 201 only requires changing the position of the connector 213 that connects to the motherboard 207.

[0190] As described above, the switch circuit board 201 and the device control circuit board 209 connected to the motherboard 207 are arranged according to the test content of the electric elements 117 such as semiconductor elements and the number of electric elements 117 to be tested. In addition, the connection switching with the switch circuit board 201 etc. is performed by changing the position of the fork plug 205 inserted into the opening 216 of the partition wall 214.

[0191] 1, 6, 7, and 8, the connection wiring 211a connected to the transistor 117 is connected to the fork plug 205e. The connection wiring 211b connected to the transistor 117 is connected to the fork plug 205h. The connection wiring 211c connected to the transistor 117 is connected to the fork plug 205c.

[0192] By attaching and detaching the fork plugs 205e, 205f, and 205c to and from the conductive plate 204, the semiconductor device 117 to be tested can be attached and detached from the test circuit.

[0193] 6 and other figures, the number of switch circuit boards 201b that short-circuit the outputs of the current power supplies 121 may correspond to the number of the current power supplies 121. For example, if the semiconductor device testing equipment has one current power supply 121, one switch circuit board 201b (switch circuit 124b) may be sufficient.

[0194] The number of switch circuit boards 201 required is equal to or greater than the number of transistors 117 to be tested. For example, if there are 12 transistors 117 to be tested, it is preferable to prepare 12 or more switch circuit boards 201. Specifically, the number of switch circuit boards prepared corresponds to the number of electric elements 117 to be tested.

[0195] It is cost-effective to use the same board specifications for the switch circuit board 201 corresponding to the semiconductor element 117 to be tested and the switch circuit board 201 that shorts the output of the power supply device 132. In other words, the switch circuit boards 201 have a common configuration.

[0196] 7, it is preferable that a plurality of transistors or the like be mounted as switch circuits 124 on switch circuit board 201. The greater the number of switch circuits 124, the smaller the impedance that short-circuits two conductive plates 204 can be.

[0197] 12(a) and 12(b) illustrate the state in which the fork plug 205 is inserted into the opening 216 of the partition wall 214. Fig. 12(a) is a view from the front side of the partition wall 214, and Fig. 12(b) is a view from the back side of the partition wall 214.

[0198] 12, fork plug 205b and multiple fork plugs 205c (fork plugs 205c1 to 205c5) are connected to conductive plate 204b, for example. Fork plug 205e1 is connected to conductive plate 204d1, fork plug 205e2 is connected to conductive plate 204d2, fork plug 205e3 is connected to conductive plate 204d3, fork plug 205e4 is connected to conductive plate 204d4, and fork plug 205e5 is connected to conductive plate 204d5.

[0199] A large amount of noise is generated by turning on and off the switch circuit 124 of the switch circuit board 201. As a countermeasure against this, although not shown in Fig. 11(c), a metal plate that functions as a shield is placed between the two switch circuit boards 201 and is earthed.

[0200] The heat generated by the switch circuit 124 is dissipated to the conductor plate 204. A heat sink (not shown) is attached to the switch circuit 124. The ground terminal of the switch circuit 124 is connected to the ground of the switch circuit board 201. The heat of the conductor plate 204 is also dissipated via the ground copper foil of the switch circuit board 201.

[0201] 6, conductive plates 204i and 204j are attached to switch circuit board 201a. Conductive plate 204j is connected to fork plug 205j. Conductive plate 204i is connected to fork plug 205i. Fork plug 205i is connected to an output terminal of power supply device 132. Conductive plate 204j is connected to fork plug 205j. Fork plug 205j is connected to a ground terminal of power supply device 132.

[0202] When the switch circuit 124a is turned on (closed), the output terminals of the power supply device 132 are short-circuited, and a short-circuit current Im flows to ground. Therefore, the output current of the power supply device 132 is not supplied to the transistor 117. When the switch circuit 124a is open, the output current Id of the power supply device 132 is supplied to the transistor 117.

[0203] Conductive plates 204c and 204d are attached to switch circuit board 201b. Conductive plate 204c is connected to fork plug 205d. Fork plug 205d is connected to the output terminal of power supply device 132. Conductive plate 204d is connected to fork plug 205e. Fork plug 205e is connected to the collector terminal of transistor 117 to be tested.

[0204] Conductive plates 204e and 204f are attached to switch circuit board 201c. Fork plugs 205h and 205g are connected to conductive plate 204f. Fork plug 205a is connected to conductive plate 204e. Fork plug 205a is connected to the output terminal of power supply device 132. Fork plug 205h is connected to the O terminal of transistor 117 to be tested.

[0205] Conductive plates 204b and 204a are attached to switch circuit board 201d. Fork plug 205b is connected to conductor plate 204b. Fork plug 205f is connected to conductor plate 204a. Fork plug 205f is connected to fork plug 205g. Fork plug 205b is connected to fork plug 205j, which is connected to conductor plate 204a of switch circuit board 201a, and fork plug 205j is connected to power supply device 132.

[0206] 8 shows one transistor 117 for ease of illustration. A connection structure 218a is inserted into the opening 216a of the partition wall 217, a connection structure 218b is inserted into the opening 216b of the partition wall 217, and a connection structure 218c is inserted into the opening 216c of the partition wall 217.

[0207] The semiconductor device testing apparatus of the present invention tests a plurality of semiconductor devices 117 arranged on a heating / cooling plate 134. Therefore, a plurality of openings 216 are formed in a partition wall 217, as shown in FIG.

[0208] 10, n (n is a positive number equal to or greater than 1) openings 216 are formed. n is the maximum number of semiconductor elements 117 that can be tested simultaneously, or the maximum number of semiconductor elements 117 that can be placed or mounted on the heating / cooling plate 134.

[0209] Connection structure 218a1 is inserted into opening 216a1, connection structure 218b1 is inserted into opening 216b1, and connection structure 218c1 is inserted into opening 216c1.

[0210] Connection structure 218a2 is inserted into opening 216a2, connection structure 218b2 is inserted into opening 216b2, and connection structure 218c2 is inserted into opening 216c2.

[0211] Thereafter, similarly, a connection structure 218an is inserted into the opening 216an, a connection structure 218bn is inserted into the opening 216bn, and a connection structure 218cn is inserted into the opening 216cn.

[0212] Connection structure 218a is coupled to device terminal 226a of transistor 117, and connection structure 218b is coupled to device terminal 226b of transistor 117. Connection structure 218c is coupled to device terminal 226c of transistor 117.

[0213] 8, a connector 202s is connected to the collector terminal cs, gate terminal gs, and emitter terminal es of the transistor 117. A connector 202m is connected to the collector terminal cm, gate terminal gm, and emitter terminal em of the transistor 117.

[0214] The signal wiring 222 (signal wiring 222m, signal wiring 222s) connected to the connector 202 (connector 202m, connector 202s) is connected to the sample connection circuit 203. The signal wiring 235 of the sample connection circuit 203 is connected to the device control circuit board 209 via the connector 208.

[0215] The partitions (partitions 214, 215, and 217) have the function of separating each chamber (chamber C1, chamber C2, chamber A, and chamber B) and the function of preventing outside air from flowing in. In particular, since condensation may occur in chamber C1 during tests at low temperatures, dry air is allowed to flow into chamber C1.

[0216] 8, 9, 13, and 14, a fixing screw 221 is attached to the other end of connection structure 218, and connection wiring 211 is connected to connection structure 218. A fork plug 205 serving as a connection member is attached to the other end of connection wiring 211. Fixing screw 221 is not limited to a screw, and may be any type that can electrically connect connection wiring 211 to connection structure 218.

[0217] The sample connection circuit 203 is connected to a device control circuit board 209 by connection pins 206 of a connector 208. The sample connection circuits 203 are individually arranged corresponding to the respective transistors 117 to be tested, and the sample connection circuits 203 are configured to be easily removable.

[0218] Fig. 13 is an explanatory diagram of a connection structure 218 which is one embodiment of a semiconductor device testing apparatus according to the present invention. Fig. 13(a) is a diagram showing a schematic back surface, and Fig. 13(b) is a diagram showing a schematic side surface.

[0219] The heat pipe 223 is in close contact with the recess 234 of the connection structure 218. Heat conductive grease or heat dissipating silicone oil compound may be applied between the recess 234 of the connection structure 218 and the heat pipe.

[0220] The heat pipes 223 are arranged so as to fit into the recesses 234. Arranging the heat pipes 223 in the recesses on the back surface of the connection structure 218 reduces the risk of damaging the heat pipes 223. The heat pipes 223 may also be arranged on both sides of the connection structure 218.

[0221] The connection structure 218 is heated during testing, and therefore the heat pipe 223 and the heat pipe fitting 231 are also heated, causing the heat pipe 223 and the heat pipe fitting 231 to expand due to the heating.

[0222] In the present invention, a material having a linear expansion coefficient smaller than that of the heat pipe 223 is used for the heat pipe fitting 231 of the connection structure 218. Alternatively, a material having a linear expansion coefficient larger than that of the heat pipe fitting 231 is used for the heat pipe 223 of the connection structure 218. The material of the heat pipe 223 expands more in the recess 234, so that the heat pipe 223 is more firmly fitted into the recess 234. Therefore, the heat pipe 223 will not come off.

[0223] Examples of materials for the heat pipe fitting 231 include copper (linear expansion coefficient 16.8), brass (linear expansion coefficient 19), iron (linear expansion coefficient 12.1), and stainless steel (SUS304) (linear expansion coefficient 17.3). Examples of materials for the heat pipe 223 include materials with a linear expansion coefficient greater than that of the heat pipe fitting 231, such as aluminum (linear expansion coefficient 23), tin (linear expansion coefficient 26.9), and lead (linear expansion coefficient 29.1). Among these, it is preferable to use copper (linear expansion coefficient 16.8) for the material of the heat pipe fitting 231 and aluminum (linear expansion coefficient 23) for the material of the heat pipe 223. The heat pipe fitting 231 can also be made of materials other than metal, such as carbon.

[0224] The connection structure 218 mainly comprises a heat pipe fitting 231, a connection pressure part 232, and a connection holding part 233. Between the connection pressure part 232 and the connection holding part 233, an element terminal 226 of the semiconductor element is inserted. 9 is an explanatory diagram illustrating the connection state between the transistor 117 and the connection structure 218. The heat pipe 223 is disposed on the back surface of the connection structure 218.

[0225] The transistor 117 is fixed in close contact with the heating / cooling plate 134. The fixing is performed by pressing with a spring (not shown). If necessary, a heating / cooling plate is also placed above the transistor 117 so that the transistor 117 can be set to a predetermined temperature condition.

[0226] The transistors 117 to be tested must be fixed in close contact with the heating and cooling plate 134, and are therefore difficult to remove. The transistor 117 installation process begins by fixing the multiple transistors 117 to be tested to the heating and cooling plate 134. Next, the transistor 117 to be tested is selected, and a connecting structure 218 is inserted through the opening 216 in the partition wall 217 and attached to the element terminals 226 of the semiconductor element 117.

[0227] That is, the selected transistor 117 is electrically connected to the element terminal 226 of the semiconductor element 117 by inserting the connection structure 218 from the C2 chamber side into the opening 216 where the selected transistor 117 is located.

[0228] Electrical connection with semiconductor element 117 is easy since it is only necessary to select the position for inserting connection structure 218. Furthermore, by changing the signal applied to connection wiring 211 connected to connection structure 218, the test conditions and test contents of semiconductor element 117 can be easily changed.

[0229] A connection wiring 211 is connected to one end of the connection structure 218, and a constant current Id is applied to the semiconductor element 117 from the connection wiring 211. A heat pipe 223 is disposed on the rear surface side of the connection structure 218.

[0230] A current of several hundred amperes (A) flows through element terminal 226. Even if there is a slight resistance in contact portion 225, a current of several hundred amperes (A) generates a large amount of heat, overheating element terminal 226. If element terminal 226 overheats, semiconductor element 117 will also overheat, causing deterioration or destruction of semiconductor element 117.

[0231] In the present invention, heat generated at element terminal 226 is transferred to connection wiring 211 of connection structure 218 by heat pipe 223. Therefore, contact point 225 does not overheat. Cooling fan 227 is disposed below connection structure 218 to dissipate heat from heat pipe 223.

[0232] As shown in Fig. 14(a), heat dissipation fins 228 may be formed or arranged so as to be in close contact with the heat pipe 223. As shown in Fig. 14(b), a circulating water pipe 135 may be formed or arranged within the connection structure 218 to cool the connection structure 218.

[0233] Figure 9 is an explanatory diagram showing the connection state between a semiconductor module 117 having three element terminals 226 (element terminal 226a (P), element terminal 226b (O), element terminal 226c (N)) such as those shown in Figure 28, and a connection structure 218.

[0234] 9, a heat pipe 223a is formed or disposed in connection structure 218a, a heat pipe 223b is formed or disposed in connection structure 218b, and a heat pipe 223c is formed or disposed in connection structure 218c.

[0235] Note that if no current flows through the element terminal 226b (O terminal) or if the current is small, there is no need to form a heat pipe 223b in the connection structure 218b. For example, in the embodiment of FIG. 1, if the short circuit 137s or the short circuit 137m is operated, one of the transistors 117 (transistor 117s, transistor 117m) is diode-connected, and the other transistor 117 (transistor 117m, transistor 117s) is turned on (operated), no current flows through the O terminal. In this case, the connection structure 218b can be made thinner than the other connection structures 218 (connection structure 218a, connection structure 218c), thereby facilitating the connection between the connection structure 218 and the element terminal 226 of the transistor 117. Furthermore, since the space for arranging the transistor 117 can be narrow, a larger number of transistors 117 can be mounted on the heating / cooling plate 134.

[0236] 15(a), a connection structure 218 in another embodiment of the present invention mainly comprises a heat pipe fitting 231, a connection receiving portion 225, a connection pressure portion 232, and a connection holding portion 233. An element terminal 226 of a semiconductor element is inserted between the connection receiving portion 225 and the connection holding portion 233.

[0237] A spring 236 is inserted or placed in a spring hole 239 of the connection receiving portion 225 and the connection pressure portion 232. A positioning screw 237 is inserted or placed in a positioning screw hole 240 in the center of the connection receiving portion 225, and the connection receiving portion 225 and the connection pressure portion 232 are positioned relative to each other.

[0238] The spring 236 is a pressing means, a sliding means, or a positioning means. One example of the spring 236 is a coil spring. Other examples include a leaf spring, a spiral spring, and a disc spring. The spring 236 is formed or configured from a metal material. It may also be formed from heat-resistant rubber, plastic, or ceramic material.

[0239] A coil spring 236 is disposed between the connection receiving portion 225 and the connection pressure portion 232. The connection pressure portion 232 is connected by one or more fixing screws 224b. By tightening or attaching the fixing screws 224b, pressure (pressure) is applied between the connection receiving portion 225 and the connection holding portion 233.

[0240] The element terminal 226 is sandwiched between the connection receiving portion 225 and the connection holding portion 233, and the pressure of the spring 236 causes the element terminal 226 to be sandwiched between the connection receiving portion 225 and the connection holding portion 233 with a predetermined pressure (predetermined pressing force).

[0241] The pressure (pressure) can be easily adjusted by changing the spring 236. The pressure (pressure) can also be adjusted or set by the degree of tightening of the fixing screw 224b. The heat pipe metal fitting 231 and the connection holder 233 are fixed with one or more fixing screws 224a.

[0242] The connection receiving portion 225 is disposed between the connection pressure portion 232 and the connection holding portion 233. The constituent material or at least the surface material of the connection receiving portion 225 is platinum, gold, silver, tungsten, copper, nickel, molybdenum, or an alloy of a combination thereof.

[0243] Similarly, the surface of the connection holder 233 that comes into contact with the element terminal 226 is made of platinum, gold, silver, tungsten, copper, nickel, molybdenum, or an alloy of any of these.

[0244] The connection holder 233 is fixed to the heat pipe metal fitting 231 with a fixing screw 224a. The connection pressure part 232 is fixed to the connection holder 233 with a fixing screw 224b. The connection wiring 211 is fixed to the left end of the heat pipe metal fitting 231 with a fixing screw 221. 15(a) and 15(d) are explanatory diagrams for explaining the combined state of the connection holding portion 233, the connection receiving portion 225, and the connection pressure portion 232. FIG.

[0245] Connection holding portion 233 connects and fixes heat pipe 223 and heat pipe fitting 231 with screws 224a (not shown) inserted into screw holes 238a1 and 238a2. Heat pipe 223 and heat pipe fitting 231 are connected and fixed in close contact to ensure good thermal and electrical conductivity. Connection holding portion 233 is also connected and fixed to connection pressure portion 232 with screws 224b (not shown) inserted into screw holes 238b1 and 238b2.

[0246] The connection receiving portion 225 has protrusions 251 formed on both ends, and the connection pressure portion 232 has grooves 252 formed on both ends. The protrusions 251 of the connection receiving portion 225 are fitted into the grooves 252 of the connection pressure portion 232. The protrusions 251 of the connection receiving portion 225 and the grooves 252 of the connection pressure portion 232 are configured to be in electrical contact with each other.

[0247] In order to improve the contact between the element terminals 226 and the connection receiving portions 225, it is preferable to form triangular or other irregularities on the surface of the connection receiving portions 225 as shown in FIG. 15(c). In the configuration of FIG. 15, the element terminal 226 is sandwiched between the flat surface of the connection pressure portion 232 and the flat surface of the connection holding portion 233 .

[0248] 16 shows a configuration in which the element terminal 226 is sandwiched between a pressing tool mounting plate 313 and a connection holder 233. Pressing tools 311a and 311b are attached to the pressing tool mounting plate 313. The pressing tool 311 is exemplified by a metal leaf spring. The pressing tool 311 may also be made of a non-conductive material such as a silicone resin material. The pressing tool 311 is fitted into the pressing tool mounting plate 313.

[0249] The element terminal 226 is clamped between the flat surfaces of the pressing tool 311 and the connection holder 233. When the pressing tool 311 presses, the element terminal 226 and the connection holder 233 are electrically connected.

[0250] 15(a), the spring (pressure fitting) 236 was inserted into the spring hole 239 of the contact part 225. If the spring (pressure fitting) 236, the contact part 225, and the connection pressure part 232 are made of conductive materials, electricity may flow from the element terminal 226 → contact part 225 → spring (pressure fitting) 236 → connection pressure part 232. In this case, if the resistance value of the spring (pressure fitting) 236 is high, current will flow through the spring (pressure fitting) 236, causing the spring to generate heat and burn out.

[0251] In the embodiment of the present invention shown in Figure 16, spring hole 239 is formed in insulating plate 312. Pressing tool 311 contacts element terminal 226, and spring 236 presses pressing tool mounting plate 313. Insulating plate 312 is arranged above pressing tool mounting plate 313, providing insulation between pressing tool mounting plate 313 and spring 236. Spring hole 239 is formed in insulating plate 312, and spring 236 is inserted into spring hole 239. The other configuration is the same as in Figure 13, so description will be omitted. Insulating plate 312 may be an insulating film, an insulating film, or an insulating gas such as air.

[0252] Fig. 16(b) is a side view of the pressing tool attachment plate 313. Pressing tools 311a and 311b are arranged and inserted into the pressing tool attachment plate 313. Fig. 16(c) is a view seen from the direction A in Fig. 16(b).

[0253] Since the insulating plate 312 is made of an insulating material, even if the pressing tool mounting plate 313 is made of a conductive material such as metal, no current flows through the spring (pressure fitting) 236. Therefore, no current path is generated from the element terminal 226 to the contact portion 225 to the spring (pressure fitting) 236 to the connecting pressure portion 232.

[0254] The embodiment of Fig. 16(a) has a configuration in which insulation is achieved by an insulating plate 312. The insulating effect of the present invention is not limited to the configuration in which an insulating plate 312 is used, as in Fig. 16(a). For example, a configuration shown in Fig. 16(d) is exemplified.

[0255] 16(d) shows a configuration in which an insulating part 315 made of a resin material or the like is arranged around the screw hole 238b of the connection pressure part 232. Because the area around the screw hole 238b is insulated by the insulating part 315, no current flows through the fixing screw 224b. Therefore, no current path is generated from the element terminal 226 to the contact part 225 to the spring (pressure fitting) 236 to the connection pressure part 232, and the spring (pressure fitting) 236 will not be burned. As described above, the present invention is configured such that insulating plate 312 is disposed on the side of spring 236 that applies pressure, so that current does not flow to pressing tool mounting plate 313 and contact portion 225 side.

[0256] When a current flows, it flows through pressing parts such as spring 236 and fixing screw 224b, burning out spring 236 and fixing screw 224b. A test current is supplied to element terminal 226 via connection holding portion 233, which has fewer high resistance parts such as spring 236.

[0257] 17 and 18 are explanatory diagrams of a semiconductor device testing method according to a first embodiment of the present invention. Also, Fig. 23 is a timing chart illustrating the semiconductor device testing method of the present invention. The semiconductor device 117 to be tested is shown in Figs. 28(a) and 28(b) by way of example, but is not limited to these. Further, as the semiconductor element 117, as shown in FIG. 29, three or more transistors are configured as one package.

[0258] Figure 29 shows an inverter that rotates a three-phase motor 229. Three-phase AC is generated by six transistors in a semiconductor device 117. Inverters are used to rotate three-phase motors such as those used in trains.

[0259] The waveforms applied to the UVW phases of the motor 229 are shown in Fig. 30. The UVW phases are analog waveforms, but as shown in Fig. 31, these analog waveforms are made pseudo-analog by repeatedly turning on and off the transistor 117 in the semiconductor element 117 at high speed, changing the ratio of the on time to the off time.

[0260] A control method that obtains a pseudo-analog signal by varying the ratio of ON time to OFF time while keeping the ON / OFF cycle constant is called PWM (Pulse Width Modulation), and the ratio of ON time to OFF time is called the duty ratio.

[0261] FETs and IGBTs are used for the switches, and because they are driven with a clear ON or OFF state, there is almost no power consumption by the elements. By using PWM sine waves that are 120 degrees apart for each, three-phase AC can be obtained. A three-phase inverter requires six transistors as switches. Fig. 31(a) is the U-phase drive pulse, Fig. 31(b) is the V-phase drive pulse, and Fig. 31(c) is the W-phase drive pulse. Each pulse is shifted in phase by 120°.

[0262] The test can be performed by using semiconductor elements 117a, 117b, and 117c as semiconductor elements 117 that make up the inverter circuit shown in Fig. 29. Furthermore, since the test is performed as an inverter, semiconductor elements 117a, 117b, and 117c are driven to produce the PWM waveform shown in Fig. 31. Therefore, semiconductor elements 117a, 117b, and 117c are driven in the same way. However, in actual use, the phases differ by 120°.

[0263] In the following embodiment, the semiconductor element 117 will be described as a transistor 117. In Figures 17, 18, 20 and 21, the transistor 117 corresponds to the transistor 117a, the transistor 117b and the transistor 117c in Figure 29.

[0264] As shown in Figure 23, a gate drive signal Vsg is applied to the gate terminal g of transistor 117 for an on-time ton. The period of the on-time is tc. In the semiconductor device testing device of the present invention, the ton and tc times can be set arbitrarily. Increasing the ton time in the tc time increases the period during which current Id flows through transistor 117, and the change in Tj becomes faster.

[0265] 23 and 1, Ssa corresponds to switch circuit 124a. Ssb corresponds to switch circuit 124b. Ssc corresponds to switch circuit 124c. Ssd corresponds to switch circuit 124d. Current Id is the current flowing through the channel of transistor 117s or transistor 117m, and St in FIG. 23 represents a timing signal tg that applies a constant current to diodes Di and Ds shown in FIGS. 3 and 4 and measures the voltage across the diodes.

[0266] Before the start of the time t on , the switch circuit 124 a (switch circuit Ssa) is turned on (on period ta). Also, before the end of the time t on , the switch circuit Ssa is turned on (on time tb). By turning on the switch circuit Ssa, the output terminals of the power supply device 132 are short-circuited, and the charge is discharged between the channels of the transistor 117.

[0267] Before the on-period ta and after the on-time tb, the St signal goes to on level (tg), a constant current is applied to the diode of the transistor 117, the terminal voltage of the diode is measured, and temperature information Tj is obtained. When the switch circuit Ssa is turned on, the charge between the terminals of the power supply device 132 is discharged, and the charge between the channels of the transistors 117 is also discharged.

[0268] 23, after a period tb of the switch circuit Ssa, the signal St is turned on for a period tg. A constant current is applied to the diode during the period tg. Temperature information Tj is obtained during the period tg.

[0269] It is preferable to acquire the temperature information Tj before the period ta of the switch circuit Ssa and after the period tb of the switch circuit Ssa. The temperature information Tja acquired before the period ta of the switch circuit Ssa is the temperature information Tj before current is applied to the transistor 117. The temperature information Tjb acquired after the period tb of the switch circuit Ssa is the temperature information Tj acquired immediately after current is applied to the transistor 117.

[0270] The temperature information Tj is temperature information Tjb obtained immediately after current is applied to the transistor 117, but by comparing it with temperature information Tja before current is applied to the transistor 117, it can be determined or evaluated whether the temperature information Tj has been properly acquired. If the temperature information Tja and the temperature information Tjb are similar, the temperature information Tjb may not have been properly acquired. By acquiring both the temperature information Tja and the temperature information Tjb, the accuracy of the temperature information Tj is improved.

[0271] The timing of the St signal in Fig. 23 is implemented in the configurations of the transistor 117 in Fig. 28(a) and Fig. 28(b). In the configuration of the transistor 117 in Fig. 28(c), the diode Ds is independent of the transistor terminal, so there are no restrictions on the timing of applying a constant current to the diode Ds.

[0272] Fig. 27 is a timing chart illustrating the timing for acquiring temperature information Tj. In Fig. 27, signal St1 indicates the timing for acquiring temperature information Tj when testing transistor 117 in Figs. 28(a) and 28(b). Diode Di (diode Dis, diode Dim) for acquiring temperature information Tj is connected to two terminals (collector terminal, emitter terminal) of transistor 117. Because diode Di is connected to the two terminals of transistor 117, it is necessary to apply a constant current to diode Di during a period when current Id is not flowing between the channels of transistor 117 and acquire temperature information Tj.

[0273] Therefore, as in the timing of St1 in FIG. 27, the St1 signal is turned on at timings tg1 and tg2 before and after the current Id starts to flow during a period when the channel current Id is not flowing, and temperature information Tj is acquired.

[0274] 27, the St2 signal indicates the timing for acquiring temperature information Tj when testing the transistor 117 in FIG. 28(c). Diodes D (diodes Ds and Dm) that acquire temperature information Tj independent of the two terminals (gate terminal, collector terminal, and emitter terminal) of the transistor 117 are connected. Because the diodes D are independent (separate terminals) from the three terminals of the transistor 117, a constant current Ic (constant current Ics and constant current Icm) can be applied to the diodes D regardless of the period during which the current Id flows through the transistor 117. Even during the period when the current Id flows between the channels of the transistor 117, the constant current Ic can be applied to the diode D, and the temperature information Tj can be acquired.

[0275] Therefore, as in the timing of St2 in FIG. 27, the St2 signal is turned on during the period tg2 in which the channel current Id flows, and the temperature information Tj can be acquired.

[0276] Fig. 26 is a timing chart for explaining the testing method of the semiconductor device of the present invention shown in Fig. 1 etc. Vgs is the gate drive signal Vsg applied to the gate terminal g of the transistor 117 to be tested.

[0277] The switch circuit Ssa is turned on before the Vsg signal applied to the gate terminal g rises. By turning it on, the output terminals of the power supply device 132 are short-circuited. The switch circuit Ssa also remains on after the Vsg signal falls. In other words, the switch circuit Ssa is turned on before and after the on voltage is applied to the gate terminal g, shorting the channel of the transistor 117 and discharging the charge.

[0278] Furthermore, while the switch circuit Ssa is on, the switch circuit Ssb is turned on to apply a current (voltage) output by the power supply device 132 to one terminal of the transistor 117. Therefore, when the switch circuit Ssa is turned off, a current Id flows between the channels of the transistor 117. The flow of the current Id changes the inter-channel voltage Vce of the transistor 117.

[0279] The flow of the current Id causes the transistor 117 to generate heat, and the temperature information Tj increases. The temperature information Tj is obtained by passing a constant current through a diode that detects the temperature. In the above embodiment, the switch circuit Ssa is turned on to discharge the electric charge. However, the present invention can also be implemented in other ways to discharge the electric charge.

[0280] 24 is an explanatory diagram of the short circuit (discharge of electric charge, etc.) between the terminals of the power supply device 132, the discharge between the channels of the transistor 117 to be tested, and the operation of the transistor 117 (transistor 117m, transistor 117s) in the test circuit configuration of FIG.

[0281] FIG. 24(a) shows an example in which the switch circuits Ssc and Ssd are used in the off state when discharging electric charge (such as when the power supply device 132 is short-circuited). The electric charge is discharged by the switch circuit Ssa. When the switch circuit Ssb is turned on (Von), a channel current flows through the transistor 117. In FIG. 24(a), a gate-on voltage Vsg is applied to the transistors 117s and 117m at the same time. Therefore, a current flows from the cs terminal of the transistor 117s to the em terminal of the transistor 117m, and the transistor 117 is tested.

[0282] 24(b) shows an example in which the switch circuit Ssa is used in the off state when discharging electric charge (such as when the power supply device 132 is short-circuited). Discharging electric charge is performed by the switch circuits Ssc and Ssd.

[0283] By turning on the switch circuits Ssc and Ssd simultaneously, a short circuit occurs between the terminals of the power supply device 132, and the electric charge can be discharged. When the switch circuit Ssb is turned on (Von), a channel current of the transistor 117 flows.

[0284] 24(b), the gate-on voltage Vsg is applied to the transistor 117s and the transistor 117m at the same time, so that a current flows from the cs terminal of the transistor 117s to the em terminal of the transistor 117m, and the transistor 117 is tested.

[0285] 25 is a timing chart illustrating a method for testing transistors 117m and 117s in the semiconductor device testing apparatus of the present invention shown in FIG. 1, etc. In FIG. 25, the switch circuit Ssa is always in an off state. Therefore, the switch circuit Ssa can be omitted. The above matters also apply to FIG. 24(b).

[0286] 25(a), switch circuits Ssc and Ssd are turned on and off at the same timing with the same signal waveform. When switch circuits Ssc and Ssd are turned on, the output terminals of power supply device 132 are short-circuited. When switch circuit Ssb is in the on state and switch circuit Ssc is in the off state, and an on voltage is applied to gate terminal g of transistor 117, current flows between the channels of transistor 117.

[0287] In FIG. 25(a), the drive signal Vsg is simultaneously applied to the gate terminals g of the transistors 117s and 117m, so that a through current Id flows through the transistors 117s and 117m, allowing the transistor 117 to be tested.

[0288] 25(b) and 25(c), the switch circuit Ssa is always in an off state (0 V), and therefore the switch circuit Ssa can be omitted from the circuit configuration of the semiconductor device testing apparatus.

[0289] 25(b), when both the switch circuit Ssc and the switch circuit Ssd are on (Von), the output of the power supply device 132 is short-circuited. When the switch circuit Ssb is on (Von), the switch circuit Ssc is off (0 V), and an on-voltage is applied to the gate terminal g of the transistor 117s, a current flows between the channels of the transistor 117s, and the transistor 117s is subjected to a continuity test.

[0290] In Figure 25(c), when both switch circuits Ssc and Ssd are on (Von), the output of the power supply device 132 is short-circuited. Switch circuit Ssa is always in the off (0V) state. Therefore, switch circuit Ssa can be omitted from the circuit configuration of the semiconductor device testing device. Also, switch circuit Ssb is always in the off (0V) state. Therefore, switch circuit Ssb can be omitted from the circuit configuration of the semiconductor device testing device.

[0291] When both switch circuits Ssb and Ssd are off (0 V), if an on voltage is applied to the gate terminal g of transistor 117b, a current flows through the channel of transistor 117m, and transistor 117m is subjected to a continuity test.

[0292] As described above, the timing signals of FIG. 25 can be used to perform a test in which transistors 117s and 117m are simultaneously turned on, a test in which transistor 117s is turned off and transistor 117m is turned on, and a test in which transistor 117s is turned on and transistor 117m is turned off.

[0293] When starting the test of a semiconductor device, it is important to check whether the semiconductor device has an electrical connection with the test circuit. If the electrical connection is not established or is insufficient, the semiconductor device being tested will be destroyed.

[0294] For example, if the gate terminal g of the transistor 117 to be tested is not connected and is in a floating state, and a voltage is applied to the emitter terminal e and collector terminal c, the transistor 117 may be destroyed. Also, if the connection to a terminal through which a high current flows, such as the emitter terminal e, is insufficient and has resistance, the high current may flow and generate heat, which may cause the transistor 117 to overheat and be destroyed. For these reasons, it is necessary to check the connections before starting the test.

[0295] 23 is an explanatory diagram of a semiconductor device testing method of the present invention that addresses the above-mentioned issues. The present invention is characterized in that at the start of testing, a small current Ia is applied from power supply device 132 and the state of this current Ia is detected to check the connection of the semiconductor device to be tested.

[0296] 1, 6, and 19, current Ia is detected by placing a current sensor 129 in the current path and measuring, detecting, or evaluating the current with a clamp meter 128. Note that current detection is not limited to the method using current sensor 129. A wide variety of methods are possible, including a configuration in which a detection resistor is inserted in power supply wiring 212 and detection or measurement is performed based on the voltage value generated across the detection resistor, a configuration in which electromagnetic waves generated by the current flowing through transistor 117 are detected or measured, a configuration in which detection or measurement is performed using an ammeter placed in power supply device 132, and a configuration in which detection is performed based on changes in the voltage at gate terminal g of transistor 117. In this embodiment, a method of detection using current sensor 129 will be described as an example.

[0297] For example, if the current Id during testing is Ib and Ib=100 (A), then Ia is 1 (A). If an on-voltage is applied to the gate terminal g of transistor 117 and it is detected that a current flows in the path along which current Ia flows, it can be determined that transistor 117 is connected. If it is detected that current Ia cannot be detected, is unstable, or is smaller than a predetermined value Ia, it can be determined that transistor 117 is not connected or that there is a possibility of a poor connection.

[0298] The detection time for the current Ia is at least one cycle tc. After it is confirmed that the transistor 117 is normal or that the electrical connection of the transistor 117 is normal, a normal cycle test is performed. If the transistor 117 is not normal, the process stops and does not proceed to the normal cycle test.

[0299] In the embodiment of the present invention, the channel current Ia flowing through the transistor 117 is detected. However, as shown in FIG. 26, the connection state of the test sample such as a transistor may also be grasped by detecting or measuring changes or the rate of change in the inter-channel voltage Vce, the temperature information Tj, etc., and it may be determined or evaluated whether to proceed to a normal cycle test.

[0300] 26, when the gate drive signal Vsg reaches the on-voltage Vg, the transistor 117 turns on. When the transistor 117 turns on, the channel current Id starts to flow. At the same time, the channel voltage Vce of the transistor 117 changes, and the temperature information Tj also starts to change.

[0301] The time when the on-voltage Vg is applied to the transistor 117 is defined as t0, and the amount of change at the time t1 has elapsed is detected or measured. At the time t1, the current Id is Ib, Vce is Vb, and Tj is Tb. When Ib, Vb, and Tb exceed predetermined values, the connection state is determined to be normal. Furthermore, when the change rates d1, d2, and d3 from t0 to t1 exceed predetermined values, the connection state is determined to be normal.

[0302] The time t0 at which measurement or determination begins is not limited to the start time of the gate drive signal Vsg. For example, the origin may be a time a predetermined period has elapsed since t0. In one embodiment of the present invention, a minute current (about 1 A) is applied and a power cycle test is performed only once. The actual current that flows at that time is monitored and a judgment is made.

[0303] In addition, the first cycle is tested with Id=1A, and this first cycle is not counted as test 0. In the first cycle, lower limit monitoring is also forcibly enabled with the default value to detect abnormalities (poor connections). From the second cycle onwards, the test is carried out under the set conditions.

[0304] Also, set the lower limit for each test, start the test, and monitor the temperature after the measured temperature (temperature information) exceeds the set lower limit. For example, monitor that the temperature fluctuation in the 10th cycle is within 1°C, and start monitoring the lower limit at that point.

[0305] 23 is an explanatory diagram of a semiconductor element testing apparatus and a semiconductor element testing method that detects the connection state of the transistor 117 and transitions to a normal cycle test in Figures 1, 3, 4, etc. Note that the period tg for acquiring the temperature information Tj is configured so that the acquisition timing can be freely set.

[0306] During the initial period tc1, the power supply device 132 outputs a current Ia. The switch circuit Ssb is turned on during the period tf, and the switch circuit Ssd is turned on. Also, an on-voltage is applied to the gate terminal gs of the transistor 117s, and an off-voltage is applied to the gate terminal g of the transistor 117m.

[0307] Therefore, if the connection state of the transistor 117s is normal, a current Ia flows through the transistor 117s. If the current Ia is detected, the process proceeds to the next tc2 period, in which the power supply device 132 outputs a test current Id and transitions to normal test mode. If the current Ia cannot be detected, i.e., if it is not a normal value, transition to normal test mode is halted. It goes without saying that the tc1 period in which the connection state of the transistor 117s is confirmed or detected may be multiple cycle periods. It also goes without saying that, as explained in FIG. 26, the magnitudes or changes of Ib, Vb, Tb, d1, d2, and d3 may be detected or measured to determine whether to transition to the tc2 cycle.

[0308] During the period tc3, the power supply device 132 outputs a current Ia. The switch circuit Ssb is turned off, the switch circuit Ssd is turned off, and the switch circuit Ssc is turned on. Furthermore, an on-voltage is applied to the gate terminal gs of the transistor 117m, and an off-voltage is applied to the gate terminal g of the transistor 117s.

[0309] Therefore, if the connection status of transistor 117m is normal, current Ia flows through transistor 117m. If current Ia is detected, the process proceeds to the next tc4 period, in which power supply device 132 outputs test current Id and transitions to normal test mode. If current Ia cannot be detected, or if it is not a normal value, transition to normal test mode is halted. It goes without saying that the tc1 period in which the connection status of transistor 117m is confirmed or detected may span multiple cycles. It also goes without saying that, as explained in FIG. 26, the magnitudes or changes of Ib, Vb, Tb, d1, d2, and d3 may be detected or measured to determine whether to transition to the tc4 cycle.

[0310] It goes without saying that the above matters can also be applied to other semiconductor device testing apparatuses and semiconductor device testing methods of the present invention, such as those shown in Figure 19. It also goes without saying that the above matters can be combined with other embodiments of the present invention.

[0311] 17, when the switch circuit 124a is turned on, the output of the power supply device 132 is short-circuited, and the current Id output by the power supply device 132 flows to the ground as a current Im. Alternatively, when the switch circuit 124b is turned on, the charge stored between the terminals of the power supply device 132 is discharged. By passing the current Im, the voltage between the terminals of the power supply device 132 becomes 0 (V), and the transistor 117 to be tested is not destroyed by driving other than for the test.

[0312] When the switch circuits 124c and 124d are simultaneously turned on, the current Im flows, the output of the power supply device 132 is short-circuited, and the electric charge of the power supply device 132 is discharged.

[0313] It is also effective to stagger the timing at which the switch circuits 124c and 124d turn on. For example, if the switch circuit 124c turns on before the switch circuit 124d, a short circuit occurs between the channels of the transistor 117s.

[0314] Next, switch circuit 124d turns on, shorting the channel of transistor 117m. Alternatively, switch circuit 124d turns on before switch circuit 124c, shorting the channel of transistor 117m. Next, switch circuit 124c turns on, shorting the channel of transistor 117s. As described above, by sequentially turning on the switch circuits 124, the occurrence of surge voltages and the like in the semiconductor element 117 can be further suppressed.

[0315] It goes without saying that the above matters can be similarly applied to other embodiments such as those shown in Figures 3, 4, 19, 20, and 21. It also goes without saying that the above matters can be combined with or applied to other embodiments or similar operations and configurations described in this specification. The fork plug 205 is inserted through the opening 216 in the partition wall 214 and is electrically connected to the switch circuit board 201 .

[0316] After the switch circuit 124a is turned off (open), the switch circuit 124b is turned on (closed). On the other hand, the switch circuit 122a of the power supply device 132 is turned on and the switch circuit 122b is turned off, thereby controlling so that a constant current Id in the forward direction is output from the current power supply 121a.

[0317] 17(a), an on-voltage is applied to the gate terminal gs of the transistor 117s, and an off-voltage is applied to the gate terminal gm of the transistor 117m. The switch circuit 124d is turned on, and the switch circuit 124c is turned off. The switch circuits 124c and 124d are controlled by the controller 111.

[0318] 17, 18, 20, and 21, the on / off control of the transistors 117s and 117m is performed so as to obtain the PWM waveforms shown in FIG. When the switch circuit 124a is turned on, the current Id output by the power supply device 132 is supplied to the transistor 117s.

[0319] As shown in FIG. 17(a), the forward current Id flows from the power supply device 132a, through the switch circuit 124b, through the transistor 117s, through the switch circuit 124d, and then through the power supply device 132a.

[0320] Next, as shown in FIG. 17(b), the switch circuit 122a of the power supply device 132 is turned off and the switch circuit 122b is turned on, thereby controlling so that a constant current Id is output in the reverse direction from the current power supply 121b.

[0321] As shown in FIG. 17(b), the reverse current Id flows from the power supply device 132b, through the switch circuit 124d, through the diode Dis, through the switch circuit 124b, and then through the power supply device 132b. Through the above operation of FIG. 17, a test of the transistor 117s (diode Dis) is carried out.

[0322] 18, a turn-off voltage is applied to the gate terminal gs of the transistor 117s, and a turn-on voltage is applied to the gate terminal gm of the transistor 117m. Also, the switch circuit 124c is turned on, and the switch circuit 124d is turned off.

[0323] As shown in FIG. 18(c), the switch circuit 122a of the power supply device 132 is turned on and the switch circuit 122b is turned off, thereby controlling the current source 121a to output a constant current Id in the forward direction.

[0324] As shown in FIG. 18(c), the forward current Id flows from the power supply device 132a to the switch circuit 124c, through the transistor 117m, and then to the power supply device 132a.

[0325] As shown in FIG. 18(d), the switch circuit 122a of the power supply device 132 is turned off and the switch circuit 122b is turned on, thereby controlling the current source 121b to output a constant current Id in the reverse direction.

[0326] As shown in FIG. 18(d), the reverse current Id flows from the power supply device 132b to the switch circuit 124c, through the diode Dim, and then to the power supply device 132b. By the above operation of FIG. 18, the test of the transistor 117m (diode Dim) is carried out.

[0327] Tests suitable for actual operation can be performed by controlling the transistors 117a, 17b, 18a, and 18b in such a way as to produce the PWM waveforms shown in Fig. 31. Tests suitable for UVW AC drive can be achieved by performing the test method for the semiconductor element of the present invention shown in Figs. 17 and 18 on the transistors 117a, 117b, and 117c shown in Fig. 29 with a phase difference of 120°.

[0328] The semiconductor device testing apparatus of the present invention can perform testing by simultaneously passing current Id through transistors 117s and 117m by operating short circuit 137 shown in Fig. 1. In this case, switch circuits 124c and 124d are turned off, or fork plug 205h is disconnected from conductor plate 204f.

[0329] By turning on the short circuit 137s of the transistor 117s, the transistor 117s is diode-connected. Therefore, by applying an on-voltage to the gate terminal gm of the transistor 117m, a test current Id flows through the transistors 117s and 117m. Therefore, by applying an on / off signal to the gate terminal gm of the transistor 117m, the transistor 117 can be tested.

[0330] Furthermore, by turning on the short circuit 137m of the transistor 117m, the transistor 117m is diode-connected. Therefore, by applying an on-voltage to the gate terminal gs of the transistor 117s, a test current Id flows through the transistors 117s and 117m. Therefore, by applying an on / off signal to the gate terminal gs of the transistor 117s, the transistor 117 can be tested.

[0331] 3, constant current Icm or constant current Ics is supplied to diode Dis or diode Dim to acquire temperature information Tj and monitor deterioration or changes in transistor 117. Testing of transistor 117 is stopped or its operation is controlled based on the rate and amount of change in temperature information Tj.

[0332] It goes without saying that the above matters can be similarly applied to other embodiments such as those shown in Figures 19, 20, and 21. It also goes without saying that the above matters can be combined with or applied to other embodiments or similar operations and configurations described in this specification.

[0333] 19 is a diagram illustrating the configuration of a semiconductor device testing apparatus according to a second embodiment of the present invention. The difference from FIG. 1 is that a current power supply 121 that outputs a constant current in a forward direction is provided in a power supply device 132, but a current power supply 121 that outputs a constant current in a reverse direction is not provided. Also, switch circuits 124g, 124h, 124e, and 124f have been added.

[0334] The switch circuit 124c, the switch circuit 124d, the switch circuit 124e, the switch circuit 124f, the switch circuit 124g, and the switch circuit 124h are controlled by the controller 111. Other configurations or operations are the same as or similar to those in FIG. 1, and therefore will not be described. 20 and 21 are explanatory diagrams for explaining a method of testing a semiconductor device in the semiconductor device testing apparatus of the present invention shown in FIG. In FIG. 20, an on-voltage is applied to the gate terminal gs of the transistor 117s, and an off-voltage is applied to the gate terminal gm of the transistor 117m.

[0335] 20(a), the switch circuits 124g, 124b, 124d, and 124h are turned on, while the switch circuits 124a, 124c, and 124e are turned off.

[0336] As shown in FIG. 20( a ), the current Id flows in the order of the power supply device 132 ➝ the switch circuit 124 g ➝ the transistor 117 s ➝ the switch circuit 124 d ➝ the switch circuit 124 h ➝ the power supply device 132 .

[0337] 20(b), the switch circuits 124b, 124d, 124e, and 124f are turned on, and the switch circuits 124c, 124g, and 124h are turned off.

[0338] As shown in FIG. 20(b), the current Id flows in the order of the power supply device 132, the switch circuit 124e, the switch circuit 124d, the diode Dis, the switch circuit 124b, the switch circuit 124g, and the power supply device 132. Next, as shown in FIG. 21, a turn-off voltage is applied to the gate terminal gs of the transistor 117s, and a turn-on voltage is applied to the gate terminal gm of the transistor 117m.

[0339] 21(c), the switch circuits 124g, 124c, and 124h are turned on, while the switch circuits 124b, 124d, 124e, and 124f are turned off.

[0340] As shown in FIG. 21( c ), the current Id flows in the order of the power supply device 132 ➝ the switch circuit 124 g ➝ the switch circuit 124 c ➝ the transistor 117 m ➝ the switch circuit 124 h ➝ the power supply device 132 .

[0341] 21(d), the switch circuits 124c, 124e, and 124 are turned on, while the switch circuits 124b, 124g, 124d, and 124h are turned off.

[0342] As shown in FIG. 21( d ), the current Id flows in the order of the power supply device 132 ➝ the switch circuit 124 e ➝ the diode Dim ➝ the switch circuit 124 c ➝ the switch circuit 124 f ➝ the power supply device 132 .

[0343] 19, 20, and 21, the power supply device 132 can achieve the forward constant current and the reverse constant current shown in FIGS. 1, 17, and 18 with a single current power supply 121. Therefore, the cost of the power supply device 132 can be reduced.

[0344] In the embodiments of the present invention, a semiconductor device in which the transistor 117m and the transistor 117s are connected in series is tested as shown in Figures 1, 3, 4, 19, etc. However, the present invention is not limited to this. For example, it goes without saying that a test may be performed by connecting one transistor 117 to the power supply device 132. It goes without saying that the matters or contents described in this specification and drawings can be combined with each other. [Industrial Applicability]

[0345] The present invention provides a semiconductor element testing device and semiconductor testing method that can be adapted to the circuit operation of an inverter circuit or the like, and that can easily change connections depending on the test content of semiconductor elements such as transistors and the number of semiconductor elements to be tested simultaneously.In addition, since the test current is applied after confirming the connection of the semiconductor elements to be tested, the test can be performed without destroying the semiconductor elements to be tested. [Explanation of symbols]

[0346] 111 Control circuit board (controller) 112 Gate signal control circuit 113 Gate driver circuit 115 Temperature measurement circuit 116 Voltage detection circuit 117 Power Transistor 118 Constant current circuit 121 Current power supply 122 Switch Circuit 124 Switch Circuit 125 Variable Resistor Circuit 126 Drive variable circuit 127 Drive element circuit 128 Clamp Meter 129 Current Sensor 131 Control Rack 132 Power supply 133 Control circuit 134 Heating and cooling plate 135 Circulating Water Pipe 136 Chiller 137 Short Circuit 201 Switch circuit board 202 Connector 203 Sample connection circuit 204 Conductor Plate 205 fork plug 206 connecting pins 207 Motherboard 208 Connector 209 Device control circuit board 210 cabinet 211 Connection wiring 212 Power wiring 213 Connector 214 Bulkhead 215 Bulkhead 216 Opening 219 Connection bolt 220 Contact part 221 Fixing screw 222 signal wiring 223 Heat Pipe 224 Fixing screw 225 Contact point 226 Element terminal 227 Cooling Fan 228 Heat dissipation fin 229 Motor 231 Heat pipe fittings 232 Connection pressure part 233 Connection holder 236 Spring (pressure fitting) 237 Position fixing screw 238 screw holes 239 Spring hole 240 positioning screw hole 251 Convex 252 Groove 302 Voltage selection circuit 311 Pressing tool 312 Insulating board 313 Pressing tool mounting plate 315 Insulation section

Claims

1. A test apparatus for testing a power semiconductor device, the test apparatus comprising: a first transistor having a first connection portion, a second connection portion, and a first gate connection portion; and a second transistor having a third connection portion connected to the second connection portion, a fourth connection portion, and a second gate connection portion, a power supply device having a first power supply terminal and a second power supply terminal and configured to supply a test current; a gate control circuit that applies, to the first gate connection portion, an on-voltage that turns on the first transistor or an off-voltage that turns off the first transistor, and, to the second gate connection portion, an on-voltage that turns on the second transistor or an off-voltage that turns off the second transistor; a first switch circuit having a first connection terminal and a second connection terminal; a second switch circuit having a third connection terminal and a fourth connection terminal; a third switch circuit having a fifth connection terminal and a sixth connection terminal; a current detection device that detects a connection check current that flows through at least one of the first transistor and the second transistor and is smaller than the test current; the first connection portion and the first connection terminal are connected to each other, the second connection terminal and the first power supply terminal are connected to each other; the third connection terminal is connected to the first power supply terminal, the fourth connection terminal and the third connection portion are connected to each other, the second connection portion and the fifth connection terminal are connected to each other, the sixth connection terminal and the second power supply terminal are connected to each other; the fourth connection portion is connected to the second power supply terminal, the gate control circuit is capable of varying an input impedance of at least one of the first gate connection part and the second gate connection part, supplying the connection confirmation current to at least one of the first transistor and the second transistor; a power semiconductor element testing device configured to supply the test current to at least one of the first transistor and the second transistor after detecting the connection check current;

2. A test apparatus for testing a power semiconductor device, the test apparatus comprising: a first transistor having a first connection portion, a second connection portion, and a first gate connection portion; and a second transistor having a third connection portion connected to the second connection portion, a fourth connection portion, and a second gate connection portion, a power supply device having a first power supply terminal and a second power supply terminal and configured to supply a test current; a gate control circuit that applies, to the first gate connection portion, an on-voltage that turns on the first transistor or an off-voltage that turns off the first transistor, and, to the second gate connection portion, an on-voltage that turns on the second transistor or an off-voltage that turns off the second transistor; a first switch circuit having a first connection terminal and a second connection terminal; a second switch circuit having a third connection terminal and a fourth connection terminal; a third switch circuit having a fifth connection terminal and a sixth connection terminal; a current detection device that detects a connection check current that flows through at least one of the first transistor and the second transistor and is smaller than the test current; the first connection portion and the first connection terminal are connected to each other, the second connection terminal and the first power supply terminal are connected to each other; the third connection terminal is connected to the first power supply terminal, the fourth connection terminal and the third connection portion are connected to each other, the second connection portion and the fifth connection terminal are connected to each other, the sixth connection terminal and the second power supply terminal are connected to each other; the fourth connection portion is connected to the second power supply terminal, the gate control circuit is capable of varying an input impedance of at least one of the first gate connection part and the second gate connection part, turning on the first switch circuit, turning off the second switch circuit, and turning on the third switch circuit to apply an on-voltage to the first gate connection portion of the first transistor, apply an off-voltage to the second gate connection portion of the second transistor, and supply the connection check current to the first transistor; turning off the first switch circuit, turning on the second switch circuit, and turning off the third switch circuit to apply an off voltage to the first gate connection portion of the first transistor, apply an on voltage to the second gate connection portion of the second transistor, and supply the connection check current to the second transistor; a power semiconductor element testing device configured to supply the test current to at least one of the first transistor and the second transistor after detecting the connection check current;

3. A test apparatus for testing a power semiconductor device having a first transistor having a first connection portion, a second connection portion, and a first gate connection portion, a power supply device having a first power supply terminal and a second power supply terminal and configured to supply a test current; a gate control circuit that applies an on-voltage to the first gate connection portion to turn on the first transistor or an off-voltage to turn off the first transistor; a first switch circuit having a first connection terminal and a second connection terminal; a current detection device that detects a connection check current that flows through the first transistor and is smaller than the test current; the first connection portion and the first connection terminal are connected to each other, the second connection terminal and the first power supply terminal are connected to each other; the second connection portion is connected to the second power supply terminal, the gate control circuit is capable of varying the input impedance of the first gate connection part, supplying the connection confirmation current to the first transistor; a power semiconductor element testing device configured to supply the test current to the first transistor after detecting the connection check current;

4. A test apparatus for testing a power semiconductor device having a first transistor having a first connection portion, a second connection portion, and a first gate connection portion, a power supply device having a first power supply terminal and a second power supply terminal and configured to supply a test current; a gate control circuit that applies an on-voltage to the first gate connection portion to turn on the first transistor or an off-voltage to turn off the first transistor; a first switch circuit having a first connection terminal and a second connection terminal; a voltage detection circuit for measuring a terminal voltage between the first connection portion and the second connection portion; a current detection device that detects a connection check current that flows through the first transistor and is smaller than the test current; the first connection portion and the first connection terminal are connected to each other, the second connection terminal and the first power supply terminal are connected to each other; the second connection portion is connected to the second power supply terminal, the gate control circuit is capable of varying the input impedance of the first gate connection part, applying an on-voltage to the first gate connection part of the transistor and supplying the connection check current to the first transistor; a power semiconductor element testing device that, after detecting the connection check current, transitions to a test mode in which the test current is supplied to the first transistor;

5. the off-voltage includes a first off-voltage and a second off-voltage lower than the first off-voltage, 5. The power semiconductor element testing apparatus according to claim 1, 2, 3, or 4, wherein the gate control circuit periodically applies the on-voltage, the first off-voltage, and the second off-voltage to the first gate connection portion.

6. Further comprising a heating and cooling plate; the power semiconductor element is disposed on the heating / cooling plate; 5. The power semiconductor element testing device according to claim 1, wherein a drain groove is formed around the periphery of the heating / cooling plate to drain circulating water leaking from the heating / cooling plate.

7. 5. The power semiconductor device testing apparatus according to claim 1, further comprising a fourth switch circuit for short-circuiting the first power supply terminal and the second power supply terminal.

8. the first switch circuit is mounted or disposed on a switch circuit board; 5. The power semiconductor device testing device according to claim 1, wherein a first conductor plate and a second conductor plate are attached to the switch circuit board.

9. Further comprising a motherboard, the first switch circuit is mounted or disposed on a switch circuit board; 5. The power semiconductor device testing device according to claim 1, wherein the switch circuit board is connected to the motherboard by a connector.

10. 3. The power semiconductor device testing apparatus according to claim 1, wherein the first transistor and the second transistor are configured in the same package.

Images