Semiconductor Devices

Abstract

This semiconductor device comprises: a circuit board having an opening, a first conductive pattern provided on the opening periphery region of one surface among the front and back surfaces of the substrate, and a second conductive pattern provided on the opening periphery region of the other surface among the front and back surfaces of the substrate; a first conductor plate disposed to face the opening, where the surface facing the circuit board is joined with the first conductive pattern using a first joining material; a second conductor plate disposed to face the opening, where the surface facing the circuit board is joined to the second conductive pattern using a second joining material; and a semiconductor element having electrodes on both the front and back surfaces of the element, where one electrode is joined to the opening-facing surface of the first conductor plate using an electrically conductive joining material, and the other electrode is joined to the opening-facing surface of the second conductor plate using an electrically conductive joining material, where at least one of the first and second joining materials is composed from an insulating joining material.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] In recent years, hybrid and electric vehicles have become more popular in order to reduce environmental impact. Hybrid and electric vehicles are equipped with a power conversion device for supplying power from a battery to a traction motor. The inverter circuit provided in the power conversion device uses a semiconductor device called a power module, which includes power semiconductor elements. For example, a pair of upper and lower arm semiconductor elements of an inverter circuit are packaged in a single semiconductor device. Electrodes are formed on both the front and back surfaces of a semiconductor chip constituting the semiconductor element, and lead members are solder-joined to each electrode so as to sandwich the semiconductor chip (see, for example, Patent Document 1). Furthermore, a heat dissipation device is provided in the semiconductor device to dissipate heat generated by the semiconductor element. For example, an insulating sheet is pressure-bonded to the surface of the lead member opposite the semiconductor chip bonding surface, and a cooler is arranged so as to be pressed against the insulating sheet. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2005-136332 Summary of the Invention [Problem to be solved by the invention]

[0004] In semiconductor devices such as those described above, a long current path between the upper and lower arms leads to increased loss due to increased inductance, and so reducing the inductance of the upper and lower arm current paths is desirable. Furthermore, it is important to apply sufficient pressure when crimping the insulating sheet to the lead members; insufficient pressure can result in reduced heat dissipation and insulation performance. [Means for solving the problem]

[0005] A semiconductor device according to an embodiment of the present invention comprises a circuit board having an opening, a first conductive pattern provided in a peripheral area of ​​the opening on one of the front and back surfaces of the substrate, and a second conductive pattern provided in a peripheral area of ​​the opening on the other of the front and back surfaces of the substrate; a first conductor plate arranged opposite the opening, the surface facing the circuit board being bonded to the first conductive pattern with a first bonding material; a second conductor plate arranged opposite the opening, the surface facing the circuit board being bonded to the second conductive pattern with a second bonding material; and a semiconductor element having electrodes on both the front and back surfaces of the element, one of the electrodes being bonded to the surface of the first conductor plate facing the opening with a conductive bonding material and the other electrode being bonded to the surface of the second conductor plate facing the opening with a conductive bonding material, wherein at least one of the first and second bonding materials is an insulating bonding material. A semiconductor device according to another aspect of the present invention is a semiconductor device comprising: a first semiconductor element having electrodes on both the front and back surfaces of the element and constituting an upper arm; a second semiconductor element having electrodes on both the front and back surfaces of the element and constituting a lower arm; a positive terminal; a negative terminal; and an output terminal; and the semiconductor device comprises: a first opening; a second opening provided adjacent to the first opening; a first conductive pattern provided in a peripheral region of the first opening on one of the front and back surfaces of a substrate; a second conductive pattern provided in a peripheral region of the first opening on the other of the front and back surfaces of the substrate; a third conductive pattern provided in a peripheral region of the second opening on one of the front and back surfaces of the substrate; a fourth conductive pattern provided in a peripheral region of the second opening on the other of the front and back surfaces of the substrate; and a circuit board having through holes that electrically connect the second conductive pattern and the third conductive pattern in a region between the first opening and the second opening; and a semiconductor element disposed so as to face the first opening and whose surface facing the circuit board is the first conductive pattern. a first conductor plate bonded to the conductive pattern with a conductive bonding material and connected to the positive terminal; a second conductor plate arranged to face the first opening, having a surface facing the circuit board bonded to the second conductive pattern with a conductive bonding material and connected to the output terminal; a third conductor plate arranged to face the second opening, having a surface facing the circuit board bonded to the third conductive pattern with a conductive bonding material and connected to the output terminal; and a fourth conductor plate arranged to face the second opening, having a surface facing the circuit board bonded to the fourth conductive pattern with a conductive bonding material and connected to the negative terminal; the first semiconductor element has electrodes on both the front and back surfaces of the element bonded to the opening-facing surfaces of the first conductor plate and the second conductor plate, respectively, with a conductive bonding material; and the second semiconductor element has electrodes on both the front and back surfaces of the element bonded to the opening-facing surfaces of the third conductor plate and the opening-facing surfaces of the fourth conductor plate, respectively, with a conductive bonding material. [Effects of the Invention]

[0006] According to the present invention, it is possible to reduce loss due to the influence of inductance, and improve heat dissipation performance and insulation performance. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a circuit diagram showing an example of a circuit configuration of a semiconductor device. [Figure 2] FIG. 2 is a perspective view showing the appearance of the semiconductor device. [Figure 3] FIG. 3 is an exploded view of the semiconductor device. [Figure 4] FIG. 4 is a diagram showing the front surface side of the circuit board. [Figure 5] FIG. 5 is a diagram showing the back side of the circuit board. [Figure 6] FIG. 6 is a diagram showing the layout of semiconductor elements on a circuit board. [Figure 7] FIG. 7 is a diagram illustrating a current path. [Figure 8] FIG. 8 is a cross-sectional view taken along line AA in FIG. [Figure 9] FIG. 9 is a cross-sectional view taken along the line BB in FIG. [Figure 10] FIG. 10 is a diagram showing the front surface side of the circuit board in the second embodiment. [Figure 11] FIG. 11 is a diagram showing the back surface side of the circuit board in the second embodiment. [Figure 12] FIG. 12 is a diagram illustrating a current path in the second embodiment. [Figure 13] FIG. 13 is a cross-sectional view taken along CC in FIG. [Figure 14] FIG. 14 is an exploded perspective view of the semiconductor device according to the third embodiment. [Figure 15] FIG. 15 is a diagram showing the front surface side of a circuit board according to the third embodiment. [Figure 16] FIG. 16 is a diagram showing the back surface side of the circuit board in the third embodiment. [Figure 17] FIG. 17 is a diagram showing the front surface side of the circuit board in the first modification. [Figure 18] FIG. 18 is a cross-sectional view taken along line DD in FIG. [Figure 19]FIG. 19 is a diagram illustrating the second modification. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The following description and drawings are examples for explaining the present invention, and appropriate omissions and simplifications have been made for clarity of explanation. Furthermore, in the following description, identical or similar elements and processes are given the same reference numerals, and duplicate explanations may be omitted. Note that the content described below merely shows an example of an embodiment of the present invention, and the present invention is not limited to the following embodiment, and can be implemented in various other forms.

[0009] (First embodiment) 1 is a circuit diagram showing an example of a circuit configuration of a semiconductor device according to the present embodiment. The semiconductor device 300 includes an upper arm 301 configured with an IGBT (insulated gate bipolar transistor) 321U and a diode 322U, and a lower arm 302 configured with an IGBT 321L and a diode 322L. Here, an IGBT is used as the switching element, but a configuration using a FET (field effect transistor) or the like may also be used. When a FET is used, a semiconductor element using SiC may also be used.

[0010] The upper arm 301 has a positive terminal 311 and a signal terminal 314. The lower arm 302 has a negative terminal 312 and a signal terminal 315. The positive terminal 311 and the negative terminal 312 are connected to a capacitor or the like, and power is supplied from outside to the semiconductor device 300. The signal terminals 314 and 315 are connected to a control board (not shown), and the switching operations of the IGBTs 321L and 321U are controlled by the control board.

[0011] The semiconductor device 300 includes an AC terminal 313 and an intermediate connector 303 electrically connected to the AC terminal 313. The intermediate connector 303 electrically connects the upper arm 301 and the lower arm 302. The AC terminal 313 outputs a current to the outside of the semiconductor device 300. The semiconductor device 300 controls the current output from the AC terminal 313 by repeatedly turning on and off the IGBTs 321U and 321L.

[0012] The semiconductor device 300 causes the IGBT 321U to operate on and the IGBT 321L to operate off, thereby causing a current to flow from the positive terminal 311 to the AC terminal 313. On the other hand, the semiconductor device 300 causes the IGBT 321U to operate off and the IGBT 321L to operate on, thereby causing a current to flow from the AC terminal 313 to the negative terminal 312. Since the IGBTs 321U and 321L have parasitic capacitance, a small amount of current flows from the positive terminal 311 to the negative terminal 312 via the parasitic capacitance during switching operation.

[0013] Current path U, indicated by the dashed line, is the path of current through the parasitic capacitance that occurs when IGBT321U is turned on. Current path L, indicated by the dotted line, is the path of current through the parasitic capacitance that occurs when IGBT321L is turned on. If the inductance of current path U or current path L is large, it will cause an increase in loss during switching.

[0014] 2 is a perspective view showing the appearance of semiconductor device 300. Semiconductor device 300 is sealed with sealing resin 330. Positive electrode terminal 311, negative electrode terminal 312, AC terminal 313, and signal terminals 314 and 315 provided on semiconductor device 300 are exposed from sealing resin 330. Resin insulating material 380 is provided on both the front and back surfaces of semiconductor device 300 sealed with sealing resin 330.

[0015] FIG. 3 is a development view of the semiconductor device 300 excluding the sealing resin 330 and the insulating resin 380. In the following description, the x-y-z coordinate axes are set as shown in FIG. 3. The components constituting the semiconductor device 300 can be roughly classified into three groups based on their positions in the z direction. First, the first layer, which is the lowest in the z direction, contains the first conductor plate 341, the third conductor plate 343, the negative terminal 312, and the signal terminals 314 and 315. The second layer, which is above the first layer, contains the IGBTs 321U and 321L, the diodes 322U and 322L, and the circuit board 400. The third layer, which is above the second layer, contains the second conductor plate 342 and the fourth conductor plate 344.

[0016] A first opening 401 and a second opening 402 are formed adjacent to each other in the circuit board 400. The IGBT 321U and the diode 322U are disposed in a region corresponding to the first opening 401, and the IGBT 321L and the diode 322L are disposed in a region corresponding to the second opening 402. In the exploded perspective view of Fig. 3, the IGBTs 321U and 321L and the diodes 322U and 322L located on the second layer and the circuit board 400 are shown separated into upper and lower parts in the z direction for ease of viewing.

[0017] The first conductor plate 341 and the third conductor plate 343 are arranged side by side in the y direction so as to face the first opening 401 and the second opening 402, respectively. The second conductor plate 342 and the fourth conductor plate 344 are arranged side by side in the y direction so as to face the first opening 401 and the second opening 402, respectively. The IGBT 321U and the diode 322U are arranged so as to be sandwiched between the first conductor plate 341 and the second conductor plate 342. The IGBT 321L and the diode 322L are arranged so as to be sandwiched between the third conductor plate 343 and the fourth conductor plate 344. The first to fourth conductor plates 341 to 344 are formed of copper, a copper alloy, aluminum, an aluminum alloy, or the like.

[0018] In the IGBTs 321U and 321L, a collector electrode is provided on the back surface (negative surface in the z direction) of the IGBT chip, and an emitter electrode and a control signal electrode are provided on the front surface (positive surface in the z direction). In the diodes 322U and 322L, a cathode electrode is provided on the back surface (negative surface in the z direction) of the diode chip, and an anode electrode is provided on the front surface (positive surface in the z direction).

[0019] The collector electrode of the IGBT 321U is bonded to the opening-facing surface on the front side of the first conductor plate 341 in the drawing by bonding material 350, and the cathode electrode of the diode 322U is bonded to the opening-facing surface on the back side of the second conductor plate 342 by bonding material 351, and the anode electrode of the diode 322U is bonded to the opening-facing surface on the back side of the second conductor plate 342 by bonding material 353. The first conductor plate 341 has a heat dissipation surface 345 on the surface opposite to the surface to which the IGBT 321U and the diode 322U are bonded. The second conductor plate 342 has a heat dissipation surface 346 on the surface opposite to the surface to which the IGBT 321U and the diode 322U are bonded. Heat generated in the IGBT 321U and the diode 322U is dissipated to the outside from these heat dissipation surfaces 345, 346.

[0020] The collector electrode of the IGBT 321L is bonded to the opening-facing surface on the front side of the third conductor plate 343 in the drawing with a bonding material 354, and the cathode electrode of the diode 322L is bonded to the opening-facing surface on the back side of the fourth conductor plate 344 with a bonding material 355, and the anode electrode of the diode 322L is bonded to the opening-facing surface on the back side of the fourth conductor plate 344 with a bonding material 357. The third conductor plate 343 has a heat dissipation surface 347 on the surface opposite to the surface to which the IGBT 321L and the diode 322L are bonded. The fourth conductor plate 344 has a heat dissipation surface 348 on the surface opposite to the surface to which the IGBT 321L and the diode 322L are bonded. Heat generated in the IGBT 321L and the diode 322L is dissipated to the outside from these heat dissipation surfaces 347, 348.

[0021] The first conductor plate 341 has a positive terminal 311 at its end on the positive side in the y direction. The second conductor plate 342 has a first intermediate connection portion 303A at its end on the negative side in the y direction, which constitutes part of the intermediate connection portion 303 in FIG. 1. The third conductor plate 343 has an AC terminal 313 at its end on the negative side in the y direction. A second intermediate connection portion 303B extending in the negative side in the x direction is formed at the base of the AC terminal 313. The second intermediate connection portion 303B is joined to the first intermediate connection portion 303A of the second conductor plate 342 by a joining material 359. The joined first intermediate connection portion 303A and second intermediate connection portion 303B correspond to the intermediate connection portion 303 in FIG. 1.

[0022] The fourth conductor plate 344 has a negative electrode terminal connection portion 316 at its end on the positive side in the y direction. A negative electrode terminal 312 is disposed adjacent to the third conductor plate 343 on the positive side in the y direction. The negative electrode terminal 312 has a negative electrode terminal connection portion 317. The negative electrode terminal connection portion 317 of the negative electrode terminal 312 is connected to the negative electrode terminal connection portion 316 of the fourth conductor plate 344 by a bonding material 358. Note that the bonding materials 350 to 359 may be conductive bonding materials such as solder, a sintered material, or a conductive adhesive.

[0023] The circuit board 400 has bonding portions 422 and 423 (not shown) (see FIGS. 4 and 6 described later) on the board surface adjacent to the openings 401 and 402. The control signal electrode 3210 (see FIGS. 6 and 7 described later) of the IGBT 321U arranged in the area of ​​the first opening 401 is connected to the bonding portion 422 by a bonding wire 370. Similarly, the control signal electrode 3210 of the IGBT 321L arranged in the area of ​​the second opening 402 is connected to the bonding portion 423 by a bonding wire 371. A plurality of substrate bonding materials 410 are arranged on both the front and back surfaces of the circuit board 400 in the areas surrounding the openings 401 and 402, and the substrate bonding materials 410 bond or adhere the circuit board 400 to the first conductor plate 341, the second conductor plate 342, the third conductor plate 343, and the fourth conductor plate 344. The substrate bonding material 410 may be a conductive bonding material such as solder, a sintered material, or a conductive adhesive.

[0024] FIG. 4 is a diagram showing the front side (the surface on the positive side in the z direction) of circuit board 400. FIG. 5 is a diagram showing the back side (the surface on the negative side in the z direction) of circuit board 400. Circuit board 400 has a conductive circuit pattern formed on an insulating board base 403. The circuit pattern is formed on the front and back sides of board base 403. As described above, openings 401 and 402, which are rectangular through-holes, are formed in board base 403. Board base 403 may be formed of glass epoxy resin, glass polyimide resin, fluororesin, or the like, or may be formed of a ceramic substrate. The circuit pattern is formed of a conductive material, and for example, copper foil attached to board base 403 is used.

[0025] A second substrate pattern 431 is provided on the substrate base 403 around the first opening 401, surrounding the first opening 401. The second substrate pattern 431 is composed of five separate patterns, with gap regions 450 formed between the patterns. The second substrate pattern 431, located between the first opening 401 and the second opening 402, is composed of a bonding region 431a bonded to the second conductor plate 342 and a first intermediate connection region 431b provided with a plurality of intermediate connection through-holes 460. The bonding region 431a and the other four second substrate patterns 431 are bonded to the second conductor plate 342, which is disposed opposite the front surface of the circuit board 400, by the substrate bonding material 410 shown in FIG. 1, and are electrically connected to the second conductor plate 342. The first intermediate connection region 431b is electrically connected to a pattern (a third substrate pattern 432, described later) provided on the back surface of the circuit board 400 by the intermediate connection through-holes 460.

[0026] A plurality of control signal patterns 420 are provided on the substrate base 403 above the first opening 401 in the figure. The plurality of control signal patterns 420 are formed to extend from a position close to the first opening 401 to the upper edge of the circuit substrate 400 in the figure, passing through a gap region 450 between two second substrate patterns 431. A bonding portion 422 is formed at the opening-side end of each control signal pattern 420, and a first control terminal joint portion 424 is formed at the other end. As described above, the bonding portion 422 is connected to the control signal electrode 3210 of the IGBT 321U by a bonding wire 370. The first control terminal joint portion 424 is electrically connected to a third control terminal joint portion 426 (see FIG. 5) on the back side of the circuit substrate 400 by a through-hole.

[0027] A fourth substrate pattern 433 is provided on the substrate base 403 around the second opening 402, surrounding the second opening 402. The fourth substrate pattern 433 is composed of five separate patterns, with gap regions 450 formed between the patterns. The fourth substrate pattern 433, located between the second opening 402 and the first opening 401, is composed of a bonding region 433a bonded to the fourth conductor plate 344, a negative electrode pattern region 433b continuing above the bonding region 433a in the figure, and a negative electrode pattern region 433c continuing above the negative electrode pattern region 433b in the figure. A portion of the negative electrode pattern region 433c is located above the first opening 401 in the figure. A negative electrode connection through-hole 461 is provided at the end on the right side in the figure of the negative electrode pattern region 433c. The negative electrode connection through-hole 461 is electrically connected to a negative electrode terminal connection pattern 445 (see FIG. 5) provided on the back side of the circuit board 400. The bonding area 433a and the other four fourth substrate patterns 433 are bonded to the third conductive plate 343 arranged opposite the front surface side of the circuit board 400 by the substrate bonding material 410 shown in Figure 1, and are electrically connected to the third conductive plate 343.

[0028] A plurality of control signal patterns 421 are provided on the substrate base 403 below the second opening 402 in the drawing. The plurality of control signal patterns 421 are formed to extend from a position close to the second opening 402 to the lower edge of the circuit substrate 400 in the drawing, passing through a gap region 450 between two fourth substrate patterns 433. A bonding portion 423 is formed at the opening-side end of each control signal pattern 421, and a second control terminal joint portion 425 is formed at the other end. The second control terminal joint portion 425 is electrically connected to a fourth control terminal joint portion 427 (see FIG. 5 ) on the back side of the circuit substrate 400 by a through hole. As described above, the bonding portion 423 is connected to the control signal electrode 3210 of the IGBT 321L by a bonding wire 371.

[0029] 4, each of the second substrate pattern 431 and the fourth substrate pattern 433 is separated into a plurality of patterns, and gap regions 450 are formed between the patterns, which allows the resin to easily flow into the openings 401 and 402 when sealing the semiconductor device 300 with the sealing resin 330. As a result, productivity can be improved.

[0030] FIG. 5 is a diagram showing the back side of the circuit board 400. A first substrate pattern 430 is provided on the substrate base 403 around the first opening 401 (shown on the right side of the figure) to surround the first opening 401. A third substrate pattern 432 is provided on the substrate base 403 around the second opening 402 (shown on the left side of the figure) to surround the second opening 402. The third substrate pattern 432 has a second intermediate connection region 432a in a pattern region between the second opening 402 and the first opening 401, where multiple intermediate connection through-holes 460 are provided. The second intermediate connection region 432a is electrically connected to the first intermediate connection region 431b on the front side via the intermediate connection through-holes 460. That is, the third conductor plate 433 bonded to the third substrate pattern 432 is electrically connected to the second conductor plate 342 via the first intermediate connection region 431b, the intermediate connection through-holes 460, the first intermediate connection region 431b, and the second intermediate connection region 431a.

[0031] A fourth negative electrode pattern 445 connected to the negative electrode connection through-hole 461 is disposed above the second intermediate connection region 432a in the figure. As described above, the fourth negative electrode pattern 445 is electrically connected to the fourth substrate pattern 433 on the front surface side via the negative electrode connection through-hole 461. The first substrate pattern 430 around the first opening 401 is connected to the first conductive plate 341 by the substrate bonding material 410. The pattern region of the third substrate pattern 432 around the second opening 402, excluding the second intermediate connection region 432a, is connected to the third conductive plate 343 by the substrate bonding material 410. Note that the first substrate pattern 430 and the third substrate pattern 432 may also have a gap region 450, as in the second substrate pattern 431 and the fourth substrate pattern 433 shown in FIG. 4 . This also improves the flowability of the sealing resin 330 toward the opening side.

[0032] The third control terminal joint portion 426 is electrically connected to the first control terminal joint portion 424 on the front surface side via a through hole. The third control terminal joint portion 426 is joined to the signal terminal 314 in FIG. 3 by solder. The fourth control terminal joint portion 427 is electrically connected to the second control terminal joint portion 425 via a through hole. The fourth control terminal joint portion 427 is joined to the signal terminal 315 in FIG. 3 by solder. In addition to solder, a sintered material, a conductive adhesive, or the like may also be used as the joining material for joining the signal terminals 314, 315.

[0033] 6 is a diagram showing the arrangement of IGBTs 321U and 321L on a circuit board 400. FIG. 6 is a diagram showing the front side of the circuit board 400, with a first conductor plate 341 and a third conductor plate 343 bonded to the back side of the circuit board 400. The IGBT 321U and the diode 322U are bonded to the surface of the first conductor plate 341 facing the first opening 401. The IGBT 321L and the diode 322L are bonded to the surface of the third conductor plate 343 facing the second opening 402. A control signal electrode 3210 provided on the front side of the IGBT 321U is connected to a bonding portion 422 provided on the front side of the circuit board 400 by a bonding wire 370. A control signal electrode 3210 provided on the front side of the IGBT 321L is connected to a bonding portion 423 provided on the front side of the circuit board 400 by a bonding wire 371.

[0034] As described in FIG. 3 , the negative terminal 312 disposed on the back side of the circuit board 400 has a negative terminal connection portion 317 joined to a negative terminal connection portion 316 of the fourth conductor plate 344. Meanwhile, the negative terminal connection portion 317 is also connected by solder or the like to a negative terminal connection pattern 445 (see FIG. 5 ) provided on the back side of the circuit board 400. The negative terminal connection pattern 445 is electrically connected to a fourth board pattern 433 provided on the front side of the circuit board 400 via a negative connection through-hole 461. That is, the negative terminal 312 is connected to the fourth conductor plate 344 via the negative terminal connection portion 316, and is also connected to the fourth conductor plate 344 via the negative terminal connection pattern 445 provided adjacent to the positive terminal 311.

[0035] The signal terminal 314 is solder-bonded to a third control terminal joint 426 (see FIG. 5) provided on the back side of the circuit board 400. The third control terminal joint 426 is electrically connected to a first control terminal joint 424 of the control signal pattern 420 provided on the front side via a through-hole (see FIG. 9, which will be described later). The signal terminal 315 is solder-bonded to a fourth control terminal joint 427 (see FIG. 5) provided on the back side of the circuit board 400. The fourth control terminal joint 427 is electrically connected to a second control terminal joint 425 of the control signal pattern 421 provided on the front side via a through-hole.

[0036] Fig. 7 is a diagram for explaining a current path, and shows semiconductor device 300 in a state where sealing resin 330 and resin insulating material 380 shown in Fig. 2 have been removed. Semiconductor device 300 shown in Fig. 7 is configured by adding second conductive plate 342 and fourth conductive plate 344 to the configuration shown in Fig. 6. Fig. 8 is a cross-sectional view taken along line AA in Fig. 7. Note that Fig. 8 also shows resin insulating material 380, which is not shown in Fig. 7.

[0037] As described above, the second conductor plate 342 bonded to the IGBT 321U and the diode 322U has its conductor plate peripheral region bonded to four second substrate patterns 431 provided around the first opening 401 and to a bonding region 431a of the second substrate pattern 431 provided between the openings 401 and 402. Furthermore, the first intermediate connection portion 303A of the second conductor plate 342 is bonded to the second intermediate connection portion 303B of the AC terminal 313 (see FIG. 3 ). Meanwhile, the fourth conductor plate 344 bonded to the IGBT 321L and the diode 322L has its conductor plate peripheral region bonded to four fourth substrate patterns 433 provided around the second opening 402 and to a bonding region 433a of the fourth substrate pattern 433 provided between the openings 401 and 402. Furthermore, the negative electrode terminal connection portion 316 of the fourth conductive plate 344 is joined to the negative electrode terminal connection portion 317 of the negative electrode terminal 312 .

[0038] 8, the chip bonding region on the opening-facing surface of second conductor plate 342 protrudes downward in the figure and is bonded to IGBT 321U and diode 322U (not shown) located in the area of ​​first opening 401 with bonding materials 351 and 353. Similarly, the chip bonding region on the opening-facing surface of fourth conductor plate 344 protrudes downward in the figure and is bonded to diode 322L and IGBT 321L (not shown) located in the area of ​​second opening 402 with bonding materials 357 and 355. That is, circuit board 400 is arranged so that openings 401 and 402 face the chip bonding regions of conductor plates 341 to 344 and the surface on which the circuit pattern is formed faces the conductor plate region surrounding the chip bonding region.

[0039] As described above, the first substrate pattern 430 provided on the back surface side of the substrate base 403 around the first opening 401 is bonded to the first conductor plate 341 by the substrate bonding material 410. The second substrate pattern 431 provided on the front surface side of the substrate base 403 around the first opening 401 is bonded to the second conductor plate 342 by the substrate bonding material 410. The third substrate pattern 432 provided on the back surface side of the substrate base 403 around the second opening 402 is bonded to the third conductor plate 343 by the substrate bonding material 410. The fourth substrate pattern 433 provided on the front surface side of the substrate base 403 around the second opening 402 is bonded to the fourth conductor plate 344 by the substrate bonding material 410. In addition, the first intermediate connection region 431b formed integrally with the bonding region 431a is electrically connected to the second intermediate connection region 432a provided on the back surface side and formed integrally with the third substrate pattern 432 via the intermediate connection through hole 460.

[0040] Resin insulating material 380 is bonded to heat dissipation surface 345 of first conductor plate 341 and heat dissipation surface 347 of third conductor plate 343 so as to cover them. Similarly, resin insulating material 380 is bonded to heat dissipation surface 346 of second conductor plate 342 and heat dissipation surface 348 of fourth conductor plate 344 so as to cover them. In semiconductor device 300, a cooling device such as a cooler or radiator is attached by pressing it against the surface of resin insulating material 380. Resin insulating material 380 is formed from a resin insulating material, such as epoxy resin. Resin insulating material 380 is filled with an insulating filler and has excellent thermal conductivity. When resin insulating material 380 is bonded to the heat dissipation surface, pressure is applied to resin insulating material 380 from above and below. Insufficient pressure will impair insulation performance and reduce thermal conductivity to the cooling device attached to the surface of resin insulating material 380.

[0041] In this embodiment, as shown in FIG. 8 , the areas of the first and second conductor plates 341, 342 that face the circuit board 400 around the chip bonding areas are bonded to the pattern areas (first board pattern 430 and second board pattern 431) of the circuit board 400 by the board bonding material 410. Similarly, the areas of the third and fourth conductor plates 343, 344 that face the circuit board 400 around the chip bonding areas are bonded to the pattern areas (third board pattern 432 and fourth board pattern 433) of the circuit board 400 by the board bonding material 410. Therefore, even if pressure is applied from above and below when bonding the resin insulating material 380, it is possible to suppress or prevent the end areas of the conductor plates 341-344 from bending inward in the thickness direction. As a result, sufficient surface pressure is applied to the resin insulating material 380 even in the end areas of the conductor plates 341-344, and sufficient insulation and heat conduction performance can be obtained.

[0042] Next, the current paths will be described. Current paths 101 and 102 in Fig. 7 show the paths of current flowing from the positive electrode terminal 311 to the negative electrode terminal 312. First, the first current path 101 will be described. The first current path 101 is the path of current flowing from the positive electrode terminal 311 to the negative electrode terminal 312 via the first and second intermediate connectors 303A and 303B, and corresponds to the current paths U and L in Fig. 1.

[0043] Current path U in Figure 1 is the current path when IGBT321U is in the on state and IGBT321L is in the off state, and current flows in the following order: positive terminal 311, first conductor plate 341, IGBT321U, second conductor plate 342, first intermediate connection part 303A, second intermediate connection part 303B, third conductor plate 343, diode 322L, fourth conductor plate 344, negative terminal connection part 316, negative terminal connection part 317, and negative terminal 312. Further, current path L in Figure 1 is the current path when IGBT321U is in the off state and IGBT321L is in the on state, and the current flows in the following order: positive terminal 311, first conductor plate 341, diode 322U, second conductor plate 342, first intermediate connection portion 303A, second intermediate connection portion 303B, third conductor plate 343, IGBT321L, fourth conductor plate 344, negative terminal connection portion 316, negative terminal connection portion 317, and negative terminal 312.

[0044] On the other hand, the second current path 102 is a path of current flowing from the positive terminal 311 to the negative terminal 312 via the first intermediate connection region 431b and the second intermediate connection region 432a of the circuit board 400. When the IGBT 321U is in an on state and the IGBT 321L is in an off state, the current flows in the following order: positive terminal 311, first conductor plate 341, IGBT 321U, second conductor plate 342, junction region 431a, first intermediate connection region 431b, intermediate connection through-hole 460, second intermediate connection region 432a, third conductor plate 343, diode 322L, fourth conductor plate 344, negative terminal connection portion 316, negative terminal connection portion 317, and negative terminal 312. When IGBT321U is in the off state and IGBT321L is in the on state, current flows in the following order: positive terminal 311, first conductor plate 341, diode 322U, second conductor plate 342, junction region 431a, first intermediate connection region 431b, intermediate connection through hole 460, second intermediate connection region 432a, third conductor plate 343, IGBT321L, fourth conductor plate 344, negative terminal connection portion 316, negative terminal connection portion 317, and negative terminal 312.

[0045] As described above, in this embodiment, current flows not only through first current path 101 corresponding to current paths U and L shown in FIG. 1 , but also through second current path 102 passing through first intermediate connection region 431b and second intermediate connection region 432a of circuit board 400. As shown in FIG. 7 , in second current path 102, current flows from second conductor plate 342 to third conductor plate 343 through first and second intermediate connection regions 431b and 432a of circuit board 400. Therefore, the current path from positive terminal 311 to negative terminal 312 in second current path 102 is shorter than that in first current path 101. As a result, inductance can be reduced.

[0046] In the semiconductor device 300 of this embodiment, the fourth conductor plate 344 is connected to the negative terminal 312 via the negative terminal connection portions 316 and 317, and is also connected to the negative terminal 312 via the fourth board pattern 433, the negative terminal connection through-hole 461, and the negative terminal connection pattern 445. The first current path 101 and the second current path 102 described above are paths of current flowing from the fourth conductor plate 344 to the negative terminal 312 via the negative terminal connection portions 316 and 317. On the other hand, the third current path 103 indicated by the dashed dotted line in FIG. 7 is a path of current flowing from the fourth conductor plate 344 to the bonding region 433a and the negative pattern region 433b of the fourth board pattern 433, and then to the negative terminal 312 via the negative terminal connection through-hole 461 and the negative terminal connection pattern 445 adjacent to the positive terminal 311.

[0047] Positive terminal 311 and negative terminal 312 are placed side by side in close proximity as shown in Fig. 7. The direction of the current flowing through positive terminal 311 and the direction of the current flowing through negative terminal 312 are opposite, so the inductances of the currents flowing through each other cancel each other out, and the closer they are to each other, the lower the inductance becomes.

[0048] The negative electrode connecting through-hole 461 and the negative electrode terminal connecting pattern 445 in the third current path 103 are disposed closer to the positive electrode terminal 311 than the negative electrode terminal connecting portion 316 of the fourth conductor plate 344. Therefore, the third current path 103 allows current to flow to the negative electrode terminal 312 via a path closer to the positive electrode terminal 311 than the first and second current paths 101 and 102, which flow to the negative electrode terminal 312 via the negative electrode terminal connecting portion 316. As a result, inductance can be further reduced.

[0049] Furthermore, the negative electrode pattern region 433c, which is connected above the negative electrode pattern region 433b in the figure, is arranged to overlap with a small gap on the positive z-direction side of the positive electrode terminal 311. By arranging the negative electrode pattern region 433c in this manner, an eddy current flows in the surface layer of the negative electrode pattern region 433c due to the current flowing in the positive electrode terminal 311, thereby reducing inductance.

[0050] The output current 104 output from the AC terminal 313 is a current that flows in an external device, such as a motor or a generator, connected to the semiconductor device 300. The output current 104 has two current paths. The first current path is a path through which the current flows from the positive terminal 311 to the first conductor plate 341, the IGBT 321U, the second conductor plate 342, the bonding region 431a of the circuit board 400, the first intermediate connection region 431b, the intermediate connection through-hole 460, the second intermediate connection region 432a, the third conductor plate 343, and the AC terminal 313. The second current path is a path through which the current flows from the positive terminal 311 to the first conductor plate 341, the IGBT 321U, the second conductor plate 342, the first intermediate connection portion 303A, the second intermediate connection portion 303B, and the AC terminal 313.

[0051] Output current 104 is larger than the currents flowing through current paths U and L (see FIG. 1). Therefore, first intermediate connector 303A and second intermediate connector 303B are designed to have a thicker plate thickness so that their electrical resistance is smaller than that of the patterns on circuit board 400. Therefore, when only the first current path that passes current via the patterns on circuit board 400 exists, heat generation due to electrical resistance becomes a problem, but by providing a second current path as described above, it is possible to suppress heat generation.

[0052] Fig. 9 is a cross-sectional view taken along the line BB of Fig. 7. The circuit board 400 is provided with a control signal connection through-hole 462 that electrically connects the first control terminal joint portion 424 and the third control terminal joint portion 426. The signal terminal 314 is joined to the third control terminal joint portion 426 by a control terminal joint material 415. Note that the control terminal joint material 415 may be joined to the control signal connection through-hole 462.

[0053] L1 is the distance from the control signal connection through-hole 462 provided in the control signal pattern 420 of the circuit board 400 to the control signal electrode 3210 of the IGBT 321U (see FIG. 6). L2 is the distance from the bonding portion 422 provided in the control signal pattern 420 to the control signal electrode 3210 of the IGBT 321U. h1 is the wire height of the bonding wire 370 from the surface of the IGBT 321U. h2 is the height from the surface of the IGBT 321U to the opposing surface of the second conductor plate 342. As the bonding distance of the bonding wire 370 increases, it becomes more difficult to form a low loop, and the wire height h1 increases. As the wire height h1 increases, the height h2 also needs to increase, making it more difficult to reduce the height (thickness) of the semiconductor device 300.

[0054] In the case of a configuration without using the circuit board 400, the control signal electrode 3210 of the IGBT 321U and the signal terminal 314 are directly connected by the bonding wire 370, and L1 corresponds to the connection distance. When connecting the IGBT 321U and the signal terminal 314 via the circuit board 400 as in the present embodiment, the bonding wire 370 can be connected at a distance L2 shorter than the distance L1 in the case of not using the circuit board 400, and the height dimension of the semiconductor device 300 can be made smaller to achieve miniaturization.

[0055] Note that the rectangular region indicated by the imaginary line (two-dot chain line) in FIG. 9 shows the substrate bonding material 410 that bonds the second substrate pattern 432 and the second conductor plate 432 on the surface side of the circuit board 400. In FIG. 9, when the thickness t1 of the substrate bonding material 410 on the back side is made thicker and the thickness t2 of the substrate bonding material 410 on the surface side is made thinner, the thickness direction position (z-direction position) of the circuit board 400 moves to the right side in the drawing. Then, since the height of the bonding portion 422 as seen from the surface of the IGBT 321U becomes higher, the wire height h1 also tends to become larger. Therefore, by setting t1 < t2 to make the thickness t1 of the substrate bonding material 410 on the back side thinner and suppressing the height of the bonding portion 422, it becomes easier to bond so that the wire height h1 is smaller than h2.

[0056] Also, in the case of not using the circuit board 400, when the y-direction dimensions of the conductor plates 341 and 342 are increased to enlarge the heat dissipation surfaces 345 and 346, the distance between the signal terminal 314 and the IGBT 321U increases, and the distance L1 also increases. That is, in the case of not using the circuit board 400, the connection distance L1, that is, the length of the bonding wire 370, depends on the sizes of the heat dissipation surfaces 345 and 346.

[0057] On the other hand, in this embodiment, the distance L2 between the electrode of the IGBT 321U and the bonding part 422 does not depend on the size of the heat dissipation surfaces 345, 346. Therefore, in the semiconductor device 300 of this embodiment, the size of the heat dissipation surfaces 345, 346 (i.e., the heat dissipation area) can be sufficiently ensured without increasing the height of the device, and sufficient heat dissipation performance can be obtained. In the explanation of FIG. 9, the configuration on the side of the signal terminal 314 was explained, but the same applies to the configuration on the side of the signal terminal 315, and the same effects are achieved.

[0058] (Second embodiment) 10 to 13 are diagrams illustrating a second embodiment of the present invention. The configuration of a semiconductor device 300A of the second embodiment differs from that of the semiconductor device 300 of the first embodiment in the configuration related to a circuit board 400A. Figures 10 and 11 are diagrams illustrating the circuit board 400A of the second embodiment. Fig. 10 is a diagram illustrating the front side of the circuit board 400A, and Fig. 11 is a diagram illustrating the back side of the circuit board 400A.

[0059] 10, a second substrate pattern 431A is provided on the substrate base 403 around the first opening 401, the second substrate pattern 431A being arranged to surround the first opening 401. The second substrate pattern 431A is made up of five separate patterns, with gap regions 450A formed between the patterns. Furthermore, a fourth substrate pattern 433A is provided on the substrate base 403 around the second opening 402, the fourth substrate pattern 433A being arranged to surround the second opening 402. The fourth substrate pattern 433A is made up of five separate patterns, with gap regions 450A formed between the patterns.

[0060] Compared with the configuration of the front surface side of circuit board 400 in the first embodiment shown in Fig. 4, of the five second board patterns 431A and five fourth board patterns 433A, the shapes of second board patterns 431A and fourth board patterns 433A provided between first opening 401 and second opening 402 are different from the shapes of second board patterns 431A and fourth board patterns 433 shown in Fig. 4. These two second board patterns 431A and fourth board patterns 433A are patterns corresponding to bonding regions 431a, 433a in Fig. 4. In other words, second board pattern 431A is bonded to second conductor plate 342, and fourth board pattern 433A is bonded to fourth conductor plate 344. The circuit board 400A does not have the first intermediate connection region 431b provided with the intermediate connection through-hole 460, the negative electrode pattern regions 433b and 433c, the negative electrode connection through-hole 461, and the negative electrode terminal connection pattern 445 as shown in Figures 4 and 5. The other configurations are the same as those of the circuit board 400 shown in Figure 4, and therefore descriptions thereof will be omitted.

[0061] On the back surface side of circuit board 400A shown in Fig. 11, first board pattern 430A is provided to surround first opening 401 on the right side of the figure, and third board pattern 432A is provided to surround second opening 402 on the left side of the figure. Third board pattern 432 of circuit board 400 shown in Fig. 5 had second intermediate connection region 432a where intermediate connection through-hole 460 was provided, but third board pattern 432A shown in Fig. 11 does not have such a region. In other words, third board pattern 432A is configured only with a region to be joined to third conductor plate 343.

[0062] Fig. 12 is a view similar to Fig. 7 in the first embodiment, and shows the semiconductor device 300A in a state where the sealing resin 330 and the resin insulating material 380 are removed. Fig. 13 is a cross-sectional view taken along CC in Fig. 12. The CC cross-section in Fig. 13 is a cross-section at the same position as the AA cross-section in Fig. 7. Fig. 13 also shows the resin insulating material 380, which is not shown in Fig. 12.

[0063] As shown in FIG. 13, the first conductor plate 341, on which the positive terminal 311 is formed, is bonded to a first substrate pattern 430A provided on the back side of the circuit board 400A by a substrate bonding material 410a. The second conductor plate 342 is bonded to a second substrate pattern 431A provided on the front side of the circuit board 400A by a substrate bonding material 410b. The third conductor plate 343 is bonded to a third substrate pattern 432A provided on the back side of the circuit board 400A by a substrate bonding material 410c. As shown in FIG. 12, the first intermediate connection portion 303A provided on the second conductor plate 342 is bonded to a second intermediate connection portion 303B formed at the base of the AC terminal 313 of the third conductor plate 343. The fourth conductor plate 344 is bonded to a fourth substrate pattern 433A provided on the front side of the circuit board 400A by a substrate bonding material 410d. As shown in FIG. 12, a negative electrode terminal connection part 316 provided on the fourth conductive plate 344 is joined to a negative electrode terminal connection part 317 formed on the negative electrode terminal 312.

[0064] In the second embodiment, the path of current flowing from the positive electrode terminal 311 to the negative electrode terminal 312 is only current path 101, which corresponds to current paths U and L in FIG. 1. In addition, in the second embodiment, one or both of substrate bonding materials 410a and 410b are made of an insulating material such as epoxy resin. Similarly, one or both of substrate bonding materials 410c and 410d are made of an insulating material such as epoxy resin. The other configurations are the same as those of the semiconductor device 300 of the first embodiment.

[0065] For example, if an insulating material is used for the substrate bonding material 410a and a conductive material is used for the substrate bonding material 410b, the first substrate pattern 430A becomes an isolated pattern electrically independent from the first conductive plate 341. When a current flows through the current paths U and L shown in FIG. 1, eddy currents flow through the first substrate pattern 430A, suppressing inductance. Furthermore, if insulating materials are used for both the substrate bonding materials 410a and 410b, the first and second substrate patterns 430A and 431A become isolated patterns electrically independent from the first and second conductive plates 341 and 342, and eddy currents flow through the first and second substrate patterns 430A and 431A. Although not described further, the substrate bonding materials 410c and 410d also achieve the same effects as the substrate bonding materials 410a and 410b.

[0066] (Third embodiment) FIG. 14 is an exploded perspective view of a semiconductor device 300B according to a third embodiment of the present invention. Note that FIG. 14 is an exploded perspective view illustrating a case where the sealing resin 330 and the insulating resin 380 shown in FIG. 2 are removed. The semiconductor device 300B according to the third embodiment corresponds to, for example, the circuit components on the upper arm side of the second embodiment, packaged together. As shown in FIG. 14, the semiconductor device 300B includes a first main terminal 311B and a second main terminal 313B. The first main terminal 311B corresponds to the positive terminal 311 or the negative terminal 312 in the first and second embodiments. The second main terminal 313B corresponds to the AC terminal 313 in the first and second embodiments. In FIG. 14, elements identical to those in the second embodiment are denoted by the same reference numerals. For example, a substrate bonding material 410b is disposed on the front side of the circuit board 400B, and a substrate bonding material 410a is disposed on the back side.

[0067] The semiconductor device 300B shown in FIG. 14 includes a circuit board 400B in which an opening 401B is formed. FIGS. 15 and 16 are diagrams showing the circuit board 400B, with FIG. 15 showing the front side and FIG. 16 showing the back side. As shown in FIG. 15, on the front side of the circuit board 400B, a second board pattern 431A similar to that of the circuit board 400A is provided on a board base 403B around the opening 401B. The second board pattern 431A is composed of five separate patterns, with gap regions 450A formed between the patterns. In addition, a plurality of control signal patterns 420 are formed on the board base 403B.

[0068] 16, on the back side of circuit board 400B, first board pattern 430A is provided on board base 403B around opening 401B, surrounding opening 401B. Also provided are a plurality of third control terminal joints 426. Each third control terminal joint 426 is electrically connected to a first control terminal joint 424 on the front side via a control signal connection through-hole 462 (not shown) (see FIG. 9).

[0069] 14 , the collector electrode of the IGBT 321 is bonded to the front surface side of the first conductor plate 341 having the first main terminal 311B with a bonding material 350, and the cathode electrode of the diode 322 is bonded to the front surface side with a bonding material 352. The emitter electrode of the IGBT 321 is bonded to the rear surface side of the second conductor plate 342 with a bonding material 351, and the anode electrode of the diode 322 is bonded to the rear surface side with a bonding material 353.

[0070] Substrate bonding materials 410b are disposed on second substrate patterns 431A on the front surface of circuit substrate 400B, respectively, to bond or adhere circuit substrate 400B to first conductive plate 341. Similarly, substrate bonding materials 410a are disposed on first substrate patterns 430A (not shown) on the rear surface of circuit substrate 400B, respectively, to bond or adhere circuit substrate 400B to second conductive plate 342. Note that conductive bonding materials such as solder, sintered material, and conductive adhesive are used for substrate bonding materials 410a and 410b. First intermediate connection portion 303A formed on second conductive plate 342 is bonded to second intermediate connection portion 303B formed on second main terminal 313B by bonding material 359.

[0071] The signal terminal 314 is solder-bonded to a third control terminal joint 426 (see FIG. 16) provided on the back surface side of the circuit board 400B. As described in FIG. 9, the third control terminal joint 426 is electrically connected to a first control terminal joint 424 of the control signal pattern 420 provided on the front surface side via a control signal connection through-hole 462. The IGBT 321 is connected by a bonding wire 370 to a bonding part 422 (see FIG. 15) of the control signal pattern 420 provided on the front surface side of the circuit board 400B.

[0072] In the third embodiment, as in the second embodiment, one or both of the substrate bonding materials 410a and 410b are made of an insulating material such as epoxy resin. For example, if the substrate bonding material 410a is made of an insulating material and the substrate bonding material 410b is made of a conductive material, the first substrate pattern 430A becomes an isolated pattern electrically independent from the first conductive plate 341. When a current flows between the first main terminal 311B and the second main terminal 313B, eddy currents flow in the first substrate pattern 430A, reducing inductance. Furthermore, if both the substrate bonding materials 410a and 410b are made of an insulating material, the first and second substrate patterns 430A and 431A become isolated patterns electrically independent from the first and second conductive plates 341 and 342, respectively, and eddy currents flow in the first and second substrate patterns 430A and 431A.

[0073] (Variation 1) 17 and 18 are diagrams illustrating Modification 1. Modification 1 is a modification related to a circuit board. FIG. 17 is a diagram showing the front side of a circuit board 400C, and FIG. 18 is a DD cross-sectional view of FIG. 17. The circuit board 400C shown in FIG. 17 is a modification of the circuit board 400 of the first embodiment described above, and the circuit board 400C can be used in place of the circuit board 400 in the semiconductor device 300 of the first embodiment. The circuit board 400 and the circuit board 400C have different structures of the board bases 403 and 403C, but are otherwise identical in configuration.

[0074] 17, a first opening 401 and a second opening 402 are formed in a substrate circuit 400C, and a second substrate pattern 431, a fourth substrate pattern 433, and control signal patterns 420, 421 are formed on the front surface of a substrate base 403C. Although not shown, a first substrate pattern 430, a third substrate pattern 432, third and fourth control terminal joints 426, 427, and a negative terminal connection pattern 445 are formed on the rear surface of the substrate base 403C, similar to those in the circuit substrate 400 shown in FIG.

[0075] Furthermore, second substrate pattern 431 provided between first opening 401 and second opening 402 is electrically connected to third substrate pattern 432 on the rear surface side by intermediate connection through-hole 460. Fourth substrate pattern 433 provided between first opening 401 and second opening 402 is electrically connected to third substrate pattern 432 on the rear surface side by negative electrode connection through-hole 461. Control signal patterns 420, 421 are electrically connected to third and fourth control terminal joints 426, 427 provided on the rear surface side by through-holes.

[0076] As shown in FIGS. 7 and 13, the board base 403 of the circuit boards 400, 400A, and 400B of the first to third embodiments described above is formed of a single layer of plate material made of an insulating material such as glass epoxy resin, glass polyimide resin, or fluororesin. Meanwhile, as shown in FIG. 18, the board base 403C of Modification 1 includes a first substrate 4030 on the back side, a second substrate 4031 on the front side, and a board middle layer pattern 4032 sandwiched between the first substrate 4030 and the second substrate 4031. The first substrate 4030 and the second substrate 4031 are made of an insulating material such as glass epoxy resin, glass polyimide resin, or fluororesin, just like the board base 403. The board middle layer pattern 4032 is made of a conductive material such as copper foil.

[0077] The substrate middle layer pattern 4032 is provided so as to avoid the areas where the intermediate connection through-hole 460, the negative electrode connection through-hole 461, and the through-holes provided in the control signal patterns 420 and 421 are formed. In other words, the substrate middle layer pattern 4032 is an electrically isolated pattern that is not electrically connected to any of the circuit patterns formed on the front and back surfaces of the substrate base 403C or to any of the conductor plates 341 to 344. Therefore, when a current flows through the current paths U and L, an eddy current flows in the substrate middle layer pattern 4032, thereby reducing inductance.

[0078] 17, the case where the substrate base 403 in the first embodiment is replaced with a substrate base 403C having a substrate middle layer pattern 4032 has been described. However, the present invention is not limited to this, and the configuration of the substrate base 403C described in the first modification may be applied to the substrate bases 403A and 403B in the second and third embodiments.

[0079] (Variation 2) 19 is a diagram illustrating Modification 2. Modification 2 is also a modification related to the circuit board, and can be applied to the above-described first to third embodiments. A circuit board 400D shown in FIG. 19 is a modification of the circuit board 400 of the above-described first embodiment, and the circuit board 400D can be used in place of the circuit board 400 in the semiconductor device 300 of the first embodiment.

[0080] 19 is obtained by removing the regions R1 and R2 indicated by the two-dot chain lines in the circuit board 400 shown in FIG. 4. As a result, a cutout portion 470D is formed in the first opening 401, and a cutout portion 471D is formed in the second opening 402. The first opening 401 communicates with a side region of the circuit board 400D via the cutout portion 470D. Similarly, the second opening 402 communicates with a side region of the circuit board 400D via the cutout portion 471D.

[0081] In the first embodiment described above, when the circuit board 400 (see FIG. 7 ) on which the IGBTs 321U and 321L, the diodes 322U and 322L, the conductor plates 341 to 344, the positive terminal 311, the negative terminal 312, and the signal terminals 314 and 315 are mounted is molded with the resin sealing material 330 as shown in FIG. 2 , the resin sealing material 330 flows into the openings 401 and 402 from the gap region 450 shown in FIG. 4. However, the height dimension of the gap region 450 is the sum of the thickness dimension (z-direction dimension) of the board patterns 430 to 433 and the thickness dimension of the board bonding material 410, and it is difficult to ensure a sufficient flow path cross-sectional area in the gap region 450.

[0082] Therefore, in Modification 2, by cutting out and removing a portion of circuit board 400D, cutout portions 470D, 471D that communicate with side regions of circuit board 400D are formed. The height dimension (z-direction dimension) of the gap region in cutout portions 470D, 471D is the sum of twice the thickness dimension of board patterns 430-433, the thickness dimension of board bonding material 410, and the thickness dimension of board base 403. Therefore, the flow path cross-sectional area in cutout portions 470D, 471D is significantly larger than that in gap region 450, which improves the ease with which resin sealing material 330 flows into openings 401, 402, thereby improving productivity of the resin sealing process.

[0083] According to the first to third embodiments and the first and second modifications of the present invention described above, the following advantageous effects can be achieved.

[0084] (C1) As shown in Figures 13 to 16, etc., semiconductor device 300B includes circuit board 400B having opening 401B, conductive first board pattern 430A provided in the opening periphery region on one of the front and back surfaces of the board, and conductive second board pattern 431A provided in the opening periphery region on the other of the front and back surfaces of the board, first conductor plate 341 arranged to face opening 401B and whose surface facing circuit board 400B is joined to first board pattern 430A by board joining material 410a, and and a second conductor plate (432) arranged so that the surface facing the circuit board (400B) is joined to a second substrate pattern (431A) by a substrate bonding material (410b); and semiconductor elements (321, 322) having electrodes on both the front and back surfaces of the element, one electrode being bonded to the surface facing the opening of the first conductor plate (341) by conductive bonding materials (350, 352) and the other electrode being bonded to the surface facing the opening of the second conductor plate (432) by conductive bonding materials (351, 353), and at least one of the substrate bonding materials (410a, 410b) is made of an insulating bonding material.

[0085] A substrate pattern bonded with an insulating bonding material becomes an electrically independent isolated pattern, and when a current flows in the conductive plate, an eddy current flows in the isolated substrate pattern, thereby suppressing inductance in the semiconductor device. For example, if an insulating bonding material is used for substrate bonding material 410a in Fig. 13 and a conductive bonding material is used for substrate bonding material 410b, first substrate pattern 430A becomes an electrically independent isolated pattern from first conductive plate 341, and when a current flows through current paths U and L in Fig. 1, an eddy current flows in first substrate pattern 430A, thereby suppressing inductance.

[0086] Furthermore, the surfaces of the conductor plates 341 and 342 facing the circuit board 400B are joined to the board patterns 430A and 431A provided in the peripheral region of the opening 401B. Therefore, when the resin insulating material 380 is pressure-bonded to the heat dissipation surfaces 345 and 346 of the conductor plates 341 and 342, the end regions of the conductor plates 341 and 342 (the regions facing the circuit board 400B) can be suppressed or prevented from bending inward in the thickness direction. As a result, sufficient surface pressure is applied to the resin insulating material 380 even in the end regions of the conductor plates 341 and 342, and sufficient insulation performance and heat conduction performance can be obtained.

[0087] (C2) As shown in Figures 1, 3 to 8, etc., semiconductor device 300 includes an IGBT 321U and a diode 322U having electrodes on both the front and back surfaces of the element and constituting upper arm 301, an IGBT 321L and a diode 322L having electrodes on both the front and back surfaces of the element and constituting lower arm 302, a positive terminal 311, a negative terminal 312, and an AC terminal 313 which is an output terminal.Then, a first opening 401, a second opening 402 provided adjacent to the first opening 401, a conductive first substrate pattern 430 provided in the peripheral region of the first opening 401 on one of the front and back surfaces of the substrate (i.e., the substrate surface on the back side), a conductive second substrate pattern 431 provided in the peripheral region of the first opening 401 on the other of the front and back surfaces of the substrate (i.e., the substrate surface on the front side), a conductive third substrate pattern 432 provided in the peripheral region of the second opening 402 on the substrate surface on the back side, a conductive third substrate pattern 433 provided in the peripheral region of the second opening 402 on the substrate surface on the front side, a conductive third substrate pattern 434 provided in the peripheral region of the second opening 402 on the substrate surface on the front side, a conductive third substrate pattern 435 provided in the peripheral region of the second opening 402 on the substrate surface on the front side, a conductive third substrate pattern 436 provided in the peripheral region of the second opening 402 on the substrate surface on the front side, a conductive third substrate pattern 437 provided in the peripheral region of the second opening 402 on the substrate surface on the front side, a conductive third substrate pattern 438 provided in the peripheral region of the second opening 402 on the substrate surface on the front side, a conductive third substrate pattern 439 ... a conductive fourth substrate pattern 433 provided in the peripheral region of the opening 402, and a circuit board 400 having an intermediate connection through hole 460 that electrically connects the second substrate pattern 431 and the third substrate pattern 432 in the region between the first opening 401 and the second opening 402; a first conductor plate 341 that is disposed so as to face the first opening 401 and has a surface that faces the circuit board 400 joined to the first substrate pattern 430 by a conductive substrate joining material 410, and is connected to the positive terminal 311; a second conductor plate 342 which is disposed so as to face the second opening 402 and has a surface facing the circuit board 400 joined to the second board pattern 431 by a conductive board bonding material 410 and is connected to the AC terminal 313; a third conductor plate 343 which is disposed so as to face the second opening 402 and has a surface facing the circuit board 400 joined to the third board pattern 432 by a conductive board bonding material 410 and is connected to the AC terminal 313; and a fourth conductor plate 344 which is disposed so as to face the second opening 402 and has a surface facing the circuit board 400 joined to the fourth board pattern 432 by a conductive board bonding material 410. and a fourth conductor plate 344 bonded to the negative terminal 312 by a conductive substrate bonding material 410, and connected to the negative terminal 312. The IGBT 321U and the diode 322U have electrodes on both the front and back surfaces of the element bonded to the opening-facing surfaces of the first conductor plate 341 and the second conductor plate 342 by conductive bonding materials 350 to 353, respectively, and the IGBT 321L and the diode 322L have electrodes on both the front and back surfaces of the element bonded to the opening-facing surfaces of the third conductor plate 343 and the fourth conductor plate 344 by conductive bonding materials 354 to 357, respectively.

[0088] As described above, semiconductor device 300 is provided with intermediate connection through-hole 460 that electrically connects second substrate pattern 431 and third substrate pattern 432 in the region between first opening 401 and second opening 402. As a result, as shown in Fig. 7, not only first current path 101 corresponding to current paths U and L but also second current path 102, which is a current path shorter than first current path 101, is formed. As a result, inductance can be reduced.

[0089] Furthermore, the surfaces of the conductor plates 341 and 342 facing the circuit board 400 are joined to the board patterns 430 and 431 provided in the peripheral region of the opening 401, and the surfaces of the conductor plates 343 and 344 facing the circuit board 400 are joined to the board patterns 432 and 433 provided in the peripheral region of the opening 402. Therefore, when the resin insulating material 380 is pressure-bonded to the heat dissipation surfaces 345 to 348 of the conductor plates 341 to 344, it is possible to suppress or prevent the end regions of the conductor plates 341 to 344 (the regions facing the circuit board 400) from bending inward in the thickness direction. As a result, sufficient surface pressure is applied to the resin insulating material 380 even in the end regions of the conductor plates 341 to 344, and sufficient insulation performance and heat conduction performance can be obtained.

[0090] 4 to 7, the above-mentioned (C2) further includes negative electrode pattern regions 433b, 433c, a negative electrode connection through-hole 461, and a negative electrode terminal connection pattern 445, which are conductive patterns that electrically connect the negative electrode terminal 312, which is juxtaposed adjacent to the positive electrode terminal 311, to the bonding region 433a of the fourth substrate pattern 433. The negative electrode pattern regions 433b, 433c, the negative electrode connection through-hole 461, and the negative electrode terminal connection pattern 445 are arranged closer to the positive electrode terminal 311 than the connection position between the fourth conductor plate 344 and the negative electrode terminal 312.

[0091] 7 is disposed closer to the positive terminal 311 than the negative terminal connection portion 316 of the fourth conductor plate 344. By forming the third current path 103, which branches off from the second current path 102 and through which current flows closer to the positive terminal 311, it is possible to further reduce inductance.

[0092] (C4) In (C2) above, as shown in FIGS. 3 and 7, the second conductor plate 342 is joined to the AC terminal 313 by a conductive joining material 359. If the current path from the positive terminal 311 to the AC terminal 313 were a current path from the second conductor plate 342 via the first intermediate connection portion 303A, the second intermediate connection portion 303B, and the third conductor plate 343 to the AC terminal 313, i.e., if the current path were only a current path via the pattern of the circuit board 400, heat generation due to electrical resistance would be a problem. However, in the configuration shown in FIGS. 3 and 7, the first intermediate connection portion 303A of the second conductor plate 342 is joined to the second intermediate connection portion 303B of the AC terminal 313. In this way, by providing a current path with lower electrical resistance in addition to the current path via the pattern of the circuit board 400, heat generation can be suppressed.

[0093] (C5) In (C2) above, as shown in FIGS. 4 to 7, the positive terminal 311 connected to the first conductive plate 341 is disposed such that a portion of the positive terminal 311 faces the back surface of the circuit board 400, which is one surface of the circuit board 400, with a gap therebetween. The negative pattern region 433c is disposed on the front surface of the circuit board 400, which is the surface opposite the surface facing the positive terminal. The negative pattern region 433c is disposed so as to be spaced apart from the positive terminal 311 on the positive side in the z direction and to extend widely. Therefore, when a current flows through the positive terminal 311, an eddy current flows in the negative pattern region 433c, thereby reducing inductance. In the example shown in FIG. 4, the negative pattern region 433c is provided contiguous with the fourth board pattern 433, but it may be formed as a pattern separated from the fourth board pattern 433.

[0094] (C6) In the above (C2), as shown in Figures 17 and 18, the semiconductor device 300 further includes an electrically isolated conductive substrate intermediate layer pattern 4032 provided inside the substrate base portion 403C of the circuit substrate 400C. For example, when a current flows through the first conductive plate 341 or the second conductive plate 342, an eddy current flows through the substrate intermediate layer pattern 4032 so as to reduce inductance. As a result, loss due to the influence of inductance can be reduced.

[0095] (C7) In (C2) above, as shown in Figures 2, 4, 5, etc., of a pair of conductive first and second substrate patterns 430, 431 provided in peripheral regions on both the front and back surfaces of the substrate around the same opening (e.g., first opening 401), second substrate pattern 431 is formed so that a plurality of adjacent separated patterns with gap regions 450 interposed therebetween surround the periphery of first opening 401, and first substrate pattern 430 is formed so as to surround the periphery of first opening 401 without any gaps, and circuit substrate 400 is sealed with sealing resin 330. By forming gap regions 450 in second substrate pattern 431, sealing resin 330 can more easily flow into first opening 401, thereby improving productivity of the resin sealing process.

[0096] (C8) In the above (C1) or (C2), as shown in Figures 4 to 9, the semiconductor device 300 further includes a control signal terminal 314 and a control signal pattern 420 formed on the circuit board 400 and electrically connecting the control signal terminal 314 and the control signal electrode 3210 provided on the IGBT 321U, and on the surface of the circuit board 400 on which the control signal pattern 420 is formed, a conductive second substrate pattern 431 consisting of a plurality of separated patterns adjacent to each other with a gap region 450 interposed therebetween is formed so as to surround the periphery of the first opening 401, and the control signal pattern 420 extends from the inner substrate region surrounded by the second substrate pattern 431 through the gap region 450 to the outer substrate region, and the control signal electrode 3210 is connected to the second substrate pattern 431 in the inner substrate region by a bonding wire 370.

[0097] 6 and 9, bonding wire 370 is wired to connect bonding portion 422 provided adjacent to first opening 401 of circuit board 400 to control signal electrode 3210 of IGBT 321U, so that distance L1 required for connection is shorter than distance L1 when circuit board 400 is not used. As a result, it is possible to further reduce the wire height, thereby reducing the height dimension of semiconductor device 300 and achieving miniaturization.

[0098] (C9) In the above (C8), as shown in Figures 4, 5, 9, etc., the front-side substrate bonding material 410 that bonds the conductive second substrate pattern 431 on the surface on which the control signal pattern 420 is formed to the second conductor plate 342 that faces the second substrate pattern 431 is formed thicker than the back-side substrate bonding material 410 that bonds the conductive first substrate pattern 430 on the surface opposite to the surface on which the control signal pattern 420 is formed to the first conductor plate 341 that faces the first substrate pattern 430. Setting the thickness in this way makes it easier to perform bonding so that the wire height h1 is smaller than h2.

[0099] The above-described embodiments and various modifications are merely examples, and the present invention is not limited to these details as long as the features of the invention are not impaired. Furthermore, although various embodiments and modifications have been described above, the present invention is not limited to these details. Other aspects conceivable within the scope of the technical idea of ​​the present invention are also included within the scope of the present invention. [Explanation of symbols]

[0100] 101, 102, 103...current path, 300, 300A, 300B...semiconductor device, 301...upper arm, 302...lower arm, 303...intermediate connection portion, 303A...first intermediate connection portion, 303B...second intermediate connection portion, 311...positive terminal, 311B...first main terminal, 312...negative terminal, 313...AC terminal, 313B...second main terminal, 314, 315...signal terminal, 316...negative terminal connection part, 317... negative terminal connection part, 321, 321L, 321U... IGBT, 322, 322L, 322U... diode, 330... sealing resin, 341 to 344... conductive plate, 350 to 359... bonding material, 370, 371... bonding wire, 380... resin insulating material, 400, 400A, 400B, 400C, 400D... circuit board, 401, 401B, 402... opening, 403 , 403C... substrate base, 410, 410a to 410d... substrate bonding material, 415... control terminal bonding material, 420, 421... control signal pattern, 422, 423... bonding portion, 430, 430A... first substrate pattern, 431, 431A... second substrate pattern, 432, 432A... third substrate pattern, 433, 433A... fourth substrate pattern, 431b... first intermediate connection area, 4 32a...second intermediate connection region, 431a, 433a...bonding region, 433b, 433c...negative electrode pattern region, 445...negative electrode terminal connection pattern, 450, 450A...gap region, 460...intermediate connection through hole, 461...negative electrode connection through hole, 462...control signal connection through hole, 470D, 471D...cutout portion, 3210...control signal electrode, 4032...substrate middle layer pattern

Claims

1. a circuit board having an opening, a first conductive pattern provided in a peripheral region of the opening on one of the front and rear surfaces of the board, and a second conductive pattern provided in a peripheral region of the opening on the other of the front and rear surfaces of the board; a first conductor plate disposed to face the opening, the surface of the first conductor plate facing the circuit board being bonded to the first conductive pattern with a first bonding material; a second conductor plate disposed to face the opening, the surface of the second conductor plate facing the circuit board being bonded to the second conductive pattern by a second bonding material; a semiconductor element having electrodes on both the front and rear surfaces of the element, one of the electrodes being joined to the opening-facing surface of the first conductor plate by a conductive bonding material, and the other of the electrodes being joined to the opening-facing surface of the second conductor plate by a conductive bonding material; At least one of the first and second bonding materials is an insulating bonding material.

2. A semiconductor device comprising: a first semiconductor element having electrodes on both the front and back surfaces of the element and constituting an upper arm; a second semiconductor element having electrodes on both the front and back surfaces of the element and constituting a lower arm; a positive terminal; a negative terminal; and an output terminal; a circuit board having a first opening, a second opening provided adjacent to the first opening, a first conductive pattern provided in a peripheral region of the first opening on one of the front and back surfaces of a substrate, a second conductive pattern provided in a peripheral region of the first opening on the other of the front and back surfaces of the substrate, a third conductive pattern provided in a peripheral region of the second opening on one of the front and back surfaces of the substrate, a fourth conductive pattern provided in a peripheral region of the second opening on the other of the front and back surfaces of the substrate, and a through hole electrically connecting the second conductive pattern and the third conductive pattern in a region between the first opening and the second opening; a first conductor plate that is disposed so as to face the first opening, and whose surface facing the circuit board is joined to the first conductive pattern with a conductive bonding material, and that is connected to the positive electrode terminal; a second conductor plate that is disposed so as to face the first opening, has a surface facing the circuit board joined to the second conductive pattern with a conductive bonding material, and is connected to the output terminal; a third conductor plate that is disposed so as to face the second opening, and whose surface facing the circuit board is joined to the third conductive pattern with a conductive bonding material, and that is connected to the output terminal; a fourth conductor plate that is arranged to face the second opening, has a surface facing the circuit board and is joined to the fourth conductive pattern with a conductive bonding material, and is connected to the negative electrode terminal; the first semiconductor element has electrodes on both the front and back surfaces of the element bonded to the opening-facing surfaces of the first conductor plate and the second conductor plate, respectively, by a conductive bonding material; The second semiconductor element has electrodes on both the front and back surfaces of the element bonded to the opening-facing surfaces of the third and fourth conductor plates, respectively, with a conductive bonding material.

3. 3. The semiconductor device according to claim 2, a fifth conductive pattern electrically connecting the negative electrode terminal, which is juxtaposed adjacent to the positive electrode terminal, to the fourth conductive pattern; the fifth conductive pattern is disposed closer to the positive electrode terminal than to a connection position between the fourth conductor plate and the negative electrode terminal.

4. 3. The semiconductor device according to claim 2, The second conductive plate is joined to the output terminal by a conductive joining material.

5. 3. The semiconductor device according to claim 2, the positive electrode terminal connected to the first conductive plate is disposed so that a portion of the positive electrode terminal faces the one surface of the circuit board via a gap between the positive electrode terminal and the circuit board; The semiconductor device further includes a sixth conductive pattern arranged on a surface of the circuit board opposite to the surface facing the positive electrode terminal.

6. 3. The semiconductor device according to claim 2, The semiconductor device further comprises an electrically isolated seventh conductive pattern provided inside the substrate base of the circuit board.

7. 3. The semiconductor device according to claim 1, one of the pair of conductive patterns provided in peripheral regions on both the front and back surfaces of the substrate around the same opening is formed so that a plurality of separated patterns adjacent to each other with a gap interposed therebetween surround the periphery of the same opening, and the other is formed so that the periphery of the same opening is seamlessly surrounded, The semiconductor device, wherein the circuit board is sealed with a sealing resin.

8. 3. The semiconductor device according to claim 1, a control signal terminal; a control signal pattern formed on the circuit board and electrically connecting the control signal terminal and a control signal electrode provided on the semiconductor element; the conductive pattern, which is made up of a plurality of separated patterns adjacent to each other with gaps therebetween, is formed on a surface of the circuit board on which the control signal pattern is formed so as to surround the periphery of the opening; The control signal pattern extends from an inner substrate region surrounded by the conductive pattern through the gap to an outer substrate region, and the control signal electrode is connected to the conductive pattern in the inner substrate region by a bonding wire.

9. 9. The semiconductor device according to claim 8, a bonding material that bonds the conductive pattern on the surface on which the control signal pattern is formed to a thickness greater than a bonding material that bonds the conductive pattern on the surface opposite to ...

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