Reconfigurable circuit and reconfigurable program

Abstract

To provide a reconfiguration circuit and a reconfiguration program, which reduce the time required for reconfiguration compared with a case where a processing circuit for performing predetermined processing and a storage unit for storing parameters of the processing circuit are reconfigured in one reconfiguration area.SOLUTION: A reconfiguration circuit is provided, comprising a storage unit located in a static area and configured to store parameters of a processing circuit for performing predetermined processing, and a reconfiguration area that can be reconfigured as a parameter access circuit for accessing the processing circuit and the storage unit.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a reconfiguration circuit and a reconfiguration program. [Background technology]

[0002] Patent Document 1 discloses a reconfigurable device capable of partial reconfiguration, which has a reconfiguration reservation means configured with software that sets reconfiguration reservation information for a data processing circuit that executes data processing in a predetermined reservation setting area according to a job that requires data processing, a register reservation means configured with software that sets a register setting value to be set in the data processing circuit in the reservation setting area, a reconfiguration means configured with hardware that reconfigures the data processing circuit and a setting information storage area based on the reconfiguration reservation information set by the reconfiguration reservation means, and a register setting means configured with hardware that sets the register setting value set in the reservation setting area in the setting information storage area.

[0003] Patent Document 2 discloses a management device that includes a parameter management unit that saves, in a memory unit, a first parameter used in a first process performed by a first circuit module implemented in a first area of ​​a reconfigurable electronic device resource before the first circuit module is deleted from the resource, and a parameter adjustment unit that adjusts the first parameter saved in the memory unit and obtains a second parameter when a second circuit module associated with the first process is implemented in a second area of ​​the resource to resume the first process, and the parameter management unit sets the second parameter to the second circuit module implemented in the second area to resume the first process. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-165803 [Patent Document 2] Patent No. 6824806 Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention aims to provide a reconfigurable circuit and a reconfiguration program that can shorten the time required for reconfiguration compared to when a processing circuit that executes predetermined processing and a memory unit that stores parameters of the processing circuit are reconfigured into a single reconfiguration area. [Means for solving the problem]

[0006] The reconfigurable circuit according to the first aspect includes a memory unit arranged in a static area for storing parameters of a processing circuit that executes predetermined processing, and a reconfigurable area that can be reconfigured as a parameter access circuit for accessing the processing circuit and the memory unit.

[0007] A reconfiguration circuit according to a second aspect is the reconfiguration circuit according to the first aspect, wherein the reconfiguration region includes a plurality of partial reconfiguration regions.

[0008] A reconfiguration circuit according to a third aspect is the reconfiguration circuit according to the second aspect, wherein the plurality of partial reconfiguration regions include a first reconfiguration region that can be reconfigured as the processing circuit and a second reconfiguration region that can be reconfigured as the parameter access circuit.

[0009] A reconfigurable circuit according to a fourth aspect is a reconfigurable circuit according to any one of the first to third aspects, and further comprises a processor, wherein the processor executes in parallel a process of setting parameters in the memory unit and a process of reconfiguring a circuit in the reconfiguration area.

[0010] A reconfiguration circuit according to a fifth aspect is the reconfiguration circuit according to any one of the first to fourth aspects, wherein the storage unit is arranged adjacent to the parameter access circuit.

[0011] A reconfiguration program according to a sixth aspect causes a computer to execute, in parallel, a process of setting parameters in a memory unit that stores parameters of a processing circuit that is placed in a static area and that executes predetermined processing, and a process of reconfiguring a circuit in a reconfiguration area that can be reconfigured as a parameter access circuit for accessing the processing circuit and the memory unit. [Effects of the Invention]

[0012] According to the first aspect, the time required for reconstruction can be shortened compared to when a processing circuit that executes predetermined processing and a storage unit that stores parameters of the processing circuit are reconstructed into one reconstruction area.

[0013] According to the second aspect, a plurality of circuits can be reconfigured individually.

[0014] According to the third aspect, when processing circuits with common parameters are reconfigured in the first partial reconfiguration region, there is no need to reconfigure the parameter access circuit.

[0015] According to the fourth and sixth aspects, the time required for reconfiguration can be reduced compared to when the process of setting parameters in the storage unit and the process of reconfiguring the circuit in the reconfiguration area are performed sequentially.

[0016] According to the fifth aspect, the time required for parameter setting processing can be reduced compared to when the storage unit is located in a position not adjacent to the parameter access circuit. [Brief explanation of the drawings]

[0017] [Figure 1] FIG. 2 is a block diagram showing the configuration of a reconfiguration circuit according to the present embodiment. [Figure 2] FIG. 1 is a diagram showing the arrangement of a static area and a reconfigurable area of ​​a reconfigurable circuit. [Figure 3]FIG. 1 is a block diagram showing a configuration of a conventional reconfiguration circuit. [Figure 4] FIG. 2 is a block diagram showing the hardware configuration of a control unit. [Figure 5] 10 is a flowchart illustrating an example of the flow of a reconstruction process. DETAILED DESCRIPTION OF THE INVENTION

[0018] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0019] 1 shows the configuration of a reconfigurable circuit 10 according to this embodiment. The reconfigurable circuit 10 includes a static area 12, a reconfigurable area 14, and a control unit 16.

[0020] The reconfigurable circuit 10 is configured by an integrated circuit capable of reconfiguring circuits, such as an FPGA (Field Programmable Gate Array). In this embodiment, a case will be described in which the reconfigurable circuit 10 is provided in an image forming apparatus having various functions related to image formation, such as a copy function, a scan function, a print function, and a facsimile transmission / reception function.

[0021] The static area 12 is an area that cannot be reconfigured to another circuit while the image forming apparatus is operating, i.e., while the power of the reconfiguration circuit 10 is on, and a general-purpose circuit that executes the same processing even if the circuit to be reconfigured is switched to the reconfiguration area 14 is provided.

[0022] In this embodiment, the static area 12 is provided with, for example, a memory unit 18, a decoupling unit 20, an image processing module 22, a PCI interface module 24, an image output module 26, and a general-purpose protocol control unit 28, each of which is connected via an internal bus 30.

[0023] The storage unit 18 is configured in the static area 12 and stores parameters of a processing circuit that executes predetermined processing. Specifically, the storage unit 18 includes a register 18A and a look-up table (LUT) 18B. Depending on the type of processing circuit, the storage unit 18 may be configured to include either the register 18A or the LUT 18B.

[0024] The register 18A stores parameters that are commonly used among parameters used by processing circuits of different types of processing, such as the number of pixels and image size of image data to be processed.

[0025] The LUT 18B stores process-specific parameters among parameters used by processing circuits for different types of processing, for example, if the processing executed by the processing circuit is color conversion processing, a lookup table for color conversion is stored.

[0026] The decoupling unit 20 is a circuit that absorbs noise components and the like generated by the operation of the processing circuits reconfigured in the reconfiguration area 14, and decouples the reconfiguration area 14 and the static area 12 so as not to affect the operation of the circuits provided in the static area 12.

[0027] The image processing module 22 is a circuit that executes predetermined general-purpose image processing on image data to be processed. The image processing module 22 also includes a register 22A and a lookup table (LUT) 22B. The register 22A and the lookup table 22B store various parameters used in the image processing executed by the image processing module 22.

[0028] The PCI interface module 24 is a circuit that executes processing related to data communication with a higher-level device via a PCI interface. The PCI interface module 24 also includes a register 24A and a lookup table (LUT) 24B. The register 24A and the lookup table 24B store various parameters used in the data communication processing executed by the PCI interface module 24.

[0029] The image output module 26 is a circuit that executes image output processing to output image data processed by the image processing module 22 and the processing circuit reconfigured in the reconstruction circuit 10 to a higher-level device. The image output module 26 also includes a register 26A. The register 26A stores various parameters used in the image processing executed by the image processing module 22.

[0030] The general-purpose protocol control unit 28 controls each circuit connected via the internal bus 30 in accordance with instructions from the control unit 16 .

[0031] The reconstruction area 14 includes a first partial reconstruction area 14-1 that can be reconfigured as an image processing circuit 32, which is an example of a processing circuit that executes predetermined processing, and a second partial reconstruction area 14-2 that can be reconfigured as a parameter access circuit 34 for accessing the storage unit 18. Note that when there is no need to distinguish between the first partial reconstruction area 14-1 and the second partial reconstruction area 14-2, they will be referred to as the partial reconstruction area 14.

[0032] In this embodiment, a case will be described in which the reconstruction area 14 includes two partial reconstruction areas 14, but this is not limiting. The image processing circuit 32 and the parameter access circuit 34 may be reconstructed in one reconstruction area without providing multiple partial reconstruction areas 14. Also, the reconstruction area 14 may be configured to include three or more partial reconstruction areas 14. Furthermore, the processing circuit reconstructed in the reconstruction area 14-1 is not limited to an image processing circuit.

[0033] The control unit 16 reconfigures the circuits in the reconfiguration area 14 based on the circuit configuration information acquired from the higher-level device. Specifically, the control unit 16 reconfigures the image processing circuit 32 in the first partial reconfiguration area 14-1 based on the circuit configuration information of the image processing circuit 32. The control unit 16 also reconfigures the parameter access circuit 34 in the second partial reconfiguration area 14-2 based on the circuit configuration information of the parameter access circuit 34.

[0034] Here, the circuit configuration information is information including connection information relating to the connections of a plurality of logic blocks included in the partial reconfiguration area 14 and parameter information relating to the settings of the circuit to be reconfigured in the partial reconfiguration area 14.

[0035] The time required to reconfigure the partial reconfiguration region 14 is the reconfiguration time required to reconfigure the circuit by connecting logic blocks based on the connection information in the circuit configuration information. However, for the partial reconfiguration region 14 to operate correctly, various settings of the reconfigured circuit are required based on the parameter information. Furthermore, the time required to reconfigure the partial reconfiguration region 14 is approximately proportional to the circuit size. Here, the circuit size is determined, for example, by the number of resource circuits included in the partial reconfiguration region 14. Furthermore, a resource circuit is a circuit that realizes basic functions required to realize the processing function of the circuit to be reconfigured. Examples of resource circuits include, but are not limited to, logic circuits and signal processing circuits (Digital Signal Processors: DSPs).

[0036] The circuit scale of the first partial reconfiguration area 14-1 is set to the size of the largest processing circuit among the processing circuits to be reconfigured in the first partial reconfiguration area 14-1.

[0037] Specifically, it is assumed that the image processing circuits to be reconfigured in the first partial reconfiguration area 14-1 are image processing circuits A, B, and C that perform different image processing. In this case, the image processing circuits A to C require different types and numbers of resource circuits, so the first partial reconfiguration area 14-1 includes the maximum number of resource circuits for each type included in the image processing circuits A to C that may be reconfigured in the first partial reconfiguration area 14-1.

[0038] The parameter access circuit 34 reads out from the register 18A and the LUT 18B parameters used when the image processing circuit 32 reconfigured in the first reconfiguration area executes image processing, and outputs the parameters to the image processing circuit 32.

[0039] For example, when the image processing circuits reconfigured in the first partial reconstruction area 14-1 are image processing circuits A, B, and C that perform different image processing, the parameter access circuit 34 is preferably a circuit that performs processing common to the image processing circuits A to C. In this case, if the image processing circuit A is reconfigured in the first partial reconstruction area 14-1 and the parameter access circuit 34 is reconfigured in the second partial reconstruction area 14-2, when the image processing circuit B is reconfigured in the first partial reconstruction area 14-1, it is not necessary to reconfigure the parameter access circuit 34 in the second partial reconstruction area 14-2, and it is sufficient to reconfigure only the first partial reconstruction area 14-1. This reduces the time required for reconstruction.

[0040] 1, the storage unit 18, that is, the register 18A and the LUT 18B, are arranged in the static area 12. The storage unit 18 is also arranged adjacent to the parameter access circuit .

[0041] 2 shows a specific arrangement of the static area 12 and the reconfiguration area 14. As shown in Fig. 2, the reconfiguration circuit 10 includes the static area 12 and the reconfiguration area 14 including a first partial reconfiguration area 14-1 and a second partial reconfiguration area 14-2. The static area 12 is an area other than the reconfiguration area 14.

[0042] The LUT 18B is placed in a static area 12A of the static area 12 that is adjacent to the reconfiguration area 14-2 where the parameter access circuit 34 is reconfigured. The register 18A is placed in an area of ​​the static area 12 other than the static area 12A where the LUT 18B is placed, for example, in an area where wiring does not get in the way.

[0043] Generally, FPGAs are divided into resource circuits such as memory, logic circuits, and DSPs, and their mounting locations and capacities are determined by the device. Furthermore, incorporating a storage unit 18 into the reconfiguration area 14 tends to worsen resource utilization and wiring efficiency.

[0044] Conventionally, as shown in Figure 3, an image processing circuit 32 including a register 18A and an LUT 18B was reconfigured in the reconfiguration area 14. For this reason, the configuration of Figure 3 tends to deteriorate the utilization rate of the resource circuit and the wiring efficiency, making it difficult to shorten the time required for reconfiguration. In contrast, as shown in Figures 1 and 2, in the reconfiguration circuit 10, the register 18A and the LUT 18B are arranged in the static area 12, and the LUT 18B is arranged adjacent to the parameter access circuit 34, so the time required for reconfiguration is shortened compared to the configuration of Figure 3.

[0045] Fig. 4 is a block diagram showing the hardware configuration of the control unit 16. As shown in Fig. 4, the control unit 16 includes a computer 17. The computer 17 includes a CPU (Central Processing Unit) 17A, a ROM (Read Only Memory) 17B, a RAM (Random Access Memory) 17C, and an input / output interface (I / O) 17D. The CPU 17A, the ROM 17B, the RAM 17C, and the I / O 17D are connected to each other via a system bus 17E. The system bus 17E includes a control bus, an address bus, and a data bus. The CPU 17A is an example of a processor.

[0046] Furthermore, a communication unit 19 and a storage unit 21 are connected to the I / O 17D.

[0047] The communication unit 19 is an interface for performing data communication with a higher-level device that outputs circuit configuration information.

[0048] The storage unit 21 is configured by a nonvolatile memory and stores a reconstruction program 21A, which will be described later. The CPU 17A loads the reconstruction program 21A stored in the storage unit 21 into the RAM 17C and executes it.

[0049] Next, the reconstruction process executed by the CPU 17A of the control unit 16 will be described with reference to Fig. 5. The reconstruction process shown in Fig. 5 is performed by the CPU 17A executing the reconstruction program 21A.

[0050] In step S100, CPU 11A determines whether circuit configuration information has been received from the host device. If circuit configuration information has been received from the host device, the process proceeds to steps S102 and S104. On the other hand, if circuit configuration information has not been received from the host device, the process waits until circuit configuration information is received.

[0051] The processes of steps S102 and S104 are executed in parallel. In step S102, the CPU 17A reconfigures circuits in the reconfiguration area 14 based on the connection information in the received circuit configuration information. For example, if the received circuit configuration information is circuit configuration information related to the image processing circuit 32 and the parameter access circuit 34, the image processing circuit 32 is reconfigured in the first partial reconfiguration area 14-1, and the parameter access circuit 34 is reconfigured in the second partial reconfiguration area 14-2. If the received circuit configuration information is circuit configuration information related to the image processing circuit 32, the image processing circuit 32 is reconfigured in the first partial reconfiguration area 14-1. If the received circuit configuration information is circuit configuration information related to the parameter access circuit 34, the parameter access circuit 34 is reconfigured in the second partial reconfiguration area 14-2. In this way, when the received circuit configuration information is the circuit configuration information of either the image processing circuit 32 or the parameter access circuit 34, it is necessary to reconstruct only one of the first partial reconstructed area 14-1 and the second partial reconstructed area 14-2, thereby reducing the time required for reconstruction.

[0052] In step S104, the CPU 17A sets parameters in the register 18A and the LUT 18B based on the parameter information in the received circuit configuration information.

[0053] 3, the register 18A and the LUT 18B are provided in the image processing circuit 32 reconfigured in the reconstruction area 14, and therefore it is necessary to set parameters in the register 18A and the LUT 18B after reconfiguring the image processing circuit 32. In contrast, in this embodiment, the circuit reconstruction process for the reconstruction area 14 and the parameter setting process for the storage unit 18 are executed in parallel, thereby reducing the time required for the reconstruction.

[0054] In this embodiment, the reconstruction program is installed in the storage unit 21, but the present invention is not limited to this. The reconstruction program 21A according to this embodiment may be provided in a form recorded on a computer-readable storage medium. For example, the reconstruction program according to this embodiment may be provided in a form recorded on an optical disc such as a CD (Compact Disc)-ROM or a DVD (Digital Versatile Disc)-ROM, or in a form recorded on a semiconductor memory such as a USB (Universal Serial Bus) memory or a memory card. The reconstruction program according to this embodiment may also be obtained from an external device via a communication line.

[0055] In the above embodiment, the term "processor" refers to a processor in a broad sense, and includes general-purpose processors (e.g., CPU: Central Processing Unit, etc.) and dedicated processors (e.g., GPU: Graphics Processing Unit, ASIC: Application Specific Integrated Circuit, FPGA: Field Programmable Gate Array, programmable logic device, etc.).

[0056] Furthermore, the operations of the processors in the above embodiments may not only be performed by a single processor, but may also be performed by multiple processors located at physically separate locations working together. Furthermore, the order of the operations of the processors is not limited to the order described in the above embodiments, and may be changed as appropriate. [Explanation of symbols]

[0057] 10 Reconfigurable circuit 12 Static Area 12A Static Area 14 Reconstruction area 14-1 First partial reconstruction area 14-2 Second partial reconstruction area 16 Control Unit 17 Computer 18 Memory section 18A Resistor 18B LUT 19 Communications Department 20 Decoupling section 21 Memory section 21A Reconstruction Program 22 Image Processing Module 24 PCI interface module 26 Image Output Module 28 General-purpose protocol control section 30 Internal Bus 32 Image processing circuit 34 Parameter Access Circuit

Claims

1. a storage unit arranged in the static area and storing parameters of a processing circuit that executes predetermined processing; a reconfigurable area that is a parameter access circuit for accessing a processing circuit and the storage unit and that can be reconfigured as a circuit that executes common processing for a plurality of processing circuits; A reconfiguration circuit comprising:

2. The reconstruction region includes a plurality of partial reconstruction regions. The reconfiguration circuit of claim 1 .

3. The plurality of partial reconfiguration regions include a first partial reconfiguration region that can be reconfigured as the processing circuit and a second partial reconfiguration region that can be reconfigured as the parameter access circuit. The reconfiguration circuit according to claim 2.

4. a processor; The processor: A process of setting parameters in the storage unit and a process of reconfiguring a circuit in the reconfiguration area are executed in parallel. The reconfigurable circuit according to any one of claims 1 to 3.

5. The storage unit is disposed adjacent to the parameter access circuit. The reconfigurable circuit according to any one of claims 1 to 4.

6. On the computer, The processing unit is arranged in a static area, and executes in parallel a process of setting parameters in a storage unit that stores parameters of a processing circuit that executes a predetermined process, and a process of reconfiguring a circuit in a reconfigurable area, which is a parameter access circuit for accessing the processing circuit and the storage unit and can be reconfigured as a circuit that executes a common process for a plurality of processing circuits. A reconstruction program that executes the process.

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