wiring board

Abstract

To provide a technique capable of reducing the parasitic inductance and parasitic resistance for a component constituting a high frequency circuit formed on a glass board.SOLUTION: A component (capacitor 90) constituting a high frequency circuit provided on a first surface (11) of a glass board (10) and a bottom part (21) on the first surface of a through hole (20) provided on the glass board have a superimposed portion on the first surface. Due to formation of the capacitor 90 right above a via being the through hole, conductive wiring from the via to the capacitor becomes unnecessary. By forming the capacitor on the glass board having the high flatness before the through hole is formed and then forming the through hole, the capacitor can be stably manufactured.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a wiring board. [Background technology]

[0002] 2. Description of the Related Art In recent years, electronic devices have become more sophisticated and smaller in size, and accordingly, wiring boards mounted on the electronic devices are also required to have higher functionality and higher density.

[0003] For example, Patent Document 1 discloses that in order to increase the withstand voltage of a thin film capacitor formed on a glass substrate, "a high-frequency component comprises a substrate including glass, having a first surface located on a first side and a second surface located on a second side opposite the first side, and a capacitor located on the first surface of the substrate. The capacitor has a first-surface first conductive layer located on the first surface of the substrate, a first-surface first insulating layer located on the first-surface first conductive layer, and a first-surface second conductive layer 1 located on the first-surface first insulating layer. The first-surface first insulating layer contains an inorganic material having a breakdown field of 6 MV / cm or more." [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2018-74134 Summary of the Invention [Problem to be solved by the invention]

[0005] Generally, high-frequency circuits formed on a glass substrate are often formed using a portion of a conductor layer connected to a through-hole provided in the glass substrate. Therefore, components forming the high-frequency circuits formed on the glass substrate may have unintended parasitic inductance and parasitic resistance. These parasitic components may degrade the filter characteristics of the resonant circuit. However, Patent Document 1 does not consider such a point.

[0006] Therefore, an object of the present invention is to provide a technique capable of reducing the parasitic inductance and parasitic resistance of components constituting a high-frequency circuit formed on a glass substrate. [Means for solving the problem]

[0007] In order to solve the above problems, one representative wiring board of the present invention is: A wiring board having a glass substrate having a through hole and components that constitute a high-frequency circuit on a first surface of the glass substrate, The bottom of the through hole on the first surface and a component that constitutes the high-frequency circuit have an overlapping portion on the first surface. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a technique capable of reducing the parasitic inductance and parasitic resistance of components constituting a high frequency circuit formed on a glass substrate. Problems, configurations, and effects other than those described above will become apparent from the following description of the preferred embodiments. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a schematic diagram of a cross-sectional structure of a conventional wiring board. [Figure 2] FIG. 2 is a schematic diagram of a cross-sectional structure of a main part of the first embodiment. [Figure 3] FIG. 3 is a schematic diagram of a cross-sectional structure of the wiring board of the first embodiment. [Figure 4] Fig. 4 is a schematic diagram of the cross-sectional structure of the main part of the second embodiment. [Figure 5A] FIG. 5A is a cross-sectional view schematically showing the shape of a capacitor at room temperature. [Figure 5B] FIG. 5B is a cross-sectional view schematically showing deformation of a capacitor at low temperatures. [Figure 5C]FIG. 5C is a cross-sectional view schematically showing deformation of a capacitor at high temperatures. [Figure 6] FIG. 6 is a cross-sectional view showing a schematic diagram of the deformation of a capacitor at high temperatures. [Figure 7] FIG. 7 is a schematic diagram of a cross-sectional structure of a wiring board according to the third embodiment. [Figure 8] FIG. 8 is a diagram illustrating a method for manufacturing a wiring board. [Figure 9] FIG. 9 is a schematic diagram of a cross-sectional structure of a wiring board according to the present disclosure. [Figure 10] FIG. 10 is a schematic diagram of a cross-sectional structure of a wiring board of a comparative example. [Figure 11] FIG. 11 is a diagram of a resonant circuit used to verify the effect. [Figure 12] FIG. 12 is a diagram showing frequency characteristics of an example of the present disclosure and a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Note that the present invention is not limited to this embodiment. In addition, in the description of the drawings, the same parts are designated by the same reference numerals. When there are multiple components with the same or similar functions, they may be described using the same reference numeral with different subscripts. When there is no need to distinguish between these multiple components, the subscripts may be omitted. In order to facilitate understanding of the invention, the position, size, shape, range, etc. of each component shown in the drawings may not represent the actual position, size, shape, range, etc. Therefore, the present invention is not necessarily limited to the position, size, shape, range, etc. disclosed in the drawings.

[0011] In the present disclosure, the term "glass substrate" is also referred to as a glass core substrate, and includes a glass substrate coated with a metal layer, a dielectric layer, an insulating layer, or the like. Furthermore, the glass substrate typically has optical transparency, and the components and their blending ratios of the glass material constituting the glass substrate are not particularly limited. For example, glass containing silicate as a main component, such as alkali-free glass, alkali glass, borosilicate glass, quartz glass, sapphire glass, and photosensitive glass, can be used as the glass substrate. From the viewpoint of use in semiconductor packages and semiconductor modules, it is desirable to use alkali-free glass as the glass substrate 10. The content of alkali components contained in the alkali-free glass is preferably 0.1 mass % or less. The thickness of the glass substrate is preferably 1 mm or less, and more preferably 0.1 mm to 0.8 mm in consideration of ease of handling during production.

[0012] In this disclosure, "components constituting a high frequency circuit" refers to components constituting an electronic circuit intended for use with high frequency signals of 0.1 GHz or higher, and includes capacitors, inductors, and the like.

[0013] In the present disclosure, "having an overlapping portion on a surface" means that there is an overlapping portion in a plan view when the surface is viewed from the normal direction of the surface. This includes cases where one region is entirely contained within the other region, and cases where they completely overlap.

[0014] In the present disclosure, a "through hole" generally refers to a hole that extends from a first surface of a glass substrate to a second surface opposite the first surface, and does not necessarily need to extend completely from the first surface to the second surface of the glass substrate. Furthermore, after the through hole is formed, the interior of the hole may be filled with a conductive material, or a conductive layer may be formed on the inner wall of the hole and an insulating material such as resin may be filled in the center of the hole. The cross-sectional shape of the through hole formed in the glass substrate may be rectangular, X-shaped (i.e., a shape in which the diameter at one end of the through hole is smaller than the diameter at the other end), tapered (i.e., a shape in which the diameter at one end of the through hole is smaller than the diameter at the other end), O-shaped (i.e., a shape in which the diameter at the center is larger than the diameter at one end of the through hole), or other shape. The shape of the opening of the through hole on the first surface or the second surface of the glass substrate may be circular, elliptical, or polygonal.

[0015] Furthermore, the "bottom" of the through-hole means the surface where the through-hole or the conductive film or insulating film in contact with the through-hole comes into contact with the first surface or the second surface of the glass substrate. Furthermore, when the cross section of the through hole is tapered, the end with a smaller diameter may be referred to as the "bottom" and the end with a larger diameter may be referred to as the "top."

[0016] <Prior art> Next, the configuration of a conventional wiring board will be described with reference to Fig. 1. Fig. 1 is a schematic diagram of the cross-sectional structure of a conventional wiring board. In Fig. 1, a through hole 20 is formed in a glass substrate 10, a conductive layer 40 is formed on the side wall of the through hole, and the center of the through hole 20 is filled with an insulating resin. In addition, a bottom 21 of the through hole is connected to a conductive layer 91 formed on the surface of the glass substrate on the square side in the Z axis direction. The conductive layer 91, together with an insulator 92 and a conductor 93 formed above it, forms a MIM (Metal-Insulator-Metal) capacitor 90. This capacitor 90 constitutes part of an LC filter and is a part of a component that constitutes a high-frequency circuit. The conductor 93 is connected to the wiring of a wiring board. On the other hand, the conductive layer 40 on the side wall is connected to an internal wiring layer 41 formed on the surface on the negative side of the Z axis of the glass substrate, and the internal wiring layer 41 is connected to a via portion 50 which is part of a wiring layer formed as a build-up layer on the glass substrate. The via portion 50 is then connected to a pad portion 51 formed on the outermost shell of the wiring layer, and a solder ball 60 is placed on the pad portion 51.

[0017] 1, when the surface of the wiring board is viewed from above the z-axis, there is no planar overlap between bottom 21 of through hole 20 and the capacitor 90, which is a component constituting the high-frequency circuit. The center of the through hole is spaced a distance L from the center of capacitor 90. As a result, the presence of the conductive layer 91 at the distance L causes unintended parasitic inductance and parasitic resistance to occur in the capacitor 90.

[0018] First Embodiment Next, the configuration of the capacitor and through hole, which are essential parts of the wiring board according to the first embodiment of the present disclosure, will be described with reference to Fig. 2. Fig. 2 is a schematic diagram of the cross-sectional structure of the wiring board according to the first embodiment. In Fig. 2, a through hole 20 is formed in a glass substrate 10, and a conductive layer 40 is formed on the side wall of the through hole. In the first embodiment, an MIM capacitor 90 consisting of a conductive layer 91 and an insulator 92 and a conductor 93 formed thereon is formed in the positive direction of the z-axis of the through hole 20. In other words, the capacitor 90, which is a component constituting a high-frequency circuit provided on the first surface of the glass substrate 10, and the bottom 21 of the through hole provided in the glass substrate on the first surface have an overlapping portion on the first surface.

[0019] This shortens the wiring distance from the bottom of the through hole to the capacitor 90, which is required in the conventional example, and suppresses the occurrence of parasitic inductance and parasitic resistance, thereby improving the performance of the high frequency circuit. Furthermore, an area for forming wiring from the bottom of the through-hole to the capacitor 90 is not required on the first surface of the glass substrate, and high density wiring boards can be achieved. 2, the center of through-hole 20 on the first surface of the glass substrate and the center of capacitor 90 are approximately aligned, but these do not necessarily have to be the same. By forming bottom 21 of through-hole 20 and conductive layer 91 of capacitor 90 to overlap, it is possible to sufficiently reduce the parasitic inductance and parasitic resistance of components that make up a high-frequency circuit compared to conventional examples.

[0020] 2, the through hole 20 has the conductive layer 40 formed only on its side wall and is described as a conformal via. However, the through hole 20 does not necessarily have to be a conformal via, and the entire through hole 20 may be filled with a conductor to form a filled via.

[0021] Next, an example in which the capacitor and through hole according to the first embodiment are applied to a wiring board will be described with reference to Fig. 3. In the following description, components that are the same as or equivalent to those in the first embodiment described above will be given the same reference numerals, and their description will be simplified or omitted. 3, a conductive layer 40 is formed on the sidewall of through-hole 20, and an insulating material such as resin is filled in the center. In this case, the coefficient of thermal expansion (CTE) of the material filled in through-hole 20 is preferably 40 ppm / K or less, more preferably 30 ppm / K or less, and even more preferably 20 ppm / K or less. By adopting such a configuration, it becomes possible to suppress changes in the capacitance of the capacitor due to temperature changes in the wiring board, as will be described later.

[0022] 3, similarly to the conventional example, the conductor 93 constituting the capacitor is connected to the external wiring 42 through a via portion 50 formed by opening the insulating layer 30. The conductive layer 40 formed on the side wall of the through hole 20 is also connected to the external wiring 42 formed on the wiring board through the internal wiring layer 41, the via portion 50, etc. Except for the positional relationship between the capacitor 90 and the through-hole 20, the configuration and manufacturing method of the wiring board described above are not limited to the above configuration, and can be modified as appropriate.

[0023] Second Embodiment Next, the configuration of the capacitor and the through hole, which are the main parts of the wiring board according to the second embodiment of the present disclosure, will be described with reference to Fig. 4. Fig. 4 is a schematic diagram of the cross-sectional structure of the wiring board according to the second embodiment. In the following description, components that are the same as or equivalent to those in the first embodiment described above will be assigned the same reference numerals, and their description will be simplified or omitted. The second embodiment differs from the first embodiment in that the diameter of through hole 20 is tapered, narrowing in the z-axis direction. That is, in the second embodiment, the diameter φ1 of bottom 21 of through hole 20 that overlaps capacitor 90 is smaller than the diameter φ2 of second surface 12 on the opposite side of the glass substrate. In this way, by configuring capacitor 90 on the smaller-diameter side of through hole 20, it is possible to suppress changes in the capacitance of the capacitor due to temperature changes in the wiring substrate.

[0024] Next, referring to Figures 5A, 5B, 5C, and 6, we will explain how by configuring capacitor 90 on the smaller diameter side (bottom) of through hole 20, changes in the capacitance of the capacitor can be suppressed in response to temperature changes in the wiring board.

[0025] 5A, 5B, and 5C are cross-sectional views each showing a schematic diagram of deformation of a capacitor 90 due to temperature changes when the capacitor 90 is arranged on the larger diameter side (top) of through-hole 20. FIG. In the case where a component constituting a high-frequency circuit provided on first surface 11 of glass substrate overlaps with the bottom of through-hole 20 provided in the glass substrate on first surface 11, deformation of through-hole 20 due to temperature change leads to deformation of capacitor 90. As a result, the capacitance of the capacitor may be affected. FIG. 5A shows the shapes of through-hole 20 and capacitor 90 at room temperature, and no deformation is observed in capacitor 90.

[0026] However, the thermal expansion coefficients and elastic moduli of the materials of the glass substrate 10, the internal wiring layer 41, and the conductive layer 91, or the insulating layer, are significantly different. For example, the coefficient of thermal expansion (CTE) of glass is approximately 3 to 10 ppm / K and the elastic modulus is 60 GPa to 100 GPa, but in the case of copper used for the wiring layer and the conductive layer, the CTE is approximately 16 ppm / K and the elastic modulus is 80 GPa, and the thermal expansion coefficient of the insulating resin layer is 10 to 60 ppm / K and the elastic modulus is approximately 1 to 20 GPa.

[0027] In other words, glass is less likely to deform due to temperature changes, and because its thermal expansion coefficient is smaller than that of other materials, when a temperature change occurs, differences in the thermal expansion coefficient and contraction rate occur between glass and other nearby materials, and this tends to manifest as structural deformation. Therefore, when a component constituting a high-frequency circuit provided on first surface 11 of glass substrate and bottom 21 of through hole 20 provided in the glass substrate overlap on first surface 11, deformation may occur in capacitor 90, which is a component constituting the high-frequency circuit. The magnitude of this deformation also varies depending on the substance filled in through hole 20.

[0028] Fig. 5B shows a schematic diagram of the structure of the wiring board when it shrinks at a low temperature, and Fig. 5C shows a schematic diagram of the structure of the wiring board when it expands at a high temperature. For this reason, it is desirable that the substance filled into the through hole 20 is a material with a thermal expansion coefficient close to that of the glass substrate, and the coefficient of thermal expansion (CTE) is preferably 40 ppm / K or less, more preferably 30 ppm / K or less, and particularly preferably 20 ppm / K or less. If it is 40 ppm / K or less, the capacitance fluctuation can be suppressed to a level that can withstand general use. If it is 30 ppm / K or less, it can be used in applications that require control of capacitance fluctuation. If it is 20 ppm / K or less, it can be used in applications where capacitance fluctuation is even more stringent.

[0029] Examples of materials that meet these requirements include: (Example of material) 40 ppm or less ABF-GX92 (Ajinomoto Fine-Techno) 30 ppm or less NX04 series (Sekisui Chemical) ABF-GXT31 (Ajinomoto Fine-Techno) 20 ppm or less ABF-GL102, 103 (Ajinomoto Fine-Techno) GX-E4 (Ajinomoto Fine Techno) The CTE was measured by TMA (tensile) at 25℃-150℃.

[0030] Next, a comparison of the deformation of capacitors due to temperature changes when capacitor 90 is configured on the smaller diameter side (bottom) of through-hole 20 will be described with reference to FIG. 5A, 5B, and 5C show the temperature change when capacitor 90 is configured on the larger diameter side (top) of through-hole 20, while FIG. 6 shows the deformation at high temperatures when capacitor 90 is configured on the smaller diameter side (bottom) of through-hole 20. In other words, Figures 5C and 6 show the difference in the amount of deformation at high temperatures when capacitor 90 is formed in the larger diameter (Top) of the through-hole (Figure 5C) and when capacitor 90 is formed in the smaller diameter (Bottom) of the through-hole (Figure 6).

[0031] As is clear from these results, the structure in which the capacitor is formed on the small surface (bottom) of the through hole 20 (Figure 6) can better suppress deformation of the capacitor due to temperature changes, and can further suppress fluctuations in the capacitance of the capacitor. For example, under high temperature conditions, when the material expands, the CTE of glass is 3 ppm, that of Cu is 16 ppm, and that of resin is about 20 ppm, so the material inside the through hole 20 expands more than the glass, but by forming the capacitor 90 on the small surface of the through hole 20, the impact can be minimized. In other words, by adopting a structure such as that shown in Figure 6, the insulating material is more likely to expand on the second surface 12, which is the surface opposite to the surface on which the capacitor is formed, and as a result, the bottom 21 of the through hole is less likely to deform, thereby suppressing capacitance fluctuations.

[0032] <Third embodiment> Next, a third embodiment of the present disclosure will be described with reference to Fig. 7. Fig. 7 is a schematic diagram of a cross-sectional structure of a wiring board according to the third embodiment. In the following description, components that are the same as or equivalent to those in the first and second embodiments described above will be denoted by the same reference numerals, and their description will be simplified or omitted. The third embodiment is the same as the second embodiment in that the diameter of the through hole 20 narrows in the z-axis direction, forming a tapered shape that forms the capacitor 90 on the small side of the through hole 20. However, the third embodiment differs from the second embodiment in that the film thickness of the conductive layer 91 at the bottom 21 of the through hole is thicker than that of the conductive layer 91 in the area that does not overlap with the bottom 21. In other words, the conductive layer 91 in contact with the first surface of the capacitor 90, which is a component that constitutes a high-frequency circuit, is formed to have a larger thickness at the bottom 21 of the through hole compared to the portion that does not overlap with the through hole. In the third embodiment, the bottom 21 is more susceptible to stress distortion due to thermal expansion than other locations, but by increasing the thickness of the conductive film at the bottom 21, the amount of deformation of the capacitor 90 due to thermal expansion can be further suppressed, and the performance of the capacitor as a high-frequency component can be further improved.

[0033] <Manufacturing method> Next, a method for manufacturing a wiring board according to the present disclosure will be described with reference to FIG. (Process 1) First, as shown in FIG. 8(a), a 500 μm thick alkali-free glass (EN-A1 AGC Inc.) is prepared as the glass substrate 10, and surface contaminants are removed by ultrasonic cleaning or the like. Thereafter, the glass substrate is irradiated with a laser from the first surface side to form a laser-modified portion 13, which will be the starting point of the through hole. The laser-modified portion 13 is formed so as to extend downward, for example vertically, from the first surface 11 and so that its lower end remains on the glass substrate 10.

[0034] (Process 2) A hydrofluoric acid resistant metal film (in a range of 10 nm to 500 nm) is formed on the first surface 11 of the glass substrate by sputtering or the like. Then, a copper coating (in a range of 100 nm to 500 nm) that will become part of the conductive layer 91 is formed on the hydrofluoric acid resistant metal film by sputtering, electroless plating or the like. This forms a seed layer for electrolytic plating on the first surface of the glass substrate. The material of the hydrofluoric acid resistant metal film can be appropriately selected from, for example, chromium, nickel, and nickel chromium.

[0035] (Step 3) Next, a photoresist for pattern formation is formed on the seed layer. Specifically, a dry photoresist (RD1225) manufactured by Showa Denko Materials Inc. is used to laminate on the first surface 11, and after a pattern is drawn, the seed layer is exposed by developing. Thereafter, power is supplied to the seed layer and electrolytic copper plating is performed, thereby obtaining a pattern of conductive layer 91 having a thickness of 2 μm or more and 10 μm or less. The pattern of conductive layer 91 can then be used as the lower electrode of a capacitor. After plating, the dry film resist that is no longer needed is dissolved and peeled off.

[0036] (Step 4) In the next step, a dielectric film is formed as an insulator 92 on the pattern of the conductive layer 91. Any known method can be used to form the dielectric film, and for example, a method of forming SiN, SiO2, TaOx, or the like by plasma CVD can be selected.

[0037] (Step 5) In the next step, the upper electrode of the capacitor is formed on the dielectric film. First, a copper coating 95 (Cu, Ti / Cu) or the like is formed on the dielectric film by sputtering or electroless plating to a thickness of 100 nm to 500 nm. Then, a dry film resist 96 is used to laminate the first surface.

[0038] (Step 6) Next, as shown in Figure 8(b), a pattern is drawn on the dry film resist 96 and then developed to expose the copper coating 95 that will become the seed layer, and power is supplied to the seed layer to perform electrolytic copper plating to form an upper electrode (conductor 93) with a thickness of 2 μm or more and 10 μm or less.

[0039] (Step 7) Next, as shown in FIG. 8(c), the upper electrode seed layer, the dielectric, the lower electrode seed layer, and the hydrofluoric acid resistant metal film are etched using the conductor 93 as an etching mask. Cu can be removed by wet etching, dielectrics by dry etching, and Ti by dry and wet etching. Hydrofluoric acid-resistant metal films can also be etched with an etching solution appropriate for the metal film. For these etching methods, known etching techniques can be used as appropriate.

[0040] (Step 8) Next, as shown in FIG. 8(d), insulating resin 70 (ABF-GL103 manufactured by Ajinomoto Fine-Techno Co., Inc., 32.5 μm thick) is laminated onto the capacitor and the wiring. Thereafter, in order to attach the glass carrier 80, a temporary adhesive (Revalpha manufactured by Nitto Denko Corporation) is applied to the insulating resin 70, and the glass carrier is attached. The thickness of the glass carrier is preferably in the range of 0.7 mm to 1.5 mm in consideration of transportability after thinning, but can be appropriately set depending on the thickness of the glass substrate. In this disclosure, a glass carrier is exemplified as the support, but the support does not have to be made of glass, and may be made of metal or resin, for example.

[0041] (Step 9) Next, the surface of the glass substrate opposite to the first surface 11 is etched with a hydrogen fluoride solution to form through-holes and thin the glass substrate 10. According to this method, the glass in the portion where the laser-modified portion 13 is not formed is etched with a hydrogen fluoride solution, and is thinned parallel to the first surface of the glass substrate. When the hydrogen fluoride solution comes into contact with the laser-modified portion 13, the laser-modified portion is preferentially dissolved, and through-holes 20 are formed. As a result, the glass substrate is thinned while the through-holes are formed. In other words, thinning and the formation of the through-holes are performed in a single etching process. The lower surface of the thinned glass substrate becomes the second surface 12 on which the second-side wiring layer is formed.

[0042] The etching depth with the hydrogen fluoride solution can be appropriately set depending on the thickness of the glass device. For example, if the thickness of the glass substrate used in step 1 is 400 μm, the etching depth is preferably in the range of 100 μm to 350 μm. The thickness of the glass substrate after thinning is preferably 50 μm or more and 300 μm or less. In this way, by etching from one side of the glass substrate 10, it is possible to form the capacitor 90 on the side of the through-hole 20 with a smaller diameter, as shown in the second embodiment.

[0043] (Step 10) Next, a copper film or a material equivalent thereto is formed as a conductive layer 40 on the sidewalls and bottom of the through-holes 20 by sputtering, electroless plating, or the like on the second surface 12 of the glass substrate to a thickness of 100 nm to 500 nm. This forms a seed layer on the second surface 12 of the glass substrate.

[0044] (Step 11) Next, similarly to step 3, a pattern is formed on the second surface 12 with a dry film resist, power is supplied to the seed layer, and electrolytic plating is performed to form a conductive film with a thickness of 2 μm or more and 10 μm or less. Furthermore, by controlling this electrolytic plating process, the film thickness of the conductive layer 91 at the bottom 21 of the through hole shown in the third embodiment can be made thicker than the conductive layer 91 in the area that does not overlap with the bottom 21. The unnecessary dry film resist is then dissolved and peeled off to form a through electrode, and the unnecessary seed layer is then removed, and an outer protective film such as an insulating resin or a solder resist is coated to form the internal wiring layer 41 on the second surface 12.

[0045] (Step 12) 8(e), the through-holes 20 are filled with a filling material 23 such as an insulating resin. After that, an interlayer insulating layer 22 is formed so as to cover the second surface 12. The filling material 23 filling the through holes 20 may be the same material as or a different material from the interlayer insulating layer 22. For example, the through holes may be filled by using a printing method to fill and harden only the through holes 20 with a soft resin, and then the interlayer insulating resin may be formed, or the filling of the through holes 20 and the formation of the interlayer insulating layer may be performed continuously in the same process. Furthermore, the filling material 23 is not limited to insulating resin, and may be filled with other metal materials such as Cu plating. Thereafter, the glass carrier 80 that was temporarily attached in step 8 is removed.

[0046] (Step 13) Thereafter, using known manufacturing methods, wiring and build-up layers can be formed on the front and back surfaces in the same way as with FC-BGA substrates, and an inductor (coil) (not shown) can be formed at the same time as the wiring is formed. Regarding the inductor configuration, it is possible to form a coil of any shape, such as a solenoid or spiral.

[0047] According to the manufacturing method of the present disclosure, the capacitor can be manufactured on the first surface of the highly flat glass substrate before the through-hole 20 is formed, and therefore the capacitor can be formed with high precision. Furthermore, the diameter φ1 of the bottom 21 of the through hole 20 that overlaps the capacitor 90 is smaller than the diameter φ2 of the second surface 12 on the opposite side of the glass substrate. In this way, by configuring the capacitor 90 on the smaller diameter side of the through hole 20, it is possible to suppress changes in the capacitance of the capacitor due to changes in the temperature of the wiring substrate.

[0048] <Verification of effectiveness> Next, with reference to FIGS. 9 to 12, the reflection characteristics (S11) of the high-frequency circuit when comparing a wiring board employing a main portion of the wiring board according to the second embodiment of the present disclosure with a wiring board of a comparative example will be described. 9 is a schematic diagram of a cross-sectional structure of a wiring board employing a main part of the wiring board according to the second embodiment of the present disclosure. In the following description, the same or equivalent components as those in the first and second embodiments described above are denoted by the same reference numerals, and their description will be simplified or omitted. Specifically, the glass substrate 10 is made of alkali-free glass (EN-A1 (AGC) 0.15 mm thick), and the interlayer insulating resin and through-hole filling material are made of GL103 (Ajinomoto Fine-Techno). The conductive layer is made of electrolytic copper plating, and the capacitor dielectric is made of SiN. In the example of Figure 9, the diameters of the through-holes are Top: 80 μm, Bottom: 50 μm, and the capacitor is located on the bottom side, directly above the through-hole.

[0049] 10 is a schematic diagram of a cross-sectional structure of a wiring board that employs a main part of the wiring board of the comparative example. In the following description, the same or equivalent components as those in the conventional example, the first embodiment, and the second embodiment described above are denoted by the same reference numerals, and their description will be simplified or omitted. The wiring board of the comparative example is a glass substrate with a through-hole formed therein and a capacitor formed thereon, and does not employ the method of providing a laser modified portion employed in the present disclosure to simultaneously form the through-hole and thin the glass substrate, resulting in a thicker glass substrate than that shown in FIG. Other specific configurations include alkali-free glass (EN-A1 (AGC) 0.15 mm thick) for the glass substrate 10, GX13 (Ajinomoto Fine-Techno) for the interlayer insulating resin and through-hole filling material, electrolytic copper plating for the conductive layer, and SiN for the capacitor dielectric. The diameter of the through-hole is 80 μm at the top and 50 μm at the bottom, and the capacitor is positioned 500 μm away from the top side of the through-hole.

[0050] Although inductors, which are components that make up the high-frequency circuit, are not shown in Figures 9 and 10, a parallel resonant circuit consisting of an inductor and a capacitor as shown in Figure 11 was created using the circuit boards of Figures 9 and 10, and the S parameters (S11 reflection characteristics) were measured and compared using a network analyzer.

[0051] The measurement method is as follows. Measurement equipment: Network analyzer (N5225B) Measurement frequency range: 100MHz to 10GHz Calibration: SOL calibration Measurement method: Reflection method (1 port) Measuring probe: SG / GS 200 As a result, an S11 waveform as shown in FIG. 12 was obtained, and it was confirmed that the example of the present disclosure had a steeper and better frequency characteristic than the comparative example.

[0052] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the gist of the present invention. [Explanation of symbols]

[0053] 10: glass substrate, 11: first surface, 12: second surface, 13: laser modified portion, 20: through hole, 21: bottom, 22: interlayer insulating layer, 23: filling material, 30: insulating layer, 40: conductive layer, 41: internal wiring layer, 42: external wiring, 50: via portion, 51: pad portion, 60: Solder ball, 70: Insulating resin, 80: Glass carrier 90: capacitor, 91: conductive layer, 92: insulator, 93: conductor, 94: Hydrofluoric acid resistant metal film, 95: Copper coating, 96: Dry film resist

Claims

1. A wiring board having a glass substrate having a through hole and a capacitor on a first surface of the glass substrate, the capacitor includes a conductive layer, an insulator, and a conductor; the conductive layer is in contact with the first surface, the insulator is above the conductive layer; the conductor is above the insulator, The wiring board has a bottom of the through hole on the first surface and the capacitor, the bottom having an overlapping portion on the first surface.

2. 2. The wiring board according to claim 1, The wiring board is characterized in that the through holes are filled with a material having a coefficient of thermal expansion (CTE) of 40 ppm / K or less.

3. 3. The wiring board according to claim 1, The through-hole has a diameter on the first surface that is smaller than a diameter on a second surface that is the surface opposite to the first surface. A wiring board characterized by:

4. 4. The wiring board according to claim 1, The conductive layer has a larger thickness at the bottom of the through hole than at a portion not overlapping the through hole. A wiring board characterized by:

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