Oscillator manufacturing method and oscillator group

Abstract

To provide a manufacturing method for reducing the possibility of a deterioration in characteristics of an oscillation signal due to an unnecessary circuit, and efficiently manufacturing a plurality of types of oscillators.SOLUTION: A method for manufacturing an oscillator includes: storing a first vibrator and a first integrated circuit device oscillating the first vibrator in a first container to manufacture a first oscillator; and storing a second vibrator and a second integrated circuit device oscillating the second vibrator in a second container to manufacture a second oscillator. The first integrated circuit device includes a first oscillation circuit, and a frequency control circuit generating a frequency control signal including at least one of a temperature compensation signal and a frequency setting signal. The second integrated circuit device includes a second oscillation circuit, and does not include the frequency control circuit generating a frequency control signal including at least one of a temperature compensation signal and a frequency setting signal. The first container and the second container are the containers of the same type.SELECTED DRAWING: Figure 18

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing an oscillator and to an oscillator. [Background technology]

[0002] Patent Document 1 describes an oscillator that includes a temperature compensation circuit, a frequency adjustment circuit, and an initial deviation correction circuit, and that selectively adds together the temperature compensation voltage, frequency adjustment voltage, and initial deviation correction voltage output from these circuits by controlling switches based on control data stored in a memory, and supplies the resulting voltage to a voltage-controlled oscillator circuit as a control voltage. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2003 / 021765 Summary of the Invention [Problem to be solved by the invention]

[0004] In the oscillator described in Patent Document 1, for example, a common circuit can be used to switch between the presence and absence of a temperature compensation function. However, even if the oscillator does not have a temperature compensation function, since a temperature compensation circuit is built in, there is a risk that the presence of an unnecessary circuit will degrade the signal characteristics. [Means for solving the problem]

[0005] One aspect of the method for manufacturing an oscillator according to the present invention is to A method for manufacturing a plurality of types of oscillators including a first oscillator and a second oscillator, manufacturing the first oscillator by housing a first resonator and a first integrated circuit device that causes the first resonator to oscillate in a first container; and manufacturing the second oscillator by housing a second vibrator and a second integrated circuit device that causes the second vibrator to oscillate in a second container; the first integrated circuit device includes a first oscillation circuit that oscillates the first vibrator to output a first oscillation signal, and a frequency control circuit that generates a frequency control signal including at least one of a temperature compensation signal that compensates for a frequency temperature characteristic of the first oscillation signal and a frequency setting signal that sets the frequency of the first oscillation signal to a frequency corresponding to a voltage of a signal input from outside the first integrated circuit device, the second integrated circuit device includes a second oscillation circuit that oscillates the second vibrator to output a second oscillation signal, and does not include a frequency control circuit that generates a frequency control signal that includes at least one of a temperature compensation signal that compensates for the frequency temperature characteristic of the second oscillation signal and a frequency setting signal that sets the second oscillation signal to a frequency that corresponds to the voltage of a signal that is input from outside the second integrated circuit device; The first container and the second container are the same type of container.

[0006] One aspect of the oscillator according to the present invention is An oscillator included in an oscillator group consisting of multiple types of oscillators, a first oscillator; a first integrated circuit device that causes the first vibrator to oscillate; a first container that houses the first vibrator and the first integrated circuit device; Equipped with The first integrated circuit device includes a first oscillation circuit that oscillates the first oscillator to output a first oscillation signal, a temperature compensation signal that compensates for the frequency temperature characteristics of the first oscillation signal, and a frequency control circuit that generates a frequency control signal including at least one of a frequency setting signal that sets the first oscillation signal to a frequency corresponding to a voltage of a signal input from outside the first integrated circuit device, another oscillator included in the oscillator group includes a second vibrator, a second integrated circuit device that causes the second vibrator to oscillate, and a second container that houses the second vibrator and the second integrated circuit device; the second integrated circuit device includes a second oscillation circuit that oscillates the second vibrator to output a second oscillation signal, and does not include a frequency control circuit that generates a frequency control signal that includes at least one of a temperature compensation signal that compensates for the frequency temperature characteristic of the second oscillation signal and a frequency setting signal that sets the second oscillation signal to a frequency that corresponds to the voltage of a signal that is input from outside the second integrated circuit device; The first container and the second container are the same type of container.

[0007] Another aspect of the oscillator according to the present invention is An oscillator included in an oscillator group consisting of multiple types of oscillators, a second oscillator; and a second integrated circuit device that causes the second vibrator to oscillate; a second container that houses the second vibrator and the second integrated circuit device; Equipped with the second integrated circuit device includes a second oscillation circuit that oscillates the second vibrator to output a second oscillation signal, and does not include a frequency control circuit that generates a frequency control signal that includes at least one of a temperature compensation signal that compensates for the frequency temperature characteristic of the second oscillation signal and a frequency setting signal that sets the second oscillation signal to a frequency that corresponds to the voltage of a signal that is input from outside the second integrated circuit device; each of the other oscillators included in the oscillator group includes a first vibrator, a first integrated circuit device that causes the first vibrator to oscillate, and a first container that houses the first vibrator and the first integrated circuit device; the first integrated circuit device includes a first oscillation circuit that oscillates the first vibrator to output a first oscillation signal, and a frequency control circuit that generates a frequency control signal including at least one of a temperature compensation signal that compensates for a frequency temperature characteristic of the first oscillation signal and a frequency setting signal that sets the frequency of the first oscillation signal to a frequency corresponding to a voltage of a signal input from outside the first integrated circuit device, The first container and the second container are the same type of container. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 2 is a diagram showing the configuration of an oscillator group 1. [Figure 2] FIG. 2 is a functional block diagram of a first oscillator. [Figure 3] FIG. 2 is a diagram showing a configuration example of a power supply circuit of a first oscillator. [Figure 4] FIG. 2 is a diagram showing a configuration example of an oscillation circuit of a first oscillator. [Figure 5] FIG. 2 is a diagram showing an example of the configuration of a frequency control circuit. [Figure 6] FIG. 2 is a diagram showing a configuration example of an output circuit. [Figure 7] FIG. 10 is a diagram showing an example of a timing chart for writing and reading data to and from a nonvolatile memory. [Figure 8] FIG. 2 is a functional block diagram of a second oscillator. [Figure 9] FIG. 2 is a diagram showing a configuration example of a power supply circuit of a second oscillator. [Figure 10] FIG. 2 is a diagram showing a configuration example of an oscillation circuit of a second oscillator. [Figure 11] FIG. 2 is a diagram showing an example of a layout arrangement of the first integrated circuit device according to the first embodiment. [Figure 12] FIG. 4 is a diagram showing an example of a layout arrangement of a second integrated circuit device according to the first embodiment. [Figure 13] FIG. 10 is a diagram showing an example of phase noise. [Figure 14] FIG. 10 is a diagram showing an example of frequency temperature characteristics. [Figure 15] FIG. 2 is a perspective view of a first oscillator and a second oscillator. [Figure 16] FIG. 2 is a cross-sectional view of a first oscillator and a second oscillator. [Figure 17] FIG. 4 is a plan view showing a plurality of electrodes formed on the first container and the second container. [Figure 18] FIG. 4 is a flowchart showing an example of a procedure for a method for manufacturing an oscillator according to the present embodiment. [Figure 19] FIG. 20 is a flowchart showing an example of the detailed procedure of step S2 in FIG. 18. [Figure 20] FIG. 20 is a flowchart showing an example of the detailed procedure of step S4 in FIG. 18. [Figure 21] FIG. 10 is a diagram showing an example of a layout arrangement of a first integrated circuit device according to a second embodiment. [Figure 22] FIG. 10 is a diagram showing an example of a layout arrangement of a second integrated circuit device according to the second embodiment. [Figure 23] FIG. 10 is a plan view showing a plurality of electrodes formed in a first container in the second embodiment. [Figure 24] FIG. 10 is a plan view showing a plurality of electrodes formed in a second container in the second embodiment. [Figure 25] FIG. 10 is a diagram showing an example of a layout arrangement of a first integrated circuit device according to a third embodiment. [Figure 26] FIG. 10 is a diagram showing an example of a layout arrangement of a second integrated circuit device according to the third embodiment. [Figure 27] FIG. 11 is a plan view showing a plurality of electrodes formed in a first container in a third embodiment. [Figure 28] FIG. 11 is a plan view showing a plurality of electrodes formed in a second container in the third embodiment. [Figure 29] FIG. 10 is a diagram showing an example of a layout arrangement of a first integrated circuit device according to a fourth embodiment. [Figure 30] FIG. 10 is a diagram showing an example of a layout arrangement of a second integrated circuit device according to the fourth embodiment. [Figure 31] FIG. 10 is a plan view showing a plurality of electrodes formed in a first container in a fourth embodiment. [Figure 32] FIG. 10 is a plan view showing a plurality of electrodes formed in a second container in the fourth embodiment. [Figure 33] FIG. 13 is a diagram showing an example of a layout arrangement of a first integrated circuit device according to the fifth embodiment. [Figure 34] FIG. 13 is a diagram showing an example of a layout arrangement of a second integrated circuit device according to the fifth embodiment. [Figure 35] FIG. 13 is a cross-sectional view of a first oscillator and a second oscillator according to a fifth embodiment. [Figure 36] FIG. 13 is a plan view showing a plurality of electrodes formed on the first surfaces of the substrates of the first container and the second container in the fifth embodiment. [Figure 37]FIG. 13 is a plan view showing a plurality of electrodes formed on a second surface of a substrate of a first container in a fifth embodiment. [Figure 38] FIG. 13 is a plan view showing a plurality of electrodes formed on a second surface of a substrate of a second container in the fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Note that the embodiments described below do not unduly limit the content of the present invention as defined in the claims. Furthermore, not all of the configurations described below are necessarily essential components of the present invention.

[0010] 1. First embodiment 1-1. Oscillators FIG. 1 is a diagram showing the configuration of an oscillator group 1 of this embodiment. The oscillator group 1 is made up of a plurality of oscillators, each of which has a resonator and an integrated circuit device housed in a container. The plurality of oscillators includes a first oscillator 2a and a second oscillator 2b. The first oscillator 2a includes a first resonator 5a, a first integrated circuit device 4a that causes the first resonator 5a to oscillate, and a first container 3a that houses the first resonator 5a and the first integrated circuit device 4a. In addition, the second oscillator 2b includes a second vibrator 5b, a second integrated circuit device 4b that causes the second vibrator 5b to oscillate, and a second container 3b that accommodates the second vibrator 5b and the second integrated circuit device 4b.

[0011] The first container 3a and the second container 3b are the same type of container. Specifically, the first container 3a and the second container 3b have the same shape of the container itself, and the same shapes, positions, and numbers of electrodes and wiring patterns formed on the containers, ignoring manufacturing errors. For example, the first container 3a and the second container 3b may be ceramic packages with the same model number.

[0012] The first integrated circuit device 4a and the second integrated circuit device 4b have different circuit configurations, which causes the first oscillator 2a and the second oscillator 2b to have different functions. In this embodiment, the first integrated circuit device 4a includes a first oscillation circuit that oscillates a first resonator 5a to output a first oscillation signal, and a frequency control circuit that generates a frequency control signal including at least one of a temperature compensation signal that compensates for the frequency-temperature characteristics of the first oscillation signal and a frequency setting signal that sets the first oscillation signal to a frequency corresponding to the voltage of a signal input from outside the first integrated circuit device 4a. On the other hand, the second integrated circuit device 4b includes a second oscillation circuit that oscillates a second resonator 5b to output a second oscillation signal, but does not include a frequency control circuit that generates a frequency control signal including at least one of a frequency setting signal that sets the second oscillation signal to a frequency corresponding to the voltage of a signal input from outside the second integrated circuit device 4b.

[0013] In this way, the oscillator group 1 is composed of a plurality of oscillators each having a resonator and an integrated circuit device housed in the same type of container and each having different functions. The integrated circuit devices included in the plurality of oscillators constituting the oscillator group 1 constitute an integrated circuit device group, and the first integrated circuit device 4a and the second integrated circuit device 4b are included in the plurality of integrated circuit devices constituting the integrated circuit device group.

[0014] 1-2. Functional configuration of the first oscillator 2 is a functional block diagram of the first oscillator 2a. As shown in FIG. 2, the first oscillator 2a includes a first resonator 5a and a first integrated circuit device 4a. The first integrated circuit device 4a has, as external connection terminals, a VDD terminal, a VSS terminal, an OUT terminal, an OE terminal, an XI terminal, and an XO terminal. The VDD terminal, the VSS terminal, the OUT terminal, and the OE terminal are electrically connected to the VDD1 terminal, the VSS1 terminal, the OUT1 terminal, and the OE1 terminal, which are multiple external terminals of the first oscillator 2a, respectively. The XI terminal is electrically connected to one end of the first resonator 5a, and the XO terminal is electrically connected to the other end of the first resonator 5a.

[0015] In this embodiment, the first integrated circuit device 4a includes a power supply circuit 110, an oscillator circuit 120, a frequency control circuit 130, an output circuit 140, a logic circuit 150, a nonvolatile memory 160, variable capacitance circuits 171 and 172, and capacitance elements 191 and 192. Note that the first integrated circuit device 4a may be configured such that some of these elements are omitted or modified, or other elements are added.

[0016] The power supply circuit 110 generates a constant power supply voltage Vreg based on a power supply voltage VDD supplied from the outside via a VDD1 terminal and a VDD terminal, and a ground voltage VSS supplied from the outside via a VSS1 terminal and a VSS terminal, and supplies the voltage to each circuit. The power supply circuit 110 may also generate various reference voltages and supply them to each circuit as appropriate.

[0017] Fig. 3 is a diagram showing an example of the configuration of the power supply circuit 110. In the example of Fig. 3, the power supply circuit 110 includes a bandgap reference circuit 111, an operational amplifier 112, a resistive element 113, a capacitive element 114, an N-channel MOS transistor 115, and resistive elements 116 and 117.

[0018] The bandgap reference circuit 111 uses the bandgap voltage of silicon to generate a constant reference voltage independent of the power supply voltage VDD or temperature.

[0019] The MOS transistor 115 and the resistor elements 116 and 117 are connected in series between a node to which a power supply voltage VDD is supplied and a node to which a ground voltage VSS is supplied.

[0020] A reference voltage output from the bandgap reference circuit 111 is input to a non-inverting input terminal of the operational amplifier 112, and a voltage obtained by dividing the power supply voltage VDD by resistor elements 116 and 117 is input to an inverting input terminal of the operational amplifier 112. The output terminal of the operational amplifier 112 is connected to the gate of the MOS transistor 115 via a resistor element 113.

[0021] The capacitance element 114 is connected between the gate of the MOS transistor 115 and a node to which the ground voltage VSS is supplied, and the resistance element 113 and the capacitance element 114 form a low-pass filter that smoothes the output signal of the operational amplifier 112. The voltage at the drain of the MOS transistor 115 is output as the power supply voltage Vreg.

[0022] 2, the capacitance element 191 is connected between a VDD terminal to which a power supply voltage VDD is supplied and a VSS terminal to which a ground voltage VSS is supplied. The capacitance element 192 is connected between a node to which a power supply voltage Vreg is supplied and a VSS terminal to which a ground voltage VSS is supplied. The capacitance elements 191 and 192 each function as a bypass capacitor, suppressing sudden fluctuations in the power supply voltage VDD and the power supply voltage Vreg due to noise, etc.

[0023] The variable capacitance circuit 171 is connected between the XI terminal and the VSS terminal. The variable capacitance circuit 172 is connected between the XO terminal and the VSS terminal. Therefore, the variable capacitance circuit 171 is connected to one end of the first oscillator 5a via the XI terminal, and the variable capacitance circuit 172 is connected to the other end of the first oscillator 5a via the XO terminal. The capacitance values ​​of the variable capacitance circuits 171 and 172 change in response to the frequency control signal Vctl output from the frequency control circuit 130.

[0024] The oscillator circuit 120 is electrically connected to both ends of the first oscillator 5a via the XI terminal and the XO terminal, and causes the first oscillator 5a to oscillate at a desired frequency to output an oscillation signal Vosc. Specifically, the oscillator circuit 120 receives the signal output from the first oscillator 5a via the XO terminal, amplifies the signal, and supplies the amplified signal to the first oscillator 5a via the XI terminal.

[0025] Fig. 4 is a diagram showing an example configuration of the oscillator circuit 120. In the example of Fig. 4, the oscillator circuit 120 includes P-channel MOS transistors 121 and 122, an N-channel MOS transistor 123, an NPN bipolar transistor 124, and capacitance elements 125 and 126. The MOS transistors 121 and 122 are enhancement type, and the MOS transistor 123 is depletion type.

[0026] The gate of the MOS transistor 121 is electrically connected to the drain of the MOS transistor 121, the gate of the MOS transistor 122, and the drain of the MOS transistor 123. The source of the MOS transistor 121 and the source of the MOS transistor 122 are supplied with a power supply voltage Vreg. The gate and source of the MOS transistor 123 are grounded and are supplied with a ground voltage VSS. The drain of the MOS transistor 122 is electrically connected to the collector of the bipolar transistor 124 and the drain of the capacitive element 126. The base of the bipolar transistor 124 is electrically connected to one end of the capacitive element 125 and the XI terminal. The emitter of the bipolar transistor 124, the other end of the capacitive element 125, and the other end of the capacitive element 126 are grounded and supplied with the ground voltage VSS.

[0027] In the oscillator circuit 120 configured as described above, a constant current Iref flows through the drain of the MOS transistor 122, and the bipolar transistor 124 performs an amplification operation when supplied with the current Iref. The collector signal of the bipolar transistor 124 is output as the oscillation signal Vosc. That is, the bipolar transistor 124 constitutes an amplifier circuit 128 that amplifies the signal from the first oscillator 5a and outputs the oscillation signal Vosc. The MOS transistors 121, 122, and 123 constitute a current source 127 that supplies the current Iref to the amplifier circuit 128. As described above, the variable capacitance circuit 171 is connected between the XI terminal and the VSS terminal, and the variable capacitance circuit 172 is connected between the XO terminal and the VSS terminal. Therefore, the capacitance elements 125 and 126 and the variable capacitance circuits 171 and 172 function as load capacitances for the first oscillator 5a, and the frequency of the oscillation signal Vosc depends on the capacitance values ​​of the capacitance elements 125 and 126 and the capacitance values ​​of the variable capacitance circuits 171 and 172.

[0028] Returning to the explanation of Figure 2, the frequency control circuit 130 generates a frequency control signal Vctl that controls the frequency of the oscillation signal Vosc based on at least one of a temperature compensation signal that compensates for the frequency temperature characteristics of the oscillation signal Vosc and a control signal input from outside the first integrated circuit device 4a.

[0029] Fig. 5 is a diagram showing an example configuration of the frequency control circuit 130. In the example of Fig. 5, the frequency control circuit 130 includes a temperature compensation circuit 136 and an AFC circuit 137. The first integrated circuit device 4a may be able to set whether or not to operate each of the temperature compensation circuit 136 and the AFC circuit 137.

[0030] When the temperature compensation function is enabled by the temperature compensation function setting bit cmpEN, the temperature compensation circuit 136 generates a temperature compensation signal Vcmp for compensating for the frequency-temperature characteristics of the oscillation signal Vosc output from the oscillation circuit 120 based on temperature compensation data cmpDT corresponding to the frequency-temperature characteristics of the first resonator 5a. The temperature compensation data cmpDT includes, for example, coefficient values ​​of each order of a temperature compensation function that compensates for the frequency-temperature characteristics of the first resonator 5a. When the temperature compensation function is disabled by the temperature compensation function setting bit cmpEN, the temperature compensation circuit 136 stops operating, thereby reducing current consumption. The temperature compensation data cmpDT is generated during the manufacturing process of the first oscillator 2a and written to the nonvolatile memory 160 together with the temperature compensation function setting bit cmpEN. When the first oscillator 2a is operating, the temperature compensation function setting bit cmpEN and the temperature compensation data cmpDT stored in the nonvolatile memory 160 are supplied to the temperature compensation circuit 136 via the logic circuit 150.

[0031] In the example of FIG. 5, the temperature compensation circuit 136 includes a temperature sensor 131, a zero-order component generating circuit 132, a first-order component generating circuit 133, a high-order component generating circuit 134, and an I / V conversion circuit 135.

[0032] The temperature sensor 131, the zeroth-order component generating circuit 132, the first-order component generating circuit 133, the high-order component generating circuit 134, and the I / V conversion circuit 135 operate when the temperature compensation function is enabled by the temperature compensation function setting bit cmpEN, and stop operating when the temperature compensation function is disabled by the temperature compensation function setting bit cmpEN.

[0033] The temperature sensor 131 detects the temperature of the first integrated circuit device 4a and adjusts the voltage according to the temperature. It outputs a temperature signal and is realized, for example, by a circuit that utilizes the temperature characteristics of a bandgap reference circuit.

[0034] The zeroth-order component generating circuit 132 outputs a current signal corresponding to the zeroth-order term of the temperature compensation function based on the zeroth-order coefficient value included in the temperature compensation data cmpDT.

[0035] The first-order component generating circuit 133 outputs a current signal corresponding to the first-order term of the temperature compensation function based on the temperature signal output from the temperature sensor 131 and the first-order coefficient value included in the temperature compensation data cmpDT.

[0036] The high-order component generating circuit 134 outputs current signals corresponding to each of the second-order and higher order terms of the temperature compensation function based on the temperature signal output from the temperature sensor 131 and each of the second-order and higher order coefficient values ​​included in the temperature compensation data cmpDT. For example, the high-order component generating circuit 134 outputs current signals corresponding to each of the second-order to seventh order terms of the temperature compensation function.

[0037] The I / V conversion circuit 135 converts into a voltage signal a current signal obtained by adding together the current signal output from the zeroth-order component generation circuit 132, the current signal output from the first-order component generation circuit 133, and the current signals output from the high-order component generation circuit 134. This voltage signal is output as the temperature compensation signal Vcmp.

[0038] The temperature compensation signal Vcmp causes the oscillation signal Vosc output by the oscillation circuit 120 to have a substantially constant frequency at any temperature within a predetermined temperature range.

[0039] When the frequency variable function is enabled by the frequency variable function setting bit afcEN, the AFC circuit 137 generates a frequency setting signal Vafc for variably setting the frequency of the oscillation signal Vosc output from the oscillation circuit 120 in accordance with the voltage level of the control signal Vc supplied from the logic circuit 150. When the frequency variable function is disabled by the frequency variable function setting bit afcEN, the AFC circuit 137 stops operating, thereby reducing current consumption. The frequency variable function setting bit afcEN is written to the nonvolatile memory 160 during the manufacturing process of the first oscillator 2a. When the first oscillator 2a is operating, the frequency variable function setting bit afcEN stored in the nonvolatile memory 160 is supplied to the AFC circuit 137 via the logic circuit 150.

[0040] When the temperature compensation function is enabled by the temperature compensation function setting bit cmpEN and the frequency variable function is disabled by the frequency variable function setting bit afcEN, the frequency control circuit 130 outputs the temperature compensation signal Vcmp as the frequency control signal Vctl. When the temperature compensation function is disabled by the temperature compensation function setting bit cmpEN and the frequency variable function is enabled by the frequency variable function setting bit afcEN, the frequency control circuit 130 outputs the frequency setting signal Vafc as the frequency control signal Vctl. When the temperature compensation function is enabled by the temperature compensation function setting bit cmpEN and the frequency variable function is enabled by the frequency variable function setting bit afcEN, the frequency control circuit 130 outputs a signal obtained by adding the temperature compensation signal Vcmp and the frequency setting signal Vafc as the frequency control signal Vctl. Furthermore, when the temperature compensation function is set to be disabled by the temperature compensation function setting bit cmpEN and the frequency variable function is set to be disabled by the frequency variable function setting bit afcEN, the frequency control circuit 130 outputs a signal of a predetermined constant voltage as the frequency control signal Vctl.

[0041] Returning to the explanation of FIG. 2, the oscillation signal Vosc is input to the output circuit 140. The output circuit 140 receives the output enable signal outEN from the logic circuit 150 when the output enable signal outEN is at a high level. When the output enable signal outEN is at a low level, the output circuit 140 outputs an oscillation signal Vout based on the oscillation signal Vosc, and when the output enable signal outEN is at a low level, it outputs a signal at the ground voltage VSS. For example, the output circuit 140 may output the oscillation signal Vout obtained by dividing the oscillation signal Vosc by a division ratio set by the output setting data outDT. The output circuit 140 may also output the oscillation signal Vout of an output type set by the output setting data outDT. The output type of the oscillation signal Vout may be, for example, a CMOS output or a clipped sign output. CMOS stands for Complementary Metal Oxide Semiconductor. The output circuit 140 may also output the oscillation signal Vout of an output capability set by the output setting data outDT. The output setting data outDT is written to the nonvolatile memory 160 during the manufacturing process of the first oscillator 2a. When the first oscillator 2a is operating, the output setting data outDT stored in the nonvolatile memory 160 is supplied to the output circuit 140 via the logic circuit 150.

[0042] 6 is a diagram showing an example of the configuration of the output circuit 140. In the example of FIG. 6, the output circuit 140 includes a waveform shaping buffer 141, a frequency divider circuit 142, a pre-buffer 143, and an output buffer 144.

[0043] The waveform shaping buffer 141 buffers the oscillation signal Vosc output from the oscillation circuit 120 and outputs an oscillation signal of a square wave.

[0044] The frequency divider circuit 142 outputs an oscillation signal obtained by dividing the oscillation signal output from the waveform shaping buffer 141 by the division ratio set by the output setting data outDT. When the division ratio is 1, the frequency divider circuit 142 outputs an oscillation signal obtained by buffering the oscillation signal output from the waveform shaping buffer 141. The oscillation signal output from the frequency divider circuit 142 is input to the pre-buffer 143.

[0045] The pre-buffer 143 outputs an oscillation signal obtained by buffering the oscillation signal output from the frequency divider circuit 142. The pre-buffer 143 also functions as a level shifter that outputs an oscillation signal with a voltage level that matches the input voltage level of the output buffer 144.

[0046] The output buffer 144 converts the oscillation signal output from the pre-buffer 143 into an oscillation signal Vout of the output type and output capacity set by the output setting data outDT. The output buffer 144 outputs the oscillation signal Vout when the output enable signal outEN is at a high level, and outputs a signal of the ground voltage VSS or high impedance when the output enable signal outEN is at a low level.

[0047] Returning to the description of FIG. 2 , the logic circuit 150 controls the operation of each circuit. That is, the logic circuit 150 performs operation settings for the first integrated circuit device 4a. Specifically, the logic circuit 150 sets the operation mode of the first oscillator 2a or the first integrated circuit device 4a to one of multiple modes, including an external communication mode and a normal operation mode, based on a control signal input to a predetermined external connection terminal of the first integrated circuit device 4a, and performs control according to the set operation mode. In this embodiment, if a control signal of a predetermined pattern is input from the OE terminal within a predetermined period after the supply of the power supply voltage VDD to the VDD terminal begins, the logic circuit 150 sets the operation mode to the external communication mode after the predetermined period has elapsed. For example, the logic circuit 150 may determine the predetermined period as the period from when the first oscillator 5a starts oscillating due to the supply of the power supply voltage VDD to when it detects that the oscillation has stabilized. Alternatively, the logic circuit 150 may count the number of pulses of the oscillation signal Vosc and determine that the predetermined period has elapsed when the count value reaches a predetermined value. Furthermore, for example, the logic circuit 150 may measure the predetermined period based on the output signal of an RC time constant circuit that starts operating when the power supply voltage VDD is supplied.

[0048] In the external communication mode, the logic circuit 150 can perform data communication with an external device (not shown) connected to the OE1 and OUT1 terminals via the OE and OUT terminals. The external device outputs a serial clock signal to the OUT1 terminal in accordance with a predetermined communication standard, and outputs a serial data signal to the OE1 terminal in synchronization with the serial clock signal. Alternatively, the external device acquires a signal output from the logic circuit 150 to the OE1 terminal via the OE terminal. In the external communication mode, the logic circuit 150 samples the serial data signal as various commands at each edge of the serial clock signal, for example, in accordance with the I2C bus standard. I2C stands for Inter-Integrated Circuit. Based on the sampled commands, the logic circuit 150 sets the operating mode and performs processes such as writing and reading data to and from the non-volatile memory 160. In this embodiment, the logic circuit 150 communicates with an external device using a two-wire bus communication standard such as an I2C bus, but may also communicate with an external device using a three-wire or four-wire bus communication standard such as an SPI bus. SPI is an abbreviation for Serial Peripheral Interface.

[0049] For example, when the logic circuit 150 samples a write command to the nonvolatile memory 160 in the external communication mode, it writes data specified in the write command to the address in the nonvolatile memory 160 specified in the write command. Furthermore, when the logic circuit 150 samples a read command to the nonvolatile memory 160 in the external communication mode, it reads data from the address in the nonvolatile memory 160 specified in the read command, converts the data into serial data, and outputs it. Figure 7 shows an example of a timing chart for writing and reading data to and from the nonvolatile memory 160 in the external communication mode after the supply of the power supply voltage VDD to the VDD terminal starts and the mode is switched to the external communication mode.

[0050] Furthermore, for example, when the logic circuit 150 samples a normal operation mode setting command in the external communication mode, it transitions the operation mode from the external communication mode to the normal operation mode. When the frequency variable function setting bit afcEN has enabled the frequency variable function, in the normal operation mode, the logic circuit 150 supplies a signal input from outside the first oscillator 2a via the OE1 terminal and the OE terminal to the AFC circuit 137 as a control signal Vc, and also supplies a high-level output enable signal outEN to the output circuit 140. That is, the frequency of the oscillation signal Vout is controlled based on the signal input to the OE1 terminal. When the frequency variable function setting bit afcEN has disabled the frequency variable function, in the normal operation mode, the logic circuit 150 supplies a signal input from outside the first oscillator 2a via the OE1 terminal and the OE terminal to the output circuit 140 as an output enable signal outEN, and also supplies a constant-voltage control signal Vc to the AFC circuit 137. That is, the output of the oscillation signal Vout from the OUT1 terminal is controlled based on the signal input to the OE1 terminal.

[0051] If a signal of a predetermined pattern is not input from the OE terminal within a predetermined period of time after the supply of the power supply voltage VDD starts, the logic circuit 150 does not set the operation mode to the external communication mode after the predetermined period of time has elapsed, but directly sets it to the normal operation mode.

[0052] The nonvolatile memory 160 is a memory that stores various types of information, such as a MONOS type memory or an EEPROM. MONOS stands for Metal Oxide Nitride Oxide Silicon, and EEPROM stands for Electrically Erasable Programmable Read-Only Memory. During the manufacturing process of the first oscillator 2a, various types of information for controlling each circuit, such as a temperature compensation function setting bit cmpEN, temperature compensation data cmpDT, a frequency variable function setting bit afcEN, and output setting data outDT, are stored in the nonvolatile memory 160. When power is applied to the first oscillator 2a, The various types of stored information are transferred to a register (not shown) that the logic circuit 150 has, and the various types of information saved in the register are supplied to each circuit as appropriate.

[0053] The oscillator circuit 120 is an example of a "first oscillator circuit," and the oscillation signal Vosc output from the oscillator circuit 120 is an example of a "first oscillation signal." The power supply circuit 110 is an example of a "first power supply circuit," and the power supply voltage Vreg output from the power supply circuit 110 is an example of a "first power supply voltage." The output circuit 140 is an example of a "first output circuit," and the oscillation signal Vout output from the output circuit 140 is an example of a "first output signal." The logic circuit 150 is an example of a "first logic circuit."

[0054] 1-3. Functional configuration of the second oscillator 8 is a functional block diagram of the second oscillator 2b. As shown in FIG. 8, the second oscillator 2b includes a second resonator 5b and a second integrated circuit device 4b. Similar to the first integrated circuit device 4a, the second integrated circuit device 4b has external connection terminals: a VDD terminal, a VSS terminal, an OUT terminal, an OE terminal, an XI terminal, and an XO terminal. The VDD terminal, the VSS terminal, the OUT terminal, and the OE terminal are electrically connected to the VDD1 terminal, the VSS1 terminal, the OUT1 terminal, and the OE1 terminal, which are multiple external terminals of the second oscillator 2b, respectively. The XI terminal is electrically connected to one end of the second resonator 5b, and the XO terminal is electrically connected to the other end of the second resonator 5b.

[0055] In this embodiment, the second integrated circuit device 4b includes a power supply circuit 210, an oscillation circuit 220, an output circuit 240, a logic circuit 250, a nonvolatile memory 260, and capacitive elements 191 and 192. Note that the second integrated circuit device 4b may be configured such that some of these elements are omitted or modified, or other elements are added.

[0056] The power supply circuit 210 generates a constant power supply voltage Vreg based on a power supply voltage VDD supplied from the outside via the VDD1 terminal and the VDD terminal, and a ground voltage VSS supplied from the outside via the VSS1 terminal and the VSS terminal, and supplies the voltage to each circuit. The power supply circuit 210 also generates various reference voltages and supplies them to each circuit as appropriate.

[0057] 9 is a diagram showing an example of the configuration of the power supply circuit 210. In the example of Fig. 9, the power supply circuit 210 includes a bandgap reference circuit 211, an operational amplifier 212, a resistive element 213, a capacitive element 214, an N-channel MOS transistor 215, and resistive elements 216 and 217.

[0058] The bandgap reference circuit 211 uses the bandgap voltage of silicon to generate a constant reference voltage independent of the power supply voltage VDD or temperature.

[0059] The MOS transistor 215 and the resistor elements 216 and 217 are connected in series between a node to which a power supply voltage VDD is supplied and a node to which a ground voltage VSS is supplied.

[0060] A reference voltage output from the bandgap reference circuit 211 is input to a non-inverting input terminal of the operational amplifier 212, and a voltage obtained by dividing the power supply voltage VDD by resistor elements 216 and 217 is input to an inverting input terminal of the operational amplifier 212. The output terminal of the operational amplifier 212 is connected to the gate of the MOS transistor 215 via a resistor element 213.

[0061] The capacitance element 214 is connected between the gate of the MOS transistor 215 and a node to which the ground voltage VSS is supplied, and the resistance element 213 and the capacitance element 214 form a filter that smoothes the output signal of the operational amplifier 212. The drain voltage of the transistor 215 is output as the power supply voltage Vreg.

[0062] 8, the capacitive element 291 is connected between a VDD terminal to which a power supply voltage VDD is supplied and a VSS terminal to which a ground voltage VSS is supplied. Furthermore, the capacitive element 292 is connected between a node to which a power supply voltage Vreg is supplied and a VSS terminal to which a ground voltage VSS is supplied. The capacitive elements 291 and 292 each function as a bypass capacitor, suppressing sudden fluctuations in the power supply voltage VDD and the power supply voltage Vreg due to noise, etc.

[0063] The oscillator circuit 220 is electrically connected to both ends of the second oscillator 5b via the XI terminal and the XO terminal, and causes the second oscillator 5b to oscillate at a desired frequency to output an oscillation signal Vosc. Specifically, the oscillator circuit 220 receives the signal output from the second oscillator 5b via the XO terminal, amplifies the signal, and supplies the amplified signal to the second oscillator 5b via the XI terminal.

[0064] Fig. 10 is a diagram showing an example configuration of the oscillation circuit 220. In the example of Fig. 10, the oscillation circuit 220 includes P-channel MOS transistors 221 and 222, an N-channel MOS transistor 223, an NPN bipolar transistor 224, and capacitive elements 225 and 226. The MOS transistors 221 and 222 are enhancement type, and the MOS transistor 223 is depletion type.

[0065] The gate of the MOS transistor 221 is electrically connected to the drain of the MOS transistor 221, the gate of the MOS transistor 222, and the drain of the MOS transistor 223. The power supply voltage Vreg is supplied to the sources of the MOS transistor 221 and the MOS transistor 222. The gate and source of the MOS transistor 223 are grounded and are supplied with the ground voltage VSS. The drain of the MOS transistor 222 is electrically connected to the collector of the bipolar transistor 224, one end of the capacitance element 226, and the XI terminal. The base of the bipolar transistor 224 is electrically connected to one end of the capacitance element 225 and the XO terminal. The emitter of the bipolar transistor 224, the other end of the capacitance element 225, and the other end of the capacitance element 226 are grounded and are supplied with the ground voltage VSS.

[0066] In the oscillator circuit 220 configured as described above, a constant current Iref flows through the drain of the MOS transistor 222, and the bipolar transistor 224 performs an amplification operation by receiving the current Iref. The collector signal of the bipolar transistor 224 is output as the oscillation signal Vosc. That is, the bipolar transistor 224 constitutes an amplifier circuit 228 that amplifies the signal from the second oscillator 5b and outputs the oscillation signal Vosc. The MOS transistors 221, 222, and 223 constitute a current source 227 that supplies the current Iref to the amplifier circuit 228. The capacitive elements 225 and 226 function as load capacitances for the second oscillator 5b, and the frequency of the oscillation signal Vosc depends on the capacitance values ​​of the capacitive elements 225 and 226.

[0067] Returning to the explanation of FIG. 8, the oscillation signal Vosc is input to the output circuit 240. When the output enable signal outEN supplied from the logic circuit 250 is at a high level, the output circuit 240 outputs an oscillation signal Vout based on the oscillation signal Vosc, and when the output enable signal outEN is at a low level, the output circuit 240 outputs a signal of the ground voltage VSS. For example, the output circuit 240 may output an oscillation signal Vout obtained by dividing the oscillation signal Vosc by a division ratio set by the output setting data outDT. Furthermore, the output circuit 240 may output an oscillation signal Vout of an output type set by the output setting data outDT. The output type of the oscillation signal Vout may be, for example, a CMOS output or a clipped sign output. Furthermore, the output The circuit 240 may output an oscillation signal Vout with an output capability set by the output setting data outDT. The output setting data outDT is written to the nonvolatile memory 260 during the manufacturing process of the second oscillator 2b. When the second oscillator 2b is in operation, the output setting data outDT stored in the nonvolatile memory 260 is supplied to the output circuit 240 via the logic circuit 250. An example of the configuration of the output circuit 240 is the same as that shown in FIG. 6, and therefore illustration and description thereof will be omitted.

[0068] The logic circuit 250 controls the operation of each circuit. That is, the logic circuit 250 performs operation settings for the second integrated circuit device 4b. Specifically, the logic circuit 250 sets the operation mode of the second oscillator 2b or the second integrated circuit device 4b to one of multiple modes, including an external communication mode and a normal operation mode, based on a control signal input to a predetermined external connection terminal of the second integrated circuit device 4b, and performs control according to the set operation mode. In this embodiment, if a control signal of a predetermined pattern is input from the OE terminal within a predetermined period after the supply of the power supply voltage VDD to the VDD terminal begins, the logic circuit 250 sets the operation mode to the external communication mode after the predetermined period has elapsed. For example, the logic circuit 250 may determine the predetermined period as the period from when the second oscillator 5b starts oscillating due to the supply of the power supply voltage VDD to when it detects that the oscillation has stabilized, or it may count the number of pulses of the oscillation signal Vosc and determine that the predetermined period has elapsed when the count value reaches a predetermined value. Furthermore, for example, the logic circuit 250 may measure the predetermined period based on the output signal of an RC time constant circuit that starts operating when the power supply voltage VDD is supplied.

[0069] In the external communication mode, the logic circuit 250 can perform data communication with an external device (not shown) connected to the OE1 and OUT1 terminals via the OE and OUT terminals. The external device outputs a serial clock signal to the OUT1 terminal in accordance with a predetermined communication standard, and outputs a serial data signal to the OE1 terminal in synchronization with the serial clock signal. Alternatively, the external device acquires a signal output from the logic circuit 250 to the OE1 terminal via the OE terminal. In the external communication mode, the logic circuit 250 samples the serial data signal as various commands at each edge of the serial clock signal, for example, in accordance with the I2C bus standard. Then, the logic circuit 250 performs processes such as setting the operating mode and writing and reading data to and from the nonvolatile memory 260 based on the sampled commands. Note that in this embodiment, the logic circuit 250 communicates with the external device using a two-wire bus communication standard such as the I2C bus. However, the logic circuit 250 may also communicate with the external device using a three-wire or four-wire bus communication standard such as the SPI bus.

[0070] For example, when the logic circuit 250 samples a write command to the nonvolatile memory 260 in the external communication mode, it writes data specified in the write command to the address in the nonvolatile memory 260 specified in the write command. Also, when the logic circuit 250 samples a read command to the nonvolatile memory 260 in the external communication mode, it reads data from the address in the nonvolatile memory 260 specified in the read command, converts it to serial data, and outputs it. An example of a timing chart when data is written to and read from the nonvolatile memory 260 is the same as that shown in FIG.

[0071] Furthermore, for example, when the logic circuit 250 samples a normal operation mode setting command in the external communication mode, it transitions the operation mode from the external communication mode to the normal operation mode. In the normal operation mode, the logic circuit 250 supplies a signal input from outside the second oscillator 2b via the OE1 terminal and the OE terminal to the output circuit 240 as an output enable signal outEN. Therefore, in the normal operation mode, the output of the oscillation signal Vout from the OUT1 terminal is controlled based on the control signal input to the OE1 terminal.

[0072] If a signal of a predetermined pattern is not input from the OE terminal within a predetermined period of time after the supply of the power supply voltage VDD starts, the logic circuit 250 does not set the operation mode to the external communication mode after the predetermined period of time has elapsed, but directly sets it to the normal operation mode.

[0073] The nonvolatile memory 260 is a memory that stores various types of information, such as a MONOS memory or an EEPROM. During the manufacturing process of the second oscillator 2b, various types of information for controlling each circuit, such as output setting data outDT, are stored in the nonvolatile memory 260. When the second oscillator 2b is powered on, the various types of information stored in the nonvolatile memory 260 are transferred to registers (not shown) included in the logic circuit 250, and the various types of information stored in the registers are supplied to each circuit as appropriate.

[0074] The oscillator circuit 220 is an example of a "second oscillator circuit," and the oscillation signal Vosc output from the oscillator circuit 220 is an example of a "second oscillator signal." The power supply circuit 210 is an example of a "second power supply circuit," and the power supply voltage Vreg output from the power supply circuit 210 is an example of a "second power supply voltage." The output circuit 240 is an example of a "second output circuit," and the oscillation signal Vout output from the output circuit 240 is an example of a "second output signal." The logic circuit 250 is an example of a "second logic circuit."

[0075] 1-4. Layout of the first integrated circuit device and the second integrated circuit device Fig. 11 is a diagram showing an example of the layout arrangement of the first integrated circuit device 4a in the first embodiment. In the example of Fig. 11, the first integrated circuit device 4a has a rectangular semiconductor substrate 100 having four sides 100a, 100b, 100c, and 100d in a plan view. The power supply circuit 110, the oscillator circuit 120, the frequency control circuit 130, the output circuit 140, the logic circuit 150, the nonvolatile memory 160, the variable capacitance circuits 171 and 172, and the capacitance elements 191 and 192 shown in Fig. 2 are formed on the semiconductor substrate 100.

[0076] The power supply circuit 110 is arranged in a rectangular area along sides 100c and 100d. The oscillation circuit 120 is arranged in a rectangular area along sides 100b. The output circuit 140 is arranged in a rectangular area along sides 100a and 100d. The logic circuit 150 and non-volatile memory 160 are arranged in a rectangular area along side 100c. The frequency control circuit 130 is arranged in a first area A1 other than the areas where the power supply circuit 110, the oscillation circuit 120, the output circuit 140, the logic circuit 150, and the non-volatile memory 160 are arranged. In this embodiment, the frequency control circuit 130 and the variable capacitance circuits 171 and 172 are located between two circuits out of the oscillation circuit 120, the output circuit 140, and the power supply circuit 110. In the example of FIG. 11, the frequency control circuit 130 and the variable capacitance circuits 171 and 172 are located between the output circuit 140 and the power supply circuit 110. Although not shown in FIG. 11, the capacitive elements 191 and 192 are arranged in a vacant region of the semiconductor substrate 100.

[0077] A rectangular pad 181 serving as a VDD terminal is arranged along side 100a in the layout area for the output circuit 140. A rectangular pad 182 serving as a VSS terminal is arranged along sides 100c and 100d in the layout area for the power supply circuit 110. A rectangular pad 183 serving as an OUT terminal is arranged along sides 100a and 100d in the layout area for the output circuit 140. A rectangular pad 184 serving as an OE terminal is arranged along side 100c in the layout area for the logic circuit 150 and the nonvolatile memory 160. A rectangular pad 185 serving as an XO terminal and a rectangular pad 186 serving as an XI terminal are arranged along side 100b in the layout area for the oscillator circuit 120.

[0078] When the intersection of side 100a and side 100b is the origin, the direction along side 100a is the x direction, and the direction along side 100b is the y direction, the x coordinate value of the center point of pad 185 and the x coordinate value of the center point of pad 186 are both x11, and the y coordinate value of the center point of pad 185 is y13. is greater than the y-coordinate value y12 of the center point of pad 186. The x-coordinate value of the center point of pad 181 and the x-coordinate value of the center point of pad 184 are both x12 which is greater than x11, and the x-coordinate value of the center point of pad 183 and the x-coordinate value of the center point of pad 182 are both x13 which is greater than x12. The y-coordinate value of the center point of pad 181 and the y-coordinate value of the center point of pad 183 are both y11 which is less than y12, and the y-coordinate value of the center point of pad 184 and the y-coordinate value of the center point of pad 182 are both y14 which is greater than y13.

[0079] Fig. 12 is a diagram showing an example of the layout arrangement of the second integrated circuit device 4b in the first embodiment. In the example of Fig. 12, the second integrated circuit device 4b has a rectangular semiconductor substrate 200 having four sides 200a, 200b, 200c, and 200d in a plan view. The power supply circuit 210, the oscillator circuit 220, the output circuit 240, the logic circuit 250, the nonvolatile memory 260, and the capacitive elements 291 and 292 shown in Fig. 8 are formed on the semiconductor substrate 200.

[0080] The power supply circuit 210 is arranged in a rectangular area along sides 200c and 200d. The oscillator circuit 220 is arranged in a rectangular area along sides 200b. The output circuit 240 is arranged in a rectangular area along sides 200a and 200d. The logic circuit 250 and non-volatile memory 260 are arranged in a rectangular area along side 200c. Although not shown in FIG. 12, the capacitive elements 291 and 292 are arranged in empty areas of the semiconductor substrate 200.

[0081] A rectangular pad 281 serving as a VDD terminal is arranged along side 200a in the layout area for the output circuit 240. A rectangular pad 282 serving as a VSS terminal is arranged along sides 200c and 200d in the layout area for the power supply circuit 210. A rectangular pad 283 serving as an OUT terminal is arranged along sides 200a and 200d in the layout area for the output circuit 240. A rectangular pad 284 serving as an OE terminal is arranged along side 200c in the layout area for the logic circuit 250 and the nonvolatile memory 260. A rectangular pad 285 serving as an XO terminal and a rectangular pad 286 serving as an XI terminal are arranged along side 200b in the layout area for the oscillator circuit 220.

[0082] If the intersection of sides 200a and 200b is the origin, the direction along side 200a is the x direction, and the direction along side 200b is the y direction, the x coordinate value of the center point of pad 285 and the x coordinate value of the center point of pad 286 are both x21, and the y coordinate value y23 of the center point of pad 285 is greater than the y coordinate value y22 of the center point of pad 286. The x coordinate value of the center point of pad 281 and the x coordinate value of the center point of pad 284 are both x22 greater than x21, and the x coordinate value of the center point of pad 283 and the x coordinate value of the center point of pad 282 are both x23 greater than x22. The y coordinate value of the center point of pad 281 and the y coordinate value of the center point of pad 283 are both y21 smaller than y22, and the y coordinate value of the center point of pad 284 and the y coordinate value of the center point of pad 282 are both y24 greater than y23.

[0083] In the examples of Figures 11 and 12, pads 181 and 281 have the same size and shape, pads 182 and 282 have the same size and shape, pads 183 and 283 have the same size and shape, pads 184 and 284 have the same size and shape, pads 185 and 285 have the same size and shape, and pads 186 and 286 have the same size and shape.

[0084] Furthermore, the first integrated circuit device 4a and the second integrated circuit device 4b are the same size, and the relative positional relationship between the pads 181 to 186 is the same as the relative positional relationship between the pads 281 to 286. In other words, when the center point of any two corresponding pads, for example, the pads 181 and 182, is assumed to be the origin, the center of each of the pads 181 to 186 is The coordinates of the center point and the coordinates of the center points of the pads 281 to 286 coincide with each other. In particular, in the examples of Figures 11 and 12, the coordinates (x12, y11) of the center point of pad 181 and the coordinates (x22, y21) of the center point of pad 281 are equal, the coordinates (x13, y14) of the center point of pad 182 and the coordinates (x23, y24) of the center point of pad 282 are equal, the coordinates (x13, y11) of the center point of pad 183 and the coordinates (x23, y21) of the center point of pad 283 are equal, the coordinates (x12, y14) of the center point of pad 184 and the coordinates (x22, y24) of the center point of pad 284 are equal, the coordinates (x11, y13) of the center point of pad 185 and the coordinates (x21, y23) of the center point of pad 285 are equal, and the coordinates (x11, y12) of the center point of pad 186 and the coordinates (x21, y22) of the center point of pad 286 are equal. That is, the first integrated circuit device 4a and the second integrated circuit device 4b have the same size, and the positions of the pads 181 to 186 on the first integrated circuit device 4a are the same as the positions of the pads 281 to 286 on the second integrated circuit device 4b.

[0085] Furthermore, the layout area of ​​the power supply circuit 110 and the layout area of ​​the power supply circuit 210 are the same or nearly the same in size, shape, and position. The layout area of ​​the oscillator circuit 120 and the layout area of ​​the oscillator circuit 220 are the same or nearly the same in size, shape, and position. The layout area of ​​the output circuit 140 and the layout area of ​​the output circuit 240 are the same or nearly the same in size, shape, and position. The layout area of ​​the logic circuit 150 and the nonvolatile memory 160 and the layout area of ​​the logic circuit 250 and the nonvolatile memory 260 are the same or nearly the same in size, shape, and position. Therefore, it is possible to standardize the layout of at least a portion of the multiple wiring patterns connecting these multiple circuits. Furthermore, at least one pair of the oscillator circuit 120 and the oscillator circuit 220, the output circuit 140 and the output circuit 240, the power supply circuit 110 and the power supply circuit 210, and the logic circuit 150 and the logic circuit 250 may have the same circuit configuration. If the oscillator circuit 120 and the oscillator circuit 220 have the same circuit configuration, they can have a common layout, if the output circuit 140 and the output circuit 240 have the same circuit configuration, they can have a common layout, if the power supply circuit 110 and the power supply circuit 210 have the same circuit configuration, they can have a common layout, and if the logic circuit 150 and the logic circuit 250 have the same circuit configuration, they can have a common layout. Therefore, the number of development steps for the first integrated circuit device 4a or the second integrated circuit device 4b can be reduced.

[0086] Furthermore, while the first integrated circuit device 4a includes a frequency control circuit 130, the second integrated circuit device 4b does not. Therefore, in order to effectively utilize the second area A2 of the second integrated circuit device 4b, which corresponds to the first area A1 in which the frequency control circuit 130 is arranged in the first integrated circuit device 4a, at least one of the following is arranged in the second area A2: capacitive elements 291 and 292 which are bypass capacitors; capacitive element 214 which is a smoothing capacitor included in the power supply circuit 210; current source 227 included in the oscillator circuit 220; and bandgap reference circuit 211 included in the power supply circuit 210. In the example of FIG. 12 , the capacitive elements 291, 292, and 214, the current source 227, and the bandgap reference circuit 211, which are larger in size than the capacitive elements 191, 192, and 114, the current source 127, and the bandgap reference circuit 111, respectively, are arranged in the second area A2. Increasing the size of the capacitive elements 291 and 292, which are bypass capacitors, increases their capacitance values, improving the effect of suppressing fluctuations in the power supply voltage VDD and the power supply voltage Vreg. Increasing the size of the capacitive element 214, which is a smoothing capacitor, increases its capacitance value, improving the effect of reducing noise in the power supply voltage Vreg by the low-pass filter formed by the resistive element 113 and the capacitive element 114. Increasing the size of the bandgap reference circuit 211 and the current source 227 reduces 1 / f noise generated in the bandgap reference circuit 211 and the current source 227, reducing the phase noise of the oscillation signal Vout. In FIG. 13, the solid line shows an example of the phase noise of the oscillation signal Vout output from the second oscillator 2b. In FIG. 13, the dashed line shows an example of the phase noise of the oscillation signal Vout output from the first oscillator 2a. In FIG. 13, the horizontal axis is the offset frequency with the target frequency set to 0, and the vertical axis is the phase noise. In the example of Fig. 13, the phase noise of the second oscillator 2b is smaller in the frequency band where the offset frequency is 1 MHz or less.

[0087] Furthermore, since the second oscillator 2b does not include a frequency control circuit having a temperature compensation circuit and an AFC circuit in the second integrated circuit device 4b, the current consumption is reduced compared to the first oscillator 2a having the first integrated circuit device 4a including the frequency control circuit 130 having the temperature compensation circuit 136 and the AFC circuit 137.

[0088] On the other hand, since the first integrated circuit device 4a of the first oscillator 2a includes the temperature compensation circuit 136, when the temperature compensation function is enabled, the oscillation signal Vout exhibits excellent frequency-temperature characteristics. FIG. 14 shows an example of the frequency-temperature characteristics of the oscillation signal Vout output from the first oscillator 2a when the temperature compensation function is enabled, using a solid line. In FIG. 14, the dashed line shows an example of the frequency-temperature characteristics of the oscillation signal Vout output from the second oscillator 2b. In FIG. 14, the horizontal axis represents temperature, and the vertical axis represents frequency deviation from the target frequency. In the example of FIG. 14, the frequency-temperature characteristics of the first resonator 5a and the second resonator 5b are cubic curves. Therefore, the frequency-temperature characteristics of the oscillation signal Vout output from the second oscillator 2b, which does not have a temperature compensation function, are similar to those of the second resonator 5b, and the frequency deviation varies within a range of approximately ±20 ppm in the temperature range from −40°C to +100°C. In contrast, the frequency deviation of the oscillation signal Vout output from the first oscillator 2a falls within a range of approximately ±2 ppm in the temperature range from −40° C. to +100° C.

[0089] Furthermore, since the first integrated circuit device 4a of the first oscillator 2a includes the AFC circuit 137, when the frequency variable function is enabled, the oscillation signal Vout can be set to a desired target frequency within a predetermined frequency range.

[0090] 1-5. Structure of the first oscillator and the second oscillator 15, 16, and 17 are diagrams showing an example of the structure of the first oscillator 2a and the second oscillator 2b. FIG. 15 is a perspective view of the first oscillator 2a and the second oscillator 2b, and FIG. 16 is a cross-sectional view of the first oscillator 2a and the second oscillator 2b. FIG. 17 is a plan view showing a plurality of electrodes formed in the first container 3a and the second container 3b. Note that FIG. 16 is a cross-sectional view of the first oscillator 2a and the second oscillator 2b taken along line AA in FIG. 17.

[0091] 15 and 16, the first oscillator 2a has a first integrated circuit device 4a, a first vibrator 5a, a first container 3a that houses the first integrated circuit device 4a and the first vibrator 5a, and a first lid 6a that hermetically seals the housing space 7 that houses the first vibrator 5a. Similarly, the second oscillator 2b has a second integrated circuit device 4b, a second vibrator 5b, a second container 3b that houses the second integrated circuit device 4b and the second vibrator 5b, and a second lid 6b that hermetically seals the housing space 7 that houses the second vibrator 5b.

[0092] The first vibrator 5a and the second vibrator 5b are, for example, AT-cut quartz crystal vibrators based on quartz crystal, and oscillate at a resonant frequency determined by their external shape and dimensions, thereby oscillating at a desired frequency. In this embodiment, the first vibrator 5a and the second vibrator 5b are of the same type and have the same size, shape, and terminal positions. However, the first vibrator 5a and the second vibrator 5b may be of different types and may differ in at least one of size, shape, and terminal positions, as long as they can be housed in the same type of first container 3a and second container 3b, respectively.

[0093] The first container 3a and the second container 3b are made of ceramic or the like, and as shown in FIGS. 16 and 17, are constructed by laminating a substrate 31, a first frame substrate 32, and a second frame substrate 33. 16 and 17, electrodes 41, 42, 43, 44, 45, and 46 are provided on a first surface 31a of the substrate 31, and a plurality of external terminals 8 are provided on a second surface 31b of the substrate 31. The plurality of external terminals 8 correspond to the VDD1 terminal, VSS1 terminal, OUT1 terminal, and OE1 terminal shown in FIG. 2 or 8, respectively. Each external terminal 8 and each electrode 41, 42, 43, and 44 are electrically connected by wiring (not shown).

[0094] 17, the pads 181, 182, 183, 184, 185, and 186 of the first integrated circuit device 4a shown in FIG. 11 are electrically and mechanically connected to the electrodes 41, 42, 43, 44, 45, and 46 provided on the first surface 31a of the substrate 31 via bonding members 61 such as conductive adhesive or gold bumps. The pads 181, 182, 183, 184, 185, and 186 correspond to the VDD terminal, VSS terminal, OUT terminal, OE terminal, XO terminal, and XI terminal of the first oscillator 2a shown in FIG. 2, respectively.

[0095] 17, the pads 281, 282, 283, 284, 285, and 286 of the second integrated circuit device 4b shown in FIG. 12 are electrically and mechanically connected to the electrodes 41, 42, 43, 44, 45, and 46 provided on the first surface 31a of the substrate 31 via bonding members 61 such as conductive adhesive or gold bumps. The pads 281, 282, 283, 284, 285, and 286 correspond to the VDD terminal, VSS terminal, OUT terminal, OE terminal, XO terminal, and XI terminal of the second oscillator 2b shown in FIG. 8, respectively.

[0096] 16 and 17, the first frame substrate 32 is an annular substrate from which a portion including the position of the first integrated circuit device 4a or the second integrated circuit device 4b has been removed. Electrodes 75 and 76 are provided on a first surface 32a of the first frame substrate 32, and a second surface 32b of the first frame substrate 32 is bonded to a second surface 31b of the substrate 31. As indicated by the dashed-dotted lines in FIG. 17, the terminals 55 and 56 of the first vibrator 5a or the second vibrator 5b are electrically and mechanically connected to the electrodes 75 and 76 provided on the first surface 32a of the first frame substrate 32 via bonding members 62 such as conductive adhesive or gold bumps. The electrodes 75 and 76 provided on the first surface 32a of the first frame substrate 32 are electrically connected to the electrodes 45 and 46 provided on the first surface 31a of the substrate 31 via wiring (not shown).

[0097] 16, the second frame substrate 33 is an annular substrate from which a portion including the position of the first vibrator 5a or the second vibrator 5b has been removed. The first lid 6a or the second lid 6b is made of metal, ceramic, glass, or the like, and is joined to the second frame substrate 33 via a joining member 63 such as a seal ring or low-melting-point glass, thereby forming an accommodating space 7 that accommodates the first vibrator 5a or the second vibrator 5b and is hermetically sealed. The accommodating space 7 is an airtight space and is in a reduced pressure state, preferably closer to a vacuum.

[0098] In this embodiment, the first container 3a and the second container 3b are the same type of container. Therefore, the shapes of the electrodes 41, 42, 43, 44, 45, and 46 provided in the first container 3a are the same as the shapes of the electrodes 41, 42, 43, 44, 45, and 46 provided in the second container 3b. Furthermore, the positions of the electrodes 41, 42, 43, 44, 45, and 46 in the first container 3a are the same as the positions of the electrodes 41, 42, 43, 44, 45, and 46 in the second container 3b. 11 and 12, the first integrated circuit device 4a and the second integrated circuit device 4b have the same size, and the positions of the pads 181, 182, 183, 184, 185, and 186 on the first integrated circuit device 4a are the same as the positions of the pads 281, 282, 283, 284, 285, and 286 on the second integrated circuit device 4b. Therefore, as shown in FIG. 17, the positions where the pads 181, 182, 183, 184, 185, and 186 on the first integrated circuit device 4a are joined to the electrodes 41, 42, 43, 44, 45, and 46 on the first container 3a are joined to the pads 281, 282, 283, 284, 285, and 286 on the second integrated circuit device 4b are joined to the electrodes 41, 42, 43, 44, and 45 on the second container 3b. , 46 are joined at the same positions. That is, the first integrated circuit device 4a and the second integrated circuit device 4b can be mounted in the same type of first container 3a and second container 3b, respectively. Therefore, the man-hours required for determining mounting conditions and man-hours required for designing the container are not required for either the first oscillator 2a or the second oscillator 2b, and the overall manufacturing cost of the first oscillator 2a and the second oscillator 2b is reduced.

[0099] Furthermore, because the position where the first integrated circuit device 4a is bonded to the first container 3a and the position where the second integrated circuit device 4b is bonded to the second container 3b are the same, when the first container 3a and the second container 3b are stacked in a plan view, the first integrated circuit device 4a and the second integrated circuit device 4b overlap. Therefore, according to the examples of Figures 11 and 12, the oscillator circuit 120 and the oscillator circuit 220 at least partially overlap, the output circuit 140 and the output circuit 240 at least partially overlap, the power supply circuit 110 and the power supply circuit 210 at least partially overlap, and the logic circuit 150 and the logic circuit 250 at least partially overlap. In other words, by arranging each pair of these multiple circuits so that they at least partially overlap, it becomes possible to standardize many parts of the layout of the first integrated circuit device 4a and the layout of the second integrated circuit device 4b, thereby reducing the number of steps required to develop the first integrated circuit device 4a or the second integrated circuit device 4b.

[0100] The electrodes 41, 42, 43, 44, 45, and 46 of the first container 3a are an example of the "first to Nth electrodes," and the electrodes 41, 42, 43, 44, 45, and 46 of the second container 3b are an example of the "N+1th to 2Nth electrodes." The pads 181, 182, 183, 184, 185, and 186 of the first integrated circuit device 4a are an example of the "first to Nth pads," and the pads 281, 282, 283, 284, 285, and 286 of the second integrated circuit device 4b are an example of the "N+1th to 2Nth pads." In this embodiment, the integer N is 6.

[0101] 1-6. Oscillator manufacturing method 18 is a flow chart showing an example of the steps of the method for manufacturing the oscillator of this embodiment. For example, a manufacturing device (not shown) performs each step of FIG.

[0102] In the example of Figure 18, if a first oscillator 2a is to be manufactured in step S1, in step S2, the manufacturing equipment places a first resonator 5a and a first integrated circuit device 4a in a first container 3a to manufacture the first oscillator 2a.

[0103] Next, if a second oscillator 2b is to be manufactured in step S3, the manufacturing equipment houses the second resonator 5b and the second integrated circuit device 4b in a second container 3b to manufacture the second oscillator 2b in step S4.

[0104] FIG. 19 is a flowchart showing an example of the detailed procedure of step S2 in FIG.

[0105] In the example of FIG. 19, first, in step S21, the manufacturing equipment connects the pads 181 to 186 of the first integrated circuit device 4a to the electrodes 41 to 46 of the first container 3a, respectively.

[0106] Next, in step S22, the manufacturing equipment connects the terminals 55 and 56 of the first vibrator 5a to the electrodes 75 and 76 of the first container 3a, respectively.

[0107] Next, in step S23, the manufacturing equipment joins the first lid 6a to the first container 3a.

[0108] Next, in step S24, if the first oscillator 2a having a temperature compensation function is to be manufactured, the manufacturing device creates temperature compensation data cmpDT in step S25. If the first oscillator 2a to be manufactured does not have a temperature compensation function in step S24, the manufacturing device does not perform step S25.

[0109] Next, in step S26, the manufacturing equipment sets whether or not to operate the temperature compensation circuit 136. Specifically, if the first oscillator 2a to be manufactured is one that has a temperature compensation function, the manufacturing equipment writes a temperature compensation function setting bit cmpEN into the nonvolatile memory 160 to operate the temperature compensation circuit 136, and if the first oscillator 2a to be manufactured is one that does not have a temperature compensation function, the manufacturing equipment writes a temperature compensation function setting bit cmpEN into the nonvolatile memory 160 to prevent the temperature compensation circuit 136 from operating.

[0110] Next, in step S27, the manufacturing equipment sets whether or not to operate the AFC circuit 137. Specifically, if the first oscillator 2a to be manufactured is one that has a frequency variable function, the manufacturing equipment writes a frequency variable function setting bit afcEN for operating the AFC circuit 137 into the nonvolatile memory 160, and if the first oscillator 2a to be manufactured is one that does not have a frequency variable function, the manufacturing equipment writes a frequency variable function setting bit afcEN for not operating the AFC circuit 137 into the nonvolatile memory 160.

[0111] Finally, in step S28, the manufacturing equipment sets the output type, output capacity, and frequency division ratio of the output circuit 140. Specifically, the manufacturing equipment writes the output setting data outDT, in which the output type, output capacity, and frequency division ratio are set, into the nonvolatile memory 160.

[0112] FIG. 20 is a flowchart showing an example of the detailed procedure of step S4 in FIG.

[0113] In the example of FIG. 20, first, in step S41, the manufacturing equipment connects the pads 281 to 286 of the second integrated circuit device 4b to the electrodes 41 to 46 of the second container 3b, respectively.

[0114] Next, in step S42, the manufacturing equipment connects terminals 55 and 56 of second vibrator 5b to electrodes 75 and 76 of second container 3b, respectively.

[0115] Next, in step S43, the manufacturing equipment joins the second lid 6b to the second container 3b.

[0116] Finally, in step S44, the manufacturing equipment sets the output type, output capacity, and frequency division ratio of the output circuit 240. Specifically, the manufacturing equipment writes the output setting data outDT, in which the output type, output capacity, and frequency division ratio are set, into the nonvolatile memory 260.

[0117] The first oscillator 2a and the second oscillator 2b may be manufactured in the same factory or in different factories, and may be manufactured in the same country or in different countries.

[0118] 1-7.Effects As described above, according to the first embodiment, the first oscillator 2a is manufactured by housing the first resonator 5a and the first integrated circuit device 4a having the frequency control circuit 130 in the first container 3a, and the second oscillator 2b is manufactured by housing the second resonator 5b and the second integrated circuit device 4b having no frequency control circuit in the second container 3b. This makes it possible to manufacture multiple types of oscillators with different frequency control functions. Furthermore, since the second integrated circuit device 4b does not have a frequency control circuit, the risk of the characteristics of the oscillation signal Vout being degraded by an unnecessary frequency control circuit in the second oscillator 2b is reduced. Furthermore, according to the first embodiment, the first container 3a and the second container 3b are the same type of container, so that the development of the first oscillator 2a or the second oscillator 2b does not require the man-hours for setting mounting conditions or the man-hours for container design, and this makes it possible to manufacture multiple types of oscillators. Therefore, the oscillator can be efficiently manufactured.

[0119] Furthermore, in the first embodiment, the relative positional relationship between the pads 181-186 in the first integrated circuit device 4a is the same as the relative positional relationship between the pads 281-286 in the second integrated circuit device 4b. Therefore, according to the first embodiment, the six positions where the pads 181-186 are connected to the electrodes 41-46 of the first container 3a can be the same as the six positions where the pads 281-286 are connected to the electrodes 41-46 of the second container 3b, thereby improving the degree of freedom in the size and shape of the electrodes 41-46.

[0120] Furthermore, in the first embodiment, the first vibrator 5a and the second vibrator 5b have the same size and shape, and the first integrated circuit device 4a and the second integrated circuit device 4b have the same size and shape, so that the first container 3a and the second container 3b can be made to an optimal size.

[0121] Furthermore, in the first embodiment, at least one of the capacitive elements 291 and 292, which are bypass capacitors, the capacitive element 214, which is a smoothing capacitor, the current source 227, and the bandgap reference circuit 211 is arranged in a larger size in the second area A2 of the second integrated circuit device 4b. Therefore, according to the first embodiment, the noise reduction effect of the oscillation signal Vout in the second integrated circuit device 4b is improved, and the characteristics of the second oscillator 2b can be improved.

[0122] Furthermore, according to the first embodiment, it is possible to standardize the layout of each circuit of the first integrated circuit device 4a except for the frequency control circuit 130 and the layout of each circuit of the second integrated circuit device 4b, thereby reducing the man-hours required for developing the first integrated circuit device 4a or the second integrated circuit device 4b, thereby reducing the manufacturing cost of the first oscillator 2a or the second oscillator 2b.

[0123] 2. Second embodiment In the following, in the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and explanations of the same components as those in the first embodiment are omitted or simplified, and differences from the first embodiment will be mainly described.

[0124] The functional block diagram of the first integrated circuit device 4a in the second embodiment is the same as that in Fig. 2, and the functional block diagram of the second integrated circuit device 4b is the same as that in Fig. 8, so illustration and description thereof will be omitted. In addition, an example of the procedure for manufacturing the oscillator in the second embodiment is the same as that in Figs. 18 to 20, so illustration and description thereof will be omitted.

[0125] In the second embodiment, the layout arrangement of the first integrated circuit device 4a and the second integrated circuit device 4b differs from that of the first embodiment, and the structures of the first oscillator 2a and the second oscillator 2b differ from that of the first embodiment.

[0126] Fig. 21 is a diagram showing an example of the layout arrangement of the first integrated circuit device 4a in the second embodiment. In the example of Fig. 21, the first integrated circuit device 4a has a rectangular semiconductor substrate 100 having four sides 100a, 100b, 100c, and 100d in a plan view, and a power supply circuit 110, an oscillator circuit 120, a frequency control circuit 130, an output circuit 140, a logic circuit 150, a nonvolatile memory 160, variable capacitance circuits 171 and 172, and capacitance elements 191 and 192 are formed on the semiconductor substrate 100.

[0127] In the example of FIG. 21, the power supply circuit 110 is arranged in a rectangular area along the sides 100c and 100d. The oscillation circuit 120 is arranged in a rectangular area along the side 100b. The output circuit 140 is arranged in a rectangular area along the sides 100a and 100d. The logic circuit 150 is arranged in a rectangular area along the side 100c and an L-shaped area surrounding the area where the output circuit 140 is arranged. The nonvolatile memory 160 is arranged in a rectangular region along the side 100c. The frequency control circuit 130 and variable capacitance circuits 171 and 172 are arranged in a region other than the regions where the power supply circuit 110, the oscillator circuit 120, the output circuit 140, the logic circuit 150, and the nonvolatile memory 160 are arranged. Although not shown in FIG. 21 , the capacitance elements 191 and 192 are arranged in a vacant region of the semiconductor substrate 100.

[0128] A rectangular pad 181 serving as a VDD terminal is arranged along side 100a in the layout area for the output circuit 140. A rectangular pad 182 serving as a VSS terminal is arranged along sides 100c and 100d in the layout area for the power supply circuit 110. A rectangular pad 183 serving as an OUT terminal is arranged along sides 100a and 100d in the layout area for the output circuit 140. A rectangular pad 184 serving as an OE terminal is arranged along side 100c in the layout area for the logic circuit 150 and the nonvolatile memory 160. A rectangular pad 185 serving as an XO terminal and a rectangular pad 186 serving as an XI terminal are arranged along side 100b in the layout area for the oscillator circuit 120.

[0129] If the intersection of sides 100a and 100b is the origin, the direction along side 100a is the x direction, and the direction along side 100b is the y direction, the x coordinate value of the center point of pad 185 and the x coordinate value of the center point of pad 186 are both x11, and the y coordinate value y13 of the center point of pad 185 is greater than the y coordinate value y12 of the center point of pad 186. The x coordinate value of the center point of pad 181 and the x coordinate value of the center point of pad 184 are both x12 greater than x11, and the x coordinate value of the center point of pad 183 and the x coordinate value of the center point of pad 182 are both x13 greater than x12. The y coordinate value of the center point of pad 181 and the y coordinate value of the center point of pad 183 are both y11 smaller than y12, and the y coordinate value of the center point of pad 182 are both y14 greater than y13.

[0130] Fig. 22 is a diagram showing an example of the layout arrangement of the second integrated circuit device 4b in the second embodiment. In the example of Fig. 22, the second integrated circuit device 4b has a rectangular semiconductor substrate 200 having four sides 200a, 200b, 200c, and 200d in a plan view, and a power supply circuit 210, an oscillator circuit 220, an output circuit 240, a logic circuit 250, a nonvolatile memory 260, and capacitive elements 291 and 292 are formed on the semiconductor substrate 200.

[0131] In the example of FIG. 22, the power supply circuit 210 is arranged in a rectangular area along sides 200c and 200d. The oscillator circuit 220 is arranged in a rectangular area along sides 200a, 200b, and 200c. The output circuit 240 is arranged in a rectangular area along sides 200a and 200d. The logic circuit 250 and the nonvolatile memory 260 are arranged in areas other than the areas where the power supply circuit 210, the oscillator circuit 220, and the output circuit 240 are arranged. Although not shown in FIG. 22, the capacitive elements 291 and 292 are arranged in empty areas of the semiconductor substrate 200.

[0132] A rectangular pad 281 serving as a VDD terminal is arranged along side 200a in the placement region of the output circuit 240. A rectangular pad 282 serving as a VSS terminal is arranged along sides 200c and 200d in the placement region of the power supply circuit 210. A rectangular pad 283 serving as an OUT terminal is arranged along sides 200a and 200d in the placement region of the output circuit 240. A rectangular pad 284 serving as an OE terminal is arranged along side 200c in the placement region of the logic circuit 250 and the non-volatile memory 260. A rectangular pad 285 serving as an XO terminal is arranged along sides 200b and 200c in the placement region of the oscillator circuit 220. A rectangular pad 286 serving as an XI terminal is arranged along sides 200a and 200b in the placement region of the oscillator circuit 220.

[0133] The intersection of the side 200a and the side 200b is the origin, and the direction along the side 200a is the x-direction. When the direction along 0b is the y direction, the x-coordinate value of the center point of pad 285 and the x-coordinate value of the center point of pad 286 are both x21, the x-coordinate value of the center point of pad 281 and the x-coordinate value of the center point of pad 284 are both x22 which is larger than x21, and the x-coordinate value of the center point of pad 283 and the x-coordinate value of the center point of pad 282 are both x23 which is larger than x22. The y-coordinate value of the center point of pad 286, the y-coordinate value of the center point of pad 281 and the y-coordinate value of the center point of pad 283 are all y21, and the y-coordinate value of the center point of pad 285, the y-coordinate value of the center point of pad 284 and the y-coordinate value of the center point of pad 282 are all y22 which is larger than y21.

[0134] In the examples of Figures 21 and 22, pads 181 and 281 have the same size and shape, pads 182 and 282 have the same size and shape, pads 183 and 283 have the same size and shape, pads 184 and 284 have the same size and shape, pads 185 and 285 have the same size and shape, and pads 186 and 286 have the same size and shape.

[0135] Furthermore, although the first integrated circuit device 4a and the second integrated circuit device 4b are different in size, the relative positional relationship in the x direction of pads 181 to 186 is the same as the relative positional relationship in the x direction of pads 281 to 286. In other words, when the center point of any two corresponding pads, for example, pad 181 and pad 182, is assumed to be the origin, the x coordinate of the center point of pads 181 to 186 matches the x coordinate of the center point of pads 281 to 286. 21 and 22, the x-coordinate value x11 of the center point of pads 185 and 186 is equal to the x-coordinate value x21 of the center point of pads 285 and 286, the x-coordinate value x12 of the center point of pads 181 and 184 is equal to the x-coordinate value x22 of the center point of pads 281 and 284, and the x-coordinate value x13 of the center point of pads 182 and 183 is equal to the x-coordinate value x23 of the center point of pads 282 and 283. In addition, the difference between the y-coordinate value y12 of the center point of pad 185 and the y-coordinate value y11 of the center point of pad 186 is equal to the difference between the y-coordinate value y22 of the center point of pad 285 and the y-coordinate value y21 of the center point of pad 286.

[0136] Furthermore, the layout area of ​​the power supply circuit 110 and the layout area of ​​the power supply circuit 210 are the same or nearly the same in size and shape. The layout area of ​​the oscillator circuit 120 and the layout area of ​​the oscillator circuit 220 are the same or nearly the same in size and shape. The layout area of ​​the output circuit 140 and the layout area of ​​the output circuit 240 are the same or nearly the same in size, shape, and position. The area combining the layout area of ​​the logic circuit 150 and the nonvolatile memory 160 with the remaining layout area of ​​the logic circuit 150 and the layout area of ​​the logic circuit 250 and the nonvolatile memory 260 are the same or nearly the same in size and shape. Therefore, it is possible to standardize the layout of some of the multiple wiring patterns connecting these multiple circuits. Furthermore, at least one pair of the oscillator circuit 120 and the oscillator circuit 220, the output circuit 140 and the output circuit 240, the power supply circuit 110 and the power supply circuit 210, and the logic circuit 150 and the logic circuit 250 may have the same circuit configuration. If the oscillator circuit 120 and the oscillator circuit 220 have the same circuit configuration, they can have a common layout, if the output circuit 140 and the output circuit 240 have the same circuit configuration, they can have a common layout, if the power supply circuit 110 and the power supply circuit 210 have the same circuit configuration, they can have a common layout, and if the logic circuit 150 and the logic circuit 250 have the same circuit configuration, they can have a common layout. Therefore, the number of development steps for the first integrated circuit device 4a or the second integrated circuit device 4b can be reduced.

[0137] In this embodiment, the frequency control circuit 130 and the variable capacitance circuits 171 and 172 are located between two of the oscillation circuit 120, the output circuit 140, and the power supply circuit 110. When the oscillation circuit 120 corresponds to the oscillation circuit 220, the output circuit 140 corresponds to the output circuit 240, and the power supply circuit 110 corresponds to the power supply circuit 210, the first integrated circuit The distance between the two circuits of the second integrated circuit device 4b corresponding to the two circuits of the device 4a is smaller than the distance between the two circuits of the first integrated circuit device 4a. In the example of FIG. 21, the frequency control circuit 130 and the variable capacitance circuits 171 and 172 are located between the output circuit 140 and the power supply circuit 110. Comparing FIG. 21 with FIG. 22, the distance between the two circuits, the output circuit 240 corresponding to the output circuit 140 and the power supply circuit 210 corresponding to the power supply circuit 110, is smaller than the distance between the output circuit 140 and the power supply circuit 110. In other words, since the second integrated circuit device 4b does not include a frequency control circuit or a variable capacitance circuit, the layout area for these circuits is unnecessary, and the device can be made smaller than the first integrated circuit device 4a. Furthermore, since the second integrated circuit device 4b does not include a frequency control circuit, current consumption is reduced compared to the first integrated circuit device 4a, which includes the frequency control circuit 130.

[0138] The perspective view and cross-sectional view of the first oscillator 2a and the second oscillator 2b in the second embodiment are the same as those in Figs. 15 and 16, respectively, and therefore will not be shown or described again. Fig. 23 is a plan view showing a plurality of electrodes formed in the first container 3a of the first oscillator 2a in the second embodiment. Fig. 24 is a plan view showing a plurality of electrodes formed in the second container 3b of the second oscillator 2b in the second embodiment. Note that Fig. 16 corresponds to a cross-sectional view of the first oscillator 2a and the second oscillator 2b taken along line AA in Figs. 23 and 24.

[0139] In the second embodiment, as in the first embodiment, the first container 3a and the second container 3b are the same type of container. Therefore, as shown in Figures 23 and 24, the shapes of the electrodes 41, 42, 43, 44, 45, and 46 provided in the first container 3a are the same as the shapes of the electrodes 41, 42, 43, 44, 45, and 46 provided in the second container 3b. Furthermore, the positions of the electrodes 41, 42, 43, 44, 45, and 46 in the first container 3a are the same as the positions of the electrodes 41, 42, 43, 44, 45, and 46 in the second container 3b.

[0140] 21 and 22, the first integrated circuit device 4a and the second integrated circuit device 4b are different in size, and the positions of the pads 181-186 on the first integrated circuit device 4a are different from the positions of the pads 281-286 on the second integrated circuit device 4b. However, the x coordinates of the pads 181-186 and the pads 281-286 are the same, and the difference in y coordinates between the pads 185 and 186 is equal to the difference in y coordinates between the pads 285 and 286. Therefore, the electrodes 45 and 46 in FIG. 23 or 24 have the same shape as the electrodes 45 and 46 in FIG. 17, respectively, and the tips of the electrodes 41-44 in FIG. 23 or 24 are elongated in the y direction of the first integrated circuit device 4a and the second integrated circuit device 4b relative to the electrodes 41-44 in FIG. 17. 23 and 24, the positions where the pads 185, 186 of the first integrated circuit device 4a are bonded to the electrodes 45, 46 of the first container 3a are the same as the positions where the pads 285, 286 of the second integrated circuit device 4b are bonded to the electrodes 45, 46 of the second container 3b, but the positions where the pads 181-184 of the first integrated circuit device 4a are bonded to the electrodes 41-44 of the first container 3a are different from the positions where the pads 281-284 of the second integrated circuit device 4b are bonded to the electrodes 41-44 of the second container 3b. In other words, by elongating the tips of the electrodes 41-44 in the y direction, the pads 181-186 or the pads 281-286 can be connected to the electrodes 41-46, respectively. Therefore, the first integrated circuit device 4a and the second integrated circuit device 4b can be mounted in the same type of first container 3a and second container 3b, respectively. Therefore, the man-hours required for setting mounting conditions and man-hours required for designing the container are not required for either the first oscillator 2a or the second oscillator 2b, and the overall manufacturing cost of the first oscillator 2a and the second oscillator 2b is reduced.

[0141] The other structures of the first oscillator 2a and the second oscillator 2b in the second embodiment are the same as those in the first embodiment, and therefore a description thereof will be omitted.

[0142] According to the second embodiment described above, the same effects as those of the first embodiment can be obtained. Furthermore, according to the second embodiment, the second integrated circuit device 4b can be made smaller and less expensive than the first integrated circuit device 4a, thereby reducing the manufacturing cost of the second oscillator 2b.

[0143] 3. Third embodiment Hereinafter, for the third embodiment, the same symbols will be used for configurations that are similar to those of the first or second embodiment, and explanations that are similar to those of the first or second embodiment will be omitted or simplified, and the following will mainly describe the differences from the first and second embodiments.

[0144] The functional block diagram of the first integrated circuit device 4a in the third embodiment is the same as that in Fig. 2, and the functional block diagram of the second integrated circuit device 4b is the same as that in Fig. 8, so illustration and description thereof will be omitted. In addition, an example of the procedure for manufacturing the oscillator in the third embodiment is the same as that in Figs. 18 to 20, so illustration and description thereof will be omitted.

[0145] In the third embodiment, the layout arrangement of the first integrated circuit device 4a and the second integrated circuit device 4b differs from those of the first and second embodiments, and the structures of the first oscillator 2a and the second oscillator 2b differ from those of the first and second embodiments.

[0146] Fig. 25 is a diagram showing an example of the layout arrangement of a first integrated circuit device 4a in the third embodiment. In the example of Fig. 25, the first integrated circuit device 4a has a rectangular semiconductor substrate 100 having four sides 100a, 100b, 100c, and 100d in a plan view, and a power supply circuit 110, an oscillator circuit 120, a frequency control circuit 130, an output circuit 140, a logic circuit 150, a nonvolatile memory 160, variable capacitance circuits 171 and 172, and capacitance elements 191 and 192 are formed on the semiconductor substrate 100.

[0147] In the example of FIG. 25, the power supply circuit 110 is arranged in a rectangular area along the side 100d. The oscillator circuit 120 is arranged in a rectangular area along the sides 100a and 100b. The output circuit 140 is arranged in a rectangular area along the sides 100a and 100d. The frequency control circuit 130 and the variable capacitance circuits 171 and 172 are arranged in rectangular areas along the sides 100b, 100c, and 100d. The logic circuit 150 and the non-volatile memory 160 are arranged in an area other than the areas where the power supply circuit 110, the oscillator circuit 120, the frequency control circuit 130, the output circuit 140, and the variable capacitance circuits 171 and 172 are arranged. Although not shown in FIG. 25, the capacitance elements 191 and 192 are arranged in an empty area of ​​the semiconductor substrate 100.

[0148] A rectangular pad 181 serving as a VDD terminal is arranged along side 100a in the arrangement region of the output circuit 140. A rectangular pad 182 serving as a VSS terminal is arranged along side 100d in the arrangement region of the power supply circuit 110. A rectangular pad 183 serving as an OUT terminal is arranged along sides 100a and 100d in the arrangement region of the output circuit 140. A rectangular pad 184 serving as an OE terminal is arranged near the center of the semiconductor substrate 100 in the arrangement region of the logic circuit 150 and the non-volatile memory 160. A rectangular pad 185 serving as an XO terminal is arranged along side 100b in the arrangement region of the oscillator circuit 120. A rectangular pad 186 serving as an XI terminal is arranged along sides 100a and 100b in the arrangement region of the oscillator circuit 120.

[0149] When the intersection of sides 100a and 100b is the origin, the direction along side 100a is the x direction, and the direction along side 100b is the y direction, the x coordinate value of the center point of pad 185 and the x coordinate value of the center point of pad 186 are both x11, the x coordinate value of the center point of pad 181 and the x coordinate value of the center point of pad 184 are both x12 which is larger than x11, and the x coordinate value of the center point of pad 183 and the x coordinate value of the center point of pad 182 are both larger than x12. The y coordinate value of the center point of pad 186, the y coordinate value of the center point of pad 181, and the y coordinate value of the center point of pad 183 are all y11, and the y coordinate value of the center point of pad 185, the y coordinate value of the center point of pad 184, and the y coordinate value of the center point of pad 182 are all y12, which is greater than y11.

[0150] Fig. 26 is a diagram showing an example of the layout arrangement of the second integrated circuit device 4b in the third embodiment. In the example of Fig. 26, the second integrated circuit device 4b has a rectangular semiconductor substrate 200 having four sides 200a, 200b, 200c, and 200d in a plan view, and a power supply circuit 210, an oscillator circuit 220, an output circuit 240, a logic circuit 250, a nonvolatile memory 260, and capacitive elements 291 and 292 are formed on the semiconductor substrate 200.

[0151] In the example of FIG. 26, the power supply circuit 210 is arranged in a rectangular area along sides 200c and 200d. The oscillator circuit 220 is arranged in a rectangular area along sides 200a, 200b, and 200c. The output circuit 240 is arranged in a rectangular area along sides 200a and 200d. The logic circuit 250 and the nonvolatile memory 260 are arranged in areas other than the areas where the power supply circuit 210, the oscillator circuit 220, and the output circuit 240 are arranged. Although not shown in FIG. 26, the capacitive elements 291 and 292 are arranged in empty areas of the semiconductor substrate 200.

[0152] A rectangular pad 281 serving as a VDD terminal is arranged along side 200a in the placement region of the output circuit 240. A rectangular pad 282 serving as a VSS terminal is arranged along sides 200c and 200d in the placement region of the power supply circuit 210. A rectangular pad 283 serving as an OUT terminal is arranged along sides 200a and 200d in the placement region of the output circuit 240. A rectangular pad 284 serving as an OE terminal is arranged along side 200c in the placement region of the logic circuit 250 and the non-volatile memory 260. A rectangular pad 285 serving as an XO terminal is arranged along sides 200b and 200c in the placement region of the oscillator circuit 220. A rectangular pad 286 serving as an XI terminal is arranged along sides 200a and 200b in the placement region of the oscillator circuit 220.

[0153] If the intersection of sides 200a and 200b is the origin, the direction along side 200a is the x direction, and the direction along side 200b is the y direction, the x coordinate value of the center point of pad 285 and the x coordinate value of the center point of pad 286 are both x21, the x coordinate value of the center point of pad 281 and the x coordinate value of the center point of pad 284 are both x22 which is larger than x21, and the x coordinate value of the center point of pad 283 and the x coordinate value of the center point of pad 282 are both x23 which is larger than x22. The y coordinate value of the center point of pad 286, the y coordinate value of the center point of pad 281, and the y coordinate value of the center point of pad 283 are all y21, and the y coordinate value of the center point of pad 285, the y coordinate value of the center point of pad 284, and the y coordinate value of the center point of pad 282 are all y22 which is larger than y21.

[0154] In the examples of Figures 25 and 26, pads 181 and 281 have the same size and shape, pads 182 and 282 have the same size and shape, pads 183 and 283 have the same size and shape, pads 184 and 284 have the same size and shape, pads 185 and 285 have the same size and shape, and pads 186 and 286 have the same size and shape.

[0155] Furthermore, although the first integrated circuit device 4a and the second integrated circuit device 4b are different in size, the relative positional relationship between the pads 181 to 186 and the relative positional relationship between the pads 281 to 286 are the same. In other words, when the center point of any two corresponding pads, for example, the pad 181 and the pad 182, is assumed to be the origin, the coordinates of the center point of the pads 181 to 186 and the coordinates of the center point of the pads 281 to 286 match. In particular, in the examples of FIGS. 25 and 26, The coordinates (x12, y11) of the center point of pad 181 are equal to the coordinates (x22, y21) of the center point of pad 281, the coordinates (x13, y14) of the center point of pad 182 are equal to the coordinates (x23, y24) of the center point of pad 282, the coordinates (x13, y11) of the center point of pad 183 are equal to the coordinates (x23, y21) of the center point of pad 283, the coordinates (x12, y14) of the center point of pad 184 are equal to the coordinates (x22, y24) of the center point of pad 284, the coordinates (x11, y13) of the center point of pad 185 are equal to the coordinates (x21, y23) of the center point of pad 285, and the coordinates (x11, y12) of the center point of pad 186 are equal to the coordinates (x21, y22) of the center point of pad 286. That is, although the first integrated circuit device 4a and the second integrated circuit device 4b are different in size, the positions of the pads 181 to 186 on the first integrated circuit device 4a are the same as the positions of the pads 281 to 286 on the second integrated circuit device 4b.

[0156] Furthermore, in this embodiment, the frequency control circuit 130 and the variable capacitance circuits 171 and 172 are arranged along a side of the first integrated circuit device 4a. In the example of FIG. 25, the frequency control circuit 130 and the variable capacitance circuits 171 and 172 are arranged along a side 100c of the semiconductor substrate 100 of the first integrated circuit device 4a. Therefore, in the first integrated circuit device 4a, the power supply circuit 110, the oscillator circuit 120, the output circuit 140, the logic circuit 150, and the nonvolatile memory 160 can be arranged in an area other than the arrangement area of ​​the frequency control circuit 130 and the variable capacitance circuits 171 and 172, similar to the power supply circuit 210, the oscillator circuit 220, the output circuit 240, the logic circuit 250, and the nonvolatile memory 260 in the second integrated circuit device 4b. As a result, in the examples of FIGS. 25 and 26, the arrangement area of ​​the power supply circuit 110 and the arrangement area of ​​the power supply circuit 210 are the same or approximately the same in size, shape, and position. The layout area of ​​the oscillator circuit 120 and the layout area of ​​the oscillator circuit 220 are the same or nearly the same in size, shape, and position. The layout area of ​​the output circuit 140 and the layout area of ​​the output circuit 240 are the same or nearly the same in size, shape, and position. The layout area of ​​the logic circuit 150 and the nonvolatile memory 160 and the layout area of ​​the logic circuit 250 and the nonvolatile memory 260 are the same or nearly the same in size, shape, and position.

[0157] Furthermore, at least one pair of the oscillator circuit 120 and the oscillator circuit 220, the output circuit 140 and the output circuit 240, the power supply circuit 110 and the power supply circuit 210, and the logic circuit 150 and the logic circuit 250 may have the same circuit configuration. If the oscillator circuit 120 and the oscillator circuit 220 have the same circuit configuration, they can have a common layout. If the output circuit 140 and the output circuit 240 have the same circuit configuration, they can have a common layout. If the power supply circuit 110 and the power supply circuit 210 have the same circuit configuration, they can have a common layout. If the logic circuit 150 and the logic circuit 250 have the same circuit configuration, they can have a common layout. Therefore, the development man-hours for the first integrated circuit device 4a or the second integrated circuit device 4b can be reduced.

[0158] Furthermore, since the second integrated circuit device 4b does not include a frequency control circuit, it can be made smaller than the first integrated circuit device 4a that includes the frequency control circuit 130, and current consumption is also reduced.

[0159] The perspective view and cross-sectional view of the first oscillator 2a and the second oscillator 2b in the third embodiment are the same as those in Figs. 15 and 16, respectively, and therefore will not be shown or described again. Fig. 27 is a plan view showing a plurality of electrodes formed in the first container 3a of the first oscillator 2a in the third embodiment. Fig. 28 is a plan view showing a plurality of electrodes formed in the second container 3b of the second oscillator 2b in the third embodiment. Note that Fig. 16 corresponds to a cross-sectional view of the first oscillator 2a and the second oscillator 2b taken along line AA in Figs. 27 and 28.

[0160] In the third embodiment, similarly to the first and second embodiments, the first container 3a and the second container 3b are The first and second containers 3a and 3b are the same type of container. Therefore, as shown in FIGS. 27 and 28, the shapes of the electrodes 41, 42, 43, 44, 45, and 46 provided in the first container 3a and the second container 3b are the same. Furthermore, the positions of the electrodes 41, 42, 43, 44, 45, and 46 in the first container 3a and the positions of the electrodes 41, 42, 43, 44, 45, and 46 in the second container 3b are the same. Furthermore, as shown in FIGS. 25 and 26, although the first integrated circuit device 4a and the second integrated circuit device 4b are different in size, the relative positional relationship between the pads 181 to 186 and the relative positional relationship between the pads 281 to 286 are the same. 27 and 28, the positions where the pads 181-186 of the first integrated circuit device 4a are bonded to the electrodes 41-46 of the first container 3a are the same as the positions where the pads 281-286 of the second integrated circuit device 4b are bonded to the electrodes 41-46 of the second container 3b. That is, the first integrated circuit device 4a and the second integrated circuit device 4b can be mounted in the same type of first container 3a and second container 3b, respectively. Therefore, the number of steps required for determining mounting conditions and designing the container for one of the first oscillator 2a and the second oscillator 2b is not required, and the overall manufacturing cost of the first oscillator 2a and the second oscillator 2b is reduced.

[0161] Furthermore, because the position where the first integrated circuit device 4a is bonded to the first container 3a and the position where the second integrated circuit device 4b is bonded to the second container 3b are the same, when the first container 3a and the second container 3b are stacked in a plan view, a portion of the first integrated circuit device 4a overlaps with the second integrated circuit device 4b. According to the examples of Figures 25 and 26, the oscillation circuit 120 and the oscillation circuit 220 at least partially overlap, the output circuit 140 and the output circuit 240 at least partially overlap, the power supply circuit 110 and the power supply circuit 210 at least partially overlap, and the logic circuit 150 and the logic circuit 250 at least partially overlap. In other words, by arranging each pair of these multiple circuits so that they at least partially overlap, it becomes possible to standardize many parts of the layout of the first integrated circuit device 4a and the layout of the second integrated circuit device 4b, thereby reducing the number of steps required to develop the first integrated circuit device 4a or the second integrated circuit device 4b.

[0162] Other structures of the first oscillator 2a and the second oscillator 2b in the third embodiment are the same as those in the first and second embodiments, and therefore a description thereof will be omitted.

[0163] According to the third embodiment described above, the same effects as those of the second embodiment can be obtained. Furthermore, in the third embodiment, the frequency control circuit 130 is arranged along the side 100c of the semiconductor substrate 100, so that the layout of each circuit other than the frequency control circuit 130 of the first integrated circuit device 4a can easily be made common to the layout of each circuit of the second integrated circuit device 4b. Therefore, according to the third embodiment, the number of development steps for the first integrated circuit device 4a or the second integrated circuit device 4b can be reduced, and the manufacturing cost of the first oscillator 2a or the second oscillator 2b can be reduced.

[0164] 4. Fourth embodiment Hereinafter, for the fourth embodiment, the same symbols will be used for configurations that are similar to any of the first to third embodiments, and explanations of the same parts as any of the first to third embodiments will be omitted or simplified, and the explanation will mainly focus on the differences from any of the first to third embodiments.

[0165] The functional block diagram of the first integrated circuit device 4a in the fourth embodiment is the same as that in Fig. 2, and the functional block diagram of the second integrated circuit device 4b is the same as that in Fig. 8, so illustration and description thereof will be omitted. In addition, an example of the procedure for manufacturing the oscillator in the fourth embodiment is the same as that in Figs. 18 to 20, so illustration and description thereof will be omitted.

[0166] In the fourth embodiment, the layout arrangement of the first integrated circuit device 4a and the second integrated circuit device 4b differs from those of the first to third embodiments. Also, the structures of the first oscillator 2a and the second oscillator 2b differ from those of the first to third embodiments.

[0167] Fig. 29 is a diagram showing an example of the layout arrangement of the first integrated circuit device 4a in the fourth embodiment. In the example of Fig. 29, the first integrated circuit device 4a has a rectangular semiconductor substrate 100 having four sides 100a, 100b, 100c, and 100d in a plan view, and a power supply circuit 110, an oscillator circuit 120, a frequency control circuit 130, an output circuit 140, a logic circuit 150, a nonvolatile memory 160, variable capacitance circuits 171 and 172, and capacitance elements 191 and 192 are formed on the semiconductor substrate 100.

[0168] 29, the frequency control circuit 130 and the variable capacitance circuits 171 and 172 are arranged in a rectangular area along sides 100a, 100b, and 100d, and a rectangular area along sides 100b, 100c, and 100d. The power supply circuit 110, the oscillator circuit 120, the output circuit 140, the logic circuit 150, and the non-volatile memory 160 are arranged between the two rectangular areas where the frequency control circuit 130 and the variable capacitance circuits 171 and 172 are arranged. Specifically, the power supply circuit 110 is arranged in a rectangular area along side 100d. The oscillator circuit 120 is arranged in a rectangular area along side 100b. The oscillator circuit 120 is arranged in a rectangular area between the area where the output circuit 140 is arranged and the area where the frequency control circuit 130 and the variable capacitance circuits 171 and 172 are arranged. The logic circuit 150 and the nonvolatile memory 160 are arranged in an area other than the areas where the power supply circuit 110, the oscillator circuit 120, the frequency control circuit 130, the output circuit 140, and the variable capacitance circuits 171 and 172 are arranged. Although not shown in FIG. 29 , the capacitance elements 191 and 192 are arranged in an empty area of ​​the semiconductor substrate 100.

[0169] Rectangular pad 181, which is a VDD terminal, is arranged in the center of the semiconductor substrate 100 in the arrangement region of the output circuit 140. Rectangular pad 182, which is a VSS terminal, is arranged along side 100d in the arrangement region of the power supply circuit 110. Rectangular pad 183, which is an OUT terminal, is arranged along side 100d in the arrangement region of the output circuit 140. Rectangular pad 184, which is an OE terminal, is arranged in the center of the semiconductor substrate 100 in the arrangement region of the logic circuit 150 and the nonvolatile memory 160. Rectangular pad 185, which is an XO terminal, and rectangular pad 186, which is an XI terminal, are arranged along side 100b in the arrangement region of the oscillator circuit 120.

[0170] If the intersection of sides 100a and 100b is the origin, the direction along side 100a is the x direction, and the direction along side 100b is the y direction, the x coordinate value of the center point of pad 185 and the x coordinate value of the center point of pad 186 are both x11, the x coordinate value of the center point of pad 181 and the x coordinate value of the center point of pad 184 are both x12 which is larger than x11, and the x coordinate value of the center point of pad 183 and the x coordinate value of the center point of pad 182 are both x13 which is larger than x12. The y coordinate value of the center point of pad 186, the y coordinate value of the center point of pad 181, and the y coordinate value of the center point of pad 183 are all y11, and the y coordinate value of the center point of pad 185, the y coordinate value of the center point of pad 184, and the y coordinate value of the center point of pad 182 are all y12 which is larger than y11.

[0171] Fig. 30 is a diagram showing an example of the layout arrangement of the second integrated circuit device 4b in the fourth embodiment. In the example of Fig. 30, the second integrated circuit device 4b has a rectangular semiconductor substrate 200 having four sides 200a, 200b, 200c, and 200d in a plan view, and a power supply circuit 210, an oscillator circuit 220, an output circuit 240, a logic circuit 250, a nonvolatile memory 260, and capacitive elements 291 and 292 are formed on the semiconductor substrate 200.

[0172] In the example of FIG. 30, the power supply circuit 210 is arranged in a rectangular area along the side 200c and the side 200d. 30, the oscillator circuit 220 is disposed in a rectangular region along the sides 200a, 200b, and 200c. The output circuit 240 is disposed in a rectangular region along the sides 200a and 200d. The logic circuit 250 and the nonvolatile memory 260 are disposed in a region other than the regions where the power supply circuit 210, the oscillator circuit 220, and the output circuit 240 are disposed. Although not shown in FIG. 30, the capacitive elements 291 and 292 are disposed in a vacant region of the semiconductor substrate 200.

[0173] A rectangular pad 281 serving as a VDD terminal is arranged along side 200a in the placement region of the output circuit 240. A rectangular pad 282 serving as a VSS terminal is arranged along sides 200c and 200d in the placement region of the power supply circuit 210. A rectangular pad 283 serving as an OUT terminal is arranged along sides 200a and 200d in the placement region of the output circuit 240. A rectangular pad 284 serving as an OE terminal is arranged along side 200c in the placement region of the logic circuit 250 and the non-volatile memory 260. A rectangular pad 285 serving as an XO terminal is arranged along sides 200b and 200c in the placement region of the oscillator circuit 220. A rectangular pad 286 serving as an XI terminal is arranged along sides 200a and 200b in the placement region of the oscillator circuit 220.

[0174] If the intersection of sides 200a and 200b is the origin, the direction along side 200a is the x direction, and the direction along side 200b is the y direction, the x coordinate value of the center point of pad 285 and the x coordinate value of the center point of pad 286 are both x21, the x coordinate value of the center point of pad 281 and the x coordinate value of the center point of pad 284 are both x22 which is larger than x21, and the x coordinate value of the center point of pad 283 and the x coordinate value of the center point of pad 282 are both x23 which is larger than x22. The y coordinate value of the center point of pad 286, the y coordinate value of the center point of pad 281, and the y coordinate value of the center point of pad 283 are all y21, and the y coordinate value of the center point of pad 285, the y coordinate value of the center point of pad 284, and the y coordinate value of the center point of pad 282 are all y22 which is larger than y21.

[0175] In the examples of Figures 29 and 30, pads 181 and 281 have the same size and shape, pads 182 and 282 have the same size and shape, pads 183 and 283 have the same size and shape, pads 184 and 284 have the same size and shape, pads 185 and 285 have the same size and shape, and pads 186 and 286 have the same size and shape.

[0176] Furthermore, although the first integrated circuit device 4a and the second integrated circuit device 4b are different in size, the relative positional relationship between pads 181-186 and the relative positional relationship between pads 281-286 are the same. That is, when the center point of any two corresponding pads, for example, pad 181 and pad 182, is assumed to be the origin, the coordinates of the center points of pads 181-186 match the coordinates of the center points of pads 281-286. In particular, in the examples of FIGS. 29 and 30 , the x-coordinate value x11 of the center points of pads 185 and 186 is equal to the x-coordinate value x21 of the center points of pads 285 and 286; the x-coordinate value x12 of the center points of pads 181 and 184 is equal to the x-coordinate value x22 of the center points of pads 281 and 284; and the x-coordinate value x13 of the center points of pads 182 and 183 is equal to the x-coordinate value x23 of the center points of pads 282 and 283. The difference between the y coordinate value y12 of the center point of pads 182, 184, and 185 and the y coordinate value y11 of the center point of pads 181, 183, and 186 is equal to the difference between the y coordinate value y22 of the center point of pads 282, 284, and 285 and the y coordinate value y21 of the center point of pads 281, 283, and 286.

[0177] In this embodiment, the frequency control circuit 130 and the variable capacitance circuits 171 and 172 are arranged in a region along a first side of the first integrated circuit device 4a and a region along a second side opposite to the first side. In the example of FIG. 29, the frequency control circuit 130 and the variable capacitance circuits The capacitors 171 and 172 are arranged in a rectangular region along the side 100a of the semiconductor substrate 100 of the first integrated circuit device 4a and a rectangular region along the side 100c opposite to the side 100a of the semiconductor substrate 100. Therefore, in the first integrated circuit device 4a, the power supply circuit 110, the oscillator circuit 120, the output circuit 140, the logic circuit 150, and the nonvolatile memory 160 can be arranged in the region between the two regions where the frequency control circuit 130 and the variable capacitance circuits 171 and 172 are arranged, similar to the power supply circuit 210, the oscillator circuit 220, the output circuit 240, the logic circuit 250, and the nonvolatile memory 260 in the second integrated circuit device 4b. As a result, in the examples of FIGS. 29 and 30, the arrangement region of the power supply circuit 110 and the arrangement region of the power supply circuit 210 are the same or approximately the same size and shape. The layout area of ​​the oscillator circuit 120 and the layout area of ​​the oscillator circuit 220 are the same or nearly the same in size and shape. The layout area of ​​the output circuit 140 and the layout area of ​​the output circuit 240 are the same or nearly the same in size and shape. The layout area of ​​the logic circuit 150 and the nonvolatile memory 160 and the layout area of ​​the logic circuit 250 and the nonvolatile memory 260 are the same or nearly the same in size and shape.

[0178] Furthermore, at least one pair of the oscillator circuit 120 and the oscillator circuit 220, the output circuit 140 and the output circuit 240, the power supply circuit 110 and the power supply circuit 210, and the logic circuit 150 and the logic circuit 250 may have the same circuit configuration. If the oscillator circuit 120 and the oscillator circuit 220 have the same circuit configuration, they can have a common layout. If the output circuit 140 and the output circuit 240 have the same circuit configuration, they can have a common layout. If the power supply circuit 110 and the power supply circuit 210 have the same circuit configuration, they can have a common layout. If the logic circuit 150 and the logic circuit 250 have the same circuit configuration, they can have a common layout. Therefore, the development man-hours for the first integrated circuit device 4a or the second integrated circuit device 4b can be reduced.

[0179] Furthermore, since the second integrated circuit device 4b does not include a frequency control circuit, it can be made smaller than the first integrated circuit device 4a that includes the frequency control circuit 130, and current consumption is also reduced.

[0180] The perspective view and cross-sectional view of the first oscillator 2a and the second oscillator 2b in the fourth embodiment are the same as those in Figs. 15 and 16, respectively, and therefore will not be shown or described again. Fig. 31 is a plan view showing a plurality of electrodes formed in the first container 3a of the first oscillator 2a in the fourth embodiment. Fig. 32 is a plan view showing a plurality of electrodes formed in the second container 3b of the second oscillator 2b in the fourth embodiment. Note that Fig. 16 corresponds to a cross-sectional view of the first oscillator 2a and the second oscillator 2b taken along line AA in Figs. 31 and 32.

[0181] In the fourth embodiment, as in the first to third embodiments, the first container 3a and the second container 3b are the same type of container. Therefore, as shown in FIGS. 31 and 32, the shapes of the electrodes 41, 42, 43, 44, 45, and 46 provided in the first container 3a are the same as the shapes of the electrodes 41, 42, 43, 44, 45, and 46 provided in the second container 3b. Furthermore, the positions of the electrodes 41, 42, 43, 44, 45, and 46 in the first container 3a are the same as the positions of the electrodes 41, 42, 43, 44, 45, and 46 in the second container 3b. Furthermore, as shown in FIGS. 29 and 30, although the first integrated circuit device 4a and the second integrated circuit device 4b are different in size, the relative positional relationship between the pads 181-186 and the relative positional relationship between the pads 281-286 are the same. Therefore, as shown in Figures 31 and 32, the positions where the pads 181 to 186 of the first integrated circuit device 4a are bonded to the electrodes 41 to 46 of the first container 3a are the same as the positions where the pads 281 to 286 of the second integrated circuit device 4b are bonded to the electrodes 41 to 46 of the second container 3b. In other words, the first integrated circuit device 4a and the second integrated circuit device 4b can be mounted in the first container 3a and the second container 3b, respectively, which are of the same type. Therefore, the first oscillator 2a and the second For one of the oscillators 2b, the man-hours for determining mounting conditions and the man-hours for designing the container are not required, and the manufacturing cost of the first oscillator 2a and the second oscillator 2b as a whole is reduced.

[0182] Furthermore, because the position where the first integrated circuit device 4a is bonded to the first container 3a and the position where the second integrated circuit device 4b is bonded to the second container 3b are the same, when the first container 3a and the second container 3b are stacked in a plan view, a portion of the first integrated circuit device 4a overlaps with the second integrated circuit device 4b. According to the examples of Figures 29 and 30, the oscillation circuit 120 and the oscillation circuit 220 at least partially overlap, the output circuit 140 and the output circuit 240 at least partially overlap, the power supply circuit 110 and the power supply circuit 210 at least partially overlap, and the logic circuit 150 and the logic circuit 250 at least partially overlap. In other words, by arranging each pair of these multiple circuits so that they at least partially overlap, it becomes possible to standardize many parts of the layout of the first integrated circuit device 4a and the layout of the second integrated circuit device 4b, thereby reducing the number of steps required to develop the first integrated circuit device 4a or the second integrated circuit device 4b.

[0183] Other structures of the first oscillator 2a and the second oscillator 2b in the fourth embodiment are the same as those in the first to third embodiments, and therefore a description thereof will be omitted.

[0184] According to the fourth embodiment described above, the same effects as those of the second embodiment can be obtained. Furthermore, in the fourth embodiment, the frequency control circuit 130 is divided and arranged in an area along the side 100a of the semiconductor substrate 100 and an area along the side 100c opposite to the side 100a. This makes it easy to standardize the layout of the circuits other than the frequency control circuit 130 of the first integrated circuit device 4a and the layout of the circuits of the second integrated circuit device 4b. Therefore, according to the fourth embodiment, the number of development steps for the first integrated circuit device 4a or the second integrated circuit device 4b can be reduced, thereby reducing the manufacturing cost of the first oscillator 2a or the second oscillator 2b.

[0185] 5. Fifth embodiment Hereinafter, for the fifth embodiment, the same symbols will be used for configurations that are similar to any of the first to fourth embodiments, and explanations of the same parts as any of the first to fourth embodiments will be omitted or simplified, and the following will mainly describe the differences from any of the first to fourth embodiments.

[0186] The functional block diagram of the first integrated circuit device 4a in the fifth embodiment is the same as that in Fig. 2, and the functional block diagram of the second integrated circuit device 4b is the same as that in Fig. 8, so illustration and description thereof will be omitted. In addition, an example of the procedure for the method of manufacturing the oscillator in the fifth embodiment is the same as that in Figs. 18 to 20, so illustration and description thereof will be omitted.

[0187] In the fifth embodiment, the layout arrangement of the first integrated circuit device 4a and the second integrated circuit device 4b differs from those of the first to fourth embodiments. Also, the structures of the first oscillator 2a and the second oscillator 2b differ from those of the first to fourth embodiments.

[0188] Fig. 33 is a diagram showing an example of the layout arrangement of the first integrated circuit device 4a in the fifth embodiment. In the example of Fig. 33, the first integrated circuit device 4a has a rectangular semiconductor substrate 100 having four sides 100a, 100b, 100c, and 100d in a plan view, and a power supply circuit 110, an oscillator circuit 120, a frequency control circuit 130, an output circuit 140, a logic circuit 150, a nonvolatile memory 160, variable capacitance circuits 171 and 172, and capacitance elements 191 and 192 are formed on the semiconductor substrate 100.

[0189] In the example of FIG. 33, the frequency control circuit 130 and the variable capacitance circuits 171 and 172 are formed in a rectangular area along the sides 100a, 100b, and 100d, and a rectangular area along the sides 100b, 100c, and 100d. The power supply circuit 110 is arranged in a rectangular region along side 100b, and the output circuit 140 is arranged in a rectangular region along side 100d. The power supply circuit 110, the oscillator circuit 120, the output circuit 140, the logic circuit 150, and the nonvolatile memory 160 are arranged between the two rectangular regions in which the frequency control circuit 130 and the variable capacitance circuits 171 and 172 are arranged. Specifically, the logic circuit 150 and the nonvolatile memory 160 are arranged in a rectangular region along side 100b. The power supply circuit 110 is arranged in a rectangular region along side 100d. The output circuit 140 is arranged in a rectangular region along side 100d, spaced apart from the region in which the power supply circuit 110 is arranged. The oscillator circuit 120 is arranged in a convex region between the region in which the power supply circuit 110 is arranged, the region in which the output circuit 140 is arranged, and the region in which the logic circuit 150 and the nonvolatile memory 160 are arranged. Although not shown in FIG. 33 , the capacitance elements 191 and 192 are arranged in an empty region of the semiconductor substrate 100.

[0190] Rectangular pad 181 which is a VDD terminal and rectangular pad 184 which is an OE terminal are arranged along side 100b in the arrangement region of logic circuit 150 and nonvolatile memory 160. Rectangular pad 182 which is a VSS terminal is arranged along side 100d in the arrangement region of power supply circuit 110. Rectangular pad 183 which is an OUT terminal is arranged along side 100d in the arrangement region of output circuit 140. Rectangular pad 185 which is an XO terminal and rectangular pad 186 which is an XI terminal are arranged in the center of semiconductor substrate 100 in the arrangement region of oscillator circuit 120.

[0191] If the intersection of sides 100a and 100b is the origin, the direction along side 100a is the x direction, and the direction along side 100b is the y direction, the x coordinate value of the center point of pad 184 and the x coordinate value of the center point of pad 181 are both x11, the x coordinate value of the center point of pad 185 and the x coordinate value of the center point of pad 186 are both x12 which is larger than x11, and the x coordinate value of the center point of pad 182 and the x coordinate value of the center point of pad 183 are both x13 which is larger than x12. The y coordinate value of the center point of pad 184, the y coordinate value of the center point of pad 185, and the y coordinate value of the center point of pad 182 are all y11, and the y coordinate value of the center point of pad 181, the y coordinate value of the center point of pad 186, and the y coordinate value of the center point of pad 183 are all y12 which is larger than y11.

[0192] Fig. 34 is a diagram showing an example of the layout arrangement of the second integrated circuit device 4b in the fifth embodiment. In the example of Fig. 34, the second integrated circuit device 4b has a rectangular semiconductor substrate 200 having four sides 200a, 200b, 200c, and 200d in a plan view, and a power supply circuit 210, an oscillator circuit 220, an output circuit 240, a logic circuit 250, a nonvolatile memory 260, and capacitive elements 291 and 292 are formed on the semiconductor substrate 200.

[0193] In the example of FIG. 34, the power supply circuit 210 is arranged in a rectangular region along sides 200a and 200d. The output circuit 240 is arranged in a rectangular region along sides 200c and 200d. The logic circuit 250 and nonvolatile memory 260 are arranged in rectangular regions along sides 200a, 200b, and 200c. The oscillator circuit 220 is arranged in a convex region between the arrangement region of the power supply circuit 210, the arrangement region of the output circuit 240, and the arrangement region of the logic circuit 250 and nonvolatile memory 260. Although not shown in FIG. 34, the capacitive elements 291 and 292 are arranged in empty regions of the semiconductor substrate 200.

[0194] The rectangular pad 281 serving as a VDD terminal is arranged along the sides 200b and 200c in the arrangement region of the logic circuit 250 and the nonvolatile memory 260. The rectangular pad 182 serving as a VSS terminal is arranged along the sides 200a and 100d in the arrangement region of the power supply circuit 110. The rectangular pad 183 serving as an OUT terminal is arranged along the sides 200c and 100d in the arrangement region of the output circuit 140. The rectangular pad 284 serving as an OE terminal is arranged along the sides 200a and 200b in the arrangement region of the logic circuit 250 and the nonvolatile memory 260. The rectangular pad 284 serving as an XO terminal is arranged along the sides 200a and 200b in the arrangement region of the logic circuit 250 and the nonvolatile memory 260. The pad 285 is arranged along the side 200a in the arrangement region of the oscillator circuit 220. The rectangular pad 286, which is the XI terminal, is arranged along the side 200c in the arrangement region of the oscillator circuit 220.

[0195] If the intersection of sides 200a and 200b is the origin, the direction along side 200a is the x direction, and the direction along side 200b is the y direction, the x coordinate value of the center point of pad 284 and the x coordinate value of the center point of pad 281 are both x21, the x coordinate value of the center point of pad 285 and the x coordinate value of the center point of pad 286 are both x22 which is larger than x21, and the x coordinate value of the center point of pad 282 and the x coordinate value of the center point of pad 283 are both x23 which is larger than x22. The y coordinate value of the center point of pad 284, the y coordinate value of the center point of pad 285, and the y coordinate value of the center point of pad 282 are all y21, and the y coordinate value of the center point of pad 281, the y coordinate value of the center point of pad 286, and the y coordinate value of the center point of pad 283 are all y22 which is larger than y21.

[0196] In the examples of Figures 33 and 34, pads 181 and 281 have the same size and shape, pads 182 and 282 have the same size and shape, pads 183 and 283 have the same size and shape, pads 184 and 284 have the same size and shape, pads 185 and 285 have the same size and shape, and pads 186 and 286 have the same size and shape.

[0197] Furthermore, although the first integrated circuit device 4a and the second integrated circuit device 4b are different in size, the relative positional relationship between pads 181-186 and the relative positional relationship between pads 281-286 are the same. That is, when the center point of any two corresponding pads, for example, pad 181 and pad 182, is assumed to be the origin, the coordinates of the center point of each of pads 181-186 match the coordinates of the center point of each of pads 281-286. In particular, in the examples of FIGS. 33 and 34 , the x-coordinate value x11 of the center point of pads 181 and 184 is equal to the x-coordinate value x21 of the center point of pads 281 and 284; the x-coordinate value x12 of the center point of pads 185 and 186 is equal to the x-coordinate value x22 of the center point of pads 285 and 286; and the x-coordinate value x13 of the center point of pads 182 and 183 is equal to the x-coordinate value x23 of the center point of pads 282 and 283. The difference between the y-coordinate value y12 of the center point of pads 181, 183, and 186 and the y-coordinate value y11 of the center point of pads 182, 184, and 185 is equal to the difference between the y-coordinate value y22 of the center point of pads 281, 283, and 286 and the y-coordinate value y21 of the center point of pads 282, 284, and 285.

[0198] In this embodiment, the frequency control circuit 130 and the variable capacitance circuits 171, 172 are arranged in a region along a first side of the first integrated circuit device 4a and a region along a second side opposite the first side. In the example of Fig. 33, the frequency control circuit 130 and the variable capacitance circuits 171, 172 are arranged in a rectangular region along a side 100a of the semiconductor substrate 100 of the first integrated circuit device 4a and a rectangular region along a side 100c opposite to the side 100a of the semiconductor substrate 100. Therefore, in the first integrated circuit device 4a, the power supply circuit 110, the oscillator circuit 120, the output circuit 140, the logic circuit 150, and the nonvolatile memory 160 can be arranged in the area between the two areas where the frequency control circuit 130 and the variable capacitance circuits 171 and 172 are separately arranged, similar to the power supply circuit 210, the oscillator circuit 220, the output circuit 240, the logic circuit 250, and the nonvolatile memory 260 in the second integrated circuit device 4b. As a result, in the examples of FIGS. 33 and 34, the layout area of ​​the power supply circuit 110 and the layout area of ​​the power supply circuit 210 are the same or nearly the same in size and shape. The layout area of ​​the oscillator circuit 120 and the layout area of ​​the oscillator circuit 220 are the same or nearly the same in size and shape. The layout area of ​​the output circuit 140 and the layout area of ​​the output circuit 240 are the same or nearly the same in size and shape. The layout area of ​​the logic circuit 150 and the nonvolatile memory 160 and the layout area of ​​the logic circuit 250 and the nonvolatile memory 260 have the same size and shape. Or almost the same.

[0199] Furthermore, at least one pair of the oscillator circuit 120 and the oscillator circuit 220, the output circuit 140 and the output circuit 240, the power supply circuit 110 and the power supply circuit 210, and the logic circuit 150 and the logic circuit 250 may have the same circuit configuration. If the oscillator circuit 120 and the oscillator circuit 220 have the same circuit configuration, they can have a common layout. If the output circuit 140 and the output circuit 240 have the same circuit configuration, they can have a common layout. If the power supply circuit 110 and the power supply circuit 210 have the same circuit configuration, they can have a common layout. If the logic circuit 150 and the logic circuit 250 have the same circuit configuration, they can have a common layout. Therefore, the development man-hours for the first integrated circuit device 4a or the second integrated circuit device 4b can be reduced.

[0200] Furthermore, since the second integrated circuit device 4b does not include a frequency control circuit, it can be made smaller than the first integrated circuit device 4a that includes the frequency control circuit 130, and current consumption is also reduced.

[0201] Since the perspective view of the first oscillator 2a and the second oscillator 2b in the fifth embodiment is similar to that of FIG. 15, its illustration and description will be omitted. FIG. 35 is a cross-sectional view of the first oscillator 2a and the second oscillator 2b in the fifth embodiment. FIG. 36 is a plan view showing a plurality of electrodes formed on the first surface 31a of the substrate 31 of the first container 3a and the second container 3b in the fifth embodiment. FIG. 37 is a plan view showing a plurality of electrodes formed on the second surface 31b of the substrate 31 of the first container 3a in the fifth embodiment. FIG. 38 is a plan view showing a plurality of electrodes formed on the second surface 31b of the substrate 31 of the second container 3b in the fifth embodiment. Note that FIG. 35 corresponds to a cross-sectional view of the first oscillator 2a and the second oscillator 2b taken along line AA in FIG. 36, 37, or 38.

[0202] 15 and 35, the first oscillator 2a has a first integrated circuit device 4a, a first vibrator 5a, a first container 3a that houses the first integrated circuit device 4a and the first vibrator 5a, and a first lid 6a that hermetically seals the housing space 7 that houses the first vibrator 5a. Similarly, the second oscillator 2b has a second integrated circuit device 4b, a second vibrator 5b, a second container 3b that houses the second integrated circuit device 4b and the second vibrator 5b, and a second lid 6b that hermetically seals the housing space 7 that houses the second vibrator 5b.

[0203] The first vibrator 5a and the second vibrator 5b are, for example, AT-cut quartz crystal vibrators based on quartz crystal, and oscillate at a resonant frequency determined by their external shape and dimensions, thereby oscillating at a desired frequency. In this embodiment, the first vibrator 5a and the second vibrator 5b are of the same type and have the same size, shape, and terminal positions. However, the first vibrator 5a and the second vibrator 5b may be of different types and may differ in at least one of size, shape, and terminal positions, as long as they can be housed in the same type of first container 3a and second container 3b, respectively.

[0204] The first container 3a and the second container 3b are made of ceramic or the like, and are configured by laminating a first frame substrate 32, a substrate 31, and a second frame substrate 33, as shown in Figures 35 and 36.

[0205] 35 and 36, electrodes 75, 76 are provided on the first surface 31a of the substrate 31. As indicated by the dashed dotted lines in Fig. 36, the terminals 55, 56 of the first vibrator 5a or the second vibrator 5b and the electrodes 75, 76 provided on the first surface 31a of the substrate 31 are electrically and mechanically connected via bonding members 62 such as conductive adhesive or gold bumps.

[0206] 35, 37, and 38, electrodes 41, 42, 43, 44, 45, and 46 are provided on the second surface 31b of the substrate 31. The electrodes 75 and 76 provided on the first surface 31a of the substrate 31 and the electrodes 45 and 46 provided on the second surface 31b of the substrate 31 are electrically connected by wiring (not shown).

[0207] 37, the pads 181, 182, 183, 184, 185, and 186 of the first integrated circuit device 4a shown in FIG. 33 are electrically and mechanically connected to the electrodes 41, 42, 43, 44, 45, and 46 provided on the first surface 31a of the substrate 31 via bonding members 61 such as conductive adhesive or gold bumps. The pads 181, 182, 183, 184, 185, and 186 correspond to the VDD terminal, VSS terminal, OUT terminal, OE terminal, XO terminal, and XI terminal of the first oscillator 2a shown in FIG. 2, respectively.

[0208] 38, the pads 281, 282, 283, 284, 285, and 286 of the second integrated circuit device 4b shown in FIG. 34 are electrically and mechanically connected to the electrodes 41, 42, 43, 44, 45, and 46 provided on the first surface 31a of the substrate 31 via bonding members 61 such as conductive adhesive or gold bumps. The pads 281, 282, 283, 284, 285, and 286 correspond to the VDD terminal, VSS terminal, OUT terminal, OE terminal, XO terminal, and XI terminal of the second oscillator 2b shown in FIG. 8, respectively.

[0209] As shown in Figure 35, the first frame substrate 32 is an annular substrate from which a portion including the position of the first integrated circuit device 4a or the second integrated circuit device 4b has been removed. A plurality of external terminals 8 are provided on the second surface 32b of the first frame substrate 32. The plurality of external terminals 8 correspond to the VDD1 terminal, VSS1 terminal, OUT1 terminal, and OE1 terminal shown in Figure 2 or 8, respectively. Each external terminal 8 is electrically connected to each electrode 41, 42, 43, and 44 by wiring (not shown). The first surface 32a of the first frame substrate 32 is joined to the second surface 31b of the substrate 31.

[0210] 35, the second frame substrate 33 is an annular substrate from which a portion including the position of the first vibrator 5a or the second vibrator 5b has been removed. The first lid 6a or the second lid 6b is made of metal, ceramic, glass, or the like, and is joined to the second frame substrate 33 via a joining member 63 such as a seal ring or low-melting-point glass, thereby forming an accommodating space 7 that accommodates the first vibrator 5a or the second vibrator 5b and is hermetically sealed. The accommodating space 7 is an airtight space and is in a reduced pressure state, preferably closer to a vacuum.

[0211] In the fifth embodiment, as in the first to fourth embodiments, the first container 3a and the second container 3b are the same type of container. Therefore, as shown in FIGS. 37 and 38, the shapes of the electrodes 41, 42, 43, 44, 45, and 46 provided in the first container 3a are the same as the shapes of the electrodes 41, 42, 43, 44, 45, and 46 provided in the second container 3b. Furthermore, the positions of the electrodes 41, 42, 43, 44, 45, and 46 in the first container 3a are the same as the positions of the electrodes 41, 42, 43, 44, 45, and 46 in the second container 3b. Furthermore, as shown in FIGS. 33 and 34, although the first integrated circuit device 4a and the second integrated circuit device 4b are different in size, the relative positional relationship between the pads 181 to 186 and the relative positional relationship between the pads 281 to 286 are the same. 37 and 38, the positions where the pads 181-186 of the first integrated circuit device 4a are bonded to the electrodes 41-46 of the first container 3a are the same as the positions where the pads 281-286 of the second integrated circuit device 4b are bonded to the electrodes 41-46 of the second container 3b. That is, the first integrated circuit device 4a and the second integrated circuit device 4b can be mounted in the same type of first container 3a and second container 3b, respectively. Therefore, the man-hours for setting mounting conditions and man-hours for container design are not required for either the first oscillator 2a or the second oscillator 2b, The overall manufacturing cost of the first oscillator 2a and the second oscillator 2b is reduced.

[0212] Furthermore, because the position where the first integrated circuit device 4a is bonded to the first container 3a and the position where the second integrated circuit device 4b is bonded to the second container 3b are the same, when the first container 3a and the second container 3b are stacked in a plan view, a portion of the first integrated circuit device 4a overlaps with the second integrated circuit device 4b. According to the examples of Figures 33 and 34, the oscillation circuit 120 and the oscillation circuit 220 at least partially overlap, the output circuit 140 and the output circuit 240 at least partially overlap, the power supply circuit 110 and the power supply circuit 210 at least partially overlap, and the logic circuit 150 and the logic circuit 250 at least partially overlap. In other words, by arranging each pair of these multiple circuits so that they at least partially overlap, it becomes possible to standardize many parts of the layout of the first integrated circuit device 4a and the layout of the second integrated circuit device 4b, thereby reducing the number of steps required to develop the first integrated circuit device 4a or the second integrated circuit device 4b.

[0213] According to the fifth embodiment described above, the same effects as those of the fourth embodiment can be obtained.

[0214] 6. Variations The present invention is not limited to the present embodiment, and various modifications are possible within the scope of the present invention.

[0215] In the above embodiments, the pads 181-186 of the first integrated circuit device 4a and the pads 281-286 of the second integrated circuit device 4b are the same in size and shape, but as long as the pads 181-186 are connectable to the electrodes 41-46 of the first container 3a, respectively, and the pads 281-286 are connectable to the electrodes 41-46 of the second container 3b, respectively, the pads 181-186 and the pads 281-286 may differ in at least one of size and shape. Furthermore, the arrangement and functions of the pads 181-186 and the pads 281-286 are not limited to the examples given in the above embodiments.

[0216] Furthermore, in each of the above embodiments, the first integrated circuit device 4a has six pads 181 to 186, and the first container 3a has six electrodes 41 to 46 connected to the pads 181 to 186, respectively; however, the number of pads in the first integrated circuit device 4a and the number of electrodes provided in the first container 3a are not limited to six. Similarly, the second integrated circuit device 4b has six pads 281 to 286, and the second container 3b has six electrodes 41 to 46 connected to the pads 281 to 286, respectively; however, the number of pads in the second integrated circuit device 4b and the number of electrodes provided in the second container 3b are not limited to six. For example, in cases where the first oscillator 2a and the second oscillator 2b are oscillators that output differential oscillation signals, the number of pads in the first integrated circuit device 4a and the second integrated circuit device 4b, respectively, and the number of electrodes provided in the first container 3a and the second container 3b may be more than six. That is, for any integer N greater than or equal to 2, the first integrated circuit device 4a may have first to Nth pads, and the first container 3a may be provided with first to Nth electrodes connected to the first to Nth pads, respectively; the second integrated circuit device 4b may have N+1th to 2Nth pads, and the second container 3b may be provided with N+1th to 2Nth electrodes connected to the N+1th to 2Nth pads, respectively.

[0217] In addition, in each of the above embodiments, an AT-cut quartz crystal resonator using quartz crystal as a base material has been exemplified as the first resonator 5a and the second resonator 5b, but the base material of the first resonator 5a and the second resonator 5b can be, in addition to quartz crystal, piezoelectric single crystals such as lithium tantalate and lithium niobate, piezoelectric ceramics such as lead zirconate titanate, or silicon semiconductor materials. Furthermore, the first resonator 5a and the second resonator 5b may be, for example, tuning fork resonators, SAW resonators, or MEMS resonators. SAW stands for Surface Acoustic Wave, and MEMS stands for Micro Electro Mechanical Systems. As an excitation means for the first oscillator 5a and the second oscillator 5b, a means based on the piezoelectric effect or electrostatic driving using Coulomb force may be used.

[0218] The above-described embodiment and modifications are merely examples, and the present invention is not limited to these. For example, the embodiments and modifications can be combined as appropriate.

[0219] The present invention includes configurations that are substantially the same as the configurations described in the embodiments, for example, configurations with the same functions, methods, and results, or configurations with the same purpose and effects. The present invention also includes configurations that replace non-essential parts of the configurations described in the embodiments. The present invention also includes configurations that achieve the same effects or purposes as the configurations described in the embodiments. The present invention also includes configurations that add publicly known technology to the configurations described in the embodiments.

[0220] The following can be derived from the above-described embodiment and modifications.

[0221] One aspect of the method for manufacturing an oscillator includes: A method for manufacturing a plurality of types of oscillators including a first oscillator and a second oscillator, manufacturing the first oscillator by housing a first resonator and a first integrated circuit device that causes the first resonator to oscillate in a first container; and manufacturing the second oscillator by housing a second vibrator and a second integrated circuit device that causes the second vibrator to oscillate in a second container; the first integrated circuit device includes a first oscillation circuit that oscillates the first vibrator to output a first oscillation signal, and a frequency control circuit that generates a frequency control signal including at least one of a temperature compensation signal that compensates for a frequency temperature characteristic of the first oscillation signal and a frequency setting signal that sets the frequency of the first oscillation signal to a frequency corresponding to a voltage of a signal input from outside the first integrated circuit device, the second integrated circuit device includes a second oscillation circuit that oscillates the second vibrator to output a second oscillation signal, and does not include a frequency control circuit that generates a frequency control signal that includes at least one of a temperature compensation signal that compensates for the frequency temperature characteristic of the second oscillation signal and a frequency setting signal that sets the second oscillation signal to a frequency that corresponds to the voltage of a signal that is input from outside the second integrated circuit device; The first container and the second container are the same type of container.

[0222] According to this oscillator manufacturing method, a first oscillator is manufactured by housing a first resonator and a first integrated circuit device having a frequency control circuit in a first container, and a second oscillator is manufactured by housing a second resonator and a second integrated circuit device without a frequency control circuit in a second container, thereby making it possible to manufacture multiple types of oscillators with different frequency control functions. Furthermore, since the second integrated circuit device does not have a frequency control circuit, the risk of the oscillation signal characteristics being degraded by an unnecessary frequency control circuit in the second oscillator is reduced. Furthermore, according to this oscillator manufacturing method, since the first container and the second container are the same type of container, the development of the first oscillator or the second oscillator does not require labor hours for setting mounting conditions or labor hours for container design, and therefore multiple types of oscillators can be manufactured efficiently.

[0223] In one aspect of the method for manufacturing the oscillator, N is an integer equal to or greater than 2, The first container is provided with first to Nth electrodes, The second container is provided with N+1 to 2N electrodes, the first integrated circuit device has first to Nth pads, the second integrated circuit device has pads (N+1) to (2N), For each integer i between 1 and N, the shape of the i-th electrode and the shape of the N+i-th electrode the shape is the same, and the position of the i-th electrode in the first container and the position of the N+i-th electrode in the second container are the same; manufacturing the first oscillator includes connecting the first to Nth pads to the first to Nth electrodes, respectively; Manufacturing the second oscillator may include connecting the (N+1)th to 2Nth pads to the (N+1)th to 2Nth electrodes, respectively.

[0224] In one aspect of the method for manufacturing the oscillator, The relative positional relationship between the first to Nth pads may be the same as the relative positional relationship between the (N+1)th to 2Nth pads.

[0225] According to this method of manufacturing an oscillator, the N positions where the first to Nth pads are connected to the first to Nth electrodes, respectively, can be the same as the N positions where the N+1th to 2Nth pads are connected to the N+1th to 2Nth electrodes, respectively, thereby improving the degree of freedom in the size and shape of the first to Nth electrodes and the N+1th to 2Nth electrodes.

[0226] In one aspect of the method for manufacturing the oscillator, the first integrated circuit device includes a first output circuit that outputs a first output signal based on the first oscillation signal, a first power supply circuit that supplies a first power supply voltage to the first oscillation circuit and the first output circuit, and a first logic circuit that performs operation settings of the first integrated circuit device; the second integrated circuit device includes a second output circuit that outputs a second output signal based on the second oscillation signal, a second power supply circuit that supplies a second power supply voltage to the second oscillation circuit and the second output circuit, and a second logic circuit that performs operation settings of the second integrated circuit device; When the first container and the second container are stacked and viewed in a plane, the first oscillation circuit and the second oscillation circuit at least partially overlap each other; the first output circuit and the second output circuit at least partially overlap each other; the first power supply circuit and the second power supply circuit at least partially overlap each other; The first logic circuit and the second logic circuit may at least partially overlap each other.

[0227] According to this method for manufacturing an oscillator, it is possible to make the layout of the first integrated circuit device and the layout of the second integrated circuit device common in many parts, thereby reducing the development man-hours for the first integrated circuit device or the second integrated circuit device, thereby reducing the manufacturing cost of the first oscillator or the second oscillator.

[0228] In one aspect of the method for manufacturing the oscillator, the first integrated circuit device includes a first output circuit that outputs a first output signal based on the first oscillation signal, a first power supply circuit that supplies a first power supply voltage to the first oscillation circuit and the first output circuit, and a first logic circuit that performs operation settings of the first integrated circuit device; the second integrated circuit device includes a second output circuit that outputs a second output signal based on the second oscillation signal, a second power supply circuit that supplies a second power supply voltage to the second oscillation circuit and the second output circuit, and a second logic circuit that performs operation settings of the second integrated circuit device; At least one pair of the first oscillation circuit and the second oscillation circuit, the first output circuit and the second output circuit, the first power supply circuit and the second power supply circuit, and the first logic circuit and the second logic circuit may have the same circuit configuration.

[0229] According to this method for manufacturing an oscillator, it is possible to make at least part of the layout of the first integrated circuit device and at least part of the layout of the second integrated circuit device common, thereby reducing the development man-hours for the first integrated circuit device or the second integrated circuit device, thereby reducing the manufacturing cost of the first oscillator or the second oscillator.

[0230] In one aspect of the method for manufacturing the oscillator, the first integrated circuit device includes a first output circuit that outputs a first output signal based on the first oscillation signal, and a first power supply circuit that supplies a first power supply voltage to the first oscillation circuit and the first output circuit; The frequency control circuit may be located between two of the first oscillation circuit, the first output circuit, and the first power supply circuit.

[0231] In one aspect of the method for manufacturing the oscillator, the first integrated circuit device includes a variable capacitance circuit connected to the first vibrator and having a capacitance value that changes in response to the frequency control signal; At least one of a bypass capacitor, a smoothing capacitor, a current source, and a bandgap reference circuit may be arranged in a second region of the second integrated circuit device corresponding to a first region of the first integrated circuit device in which the frequency control circuit and the variable capacitance circuit are arranged.

[0232] According to this method for manufacturing an oscillator, the effect of reducing noise in the oscillation signal in the second integrated circuit device is improved, and therefore the characteristics of the second oscillator can be improved.

[0233] In one aspect of the method for manufacturing the oscillator, the second integrated circuit device includes a second output circuit that outputs a second output signal based on the second oscillation signal, and a second power supply circuit that supplies a second power supply voltage to the second oscillation circuit and the second output circuit, When the first oscillation circuit and the second oscillation circuit are made to correspond to each other, the first output circuit and the second output circuit are made to correspond to each other, and the first power supply circuit and the second power supply circuit are made to correspond to each other, the distance between two circuits of the second integrated circuit device that correspond to the two circuits of the first integrated circuit device may be smaller than the distance between the two circuits of the first integrated circuit device.

[0234] According to this method for manufacturing an oscillator, the second integrated circuit device can be made smaller and less expensive than the first integrated circuit device, thereby reducing the manufacturing cost of the second oscillator.

[0235] In one aspect of the method for manufacturing the oscillator, The frequency control circuit may be arranged along a side of the first integrated circuit device.

[0236] According to this method for manufacturing an oscillator, it is easy to standardize the layout of each circuit other than the frequency control circuit of the first integrated circuit device and the layout of each circuit of the second integrated circuit device, thereby reducing the development man-hours for the first integrated circuit device or the second integrated circuit device, and thereby reducing the manufacturing cost of the first oscillator or the second oscillator.

[0237] In one aspect of the method for manufacturing the oscillator, The frequency control circuit may be divided and arranged in an area along a first side of the first integrated circuit device and an area along a second side of the first integrated circuit device opposite the first side.

[0238] According to this method for manufacturing an oscillator, the circuits other than the frequency control circuit of the first integrated circuit device Since it is easy to standardize the layout of each circuit of the first integrated circuit device and the second integrated circuit device, the development man-hours for the first integrated circuit device or the second integrated circuit device can be reduced, thereby reducing the manufacturing cost of the first oscillator or the second oscillator.

[0239] In one aspect of the method for manufacturing the oscillator, The first integrated circuit device and the second integrated circuit device may be the same size.

[0240] One aspect of the oscillator is An oscillator included in an oscillator group consisting of multiple types of oscillators, a first oscillator; a first integrated circuit device that causes the first vibrator to oscillate; a first container that houses the first vibrator and the first integrated circuit device; Equipped with the first integrated circuit device includes a first oscillation circuit that oscillates the first vibrator to output a first oscillation signal, and a frequency control circuit that generates a frequency control signal including at least one of a temperature compensation signal that compensates for a frequency temperature characteristic of the first oscillation signal and a frequency setting signal that sets the frequency of the first oscillation signal to a frequency corresponding to a voltage of a signal input from outside the first integrated circuit device, another oscillator included in the oscillator group includes a second vibrator, a second integrated circuit device that causes the second vibrator to oscillate, and a second container that houses the second vibrator and the second integrated circuit device; the second integrated circuit device includes a second oscillation circuit that oscillates the second vibrator to output a second oscillation signal, and does not include a frequency control circuit that generates a frequency control signal that includes at least one of a temperature compensation signal that compensates for the frequency temperature characteristic of the second oscillation signal and a frequency setting signal that sets the second oscillation signal to a frequency that corresponds to the voltage of a signal that is input from outside the second integrated circuit device; The first container and the second container are the same type of container.

[0241] This oscillator houses a first resonator and a first integrated circuit device having a frequency control circuit in a first container, while other oscillators in the oscillator group house a second resonator and a second integrated circuit device not having a frequency control circuit in a second container, so the two oscillators have different frequency control functions. Furthermore, because the first container and the second container are the same type of container, the development of this oscillator or other oscillators does not require labor hours for setting mounting conditions or labor hours for container design, and multiple types of oscillators can be manufactured efficiently.

[0242] Another aspect of the oscillator is An oscillator included in an oscillator group consisting of multiple types of oscillators, a second oscillator; and a second integrated circuit device that causes the second vibrator to oscillate; a second container that houses the second vibrator and the second integrated circuit device; Equipped with the second integrated circuit device includes a second oscillation circuit that oscillates the second vibrator to output a second oscillation signal, and does not include a frequency control circuit that generates a frequency control signal that includes at least one of a temperature compensation signal that compensates for the frequency temperature characteristic of the second oscillation signal and a frequency setting signal that sets the second oscillation signal to a frequency that corresponds to the voltage of a signal that is input from outside the second integrated circuit device; each of the other oscillators included in the oscillator group includes a first vibrator, a first integrated circuit device that causes the first vibrator to oscillate, and a first container that houses the first vibrator and the first integrated circuit device; The first integrated circuit device oscillates the first oscillator to output a first oscillation signal. a first oscillation circuit; and a frequency control circuit that generates a frequency control signal including at least one of a temperature compensation signal that compensates for the frequency temperature characteristic of the first oscillation signal and a frequency setting signal that sets the frequency of the first oscillation signal to a frequency corresponding to a voltage of a signal input from outside the first integrated circuit device, The first container and the second container are the same type of container.

[0243] This oscillator contains a second resonator and a second integrated circuit device that does not have a frequency control circuit in a second container, while the other oscillators in the oscillator group contain a first resonator and a first integrated circuit device that has a frequency control circuit in a first container, so the two oscillators have different frequency control functions. Furthermore, because the second integrated circuit device does not have a frequency control circuit, the risk of the oscillation signal characteristics being degraded by an unnecessary frequency control circuit in the second oscillator is reduced. Furthermore, because the first container and the second container are the same type of container, the development of this oscillator or other oscillators does not require labor hours for setting mounting conditions or labor hours for container design, and multiple types of oscillators can be efficiently manufactured. [Explanation of symbols]

[0244] REFERENCE SIGNS LIST 1...oscillator group, 2a...first oscillator, 2b...second oscillator, 3a...first container, 3b...second container, 4a...first integrated circuit device, 4b...second integrated circuit device, 5a...first vibrator, 5b...second vibrator, 6a...first lid, 6b...second lid, 7...accommodation space, 8...external terminal, 31...substrate, 31a...first surface of substrate, 31b...second surface of substrate, 32...first frame substrate, 32a...first surface of first frame substrate, 32b...second surface of first frame substrate, 33...second frame substrate, 41, 42, 43, 44, 45, 46...electrodes, 55, 56...terminals, 75, 76...electrodes, 61, 62, 63...joints Material, 100... semiconductor substrate, 100a, 100b, 100c, 100d... edges of semiconductor substrate, 110... power supply circuit, 111... band gap reference circuit, 112... operational amplifier, 113... resistor element, 114... capacitor element, 115... MOS transistor, 116... resistor element, 117... resistor element, 120... oscillator circuit, 121... MOS transistor, 122... MOS transistor, 123... MOS transistor, 124... bipolar transistor, 125... capacitor element, 126... capacitor element, 127... current source, 128... amplifier circuit, 130... frequency control circuit, 13 1...temperature sensor, 132...zeroth-order component generating circuit, 133...first-order component generating circuit, 134...higher-order component generating circuit, 135...I / V conversion circuit, 136...temperature compensation circuit, 137...AFC circuit, 140...output circuit, 141...waveform shaping buffer, 142...frequency divider circuit, 143...pre-buffer, 144...output buffer, 150...logic circuit, 160...non-volatile memory, 171, 172...variable capacitance circuit, 181, 182, 183, 184, 185, 186...pad, 191, 192...capacitive element, 200...semiconductor substrate, 200a, 200b, 200c, 200d...semiconductor Edge of substrate, 210...power supply circuit, 211...bandgap reference circuit, 212...operational amplifier, 213...resistance element, 214...capacitance element, 215...MOS transistor, 216...resistance element, 217...resistance element, 220...oscillator circuit, 221...MOS transistor, 222...MOS transistor, 223...MOS transistor, 224...bipolar transistor, 225...capacitance element, 226...capacitance element, 227...current source, 228...amplifier circuit, 240...output circuit, 250...logic circuit, 260...nonvolatile memory, 281, 282, 283, 284,285,286…Pad,

Claims

1. A method for manufacturing a plurality of types of oscillators including a first oscillator and a second oscillator, comprising: manufacturing the first oscillator by housing a first resonator and a first integrated circuit device that causes the first resonator to oscillate in a first container; and manufacturing the second oscillator by housing a second vibrator and a second integrated circuit device that causes the second vibrator to oscillate in a second container; the first integrated circuit device includes: a first oscillation circuit that oscillates the first vibrator to output a first oscillation signal; a first output circuit that outputs a first output signal based on the first oscillation signal; a first power supply circuit that supplies a first power supply voltage to the first oscillation circuit and the first output circuit; and a frequency control circuit that generates a frequency control signal including at least one of a temperature compensation signal that compensates for a frequency temperature characteristic of the first oscillation signal and a frequency setting signal that sets the first oscillation signal to a frequency corresponding to a voltage of a signal input from outside the first integrated circuit device; the second integrated circuit device includes a second oscillation circuit that oscillates the second vibrator to output a second oscillation signal, a second output circuit that outputs a second output signal based on the second oscillation signal, and a second power supply circuit that supplies a second power supply voltage to the second oscillation circuit and the second output circuit, but does not include a frequency control circuit that generates a frequency control signal that includes at least one of a temperature compensation signal that compensates for a frequency temperature characteristic of the second oscillation signal and a frequency setting signal that sets the second oscillation signal to a frequency corresponding to a voltage of a signal input from outside the second integrated circuit device; the first container and the second container are the same type of container, the frequency control circuit is located between two circuits among the first oscillation circuit, the first output circuit, and the first power supply circuit; A method for manufacturing an oscillator, wherein when the first oscillation circuit corresponds to the second oscillation circuit, the first output circuit corresponds to the second output circuit, and the first power supply circuit corresponds to the second power supply circuit, a distance between two circuits of the second integrated circuit device that correspond to the two circuits of the first integrated circuit device is smaller than a distance between the two circuits of the first integrated circuit device.

2. A method for manufacturing a plurality of types of oscillators including a first oscillator and a second oscillator, comprising: manufacturing the first oscillator by housing a first resonator and a first integrated circuit device that causes the first resonator to oscillate in a first container; and manufacturing the second oscillator by housing a second vibrator and a second integrated circuit device that causes the second vibrator to oscillate in a second container; the first integrated circuit device includes a first oscillation circuit that oscillates the first vibrator to output a first oscillation signal, and a frequency control circuit that generates a frequency control signal including at least one of a temperature compensation signal that compensates for a frequency temperature characteristic of the first oscillation signal and a frequency setting signal that sets the frequency of the first oscillation signal to a frequency corresponding to a voltage of a signal input from outside the first integrated circuit device, the second integrated circuit device includes a second oscillation circuit that oscillates the second vibrator to output a second oscillation signal, and does not include a frequency control circuit that generates a frequency control signal that includes at least one of a temperature compensation signal that compensates for the frequency temperature characteristic of the second oscillation signal and a frequency setting signal that sets the second oscillation signal to a frequency that corresponds to the voltage of a signal that is input from outside the second integrated circuit device; the first container and the second container are the same type of container, A method for manufacturing an oscillator, wherein the frequency control circuit is divided and arranged in an area along a first side of the first integrated circuit device and an area along a second side of the first integrated circuit device opposite to the first side.

3. In claim 2, the first integrated circuit device includes a first output circuit that outputs a first output signal based on the first oscillation signal, a first power supply circuit that supplies a first power supply voltage to the first oscillation circuit and the first output circuit, and a first logic circuit that performs operation settings of the first integrated circuit device; the second integrated circuit device includes a second output circuit that outputs a second output signal based on the second oscillation signal, a second power supply circuit that supplies a second power supply voltage to the second oscillation circuit and the second output circuit, and a second logic circuit that performs operation settings of the second integrated circuit device; When the first container and the second container are stacked and viewed in a plane, the first oscillator circuit and the second oscillator circuit at least partially overlap each other; the first output circuit and the second output circuit at least partially overlap each other; the first power supply circuit and the second power supply circuit at least partially overlap each other; The method for manufacturing an oscillator, wherein the first logic circuit and the second logic circuit at least partially overlap each other.

4. In claim 2, the first integrated circuit device includes a first output circuit that outputs a first output signal based on the first oscillation signal, a first power supply circuit that supplies a first power supply voltage to the first oscillation circuit and the first output circuit, and a first logic circuit that performs operation settings of the first integrated circuit device; the second integrated circuit device includes a second output circuit that outputs a second output signal based on the second oscillation signal, a second power supply circuit that supplies a second power supply voltage to the second oscillation circuit and the second output circuit, and a second logic circuit that performs operation settings of the second integrated circuit device; At least one pair of the first oscillation circuit and the second oscillation circuit, the first output circuit and the second output circuit, the first power supply circuit and the second power supply circuit, and the first logic circuit and the second logic circuit have the same circuit configuration.

5. A method for manufacturing a plurality of types of oscillators including a first oscillator and a second oscillator, comprising: manufacturing the first oscillator by housing a first resonator and a first integrated circuit device that causes the first resonator to oscillate in a first container; and manufacturing the second oscillator by housing a second vibrator and a second integrated circuit device that causes the second vibrator to oscillate in a second container; the first integrated circuit device includes: a first oscillation circuit that oscillates the first oscillator to output a first oscillation signal; a frequency control circuit that generates a frequency control signal including at least one of a temperature compensation signal that compensates for a frequency temperature characteristic of the first oscillation signal and a frequency setting signal that sets the frequency of the first oscillation signal according to a voltage of a signal input from outside the first integrated circuit device; and a variable capacitance circuit that is connected to the first oscillator and has a capacitance value that changes according to the frequency control signal; the second integrated circuit device includes: a second oscillation circuit that oscillates the second vibrator to output a second oscillation signal; a second power supply circuit that generates a second power supply voltage based on a power supply voltage and a ground voltage supplied from an external source and supplies the second power supply voltage to the second oscillation circuit; and a bypass capacitor that suppresses abrupt fluctuations in the power supply voltage or the second power supply voltage supplied from the external source, but does not include a frequency control circuit that generates a frequency control signal that includes at least one of a temperature compensation signal that compensates for a frequency temperature characteristic of the second oscillation signal and a frequency setting signal that sets the second oscillation signal to a frequency corresponding to the voltage of a signal input from the outside of the second integrated circuit device; the first container and the second container are the same type of container, the second oscillation circuit includes an amplifier circuit that amplifies a signal from the second vibrator and outputs the second oscillation signal, and a current source that supplies a current to the amplifier circuit; the second power supply circuit includes a bandgap reference circuit, an operational amplifier to which a reference voltage output from the bandgap reference circuit is input, and a filter configured with a resistor and a smoothing capacitor, which smoothes an output signal of the operational amplifier; a first region of the first integrated circuit device in which the frequency control circuit and the variable capacitance circuit are arranged, and at least one of the bypass capacitor, the smoothing capacitor, the current source, and the bandgap reference circuit is arranged in a second region of the second integrated circuit device corresponding to the first region of the first integrated circuit device in which the frequency control circuit and the variable capacitance circuit are arranged.

6. In claim 5, the first integrated circuit device includes a first output circuit that outputs a first output signal based on the first oscillation signal, a first power supply circuit that supplies a first power supply voltage to the first oscillation circuit and the first output circuit, and a first logic circuit that performs operation settings of the first integrated circuit device; the second integrated circuit device includes a second output circuit that outputs a second output signal based on the second oscillation signal, and a second logic circuit that performs operation settings of the second integrated circuit device; the second power supply circuit supplies the second power supply voltage to the second oscillation circuit and the second output circuit; When the first container and the second container are stacked and viewed in a plane, the first oscillator circuit and the second oscillator circuit at least partially overlap each other; the first output circuit and the second output circuit at least partially overlap each other; the first power supply circuit and the second power supply circuit at least partially overlap each other; The method for manufacturing an oscillator, wherein the first logic circuit and the second logic circuit at least partially overlap each other.

7. In claim 5, the first integrated circuit device includes a first output circuit that outputs a first output signal based on the first oscillation signal, a first power supply circuit that supplies a first power supply voltage to the first oscillation circuit and the first output circuit, and a first logic circuit that performs operation settings for the first integrated circuit device; Including, the second integrated circuit device includes a second output circuit that outputs a second output signal based on the second oscillation signal, and a second logic circuit that performs operation settings of the second integrated circuit device; the second power supply circuit supplies the second power supply voltage to the second oscillation circuit and the second output circuit; At least one pair of the first oscillation circuit and the second oscillation circuit, the first output circuit and the second output circuit, the first power supply circuit and the second power supply circuit, and the first logic circuit and the second logic circuit have the same circuit configuration.

8. In any one of claims 5 to 7, The method for manufacturing an oscillator, wherein the first integrated circuit device and the second integrated circuit device are the same size.

9. In any one of claims 1 to 8, N is an integer equal to or greater than 2, The first container is provided with first to N-th electrodes, The second container is provided with N+1 to 2N electrodes, the first integrated circuit device has first to Nth pads; the second integrated circuit device has pads (N+1) to (2N); For each integer i greater than or equal to 1 and less than or equal to N, the shape of the i-th electrode and the shape of the N+i-th electrode are the same, and the position of the i-th electrode in the first container and the position of the N+i-th electrode in the second container are the same; manufacturing the first oscillator includes connecting the first to Nth pads to the first to Nth electrodes, respectively; The method for manufacturing an oscillator, wherein manufacturing the second oscillator includes connecting the (N+1)th to 2Nth pads to the (N+1)th to 2Nth electrodes, respectively.

10. In claim 9, A method for manufacturing an oscillator, wherein the relative positional relationship between first to Nth pads is the same as the relative positional relationship between the (N+1)th to 2Nth pads.

11. An oscillator group consisting of multiple types of oscillators including a first oscillator and a second oscillator, The first oscillator comprises: a first oscillator; a first integrated circuit device that causes the first vibrator to oscillate; a first container that houses the first vibrator and the first integrated circuit device; Equipped with the first integrated circuit device includes: a first oscillation circuit that oscillates the first vibrator to output a first oscillation signal; a first output circuit that outputs a first output signal based on the first oscillation signal; a first power supply circuit that supplies a first power supply voltage to the first oscillation circuit and the first output circuit; and a frequency control circuit that generates a frequency control signal including at least one of a temperature compensation signal that compensates for a frequency temperature characteristic of the first oscillation signal and a frequency setting signal that sets the first oscillation signal to a frequency corresponding to a voltage of a signal input from outside the first integrated circuit device; The second oscillator comprises: a second oscillator; and a second integrated circuit device that causes the second vibrator to oscillate; a second container that houses the second vibrator and the second integrated circuit device; Equipped with the second integrated circuit device includes a second oscillation circuit that oscillates the second vibrator to output a second oscillation signal, a second output circuit that outputs a second output signal based on the second oscillation signal, and a second power supply circuit that supplies a second power supply voltage to the second oscillation circuit and the second output circuit, but does not include a frequency control circuit that generates a frequency control signal that includes at least one of a temperature compensation signal that compensates for a frequency temperature characteristic of the second oscillation signal and a frequency setting signal that sets the second oscillation signal to a frequency corresponding to a voltage of a signal input from outside the second integrated circuit device; the first container and the second container are the same type of container, the frequency control circuit is located between two circuits among the first oscillation circuit, the first output circuit, and the first power supply circuit; An oscillator group, wherein when the first oscillation circuit corresponds to the second oscillation circuit, the first output circuit corresponds to the second output circuit, and the first power supply circuit corresponds to the second power supply circuit, a distance between two circuits of the second integrated circuit device corresponding to the two circuits of the first integrated circuit device is smaller than a distance between the two circuits of the first integrated circuit device.

12. An oscillator group consisting of multiple types of oscillators including a first oscillator and a second oscillator, The first oscillator comprises: a first oscillator; a first integrated circuit device that causes the first vibrator to oscillate; a first container that houses the first vibrator and the first integrated circuit device; Equipped with the first integrated circuit device includes a first oscillation circuit that oscillates the first vibrator to output a first oscillation signal, and a frequency control circuit that generates a frequency control signal including at least one of a temperature compensation signal that compensates for a frequency temperature characteristic of the first oscillation signal and a frequency setting signal that sets the frequency of the first oscillation signal to a frequency corresponding to a voltage of a signal input from outside the first integrated circuit device, The second oscillator comprises: a second oscillator; and a second integrated circuit device that causes the second vibrator to oscillate; a second container that houses the second vibrator and the second integrated circuit device; Equipped with the second integrated circuit device includes a second oscillation circuit that oscillates the second vibrator to output a second oscillation signal, and does not include a frequency control circuit that generates a frequency control signal that includes at least one of a temperature compensation signal that compensates for the frequency temperature characteristic of the second oscillation signal and a frequency setting signal that sets the second oscillation signal to a frequency that corresponds to the voltage of a signal that is input from outside the second integrated circuit device; the first container and the second container are the same type of container, The frequency control circuit is a group of oscillators arranged in a divided area along a first side of the first integrated circuit device and a area along a second side of the first integrated circuit device opposite to the first side.

13. An oscillator group consisting of multiple types of oscillators including a first oscillator and a second oscillator, The first oscillator comprises: a first oscillator; a first integrated circuit device that causes the first vibrator to oscillate; a first container that houses the first vibrator and the first integrated circuit device; Equipped with The first integrated circuit device includes a first oscillation circuit that oscillates the first oscillator to output a first oscillation signal, a temperature compensation signal that compensates for the frequency temperature characteristics of the first oscillation signal, and a frequency control circuit that generates a frequency control signal including at least one of a frequency setting signal that sets the first oscillation signal to a frequency corresponding to a voltage of a signal input from outside the first integrated circuit device, and a variable capacitance circuit that is connected to the first vibrator and has a capacitance value that changes according to the frequency control signal, The second oscillator comprises: a second oscillator; and a second integrated circuit device that causes the second vibrator to oscillate; a second container that houses the second vibrator and the second integrated circuit device; Equipped with the second integrated circuit device includes: a second oscillation circuit that oscillates the second vibrator to output a second oscillation signal; a second power supply circuit that generates a second power supply voltage based on a power supply voltage and a ground voltage supplied from an external source and supplies the second power supply voltage to the second oscillation circuit; and a bypass capacitor that suppresses abrupt fluctuations in the power supply voltage or the second power supply voltage supplied from the external source, but does not include a frequency control circuit that generates a frequency control signal that includes at least one of a temperature compensation signal that compensates for a frequency temperature characteristic of the second oscillation signal and a frequency setting signal that sets the second oscillation signal to a frequency corresponding to the voltage of a signal input from the outside of the second integrated circuit device; the first container and the second container are the same type of container, the second oscillation circuit includes an amplifier circuit that amplifies a signal from the second vibrator and outputs the second oscillation signal, and a current source that supplies a current to the amplifier circuit; the second power supply circuit includes a bandgap reference circuit, an operational amplifier to which a reference voltage output from the bandgap reference circuit is input, and a filter configured with a resistor and a smoothing capacitor, which smoothes an output signal of the operational amplifier; an oscillator group, wherein at least one of the bypass capacitor, the smoothing capacitor, the current source, and the bandgap reference circuit is arranged in a second region of the second integrated circuit device corresponding to a first region of the first integrated circuit device in which the frequency control circuit and the variable capacitance circuit are arranged.

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