Manufacturing method for electro-optical device

Abstract

To provide a method for manufacturing an electro-optic device that can achieve miniaturization.SOLUTION: The method for manufacturing an electro-optic device includes the steps of: forming a recessed part in a substrate 10a; forming a first capacitive electrode 40a, a capacitive insulation film 40b, and a second capacitive electrode 40c along the recessed part; patterning the first capacitive electrode 40a, the capacitive insulation film 40b, and the second capacitive electrode 40c at one time; removing a part of the second capacitive electrode 40c; forming interlayer insulation films 11a, 11b, 11c; and etching a region in which a part of the second capacitive electrode 40c is removed until a part of the first capacitive electrode 40a is exposed in planer view, and forming a contact hole CNT3 which penetrates the interlayer insulation films 11a, 11b, 11c and the capacitive insulation film 40b.SELECTED DRAWING: Figure 11B

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing an electro-optical device. [Background technology]

[0002] Patent Document 1 discloses a structure of a capacitance element in which a dielectric layer is sandwiched between a first electrode in a lower layer and a second electrode in an upper layer.

[0003] The method for manufacturing a capacitor element involves forming a first electrode and then forming a dielectric layer on the first electrode. Next, an oxide film is formed that functions as an etching stopper layer when forming a second electrode. After that, the oxide film in the portion that will become the capacitor element is removed, and a film that will become the second electrode is formed on the dielectric layer and the oxide film. Finally, the capacitor element is completed by forming the second electrode by etching using the oxide film as an etching stopper layer.

[0004] As described in Patent Document 2, the capacitive element is formed along a convex shape or along a concave shape, thereby ensuring capacitance and realizing miniaturization. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-123142 [Patent Document 2] Japanese Patent Application Laid-Open No. 2015-094880 Summary of the Invention [Problem to be solved by the invention]

[0006] However, in conventional capacitor elements, particularly when the capacitor element is formed along a concave shape, there is a problem in that the oxide film used as an etching stopper layer cannot be completely removed and remains inside the concave capacitor element. [Means for solving the problem]

[0007] The method for manufacturing an electro-optical device includes: extending along the first direction Step of forming recesses forming a first capacitor electrode, a capacitor insulating film, and a second capacitor electrode along the recess; the first capacitor electrode, the capacitor insulating film, and the second capacitor electrode are simultaneously patterned. a step of removing a part of the second capacitance electrode; and a step of forming an interlayer insulating film. , the layer forming a light-shielding film after forming an interlayer insulating film; a transistor having a semiconductor layer extending along the first direction so as to overlap the recess; forming a gate electrode of the transistor; and before forming the gate electrode of the transistor, In plan view, The region from which the second capacitor electrode has been partially removed is etched until the first capacitor electrode is partially exposed. forming a first contact hole penetrating the interlayer insulating film and the capacitive insulating film by etching; and [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view showing the configuration of a liquid crystal device as an electro-optical device. [Figure 2] FIG. 2 is a cross-sectional view of the liquid crystal device shown in FIG. 1 taken along line AA. [Figure 3] 2 is an enlarged plan view of a portion G of the liquid crystal device shown in FIG. 1. FIG. [Figure 4] 4 is a cross-sectional view of the liquid crystal device shown in FIG. 3 taken along line BB and line CC. [Figure 5A] 1A to 1C are plan views illustrating a method for manufacturing a liquid crystal device. [Figure 5B] 5A to 5C are cross-sectional views illustrating a method for manufacturing a liquid crystal device. [Figure 6A] 1A to 1C are plan views illustrating a method for manufacturing a liquid crystal device. [Figure 6B] 5A to 5C are cross-sectional views illustrating a method for manufacturing a liquid crystal device. [Figure 7A] 1A to 1C are plan views illustrating a method for manufacturing a liquid crystal device. [Figure 7B] 5A to 5C are cross-sectional views illustrating a method for manufacturing a liquid crystal device. [Figure 8A]1A to 1C are plan views illustrating a method for manufacturing a liquid crystal device. [Figure 8B] 5A to 5C are cross-sectional views illustrating a method for manufacturing a liquid crystal device. [Figure 9A] 1A to 1C are plan views illustrating a method for manufacturing a liquid crystal device. [Figure 9B] 5A to 5C are cross-sectional views illustrating a method for manufacturing a liquid crystal device. [Figure 10A] 1A to 1C are plan views illustrating a method for manufacturing a liquid crystal device. [Figure 10B] 5A to 5C are cross-sectional views illustrating a method for manufacturing a liquid crystal device. [Figure 11A] 1A to 1C are plan views illustrating a method for manufacturing a liquid crystal device. [Figure 11B] 5A to 5C are cross-sectional views illustrating a method for manufacturing a liquid crystal device. [Figure 12A] 1A to 1C are plan views illustrating a method for manufacturing a liquid crystal device. [Figure 12B] 5A to 5C are cross-sectional views illustrating a method for manufacturing a liquid crystal device. [Figure 13A] 1A to 1C are plan views illustrating a method for manufacturing a liquid crystal device. [Figure 13B] 5A to 5C are cross-sectional views illustrating a method for manufacturing a liquid crystal device. [Figure 14A] 1A to 1C are plan views illustrating a method for manufacturing a liquid crystal device. [Figure 14B] 5A to 5C are cross-sectional views illustrating a method for manufacturing a liquid crystal device. [Figure 15] 5A to 5C are cross-sectional views illustrating a method for manufacturing a liquid crystal device. DETAILED DESCRIPTION OF THE INVENTION

[0009] In the following figures, three mutually orthogonal axes will be referred to as the X-axis, Y-axis, and Z-axis. The direction along the X-axis will be referred to as the "X direction," the direction along the Y-axis as the "Y direction," and the direction along the Z-axis as the "Z direction." The direction of the arrow is the + direction, and the direction opposite the + direction is referred to as the - direction. Note that the +Z direction is sometimes referred to as "up" or "upward," and the -Z direction as "down" or "downward," and the view from the +Z direction is also referred to as a planar view or planar view. In addition, the surface on the +Z side will be referred to as the top surface, and the surface on the opposite side, the -Z side, will be referred to as the bottom surface.

[0010] Furthermore, in the following description, for example, the expression "on the substrate" with respect to a substrate means that the substrate is placed in contact with the substrate, that the substrate is placed via another structure, or that a portion of the substrate is placed in contact with the substrate and a portion of the substrate is placed via another structure.

[0011] First, the configuration of a liquid crystal device 100 as an electro-optical device will be described with reference to FIGS.

[0012] As shown in Figures 1 and 2, the liquid crystal device 100 of this embodiment has an element substrate 10, a counter substrate 20 arranged opposite the element substrate 10, and a liquid crystal layer 13 sandwiched between the element substrate 10 and the counter substrate 20.

[0013] The substrate 10a of the element substrate 10 is made of, for example, a glass substrate, a quartz substrate, etc. The substrate 20a of the counter substrate 20 is made of, for example, a transparent substrate such as a glass substrate, a quartz substrate, etc.

[0014] The element substrate 10 is larger in size than the counter substrate 20 in a plan view. The element substrate 10 and the counter substrate 20 are joined via a sealant 14 arranged along the outer edge of the counter substrate 20. A liquid crystal having positive or negative dielectric anisotropy is sealed in the gap between the element substrate 10 and the counter substrate 20 to provide a liquid crystal layer 13.

[0015] A display region E including a plurality of pixels P arranged in a matrix is ​​provided inside the sealing material 14. Outside the display region E is a peripheral region F. In the peripheral region F, a parting portion 23 is provided between the sealing material 14 and the display region E, surrounding the display region E. A dummy pixel region (not shown) that does not contribute to display is provided on the side of the peripheral region F closest to the display region E.

[0016] A terminal section in which a plurality of external connection terminals 43 are arranged is provided in the peripheral region F of the element substrate 10. In the peripheral region F, a data line driving circuit 47 is provided between a first side section along the terminal section and the sealing material 14. In addition, in the peripheral region F, an inspection circuit 41 is provided between the sealing material 14 and the display region E along a second side section opposite the first side section.

[0017] In the peripheral region F, a scanning line driving circuit 45 is provided between the sealant 14 along the third and fourth sides that are perpendicular to the first side and face each other and the display region E. In addition, a plurality of wirings 49 that connect the two scanning line driving circuits 45 are provided between the sealant 14 on the second side and the inspection circuit 41.

[0018] The wiring connected to the data line driving circuit 47 and the scanning line driving circuit 45 is connected to a plurality of external connection terminals 43 arranged along the first side portion. The arrangement of the inspection circuit 41 is not limited to the above.

[0019] 2, on the surface of the substrate 10a facing the liquid crystal layer 13, there are provided a light-transmitting pixel electrode 15 provided for each pixel P, a transistor 30 serving as a switching element, a wiring 49, and an alignment film 12 that covers these. The transistor 30 and the pixel electrode 15 are components of the pixel P. The element substrate 10 includes the substrate 10a, the pixel electrode 15 provided on the substrate 10a, the transistor 30, the wiring 49, and the alignment film 12.

[0020] On the surface of the substrate 20a facing the liquid crystal layer 13, there are provided a parting portion 23, an insulating film 25 formed to cover the parting portion 23, a counter electrode 21 serving as a common electrode provided to cover the insulating film 25, and an alignment film 22 covering the counter electrode 21. The counter substrate 20 in this embodiment includes at least the parting portion 23, the counter electrode 21, and the alignment film 22. Note that, although this embodiment has shown an example in which the common electrode is disposed on the counter substrate 20 side as the counter electrode 21, the present invention is not limited to this.

[0021] 1, the scanning line driving circuit 45 and the inspection circuit 41 overlap the parting portion 23 in a plan view. The parting portion 23 functions as a light-shielding portion, blocking light L from a laser light source (not shown) incident from the counter substrate 20 side from entering peripheral circuits such as the scanning line driving circuit 45, thereby preventing malfunction of the peripheral circuits. The parting portion 23 also blocks unnecessary stray light from entering the display region E, thereby suppressing a decrease in contrast.

[0022] The insulating film 25 is made of an inorganic material such as silicon oxide (SiO2) that has optical transparency. The insulating film 25 covers the parting portion 23 and is provided so that the surface on the liquid crystal layer 13 side is flat.

[0023] The counter electrode 21 is covered with an insulating film 25 and is electrically connected to vertical conductive parts 7 provided at the four corners of the counter substrate 20. The vertical conductive parts 7 are electrically connected to a common wiring 9 described later.

[0024] The pixel electrode 15 and the counter electrode 21 are made of a transparent conductive film such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide). The alignment films 12 and 22 are selected based on the optical design of the liquid crystal device 100. Materials for forming the alignment films 12 and 22 include inorganic alignment films such as silicon oxide and organic alignment films such as polyimide.

[0025] Such a liquid crystal device 100 employs an optical design of a normally white mode in which the transmittance of pixel P when no voltage is applied is greater than the transmittance when voltage is applied, or a normally black mode in which the transmittance of pixel P when no voltage is applied is less than the transmittance when voltage is applied. In the liquid crystal device 100, polarizing elements are arranged on both the light incident side and light exit side according to the optical design.

[0026] In the present embodiment, an example will be described in which the above-mentioned inorganic alignment film is used as the alignment films 12 and 22, and liquid crystal having negative dielectric anisotropy is used, and an optical design of a normally black mode is applied.

[0027] Furthermore, in the above embodiment, a transmissive liquid crystal device 100 is exemplified as an electro-optical device, but the liquid crystal device 100 may be a reflective liquid crystal device or an LCOS (Liquid Crystal on Silicon) liquid crystal device.

[0028] Furthermore, the liquid crystal device 100 has been described as an example of an electro-optical device, but the present invention is not limited to this and may be applied to, for example, an organic EL (electro luminescence) device, an electrophoretic display panel using microcapsules, or the like.

[0029] Next, the configuration of the pixel P will be described with reference to FIGS.

[0030] 4, the element substrate 10 of the liquid crystal device 100 includes a substrate 10a, a capacitive element 40, a scanning line 3, a transistor 30, a data line 6, a common line 9, and a pixel electrode 15. The substrate 10a includes a recess 10b in which the capacitive element 40 is provided. Furthermore, a plurality of interlayer insulating films 11 are stacked on the substrate 10a.

[0031] The multiple interlayer insulating films 11 include, from the bottom up, a first interlayer insulating film 11a including a part of the capacitive element 40, a second interlayer insulating film 11b including the scanning line 3, a third interlayer insulating film 11c including the semiconductor layer 30a, a fourth interlayer insulating film 11d including the gate electrode 30g, a fifth interlayer insulating film 11e including the relay electrode 5c, a sixth interlayer insulating film 11f including the data line 6 and the capacitive line 8, and a seventh interlayer insulating film 11g including the common wiring 9.

[0032] Examples of materials for the plurality of interlayer insulating films 11 include silicon oxide (Non-doped Silicate Glass: NSG) and silicon nitride. In this embodiment, silicon oxide is used as the material for forming the interlayer insulating films 11.

[0033] The capacitor element 40 includes a first capacitor electrode 40a, a capacitor insulating film 40b, and a second capacitor electrode 40c stacked in this order from the substrate 10a side. Examples of materials for the first capacitor electrode 40a and the second capacitor electrode 40c include conductive polysilicon. The capacitor insulating film 40b is made of a dielectric material. Examples of dielectric materials include silicon nitride, silicon oxide, hafnium oxide, aluminum oxide, and tantalum oxide, and these films are used as a single layer or in combination.

[0034] 3, a portion of the capacitive element 40 is provided along a substantially rectangular recess 10b1 extending in the Y direction, which is the first direction. In this way, the recess 10b is formed to overlap with the semiconductor layer 30a, so that the aperture ratio can be maintained without narrowing the opening area. In addition, a portion of the capacitive element 40 is also provided along substantially rectangular recesses 10b2 and 10b3 extending in the X direction.

[0035] The scanning lines 3 also function as light-shielding films and are provided on the first interlayer insulating film 11a. As shown in FIG. 3, the scanning lines 3 are provided along the X direction between pixels P in a plan view. Known materials having light-shielding and conductive properties can be used for the scanning lines 3. Therefore, the scanning lines 3 mainly function to block light incident on the semiconductor layer 30a from below. In this embodiment, tungsten silicide is used as the material for forming the scanning lines 3.

[0036] The transistor 30 includes a semiconductor layer 30a provided on a second interlayer insulating film 11b, a third interlayer insulating film 11c functioning as a gate insulating film, and a gate electrode 30g provided on the third interlayer insulating film 11c. An LDD (Lightly Doped Drain) structure is formed in the semiconductor layer 30a of the transistor 30. The semiconductor layer 30a is made of, for example, conductive polysilicon. The gate electrode 30g is made of, for example, conductive polysilicon. As shown in FIG. 3, the semiconductor layer 30a extends along the Y direction, which is a first direction, in a plan view.

[0037] The gate electrode 30g is electrically connected to the scanning line 3 via contact electrodes 51 and 52. The contact electrodes 51 and 52 penetrate the third interlayer insulating film 11c and the second interlayer insulating film 11b.

[0038] The relay electrode 5a is electrically connected to the source / drain region 30d and the first capacitor electrode 40a via a contact electrode 53 that penetrates the third interlayer insulating film 11c, the second interlayer insulating film 11b, the first interlayer insulating film 11a, and the capacitor insulating film 40b.

[0039] The relay electrode 5b is electrically connected to the second capacitance electrode 40c via a contact electrode 54 provided to penetrate the third interlayer insulating film 11c, the second interlayer insulating film 11b, and the first interlayer insulating film 11a.

[0040] 3, the data line 6 extends in the Y direction between pixels P. The material for forming the data line 6 is not particularly limited as long as it is a conductive, low-resistance wiring material, and examples thereof include metals such as aluminum (Al) and titanium (Ti) and metal compounds thereof. The data line 6 is electrically connected to the source / drain region 30s of the semiconductor layer 30a via a contact hole CNT7.

[0041] The capacitance line 8 and the common wiring 9 are electrically connected to the counter electrode 21 and are given a common potential. As with the data line 6, the material for forming the capacitance line 8 and the common wiring 9 is not particularly limited as long as it is a conductive, low-resistance wiring material, and examples thereof include metals such as aluminum (Al) and titanium (Ti) and metal compounds thereof.

[0042] A pixel electrode 15 is provided on the seventh interlayer insulating film 11g. The pixel electrode 15 is made of a transparent conductive film such as ITO.

[0043] Although not shown, an alignment film 12 is provided to cover the pixel electrodes 15. The alignment film 12 of the element substrate 10 and the alignment film 22 of the counter substrate 20 described above are made up of an aggregate of columns formed by depositing an inorganic material such as silicon oxide from a predetermined direction, such as an oblique direction, and growing the columns. Furthermore, the liquid crystal molecules contained in the liquid crystal layer 13 shown in FIG. 2 have negative dielectric anisotropy with respect to the alignment films 12 and 22.

[0044] Next, a method for manufacturing the liquid crystal device 100 will be described with reference to Figures 5A to 15. Note that the following describes a method for manufacturing the element substrate 10 of the liquid crystal device 100. Note that in Figures 5A to 15, the plan views correspond to Figure 3, and the cross-sectional views correspond to Figure 4.

[0045] The element substrate 10 can basically be manufactured by a method used in known semiconductor processes, such as low-pressure CVD (Chemical Vapor Deposition), atmospheric CVD, plasma CVD, photolithography, sputtering, etching, and CMP (Chemical Mechanical Planarization), or a combination of these. While the following mainly describes a preferred manufacturing method, other manufacturing methods may also be used as long as they can form an equivalent structure and satisfy the functions and characteristics of the configuration.

[0046] 5A and 5B, recesses 10b are formed in a substrate 10a serving as an insulating member. As shown in FIG. 5A, recesses 10b1 are formed in a rectangular shape along the Y direction. In this embodiment, recesses 10b2 and 10b3 are also formed in the substrate 10a in the X direction to form the capacitive element 40. The insulating member is not limited to the substrate 10a, but also includes an interlayer insulating film 11 provided on the substrate 10a.

[0047] In the process shown in FIGS. 6A and 6B, a conductive polysilicon film 40a1, a silicon nitride-containing capacitive insulating film 40b1, and a conductive polysilicon film 40c1, which will later become the capacitive element 40, are sequentially formed on the substrate 10a including the recesses 10b1, 10b2, and 10b3. Next, the polysilicon film 40a1, the capacitive insulating film 40b1, and the polysilicon film 40c1 are simultaneously patterned by dry etching. Here, "simultaneous patterning" refers to sequential dry etching processes performed in the same equipment, regardless of whether the chambers are the same. This also applies hereinafter in this specification. This completes the capacitive element 40, including the first capacitive electrode 40a, the capacitive insulating film 40b, and the second capacitive electrode 40c, which correspond to the polysilicon film 40a1, the capacitive insulating film 40b1, and the polysilicon film 40c1, respectively.

[0048] 7A and 7B, the capacitive insulating film 40b is used as an etching stopper to remove a portion of the second capacitive electrode 40c, thereby exposing a portion 40b2 of the capacitive insulating film 40b.

[0049] 8A and 8B, a first interlayer insulating film 11a made of silicon oxide or the like is formed on a substrate 10a. Next, the scanning lines 3 made of tungsten silicide or the like are patterned and formed on the first interlayer insulating film 11a along the X direction so as to overlap the capacitive elements 40.

[0050] 9A and 9B, a second interlayer insulating film 11b made of silicon oxide or the like is formed on a substrate 10a. Next, a semiconductor layer 30a made of conductive polysilicon or the like is formed by patterning on the second interlayer insulating film 11b.

[0051] 10A and 10B, contact holes CNT1 and CNT2 are formed at positions that overlap, in plan view, with the protruding portions 3a and 3b of the scanning line 3. The protruding portions 3a and 3b are located on both sides of the channel region of the semiconductor layer 30a.

[0052] First, a third interlayer insulating film 11c made of silicon oxide or the like and functioning as a gate insulating film is formed on the substrate 10a. Next, contact holes CNT1 and CNT2 are formed through the third interlayer insulating film 11c and the second interlayer insulating film 11b at positions overlapping the protruding portions 3a and 3b of the scanning line 3 in a plan view, exposing a part of the scanning line 3.

[0053] In the process shown in Figures 11A and 11B, a contact hole CNT3 is formed as a first contact hole at a position overlapping with a portion 40a2 of the first capacitance electrode 40a in a planar view, and a contact hole CNT4 is formed as a second contact hole at a position overlapping with a portion 40c2 of the second capacitance electrode 40c using an etching process.

[0054] 7A and 7B , a contact hole CNT3 is formed so as to penetrate the third interlayer insulating film 11c, the second interlayer insulating film 11b, the first interlayer insulating film 11a, and the capacitive insulating film 40b, at a position overlapping in plan view with the portion 40a2 removed in the process shown in FIG. 7A and FIG. 7B , thereby exposing a portion of the first capacitive electrode 40a. The etching conditions are adjusted so that no film remains of the capacitive insulating film 40b and no penetration of the first capacitive electrode 40a occurs.

[0055] At the entrance side of the contact hole CNT3, a part of the third interlayer insulating film 11c covering the source / drain region 30d of the semiconductor layer 30a is removed, so that a part of the source / drain region 30d of the semiconductor layer 30a is exposed.

[0056] At the same time, a contact hole CNT4 is formed so as to penetrate the third interlayer insulating film 11c, the second interlayer insulating film 11b, and the first interlayer insulating film 11a at a position overlapping with a portion 40c2 of the second capacitance electrode 40c in a planar view, thereby exposing a portion of the second capacitance electrode 40c.

[0057] 12A and 12B, a conductive polysilicon film is formed on the inner walls and bottoms of the contact holes CNT1, CNT2, CNT3, and CNT4 and on the third interlayer insulating film 11c. The polysilicon film is then patterned to form the gate electrode 30g, contact electrodes 51, 52, 53, and 54, and relay electrodes 5a and 5b.

[0058] As a result, the gate electrode 30g is electrically connected to the scanning line 3 via the contact electrodes 51 and 52. The relay electrode 5a is electrically connected to the source / drain region 30d and the first capacitor electrode 40a via the contact electrode 53. In other words, the contact electrode 53 also functions as a source / drain electrode. The relay electrode 5b is electrically connected to the second capacitor electrode 40c via the contact electrode 54.

[0059] Furthermore, as described above, since the first capacitor electrode 40a, the capacitor insulating film 40b, and the second capacitor electrode 40c are patterned simultaneously, the positional accuracy of the formed capacitor element 40 can be improved. Furthermore, since the capacitor element 40 is formed in the recess 10b, miniaturization can be achieved while maintaining capacitance. In addition, since no etching stopper layer is formed to remove a portion of the second capacitor electrode 40c, the etching stopper layer can be prevented from remaining in the capacitor element 40.

[0060] 13A and 13B, a fourth interlayer insulating film 11d made of silicon oxide or the like is formed on the substrate 10a. Next, a contact electrode 55 is formed in the fourth interlayer insulating film 11d at a position overlapping the relay electrode 5a in a plan view, and a relay electrode 5c is formed by patterning on the fourth interlayer insulating film 11d.

[0061] 14A and 14B, a fifth interlayer insulating film 11e made of silicon oxide or the like is formed on a substrate 10a. Next, a contact electrode 57 is formed at a position overlapping the source / drain region 30s in a plan view, and a data line 6 is patterned and formed on the fifth interlayer insulating film 11e. At the same time, a contact electrode 56 is formed at a position overlapping the relay electrode 5b, and a capacitance line 8 is patterned and formed. At the same time, a contact electrode 58 is formed, and a relay electrode 5f is patterned and formed.

[0062] In the process shown in FIG. 15, the remaining manufacturing process, that is, the sixth interlayer insulating film 11f, contact electrodes 59 and 60, common wiring 9, seventh interlayer insulating film 11g, contact electrode 61, and pixel electrode 15 are formed.

[0063] As described above, the manufacturing method of the liquid crystal device 100 of this embodiment includes the steps of forming the recess 10b in the substrate 10a, forming the first capacitance electrode 40a, the capacitance insulating film 40b, and the second capacitance electrode 40c along the recess 10b, simultaneously patterning the first capacitance electrode 40a, the capacitance insulating film 40b, and the second capacitance electrode 40c, removing a portion of the second capacitance electrode 40c, forming interlayer insulating films 11a, 11b, and 11c, and etching the region from which the portion of the second capacitance electrode 40c has been removed until a portion of the first capacitance electrode 40a is exposed in a planar view, thereby forming a contact hole CNT3 that penetrates the interlayer insulating films 11a, 11b, and 11c and the capacitance insulating film 40b.

[0064] According to this method, the first capacitor electrode 40a, the capacitor insulating film 40b, and the second capacitor electrode 40c are patterned simultaneously, thereby improving the positional accuracy of the formed capacitor element 40. Furthermore, since the capacitor element 40 is formed along the recess 10b, miniaturization is possible while maintaining capacitance. In addition, since an etching stopper layer for removing a portion of the second capacitor electrode 40c is not formed, it is possible to prevent the etching stopper layer from remaining in the capacitor element 40.

[0065] In the method for manufacturing the liquid crystal device 100 of this embodiment, the capacitive insulating film 40b preferably contains silicon nitride. With this method, the capacitive insulating film 40b contains silicon nitride, which can improve the performance of the capacitive element 40.

[0066] Furthermore, in the method for manufacturing the liquid crystal device 100 of this embodiment, it is preferable that the step of forming the contact hole CNT3 simultaneously forms the contact hole CNT4 for electrically connecting the second capacitor electrode 40c and the capacitor line 8. According to this method, the contact holes CNT3 and CNT4 connected to the two capacitor electrodes 40a and 40c, respectively, are simultaneously formed, thereby reducing the number of steps.

[0067] Furthermore, in the manufacturing method of the liquid crystal device 100 of this embodiment, the recess 10b preferably extends along the Y direction at a position overlapping with the semiconductor layer 30a of the transistor 30 extending along the first direction. According to this method, the recess 10b is formed so as to overlap with the semiconductor layer 30a, so that the aperture ratio can be maintained without narrowing the aperture region between pixels P.

[0068] Furthermore, the method for manufacturing the liquid crystal device 100 of this embodiment preferably includes the steps of forming the scanning lines 3 after forming the first interlayer insulating film 11a and forming the transistors 30 at positions overlapping the scanning lines 3 in a plan view, and forming the contact holes CNT3 before forming the gate electrodes 30g of the transistors 30. According to this method, the contact holes CNT3 are formed before forming the gate electrodes 30g, and therefore the contact electrodes 53 can be formed simultaneously with the gate electrodes 30g.

[0069] Furthermore, in the method for manufacturing the liquid crystal device 100 of this embodiment, it is preferable to simultaneously form the gate electrode 30g and the contact electrode 53, which also functions as a source / drain electrode, so as to be in contact with the first capacitor electrode 40a via the contact hole CNT3. According to this method, the source / drain electrode can be formed simultaneously with the gate electrode 30g, thereby reducing the number of steps. [Explanation of symbols]

[0070] 3...scanning line, 3a, 3b...extension, 5a, 5b, 5c, 5f...relay electrode, 6...data line, 7...vertical conductive portion, 8...capacitance line, 9...common wiring, 10...element substrate, 10a...substrate, 10b, 10b1, 10b2, 10b3...recess, 11...interlayer insulating film, 11a...first interlayer insulating film, 11b...second interlayer insulating film, 11c...third interlayer insulating film, 11d...fourth interlayer insulating film, 11e...fifth interlayer insulating film, 11f...sixth interlayer insulating film, 11g...seventh interlayer insulating film, 12, 22...alignment film, 13...liquid crystal layer, 14...s a gate electrode, a first capacitance electrode, a first capacitance insulating film, a second capacitance electrode, a capacitance insulating film ...

Claims

1. forming a recess in an insulating member, the recess extending along a first direction; forming a first capacitance electrode, a capacitance insulating film, and a second capacitance electrode along the recess; The first capacitor electrode, the capacitor insulating film, and the second capacitor electrode are patterned simultaneously. The process and removing a portion of the second capacitance electrode; forming an interlayer insulating film; forming a light-shielding film after forming the interlayer insulating film; the recessed portion is formed along the first direction so as to overlap with the light-shielding film in a plan view and the recessed portion. forming a transistor having an extending semiconductor layer; Before forming the gate electrode of the transistor, in a plan view, The partially removed region is etched until a portion of the first capacitor electrode is exposed, forming a first contact hole penetrating an insulating film and the capacitive insulating film; A method for manufacturing an electro-optical device comprising:

2. 2. A method for manufacturing an electro-optical device according to claim 1, comprising: The method for manufacturing an electro-optical device, wherein the capacitive insulating film contains silicon nitride.

3. 3. A method for manufacturing the electro-optical device according to claim 1, comprising: In the step of forming the first contact hole, the second capacitor electrode and the capacitor line are electrically connected. Method for manufacturing an electro-optical device, simultaneously forming a second contact hole for electrical connection - Patents.com 。

4. 2. A method for manufacturing an electro-optical device according to claim 1, comprising: The gate electrode is connected to the first capacitor electrode through the first contact hole. and forming source and drain electrodes so as to form a conductive film.

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