Microstrip line and semiconductor device

Abstract

The microstrip line according to the present disclosure comprises a dielectric substrate having a top surface and a back surface opposite the top surface, a base metal provided on the back surface of the dielectric substrate, a first metal layer provided on the top surface of the dielectric substrate and having one or more opening areas formed therein that expose the dielectric substrate, a second metal layer provided on the top surface of the dielectric substrate and spaced apart from the first metal layer within the opening area, one or more mounted components that are capacitors or inductors connected between the first metal layer and the second metal layer, and a first via hole that penetrates the dielectric substrate from the top surface to the back surface and connects the second metal layer to the base metal.

Description

[Technical Field]

[0001] The present disclosure relates to a microstrip line and a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses an impedance matching circuit for performing input / output impedance matching of approximately less than 1 Ω on a circuit board for a power amplifier that amplifies high-frequency signals of 500 MHz or higher. In this impedance matching circuit, a ground layer is additionally formed in the dielectric layer directly below the transmission line pattern formed on the pattern wiring layer of the circuit board so as to narrow the pattern width of the transmission line. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-34951 Summary of the Invention [Problem to be solved by the invention]

[0004] Generally, in wireless communications, the transmitting power amplifier, which amplifies the power to the level radiated from the antenna, accounts for the majority of the power consumption of the transmitter. Therefore, highly efficient operation of the power amplifier makes it possible to reduce the power consumption of the transmitter. Furthermore, high-output operation of the power amplifier improves communication quality over a wide area and reduces the number of base stations, contributing to cost reduction. Therefore, there is a demand for high-output and high-efficiency power amplifiers, as well as reducing the power loss that occurs in the microstrip lines included in the power amplifiers.

[0005] Generally, in a high-output power amplifier for transmission, the optimum load impedance is small, so the width of the microstrip line on the substrate is large. However, the width of the microstrip line may be limited depending on factors such as the size of the package to be connected. When there is an upper limit on the line width, one possible method for matching at a lower load impedance is to add a ground layer within the dielectric layer to make the distance from the microstrip line to the ground thinner, as described in Patent Document 1.

[0006] However, due to constraints on the layer structure, it may not be possible to thin the area from the microstrip line to the ground. In this case, it is possible to increase the capacitance of the capacitor required for matching. Conventionally, such capacitors are placed on the outside of the microstrip line. This can cause an imbalance in impedance between the area near the center axis of the microstrip line and the outside, which can result in large power losses.

[0007] An object of the present disclosure is to provide a microstrip line and a semiconductor device that can suppress power loss. [Means for solving the problem]

[0008] A microstrip line according to the present disclosure includes a dielectric substrate having a top surface and a back surface opposite to the top surface, a base metal provided on the back surface of the dielectric substrate, a first metal layer provided on the top surface of the dielectric substrate and having one or more opening areas formed therein that expose the dielectric substrate, a second metal layer provided on the top surface of the dielectric substrate and spaced apart from the first metal layer within the opening areas, and a capacitor or inductor connected between the first metal layer and the second metal layer. Multiple The device includes a mounting component and a first via hole that penetrates the dielectric substrate from the top surface to the back surface and connects the second metal layer and the base metal. A microstrip line according to the present disclosure includes a dielectric substrate having a top surface and a back surface opposite the top surface, a base metal provided on the back surface of the dielectric substrate, a first metal layer provided on the top surface of the dielectric substrate and having a plurality of opening areas formed therein that expose the dielectric substrate, a second metal layer provided on the top surface of the dielectric substrate and spaced apart from the first metal layer within each of the plurality of opening areas, one or more mounted components that are capacitors or inductors connected between the first metal layer and the second metal layer in at least one of the plurality of opening areas, and a first via hole that penetrates the dielectric substrate from the top surface to the back surface in each of the plurality of opening areas and connects the second metal layer and the base metal. do. A microstrip line according to the present disclosure includes a dielectric substrate having a top surface and a back surface opposite to the top surface, a base metal provided on the back surface of the dielectric substrate, a first metal layer provided on the top surface of the dielectric substrate and having one or more opening areas formed therein that expose the dielectric substrate, a second metal layer provided on the top surface of the dielectric substrate and spaced apart from the first metal layer within the opening areas, one or more mounted components that are capacitors or inductors connected between the first metal layer and the second metal layer, and a second metal layer that penetrates the dielectric substrate from the top surface to the back surface and has one or more mounting components formed therein that are capacitors or inductors connected between the first metal layer and the second metal layer. The mounting component comprises a first via hole connecting a metal layer and the base metal, a third metal layer provided on the top surface of the dielectric substrate and spaced apart from the first metal layer and the second metal layer within the opening area, a fourth metal layer provided inside the dielectric substrate and spaced apart from the top surface and the back surface of the dielectric substrate, a second via hole provided in the dielectric substrate and connecting the third metal layer and the fourth metal layer, and a third via hole provided in the dielectric substrate and connecting the first metal layer and the fourth metal layer, and the mounting component connects the second metal layer and the third metal layer. [Effects of the Invention]

[0009] In the microstrip line according to the present disclosure, impedance imbalance can be suppressed by adjusting the components mounted in the opening area, thereby suppressing power loss. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a plan view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view of the microstrip line according to the first embodiment. [Figure 3] FIG. 1 is a plan view of a semiconductor device according to a first comparative example. [Figure 4] FIG. 10 is a plan view of a semiconductor device according to a second comparative example. [Figure 5A] FIG. 10 is a diagram showing the reflection coefficient of a semiconductor device according to a comparative example. [Figure 5B] FIG. 10 is a diagram illustrating a reflection coefficient of the semiconductor device according to the embodiment. [Figure 6] 10 is a diagram showing the improvement in efficiency and output power of the semiconductor device according to the first embodiment compared to the semiconductor device according to the comparative example. FIG. [Figure 7] FIG. 10 is a plan view of a semiconductor device according to a modification of the first embodiment. [Figure 8] FIG. 10 is a cross-sectional view of a microstrip line according to a second embodiment. [Figure 9] FIG. 10 is a plan view of a semiconductor device according to a third embodiment. [Figure 10] FIG. 10 is a cross-sectional view of a microstrip line according to a third embodiment. [Figure 11] FIG. 10 is a plan view of a semiconductor device according to a fourth embodiment. [Figure 12] FIG. 10 is a cross-sectional view of a microstrip line according to a fourth embodiment. [Figure 13] FIG. 11 is a plan view of a semiconductor device according to a fifth embodiment. [Figure 14] FIG. 10 is a cross-sectional view of a microstrip line according to a fifth embodiment. [Figure 15]FIG. 10 is a cross-sectional view of a microstrip line according to a fifth embodiment. [Figure 16] FIG. 13 is a plan view of a semiconductor device according to a sixth embodiment. [Figure 17] FIG. 13 is a cross-sectional view of a microstrip line according to a sixth embodiment. [Figure 18] FIG. 20 is a plan view of a semiconductor device according to a modification of the sixth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] The microstrip line and the semiconductor device according to each embodiment will be described with reference to the drawings. The same or corresponding components are designated by the same reference numerals, and the repeated description may be omitted.

[0012] Embodiment 1 FIG. 1 is a plan view of a semiconductor device 100 according to a first embodiment. FIG. 2 is a cross-sectional view of a microstrip line 3 according to the first embodiment. The semiconductor device 100 is, for example, a power amplifier for transmission. The semiconductor device 100 includes the microstrip line 3 and a package 8. The package 8 has a transistor 11 and an input matching circuit 12. The microstrip line 3 is electrically connected to an output side 11b of the transistor 11 via the package 8 and a wire 9. The input side 11a of the transistor 11 is electrically connected to the input matching circuit 12 via a wire 10. As will be described later, the transistor 11 may be composed of multiple transistors.

[0013] 2 is a cross-sectional view obtained by cutting FIG. 1 along an axis L2 along the longitudinal direction of the microstrip line 3. The microstrip line 3 has a dielectric substrate 25 having an upper surface 25a and a back surface 25b opposite the upper surface 25a. A base metal 26 is provided on the back surface 25b of the dielectric substrate 25. A metal layer 20 is provided on the upper surface 25a of the dielectric substrate 25. An opening area 24 is formed in the metal layer 20, exposing the dielectric substrate 25. A metal layer 18 is provided on the upper surface of the dielectric substrate 25, inside the opening area 24, and separate from the metal layer 20. The metal layers 18 and 20 are thin metal films.

[0014] The metal layer 20 refers to the area of ​​the metal layer on the dielectric substrate 25 that is used as a microstrip line. The area of ​​the metal layer on the dielectric substrate 25 that comes into contact with the ground and the island-like area provided in the margin for adjustment after assembly are not included in the metal layer 20.

[0015] The via hole 28 penetrates the dielectric substrate 25 from the upper surface 25a to the back surface 25b. The via hole 28 is composed of a through hole formed in the dielectric substrate 25 and a metal layer formed on the inner wall of the through hole. The via hole 28 electrically connects the metal layer 18 and the base metal 26. Furthermore, a plurality of capacitors 16 are connected between the metal layers 18 and 20. In other words, the metal layer 20 and the base metal 26 are electrically connected via the capacitors 16, the metal layer 18, and the via hole 28. The base metal 26 is electrically connected to ground.

[0016] Next, comparative examples of this embodiment will be described. Fig. 3 is a plan view of a semiconductor device according to a first comparative example. The comparative example differs from this embodiment in that the microstrip line 3a does not have an opening area 24. Furthermore, the microstrip line 3a has a capacitor 13 at an end in the width direction. The capacitor 13 is electrically connected to ground.

[0017] As mentioned above, there is generally an upper limit to the width of the microstrip line 3a. On the other hand, by increasing the capacitance value of the capacitor 13, the characteristic impedance of the microstrip line 3a can be reduced. However, there is a possibility that the self-resonant frequency of the capacitor will approach the frequency of the signal passing through the microstrip line 3a. This may result in large fluctuations in the capacitance value of the capacitor 13 due to self-resonance.

[0018] 4 is a plan view of a semiconductor device according to a second comparative example. In the microstrip line 3b of the second comparative example, capacitors 14 and 15 are provided instead of capacitor 13. Capacitors 14 and 15 are connected in parallel and electrically connected to ground. When the capacitance value of capacitor 13 corresponds to the sum of the capacitance values ​​of capacitors 14 and 15, the self-resonant frequency of capacitors 14 and 15 moves away from the frequency of the signal passing through the microstrip line 3b. Therefore, fluctuations in capacitance due to self-resonance can be suppressed.

[0019] However, the problem of impedance imbalance remains. Generally, high-output amplifiers are equipped with multiple transistors, resulting in differences in the load impedance seen from each transistor. In the comparative example, capacitors 14 and 15 are connected to the ends of microstrip line 3b in the width direction. This may result in a large imbalance between the vicinity of center axis L1 along the length direction of microstrip line 3b and the outer sides of microstrip line 3b in the width direction.

[0020] Next, the effects of this embodiment will be described. In this embodiment, a capacitor 16 can be connected to the opening area 24. In this case, a plurality of capacitors 16 can be connected radially from the metal layer 18 as the center, thereby increasing the number of capacitors 16. This allows the capacitance value of each capacitor 16 to be reduced, and the self-resonant frequency of the capacitor 16 to be moved away from the frequency of the signal passing through the microstrip line 3. Therefore, fluctuations in the capacitance value of the capacitor 16 can be suppressed. As a result, power loss can be suppressed.

[0021] Furthermore, in this embodiment, by adjusting the capacitance value of the capacitor 16 in the opening area 24, it is possible to cancel out the difference in inductance depending on the distance from the plurality of transistors 11. Furthermore, when a plurality of capacitors 16 are provided, the capacitance of each capacitor 16 can be adjusted independently. This further reduces the impedance imbalance, thereby reducing power loss.

[0022] FIG. 5A is a diagram showing the reflection coefficient of a semiconductor device according to a comparative example. FIG. 5A shows the reflection coefficient of a comparative example in which a capacitor is connected to an end of a microstrip line in the width direction. FIG. 5B is a diagram showing the reflection coefficient of a semiconductor device 100 according to an embodiment. FIG. 15B shows the reflection coefficient when the via hole 28 is viewed from the output side 11b of the transistor 11. m59 and m61 are the reflection coefficients Γ when the via hole 28 is viewed from both ends of the output side 11b of the transistor 11. m60 is the reflection coefficient Γ when the via hole 28 is viewed from the output side 11b of the transistor closest to the central axis of the transistor 11. The central axis of the transistor 11 is the central axis L4 shown in FIG.

[0023] In the comparative example shown in Fig. 5A, m59 and m61 are far apart, and it can be seen that the imbalance is large. On the other hand, in the present embodiment shown in Fig. 5B, m59 and m61 are close to each other. In other words, it can be seen that the difference in load impedance when looking at via hole 28 from output side 11b of transistor 11 is small, and the imbalance is suppressed.

[0024] 6 is a diagram showing the improvement in efficiency and output power of the semiconductor device 100 according to the first embodiment compared to the semiconductor device according to the comparative example. It can be seen that suppressing the imbalance improves the efficiency and output power of the amplifier. As described above, according to this embodiment, power loss can be suppressed in the microstrip line 3 having a low characteristic impedance.

[0025] 1, two capacitors 16 are provided in one opening area 24, but the number of capacitors 16 may be one or more. As described above, by providing multiple capacitors 16, it is possible to suppress fluctuations in capacitance value. However, even if only one capacitor 16 is provided, it is possible to obtain the effect of suppressing power loss by suppressing imbalance.

[0026] One or more capacitors 16 can be connected on an arc that is centered on metal layer 18 and forms the edge of metal layer 20. Generally, the length of a capacitor's short side or longer is required for soldering. Therefore, the distance between metal layer 18 and metal layer 20 should be less than the length of the long side of capacitor 16 and greater than the length of the short side of capacitor 16. Note that capacitor 16 does not need to be arranged along axis L2 or axis L3.

[0027] 1 shows an example in which one metal layer 18 is provided in one opening area 24, but multiple metal layers 18 may be provided inside one opening area 24. The number of metal layers 18 is equal to the number of via holes 28. In other words, multiple via holes 28 may be provided to connect multiple metal layers 18 to the base metal 26. FIG. 7 is a plan view of a semiconductor device 100 according to a modification of the first embodiment. In a microstrip line 203 according to the modification, two metal layers 18 are provided in one opening area 224. The opening area 24 is not limited to a circular shape, and may be an elliptical shape, a polygonal shape, or the like.

[0028] The diameter and number of via holes 28 formed within one opening area 24 are limited by the short side of the capacitor 16 and the width of the opening area 24. The upper limit of the diameter of the via hole 28 is, for example, the length obtained by subtracting twice the length of the short side of the capacitor 16 from the narrowest width of the opening area 24 passing through the intersection of the axis L2 and the axis L3 along the width direction of the microstrip line 3. This allows multiple capacitors 16 to be soldered to both sides of the metal layer 18. Furthermore, the upper limit of the number of via holes 28 formed within one opening area 24 is, for example, the quotient of the longest width of the opening area 24 passing through the intersection of the axis L2 and the axis L3 and the diameter of the via hole 28.

[0029] Furthermore, the number and arrangement of the opening areas 24 are not limited. For example, if the imbalance of the fundamental wave is small, the imbalance can be eliminated with a single opening area 24 as shown in FIG. 1. In this case, the opening area 24 may be located on the central axis L1 or on an axis L2 offset from the central axis L1. In many cases, it is preferable to locate the opening area 24 outside the central axis L1 of the microstrip line 3 in order to suppress the imbalance.

[0030] Furthermore, multiple opening areas 24 may be formed in the metal layer 20. For example, opening areas 24 may be provided on the outside and center of the microstrip line 3 in the width direction, and the capacitance value of the capacitor 16 may be adjusted in each opening area 24. This makes it possible to eliminate imbalance even when there is a large difference in imbalance. In order to leave an area on the metal layer 20 where the capacitor 16 can be soldered, the upper limit of the number of opening areas 24 on the axis L3 is, for example, the quotient of the length obtained by subtracting the length of the short side of the capacitor 16 from the width of the microstrip line 3 and the width of the opening area 24 in the direction of the axis L3.

[0031] Furthermore, in this embodiment, an example has been shown in which one or more capacitors 16 are provided as mounted components in one opening area 24. However, this is not limiting, and one or more inductors may be provided as mounted components instead of or together with the capacitors 16. In this case, the effect of suppressing imbalance can also be obtained. When multiple mounted components are provided in one opening area 24, each mounted component may be a capacitor 16 or an inductor. The above applies to each opening area 24 when multiple opening areas 24 are provided. Alternatively, only one or more capacitors 16 may be provided in one opening area 24, and only one or more inductors may be provided in the other opening areas 24. Alternatively, it is also possible for no mounted components to be provided in any of the multiple opening areas 24. Alternatively, the inductors may be wires.

[0032] The above-described modifications can be applied as appropriate to the microstrip lines and semiconductor devices according to the following embodiments. Note that the microstrip lines and semiconductor devices according to the following embodiments have many points in common with the first embodiment, so the following description will focus on the differences from the first embodiment.

[0033] Embodiment 2 FIG. 8 is a cross-sectional view of a microstrip line 303 according to the second embodiment. The cross section shown in FIG. 8 corresponds to the cross section along the axis L2 in FIG. 1. In the microstrip line 303 of this embodiment, a capacitor 16 and an inductor 27 are connected as multiple mounted components to one opening area 24. The capacitor 16 and the inductor 27 are connected in parallel. The inductor 27 is electrically connected to the via hole 28 via the metal layer 18.

[0034] In this embodiment, a double wave short circuit can be formed by the resonance of inductor 27 and capacitor 16, which short-circuits at twice the frequency of the signal passing through microstrip line 303. This improves the efficiency of the amplifier.

[0035] Embodiment 3 FIG. 9 is a plan view of a semiconductor device 100 according to the third embodiment. FIG. 10 is a cross-sectional view of a microstrip line 403 according to the third embodiment. FIG. 10 is a cross-sectional view obtained by cutting FIG. 9 along axis L3. In the microstrip line 403, the multiple opening areas 24 are provided on both sides in the width direction of the microstrip line 403, avoiding the center in the width direction of the microstrip line 403. In other words, the multiple opening areas 24 are concentrated on the outside of the microstrip line 403. In other words, the multiple opening areas 24 are not provided on the central axis L1 of the microstrip line 403.

[0036] The plurality of opening areas 24 are arranged in the width direction of the microstrip line 403. That is, the centers of the plurality of via holes 28 are provided on the axis L3. The plurality of opening areas 24 are also provided symmetrically with respect to the central axis L1 along the length direction of the microstrip line 403, for example.

[0037] In this embodiment, the difference in inductance depending on the distance from the package 8 on the left and right outer sides of the central axis L1 can be canceled out by independently adjusting the values ​​of the capacitors 16. This makes it possible to suppress imbalance. Also, by increasing the number of capacitors 16, the capacitance value per capacitor 16 can be reduced. This moves the self-resonant frequency of the capacitor 16 away from the frequency of the signal passing through the microstrip line, making it possible to reduce fluctuations in the capacitance value of the capacitor 16.

[0038] Embodiment 4 Fig. 11 is a plan view of a semiconductor device 100 according to a fourth embodiment. Fig. 12 is a cross-sectional view of a microstrip line 503 according to the fourth embodiment. In this embodiment, the multiple open areas 24 are provided asymmetrically with respect to a central axis L1 along the length direction of the microstrip line 503, and are aligned in the width direction of the microstrip line 503. In addition, the central axis L1 along the length direction of the microstrip line 503 is offset from the central axis L4 of the transistor 11 to which the microstrip line 503 is connected.

[0039] In this embodiment as well, the difference in inductance depending on the distance from the transistor 11 on the left and right outer sides of the central axis L1 can be canceled out by independently adjusting the capacitance of the capacitor 16. Furthermore, by increasing the number of capacitors 16, the capacitance value per capacitor 16 can be reduced. Therefore, the self-resonant frequency of the capacitor 16 is moved away from the frequency of the signal passing through the microstrip line, and fluctuations in the capacitance value of the capacitor 16 can be reduced.

[0040] 11, due to size constraints of the package 8 and the transistor 11, the central axis L4 of the transistor 11 and the central axis L1 of the microstrip line 503 may not coincide. In such cases, a difference in inductance depending on the distance from the transistor 11 is likely to occur between the left and right sides of the central axis L1 of the microstrip line 503. In this case, a larger capacitance value is required on the side where the inductance depending on the distance from the transistor 11 is larger.

[0041] In contrast to this, in this embodiment, the open areas 24 can be concentrated on the side farther from the transistor 11, that is, on the opposite side of the central axis L4 with respect to the central axis L1. This allows more capacitors 16 to be provided on the side farther from the transistor 11. Therefore, imbalance can be suppressed.

[0042] Embodiment 5. Fig. 13 is a plan view of a semiconductor device 100 according to the fifth embodiment. Figs. 14 and 15 are cross-sectional views of a microstrip line 603 according to the fifth embodiment. Fig. 14 is a cross-section obtained by cutting Fig. 13 along axis L3. Fig. 15 is a cross-section obtained by cutting Fig. 13 along axis L6.

[0043] In this embodiment, the multiple aperture areas 24 include aperture area 24b and aperture area 24a that is provided outside aperture area 24b in the width direction of microstrip line 603. In other words, aperture area 24a is provided on axis L2, and aperture area 24b is provided on axis L5 that is closer to central axis L1 than axis L2.

[0044] Furthermore, the opening areas 24a and 24b are provided at different positions in the longitudinal direction of the microstrip line 603. The center of the via hole 28 in the opening area 24a is provided on the axis L3, and the center of the via hole 28 in the opening area 24b is provided on the axis L6.

[0045] In this embodiment, by adjusting the capacitor 16, for example, the inductance can be made smaller on the metal layer 18 on the axis L3 and larger on the metal layer 18 on the axis L6. This makes it possible to suppress the difference in inductance depending on the distance from the transistor 11, thereby improving imbalance. Furthermore, by increasing the number of capacitors 16, the capacitance value per capacitor 16 can be reduced. Therefore, the self-resonant frequency of the capacitor 16 is moved away from the frequency of the signal passing through the microstrip line, and fluctuations in the capacitance value of the capacitor 16 can be reduced.

[0046] In this embodiment, opening area 24b is increased on the opposite side of opening area 24a from package 8. The upper limit of the number of opening areas 24b that can be increased in the length direction of microstrip line 603 is, for example, the quotient of the length from axis L3 to the end of microstrip line 603 in the opposite direction from package 8 and the width of opening area 24b.

[0047] Embodiment 6 FIG. 16 is a plan view of a semiconductor device 100 according to a sixth embodiment. FIG. 17 is a cross-sectional view of a microstrip line 703 according to the sixth embodiment. FIG. 17 is a cross-sectional view obtained by cutting FIG. 16 along axis L2. In this embodiment, in addition to metal layer 18, a metal layer 21 is provided on the upper surface 25a of the dielectric substrate 25 inside the opening area 724, separate from the metal layers 18 and 20. Furthermore, a metal layer 32 is provided inside the dielectric substrate 25, separate from the upper surface 25a and rear surface 25b of the dielectric substrate 25. The metal layers 21 and 32 are thin metal films.

[0048] Dielectric substrate 25 is provided with via hole 31 connecting metal layer 21 and metal layer 32, and via hole 30 connecting metal layer 20 and metal layer 32. Metal layer 32 is in contact with the lower ends of via holes 30 and 31. Metal layer 20 is in contact with the upper end of via hole 30, and metal layer 21 is in contact with the upper end of via hole 31.

[0049] A mounted component, such as capacitor 16, connects metal layer 18 to metal layer 21. That is, capacitor 16 is connected to metal layer 20 through metal layer 21, via hole 31, metal layer 32, and via hole 30. In this way, capacitor 16 is connected between metal layer 18 and metal layer 20.

[0050] In this embodiment, a double wave short circuit can be configured that shorts at twice the signal frequency due to the resonance between the inductance caused by the physical length of the metal layer 32 and the capacitor 16. By adjusting the physical length of the metal layer 32 and the value of the capacitor 16, the double wave short circuit can be set to a desired frequency.

[0051] The upper limit of the diameter of via hole 28 is, for example, the narrowest width of opening area 724 passing through the intersection of axis L7 and axis L2 minus twice the length of the short side of capacitor 16. The upper limit of the diameter of via hole 31 is, for example, the widest width of opening area 724 passing through the intersection of axis L3 and axis L2 minus twice the length of the short side of capacitor 16, the length of the long side of capacitor 16, and the diameter of via hole 28.

[0052] Furthermore, a plurality of metal layers 18, 21 and a plurality of via holes 28, 30, 31 may be provided for one opening area 724. Furthermore, the number of capacitors 16 can be increased as long as the sizes of metal layers 18, 21 allow. The number of metal layers 18 is equal to the number of via holes 28, and the number of metal layers 21 is equal to the number of via holes 31. Furthermore, a plurality of opening areas 724 may be provided. Furthermore, it is possible to combine this embodiment with embodiments 1 to 4.

[0053] The upper limit of the number of via holes 28 that can be formed within one opening area 724 is the quotient of the length obtained by subtracting twice the length of the short side of the capacitor 16, the length of the long side of the capacitor 16, and the diameter of the via hole 31 from the longest width of the opening area 724 passing through the intersection of the axis L2 and the axis L7, and the diameter of the via hole 28. The upper limit of the number of opening areas 724 on the axis L3 is, for example, the quotient of the length obtained by subtracting the length of the short side of the capacitor 16 from the width of the microstrip line 703, and the width of the opening area 724 in the direction of the axis L3.

[0054] 18 is a plan view of a semiconductor device 100 according to a modification of Embodiment 6. In a microstrip line 803 according to the modification, two via holes 28 and two capacitors 16 are provided in one opening area 824. In this manner, a plurality of metal layers 18 may be provided in one opening area 824 to increase the number of capacitors 16.

[0055] The technical features described in each embodiment may be used in appropriate combination. [Explanation of symbols]

[0056] 3, 3a, 3b Microstrip line, 8 Package, 9, 10 Wire, 11 Transistor, 11a Input side, 11b Output side, 12 Input matching circuit, 13, 14, 15, 16 Capacitor, 18, 20, 21 Metal layer, 24, 24a, 24b Opening area, 25 Dielectric substrate, 25a Top surface, 25b Back surface, 26 Base metal, 27 Inductor, 28, 30, 31 Via hole, 32 Metal layer, 100 Semiconductor device, 203 Microstrip line, 224 Opening area, 303, 403, 503, 603, 703 Microstrip line, 724 Opening area, 803 Microstrip line, 824 Opening area

Claims

1. a dielectric substrate having a top surface and a back surface opposite to the top surface; a base metal provided on the back surface of the dielectric substrate; a first metal layer disposed on the top surface of the dielectric substrate and having one or more open areas formed therein exposing the dielectric substrate; a second metal layer provided on the top surface of the dielectric substrate and spaced apart from the first metal layer within the opening area; a plurality of mounting components, each of which is a capacitor or an inductor connected between the first metal layer and the second metal layer; a first via hole that penetrates the dielectric substrate from the top surface to the back surface and connects the second metal layer and the base metal; A microstrip line comprising:

2. The microstrip line according to claim 1 , wherein a plurality of the mounting components are provided for one of the opening areas.

3. 3. The microstrip line according to claim 2, wherein the plurality of mounted components include a plurality of capacitors.

4. 3. The microstrip line according to claim 2, wherein the plurality of mounted components include a capacitor and an inductor.

5. a plurality of the second metal layers are provided inside one of the opening areas; 2. The microstrip line according to claim 1, wherein a plurality of the first via holes are provided to connect the plurality of second metal layers and the base metal.

6. A dielectric substrate having an upper surface and a back surface opposite the upper surface; a base metal provided on the back surface of the dielectric substrate; a first metal layer disposed on the top surface of the dielectric substrate and having a plurality of open areas formed therein exposing the dielectric substrate; a second metal layer provided on the upper surface of the dielectric substrate and spaced apart from the first metal layer within each of the plurality of opening areas; one or more mounted components, each of which is a capacitor or an inductor, connected between the first metal layer and the second metal layer in at least one of the plurality of open areas; a first via hole that penetrates the dielectric substrate from the upper surface to the rear surface in each of the plurality of opening areas and connects the second metal layer and the base metal; A microstrip line comprising:

7. The microstrip line according to claim 6 , wherein the plurality of open areas are provided on both sides of the microstrip line in the width direction, avoiding a central portion of the microstrip line in the width direction.

8. The microstrip line according to claim 7 , wherein the plurality of opening areas are provided symmetrically with respect to a central axis along the length direction of the microstrip line and are aligned in the width direction.

9. 7. The microstrip line according to claim 6, wherein the plurality of opening areas are arranged asymmetrically with respect to a central axis along the length direction of the microstrip line and aligned in the width direction of the microstrip line.

10. 10. The microstrip line according to claim 9, wherein the central axis along the length of the microstrip line is offset from the central axis of a transistor to which the microstrip line is connected.

11. the plurality of opening areas include a first opening area and a second opening area provided outside the first opening area in a width direction of the microstrip line; The microstrip line according to claim 6 , wherein the first opening area and the second opening area are provided at different positions in the longitudinal direction of the microstrip line.

12. A dielectric substrate having an upper surface and a back surface opposite the upper surface; a base metal provided on the back surface of the dielectric substrate; a first metal layer disposed on the top surface of the dielectric substrate and having one or more open areas formed therein exposing the dielectric substrate; a second metal layer provided on the top surface of the dielectric substrate and spaced apart from the first metal layer within the opening area; one or more mounted components, each of which is a capacitor or an inductor, connected between the first metal layer and the second metal layer; a first via hole that penetrates the dielectric substrate from the top surface to the back surface and connects the second metal layer and the base metal; a third metal layer provided on the upper surface of the dielectric substrate and spaced apart from the first metal layer and the second metal layer within the opening area; a fourth metal layer provided inside the dielectric substrate and spaced apart from the top surface and the back surface of the dielectric substrate; a second via hole provided in the dielectric substrate and connecting the third metal layer and the fourth metal layer; a third via hole provided in the dielectric substrate and connecting the first metal layer and the fourth metal layer; Equipped with The microstrip line is characterized in that the mounting component connects the second metal layer and the third metal layer.

13. The microstrip line according to any one of claims 1 to 12; a package having a transistor connected to the microstrip line; A semiconductor device comprising:

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