Computer-implemented method, computer system, and computer program (area- and power-efficient mechanism for waking up store-dependent loads following store-drain merging)

Abstract

To execute a store drain merge operation to wake up a sleep state load in relation to a store entry when writing from a store queue to a cache.SOLUTION: The system includes a store queue that holds a store entry and a load queue that holds a sleeping load entry on the store entry. A load in out-of-order execution can be bypassed from the store queue, but there are certain scenarios that cannot always be forwarded. In this case, the load waits in the load queue until a store finishes writing to a cache. A processor detects a call to a store drain merge operation and generates a pair of first and second store tags (stags) corresponding to drained first and second store entries. When detecting the even / odd stag pair, the processor invalidates the corresponding stag and wakes up the first and second load entries associated with an invalid period.SELECTED DRAWING: Figure 6A

Description

[Technical Field]

[0001] FIELD OF THE INVENTION Embodiments of the present invention relate generally to computer processing systems, and more particularly to the sequencing of instructions in out-of-order processors. [Background technology]

[0002] Microprocessors implemented in modern computer processing systems often execute loads and stores out of order to avoid being idle while waiting for previous instructions to complete, while the processor can process the next instruction, which can execute immediately and independently. When data loads and stores are executed out of order, dedicated buffers are implemented to track data dependencies between the loads and stores and ensure that the loads and stores observe the data in the correct program order. In certain architectures, data stores do not write to the cache until the stores complete their out-of-order processing, and as a result, various data loads that are younger in the program sequence may require the data results of older stores. Summary of the Invention [Problem to be solved by the invention]

[0003] However, correct handling of data loads must be implemented to ensure that the load does not read data from the cache because the data has not yet been written to the cache. [Means for solving the problem]

[0004] According to a non-limiting embodiment, a computer-implemented method is provided for performing a store drain merge operation to wake up sleeping load entries on dependent store entries. The method includes detecting, by a processor, an invocation to perform a store drain merge operation and generating a pair of store tags having a first store tag corresponding to a first store entry to be drained and a second store tag corresponding to a second store entry to be drained. The method further includes determining that the pair of store tags is one of an even-type store tag and an odd-type store tag. The pair of even-type store tags includes the first store tag as an even store tag and the second store tag as an odd store tag, while the pair of odd-type store tags includes the first store tag as an odd store tag and the second store tag as an even store tag. The method further includes, in response to the step of determining the pair of even-type store tags, disabling an odd store tag included in the pair of even-type store tags, and waking up a first load entry dependent on the even store tag and a second load entry dependent on the odd store tag based on the even store tag included in the pair of even-type store tags while the odd store tag is disabled.

[0005] According to another non-limiting embodiment, a computer system is configured to perform a store drain merge operation to wake up a sleeping load entry on a dependent store entry. The computer system includes a store queue unit configured to hold at least one store entry to be completed and a load queue unit configured to hold at least one sleeping load entry on a store entry included in the store queue unit. A processor is configured to detect a call to perform the store drain merge operation and generate a pair of store tags including a first store tag corresponding to a first store entry to be drained from the store queue unit and a second store tag corresponding to a second store entry to be drained from the store queue unit. The processor determines that the pair of store tags is one of an even-type store tag and an odd-type store tag. The pair of even-type store tags includes the first store tag as an even store tag and the second store tag as an odd store tag, while the odd-type store tag includes the first store tag as an odd store tag and the second store tag as an even store tag. The processor disables an odd store tag included in the pair of even type store tags in accordance with the stage of determining the pair of even type store tags, and while the odd store tag is disabled, wakes up a first load entry dependent on the even store tag and a second load entry dependent on the odd store tag based on the even store tag included in the pair of even type store tags.

[0006] According to yet another non-limiting embodiment, a computer program product is provided for controlling a computer system to perform a store drain merge operation to wake up a sleeping load entry on a dependent store entry. The computer program product includes a computer-readable storage medium having program instructions embodied thereon. The program instructions are executable by an electronic computer processor and control the processor to perform operations including: detecting a call to perform a store drain merge operation; and generating a pair of store tags having a first store tag corresponding to a first store entry to be drained and a second store tag corresponding to a second store entry to be drained. The method further includes determining that the pair of store tags is one of an even-type store tag and an odd-type store tag. The pair of even-type store tags includes the first store tag as an even store tag and the second store tag as an odd store tag, while the odd-type store tag includes the first store tag as an odd store tag and the second store tag as an even store tag. The method further includes, in response to the step of determining the pair of even-type store tags, disabling an odd store tag included in the pair of even-type store tags, and waking up a first load entry dependent on the even store tag and a second load entry dependent on the odd store tag based on the even store tag included in the pair of even-type store tags while the odd store tag is disabled.

[0007] Additional technical features and advantages are realized through the techniques of the present invention. Embodiments and aspects of the present invention are described in detail herein and are considered a part of the claimed subject matter. For a better understanding, please refer to the detailed description and drawings. [Brief explanation of the drawings]

[0008] The details of the exclusive rights set forth herein are particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The above and other features and advantages of embodiments of the present invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0009] [Figure 1] FIG. 1 is a block diagram of an exemplary computer system for use in connection with one or more non-limiting embodiments.

[0010] [Figure 2] FIG. 1 illustrates a block diagram of a load store unit included in a computer processing system according to a non-limiting embodiment.

[0011] [Figure 3] 1 illustrates a store queue unit included in a load store unit according to a non-limiting embodiment.

[0012] [Figure 4] 1 illustrates a store queue unit operating in a first mode to read a single 16-byte store queue entry, according to a non-limiting embodiment.

[0013] [Figure 5] 10 illustrates a store queue unit operating in a second mode reading pairs of 16-byte store queue entries, according to a non-limiting embodiment.

[0014] [Figure 6A] 1 illustrates a flow diagram showing a method for waking up a sleeping load on a dependent store entry, according to a non-limiting embodiment. [Figure 6B] 1 illustrates a flow diagram showing a method for waking up a sleeping load on a dependent store entry, according to a non-limiting embodiment. [Figure 6C] 1 illustrates a flow diagram showing a method for waking up a sleeping load on a dependent store entry, according to a non-limiting embodiment.

[0015] [Figure 7] 1 illustrates a flow diagram showing a method for performing a store drain merge operation according to a non-limiting embodiment.

[0016] [Figure 8] 1 illustrates a block diagram of a computer system that may implement some or all aspects of one or more non-limiting embodiments.

[0017] The drawings illustrated herein are exemplary. There may be many variations to the drawings or the operations described therein without departing from the spirit of the invention. For example, operations may be performed in a different order, or operations may be added, deleted, or modified. Also, the term "coupled" and variations thereof describe the existence of a communication path between two elements, and do not imply a direct connection between elements where there are no intervening elements / connections between them. All of these variations are considered part of the specification.

[0018] In the accompanying drawings and the following detailed description of the disclosed embodiments, various elements shown in the drawings are provided with two or three digit reference numerals. With few exceptions, the left-most digit of each reference numeral corresponds to the figure in which the element is first shown. DETAILED DESCRIPTION OF THE INVENTION

[0019] As described above, out-of-order execution uses precise data load handling to ensure that a load does not read data from the cache before the data has actually been written to the cache. To optimize performance, a "hibernation" process may be used, in which a load reads data from a buffer (sometimes referred to as a "store queue") that holds pending store data. If there is an overlapping address between a load and a store, the store may then forward its data to the load. However, there are certain scenarios in which the store cannot always forward its data to the load. If this occurs, then the load must "hibernate" in the load queue or be temporarily set to "sleep" until the store completes and is written to the cache, so that the load can read the store's data from the cache. This is generally achieved by assigning each load in a processor a store "tag" (i.e., "stag"). A given stag is defined by a number of bits (e.g., 7 bits) and serves as a unique identifier for each store in the processor.

[0020] Stores always write to the cache in program order. When a store writes to the cache, it broadcasts its store tag to a load queue structure that contains one or more loads "sleeping" on their associated stores. The load queue structure performs a content addressable memory compare to find all loads waiting on their associated stores. If there is a compare match, the load queue commands the corresponding load to "wake up" and access the cache to return the data.

[0021] Generally, the above-described hibernation process is expensive to implement in hardware and can consume excessive amounts of power. As an alternative solution, some computing systems have managed to "merge" data stores when writing to the cache by grouping stores that are adjacent in memory and writing them to the cache in the same processor cycle. These groupings are always done in pairs of two if this is achievable in a single given processor cycle. This allows for doubling the bandwidth at which data stores write to the cache, thereby improving computer processing performance. However, when two stores write to the cache simultaneously, each store has its own unique identifying store tag ("stag"), and multiple loads can sleep on each store individually. To manage the second store tag associated with the second store in the pair, a second dedicated compare port can be added to a large load queue structure that can send both store tags at once to be compared. However, this solution adds significant cost to the computer processing system in terms of hardware area and power.

[0022] According to one or more non-limiting embodiments, a computer processing system is provided that implements a store drain merge operation capable of waking up loads based on their dependent stores without adding a second compare port. More specifically, a limited number of store tags are assigned sequentially in a circular order (sometimes referred to as a "round-robin order") that matches the program order of stores. For example, store tag 0 is assigned to the first store observed by a program, store tag 1 is observed by the next store, and so on. When store tags run out (i.e., when the number of assigned store tags reaches a set limit), the processor stalls until more store tags become available. When stores reach their "tag space" limit, younger stores in the program sequence simply wrap around store tag 0 again if store tag 0 is available. The processor accounts for the age of stores by maintaining an "oldest store tag" pointer that knows if this wraparound case occurs. With this in mind, a computer processing system according to one or more non-limiting embodiments of the present invention avoids the need to implement a second compare port in the load queue structure by grouping drain data stores into pairs of even and odd pairs to determine which loads to wake up from hibernation. Even stores are associated with even store tags, while odd stores are associated with odd store tags. Because all store drains are in order, if a store associated with tag(n) is drained, then the store associated with store tag(n+1) is guaranteed to be drained next. When the computer processing system initiates a store drain merge, the least significant bit (LSB) comparison becomes invalid, which essentially indicates that all loads waiting on store tag(n) and store tag(n+1) will wake up simultaneously.

[0023] In some cases, a store drain merge may be initiated during a given cycle associated with a first store being an odd store and a second store being an even store. Thus, in one or more non-limiting embodiments of the invention, the store drain merge described herein performs different operations based on whether the first store is an even store and the second store is an odd store, or whether the first store is an odd store and the second store is an even store.

[0024] For example, if a store-drain merge occurs on an odd store to write to the cache during a given cycle (n), then the double-drain tag comparison is grouped by disabling the LSB comparison for the next processor cycle (n+1), but only if there is an additional drain in the next cycle (n+1). If there is no drain in the next cycle (n+1), then the store tag drained in the previous cycle (n-1) is added to the single store tag and woken up in the immediately following cycle (n+1), thereby individually waking up the even store tag. If double writes continue to occur on back-to-back boundaries associated with odd store tags, then the processor continues to delay for the next single cycle until it discovers a "hole" or "catch-up" event in the store-write sequence and essentially "catches up." That is, delayed wake-up (i.e., delaying wake-up for the next cycle) can be performed continuously until a given cycle in the sequence no longer observes a double store-write, i.e., a store-drain merge operation.

[0025] Referring now to FIG. 1 , a block diagram of a processing system 100 including an instruction sequencing unit (ISU) for wide vector execution of an out-of-order (OoO) processor in single-threaded mode is generally shown in accordance with one or more embodiments of the present invention. The system 100 shown in FIG. 1 includes an instruction fetch unit / instruction decode unit (IFU / IDU) 106 that fetches and decodes instructions for input to a setup block 108, which prepares the decoded instructions for input to a mapper 110 of the ISU. According to one or more embodiments, six instructions at a time from a thread may be fetched and decoded by the IFU / IDU 106. According to one or more embodiments of the present invention, the six instructions sent to the setup block 108 may include six non-branch instructions, five non-branch instructions and one branch instruction, or four non-branch instructions and two branch instructions. In one or more embodiments, the setup block 108 checks whether there are enough resources, such as entries in the issue queue, completion tables, mappers, and register files, before transmitting fetched instructions to these blocks in the ISU.

[0026] The mappers 110 shown in Figure 1 map programmer instructions (e.g., logical register names) to the processor's physical resources (e.g., physical register addresses). Various mappers 110 are shown in Figure 1, including a condition register (CR) mapper, a link / count (LNK / CNT) register mapper, an integer exception register (XER) mapper, a unified mapper (UMapper) for mapping general purpose registers (GPRs) and vector-scalar registers (VSRs), an architected mapper (ARCH Mapper) for mapping GPRs and VSRs, and a floating-point status and control register (FPSCR) mapper.

[0027] The output from the setup block 108 is also input to a global completion table (GCT) 112 for tracking instructions currently in the ISU. The output from the setup block 108 is also input to a dispatch unit 114 for dispatching instructions to the issue queues. The ISU embodiment shown in Figure 1 includes a CR issue queue, CR ISQ 116, which receives and tracks instructions from the CR mapper and issues 120 them to an instruction fetch unit (IFU) 124 for executing CR logical and move instructions. Also shown in Figure 1 is a branch issue queue, Branch ISQ 118, which receives and tracks branch instructions and LNK / CNT physical addresses from the LNK / CNT mapper. Branch ISQ 118 may issue 122 instructions to IFU 124 to redirect an instruction fetch if the predicted branch address or direction, or both, are incorrect.

[0028] The instructions output from the dispatch logic and renamed registers from the LNK / CNT mapper, XER mapper, UMapper GPR / VSR, ARCH mapper GPR / VSR, and FPSCR mapper are input to issue queue 102. As shown in Figure 1, issue queue 102 tracks issued floating-point instructions (Fx), load instructions (L), store instructions (S), and vector-scalar unit (VSU) instructions. As shown in the embodiment of Figure 1, issue queue 102 is divided into two sections, ISQ0 1020 and ISQ1 1021, with each section holding 48 instructions.

[0029] When the processor is running in ST mode, issue queue 102 may be used as a single logical issue queue containing both ISQ0 1020 and ISQ1 1021 to process all instructions of a single thread (all 96 instructions in this example). When the processor is running in MT mode, ISQ0 1020 may be used to process 48 instructions from a first thread, and ISQ1 1021 is used to process 48 instructions from a second thread.

[0030] As shown in Figure 1, issue queue 102 issues instructions to execution units 104, which are divided into two groups: execution units 1040 and 1041. Both groups of execution units 1040 and 1041 shown in Figure 1 include full fixed-point execution units (Full FX0, Full FX1), load execution units (LU0, LU1), simple fixed-point, store data, and store address execution units (Simple FX0 / STD0 / STA0, Simple FX1 / STD1 / STA1), and floating-point, vector and multimedia extension, decimal floating-point, and store data execution units (FP / VMX / DFP / STD0, FP / VMX / DFP / STD1). LU0, Simple FX0 / STD0 / STA0, and FP / VMX / DFP / STD0 collectively form load-store unit (LSU) 1042. Similarly, LU1, simple FX1 / STD1 / STA1, and FP / VMX / DFP / STD1 form LSU 1043. Although ISQ 104 is shown with separate execution units 1040 and 1041, it should be understood that a single execution unit may be implemented without departing from the scope of the present invention.

[0031] 1, when the processor is executing in ST mode, a first group of execution units 1040 executes instructions issued from ISQ0 1020, and a second group of execution units 1041 executes instructions issued from ISQ1 1021. In an alternative embodiment, when the processor is executing in ST mode, instructions issued from both ISQ0 1020 and ISQ1 1021 in issue queue 102 may be issued to an execution unit in either the first group of execution units 1040 or the second group of execution units 1041.

[0032] According to one or more embodiments, when the processor is running in MT mode, a first group of execution units 1040 executes instructions of a first thread issued by ISQ0 1020, and a second group of execution units 1041 executes instructions of a second thread issued by ISQ1 1021.

[0033] 1 are intended to be exemplary in nature, as embodiments of the present invention may be implemented for issue queues and other elements of various different sizes. According to one or more embodiments of the present invention, the size is selectable or programmable.

[0034] Referring to FIG. 2 , an LSU 1042 included in computer processing system 100 is shown according to a non-limiting embodiment. The illustrated LSU 1042 facilitates the execution of store drain merge operations capable of waking up loads based on their dependent stores without the addition of a second compare port. However, it should be noted that the embodiments described herein are not limited to such an LSU. LSU 1042 includes one or more store queue units (STQs) 220 that hold store entries and one or more load queue units (LDQs) 225 that hold load entries. In the exemplary embodiment of FIG. 2 , LSU 1042 includes two STQs 220 (STQ0 and STQ1) and two LDQs 225 (LDQ0 and LDQ1). More or fewer STQs 200 or LDQs 225, or both, may be implemented in LSU 1042. The STQs 200 and LDQs 225 may also be designed and configured to have varying amounts of entries. In one or more non-limiting embodiments, for example, LDQ 225 may have 64 entries, while STQ 200 may have 40 entries. However, it should be understood that more or fewer load entries or store entries, or both, may be implemented.

[0035] STQ and LDQ entries are assigned (allocated) when an entry in the queue is available, typically in program order at dispatch, e.g., by a dispatch unit. STQ entries are typically freed (deallocated) when a store instruction is executed and the store is drained to the processor cache 250 (e.g., the L1 processor cache). LDQ entries are typically freed (deallocated) when a load is completed (retired) and fully executed within the processor core.

[0036] 3, an example of an STQ 300 included in LSU 1042 is shown according to a non-limiting embodiment. STQ 300 may include a store data queue (SDQ) 301 and a store reorder queue (SRQ) 302. SDQ 301, which in some embodiments may be integrated as part of SRQ 302 itself to further save chip area, is configured to store the translated address instruction or data associated with a given store queue entry.

[0037] SRQ 302 may store control bits for store entries in SDQ 301. SRQ 302 may also keep track of executed store instructions, determine the next store instruction to complete, and determine when data is available in SDQ 301. In one or more non-limiting embodiments, SRQ 302 cycles through the allocation of order entries, cycles through the draining of order entries, and cycles through the deallocation of order entries.

[0038] SRQ entries are allocated at dispatch, where the dispatched store tag (stag) is filled into the correct column. Each stag is defined by a set number of bits and is an index to an SRQ entry. In one or more non-limiting embodiments, each stag is defined by seven bits. However, it should be understood that a stag may contain more or fewer bits without departing from the scope of the present invention. Additionally, SRQ entries are deallocated at store drain. In one or more examples, a stag array holds "overflow" dispatches. For example, if the desired column in the SRQ indicates that SRQ entry "x" is still in use, information is written to the stag array at dispatch. When SRQ entry "x" is deallocated, its corresponding column in the SRQ overflow stag structure is read and copied to the main SRQ stag array structure (i.e., reading the overflow itag structure is gated depending on whether there are any valid entries in the overflow stag array for a given thread / region). SRQ 302 sends stag to issue queue ISQ0 / 1 when the store is drained and deallocated.

[0039] Continuing with reference to FIG. 3 in conjunction with FIGS. 4 and 5, STQ 300 includes a store drain merge control input 303, a stag output 310, and a drain done output 312. Store drain merge control input 303 is configured to receive a store drain merge control signal 304 that invokes either a first mode or a second mode of STQ 300. The first mode reads a single 16-byte store queue entry, while the second mode reads a pair of 16-byte store queue entries. Stag output 310 outputs to LDQ 225 either a single stag corresponding to a single store entry read from STQ 300 in response to an invocation of the first mode, or a pair of stags indicating a pair of adjacent store entries in response to an invocation of the second mode. A pair of stags may be defined as either an even-type store tag pair, where the first store tag is an even store tag and the second store tag is an odd store tag, or an odd-type store tag, where the first store tag is an odd store tag and the second store tag is an even store tag. The drain done output 312 outputs a drain done signal (D) to the LDQ 225 indicating the completion of a single drain when operating in the first mode, or the completion of a pair of drains when operating in the second mode.

[0040] 4, for example, illustrates an STQ 300 operating in a first mode to read a single 16-byte store queue entry, according to a non-limiting embodiment. In response to the system 100 determining that the store entry to be drained does not have adjacent addresses, the computing system 100 generates a logic 0 control signal 304 (e.g., a 0 bit) applied to the store drain merge control input 303. The logic 0 invokes the first mode, which causes the STQ 300 to read a single 16-byte store queue entry 306a during a single clock cycle and output a single stag 307a provided to the LDQ 225. Once the store drain entry 306a is completed, the SRQ 300 outputs a drain done signal (D) to the LDQ 225, which wakes up any sleeping loads in the LDQ 225. The LDQ 225 matches the stag 307a of the completed store entry 306a with one or more loads that were previously waiting on the store entry for completion, and executes each matching load entry to read the corresponding data from the cache 250 (e.g., L1 250).

[0041] Referring to FIG. 5, the STQ 300 is shown operating in a second mode to read a pair of 1-byte store queue entries according to a non-limiting embodiment. In response to the system 100 determining that one or more store entries to be drained have adjacent addresses, the computing system 100 generates a logic 1 control signal 304 (e.g., a 1-bit) applied to the store drain merge control input 303. The logic 1 invokes the second mode, or "store drain merge" operation, which causes the STQ 300 to read a pair of 16-byte store queue entries 306a and 306b in a single clock cycle. In this mode, the STQ 300 also outputs a pair of stags 307a and 307b corresponding to the two adjacent store entry drains 306a and 306b to the LDQ 225. Once the two store drain entries 306a and 306b are completed, the SRQ 300 outputs a drain done signal (D) to the LDQ 225, which wakes up any sleeping loads in the LDQ 225. Thus, LDQ 225 matches the stag of the completed store entry with one or more woken up loads that were previously waiting on the store entry for completion, and writes each matching load entry to cache 250 (e.g., L1 250).

[0042] As described above, the LDQ receives a pair of stags corresponding to a pair of store drain entries. If a pair of stags corresponds to a pair of store drain entries with immediately adjacent addresses (i.e., the first store entry is an address and the second store entry is an odd address), the least significant bit (LSB) of the stags will have a difference of 1. For example, an even stag may be associated with the first store entry, and an odd stag with a difference of '1' in its LSB may be associated with the second store entry with an immediately adjacent address. Thus, rather than performing two separate comparisons in the LDQ 225 using two stags, the LDQ negates the LSB of the odd stag and performs a single comparison on the woken up load entry using the single even stag.

[0043] In some cases, store merges for writing caches can occur on odd boundaries. For example, the first store entry can be an odd address, such that the immediately adjacent entry is an even address. In this case, the system uses comparison logic that allows odd and even stags to be grouped together by disabling the LSB comparison for the next processor cycle if there is an additional drain in that cycle. If there is no drain in that cycle, then a drain is added to the stags drained in the previous cycle, and a single stag is woken up in the next cycle, which wakes up the even stags. If double writes continue to occur on back-to-back boundaries aligned with odd store tags, then the processor continues the delay sequence until it has an opportunity to essentially catch up and balance the store-write sequence.

[0044] 6A, 6B, and 6C, a flow diagram illustrating comparison logic for waking up dependent loads that are asleep until the corresponding store drain entry writes to the cache is shown according to a non-limiting embodiment. The method begins at operation 600, and at operation 602, a determination is made whether a store drain merge is initiated in the current cycle. In this example, the current cycle is initially the first cycle (e.g., cycle "0") of multiple consecutive cycles (e.g., 0 through 9). The term "store drain merge" referenced in FIGS. 6A-6C refers to "merging" data stores by writing a pair of stores having immediately adjacent addresses (e.g., even and odd, or odd and even) to the cache in the same processor cycle. If it is determined that there are no immediately adjacent stores following the store data write instruction, a store drain merge operation is not invoked at operation 602, and the method proceeds to operation 604 (see FIG. 6B).

[0045] At operation 604, a determination is made whether the previous cycle performed a store drain merge operation. As described above, the current cycle at this stage of the process flow is the first cycle (i.e., cycle "0"). Therefore, a store drain merge operation was not performed in the previous cycle, and the method proceeds to operation 606, where a single stag corresponding to the single store drain entry is generated. At operation 608, a sleeping load in LDQ 225 is compared to the single stag. At operation 610, the load entry in LDQ 225 corresponding to the single stag is woken up, and the method ends at operation 612.

[0046] Referring back to operation 602 and the store drain merge initiated in the first cycle (i.e., a pair of store entries with adjacent addresses present in cycle 0), the method proceeds to operation 614, where a first stag corresponding to the first store entry and a second stag corresponding to the second store entry are generated. In operation 616, a determination is made whether the first stag is an even stag (i.e., corresponding to a store entry with an even address) or an odd stag (i.e., corresponding to a store entry with an odd address). If the first stag is an even stag, the system determines that the second stag is an odd stag and negates the LSB of the odd stag in operation 618. In operation 620, sleeping loads in LDQ 225 are compared only with even stags. In operation 622, loads sleeping on both even and odd stags are woken up only based on the comparison of the even stag, and the method ends at operation 624.

[0047] Referring back to operation 616, store drain merging may occur on odd boundaries. That is, the first stag may correspond to a store entry with an odd address, and the second stag may correspond to a store entry with an even address. Therefore, the first stag is determined to be an odd stag, and the method proceeds to operation 626, where the LSB of the even stag is negated to delay the wake-up of sleeping loads at the even stags (see FIG. 6C ). In operation 628, sleeping loads in LDQ 225 are compared only with odd stags, and in operation 630, sleeping loads on odd stags are woken up only based on the comparison of odd stags. In operation 632, the current cycle is incremented, and the method returns to operation 602.

[0048] Referring back to operation 602, a determination is made whether a store drain merge is initiated in the current cycle. At this stage in the process flow, the current cycle is the next cycle in the sequence (e.g., cycle "1"). If a store drain merge is initiated in the current cycle, the method proceeds to operation 614 and repeats the operations described above.

[0049] However, if a store drain merge has not been initiated (ie, no immediately adjacent store entries are available), then a store drain merge operation is not invoked in operation 602 and the method proceeds to operation 604 (see FIG. 6B).

[0050] At operation 604, a determination is made whether the previous cycle performed a store-drain-merge operation. Unlike the previous scenario, at this stage of the current cycle of the process flow, the current cycle has been incremented from the initial cycle. If a store-drain-merge operation was not performed in the previous cycle, the method repeats operations 606-612 described above.

[0051] However, if a drain merge operation was performed in the previous cycle, the method proceeds to operation 634 to determine whether a store drain was invoked in the current cycle. If a store drain was not invoked in the current cycle, a "catch-up" event is detected, which provides an opportunity to end the load wake-up delay in response to the even store tag. Thus, the odd stag from the previous cycle is incremented by "1" in operation 648, thereby calculating a new even stag. In operation 650, one or more loads in LDQ 225 are woken up based on the newly calculated single even stag, and the method ends at operation 652.

[0052] Returning to operation 634, a store drain may be invoked in the current cycle. Accordingly, the method proceeds to operation 636 to determine whether the store entry to be drained is an odd store entry (i.e., a store entry with an odd address) or an even store entry (i.e., a store entry with an even address). If the store entry is an even entry rather than an odd entry, a "catch-up" event is detected, which provides an opportunity to end the load wake-up delay in response to the even store tag. Accordingly, the method repeats operations 606-612 described above, which ultimately wakes up the load entry in LDQ 225 corresponding to the single stag in operation 612, ending the load wake-up delay in response to the even store tag.

[0053] However, if the store entry is an odd entry, the system invalidates the LSB of the corresponding even stag in operation 638 to delay waking up loads in LDQ 225 that are sleeping on the even stag. In operation 640, a single odd stag is generated that corresponds to the odd store entry to be drained, and in operation 642, the sleeping loads in LDQ 225 are compared to the single odd stag. In operation 644, the load entries in LDQ 225 that correspond to the single odd stag are woken up. In operation 646, the current cycle is incremented, and the method returns to operation 602.

[0054] 6A, 6B, and 6C thus provide a mechanism for delaying the wakeup of a load depending on the even store tag when a call to perform a store drain merge operation occurs on an odd boundary. Whether the LSB comparison is disabled or the even stags are woken up individually depends on the number of stores that write to the cache in the subsequent cycle. This delayed wakeup to the next cycle may be performed continuously until the sequence no longer observes a double write.

[0055] 7, a method for performing a store drain merge operation in a computing system is shown according to a non-limiting embodiment. The method begins at operation 700, where a store write instruction is received at operation 702. At operation 704, the address of the store to be drained from the STQ is determined. At operation 706, a determination is made whether the store entry to be drained has a contiguous address. If no contiguous address exists, the computing system initiates a non-store drain merge operation at operation 708. Thus, a single entry is read from the storage queue during a single clock cycle at operation 710. At operation 712, the single drained entry is written to the cache, and the method ends at operation 714.

[0056] However, if one or more adjacent addresses are detected in operation 706, the computing system initiates a store drain merge operation in operation 716. Thus, a pair of adjacent store entries is read from the storage queue during a single clock cycle in operation 718. In operation 720, the pair of drained entries is written to the cache at adjacent memory locations, and the method ends at operation 714.

[0057] It should be understood that additional processes may be included, that the processing illustrated in FIG. 7 represents an illustration, and that other processes may be added, or existing processes may be removed, modified, or rearranged without departing from the scope and spirit of the present disclosure.

[0058] Referring to FIG. 8 , a block diagram of a computer system 800 for implementing some or all aspects of one or more embodiments of the present invention is shown. The computer system 800 may be an electronic computer framework that includes and / or uses any number and combination of computing devices and networks that utilize various communication technologies, as described herein. The computer system 800 may be easily scalable, extensible, and modular, and may have the ability to be adapted to different services or reconfigured with some features independent of others. The computer system 800 may be, for example, a server, a desktop computer, a laptop computer, a tablet computer, or a smartphone. In some examples, the computer system 800 may be a cloud computing node. The computer system 800 may be described in the general context of computer system-executable instructions, such as program modules, executed by the computer system. Generally, program modules may include routines, programs, objects, components, logic, data structures, etc., that perform particular tasks or implement particular abstract data types. The computer system 800 may be implemented in a distributed cloud computing environment where tasks are performed by remote processing devices linked through a communications network. In a distributed cloud computing environment, program modules may be located in both local and remote computer system storage media including memory storage devices.

[0059] As shown in FIG. 8, computer system 800 includes one or more central processing units (CPUs) 801a, 801b, 801c, etc. (collectively or generically referred to as processor 801). Processor 801 may be a single-core processor, a multi-core processor, a computing cluster, or any number of other configurations. Processor 801, also referred to as a processing circuit, is coupled to system memory 803 and various other components via a system bus 802. System memory 803 may include read-only memory (ROM) 804 and random access memory (RAM) 805. ROM 804 is coupled to system bus 802 and may include a basic input / output system (BIOS) that controls certain basic functions of computer system 800. RAM 805 is read-write memory coupled to system bus 802 for use by processor 801. System memory 803 provides temporary memory space for the execution of the instructions described above during operation. System memory 803 may include random access memory (RAM), read-only memory, flash memory, or any other suitable memory system.

[0060] Computer system 800 includes an input / output (I / O) adapter 806 and a communications adapter 807 coupled to a system bus 802. I / O adapter 806 may be a small computer system interface (SCSI) adapter that communicates with a hard disk 808 and / or any other similar components. I / O adapter 806 and hard disk 808 are collectively referred to herein as mass storage 810.

[0061] Software 811 for execution on computer system 800 may be stored in mass storage 810. Mass storage 810 is an example of a tangible storage medium readable by processor 801, where software 811 is stored as instructions for execution by processor 801 to cause computer system 800 to operate as described herein below with respect to the various figures. Examples of computer program products and the execution of such instructions are described in more detail herein. Communications adapter 807 interconnects system bus 802 with network 812, which may be an outside network, enabling computer system 800 to communicate with other such systems. In one embodiment, a portion of system memory 803 and mass storage 810 collectively store an operating system, which may be any suitable operating system for coordinating the functions of the various components shown in FIG. 8.

[0062] Additional input / output devices are shown connected to system bus 802 via display adapter 815 and interface adapter 816. In one embodiment, adapters 806, 807, 815, and 816 may be connected to one or more I / O buses connected to system bus 802 through an intermediate bus bridge (not shown). A display 819 (e.g., a screen or display monitor) is connected to system bus 802 by display adapter 815, which may include a graphics controller and a video controller to improve performance of graphics-intensive applications. A keyboard 821, mouse 822, speakers 823, etc. may be interconnected to system bus 802 via interface adapter 816, which may include, for example, a super I / O chip that integrates multiple device adapters into a single integrated circuit. Suitable I / O buses for connecting peripherals such as hard disk controllers, network adapters, and graphics adapters typically include a common protocol such as Peripheral Component Interconnect (PCI). Thus, as configured in FIG. 8, computer system 800 includes processing functionality in the form of processor 801, storage functionality including system memory 803 and mass storage 810, input means such as keyboard 821 and mouse 822, and output functionality including speakers 823 and display 819.

[0063] In some embodiments, communications adapter 807 may transmit data using any suitable interface or protocol, such as an Internet Small Computer System Interface, among others. Network 812 may be a cellular network, a wireless network, a wide area network (WAN), a local area network (LAN), or the Internet, among others. External computing devices may be connected to computer system 800 through network 812. In some examples, the external computing device may be an external web server or a cloud computing node.

[0064] It should be understood that the block diagram of Figure 8 is not intended to indicate that computer system 800 includes all of the components shown in Figure 8. Rather, computer system 800 may include any suitable fewer or additional components (e.g., additional memory components, embedded controllers, modules, additional network interfaces, etc.) not shown in Figure 8. Furthermore, the embodiments described herein with respect to computer system 800 may be implemented with any suitable logic, where logic as referred to herein may, in various embodiments, include any suitable hardware (e.g., a processor, embedded controller, or application specific integrated circuit, among others), software (e.g., an application, among others), firmware, or any suitable combination of hardware, software, and firmware.

[0065] Various embodiments of the present invention are described herein with reference to the associated drawings. Alternate embodiments of the present invention may be devised without departing from the scope of the present invention. Various connections and relationships (e.g., above, below, adjacent, etc.) are shown between elements in the following description and in the drawings. These connections and / or relationships may be direct or indirect unless otherwise specified, and the present invention is not intended to be limited in this respect. Thus, coupling of entities may refer to either a direct or indirect coupling, and relationships between entities may be direct or indirect. Additionally, steps of various tasks and processes described herein may be combined into a more comprehensive procedure or process having additional steps or functionality not described in detail herein.

[0066] The following definitions and abbreviations will be used in interpreting the claims and the specification. As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," "contains," or "containing," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or device that comprises a list of elements is not necessarily limited to only those elements, but may include other elements not specifically listed or inherent in such composition, mixture, process, method, article, or device.

[0067] Additionally, the word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" may be understood to include any integer greater than or equal to one, i.e., 1, 2, 3, 4, etc. The term "plurality" may be understood to include any integer greater than or equal to two, i.e., 2, 3, 4, 5, etc. The term "connected" may include both an indirect "connected" and a direct "connected."

[0068] The terms "about," "substantially," "approximately," and variations thereof are intended to include the degree of error associated with measurement of a particular quantity based on the equipment available at the time of filing. For example, "about" may include a range of ±8%, or 5%, or 2% of a given value.

[0069] For the sake of brevity, conventional techniques related to making and using aspects of the present invention may or may not be described in detail herein. In particular, various aspects of computing systems and specific computer programs for implementing various technical features described herein are well known. Thus, for the sake of brevity, many conventional implementation details are only briefly described herein or omitted entirely without providing details of well-known systems and / or processes.

[0070] The present invention may be a system, method, or computer program product, or combination thereof, integrated at any possible level of technical detail. The computer program product may include one or more computer-readable storage media having computer-readable program instructions for causing a processor to perform aspects of the present invention.

[0071] A computer-readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes portable computer diskettes, hard disks, random access memories (RAMs), read-only memories (ROMs), erasable programmable read-only memories (EPROMs or flash memories), static random access memories (SRAMs), portable compact disk read-only memories (CD-ROMs), digital versatile disks (DVDs), memory sticks, floppy disks, mechanically encoded devices such as punch cards or ridge structures in grooves that record instructions, and any suitable combination of the foregoing. Computer-readable storage medium, as used herein, should not be construed as being a transitory signal per se, such as an electric wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse passing through a fiber optic cable), or an electrical signal transmitted over a wire.

[0072] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device or to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, or a wireless network, or both. The network may comprise copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in each corresponding computing / processing device.

[0073] The computer-readable program instructions for carrying out the operations of the present invention may be either assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for integrated circuits, or source or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk® or C++, and procedural programming languages ​​such as the “C” programming language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be to an external computer (e.g., through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) may execute computer-readable program instructions by utilizing state information of the computer-readable program instructions to personalize the electronic circuitry to perform aspects of the present invention.

[0074] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0075] These computer-readable program instructions may be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, executed by the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams. These computer-readable program instructions may be stored in a computer-readable storage medium that can direct a computer, programmable data processing apparatus, or other device, or combination thereof, to function in a particular manner, such that the computer-readable storage medium on which the instructions are stored may comprise an article of manufacture containing instructions that implement aspects of the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0076] The computer-readable program instructions may be loaded into a computer, other programmable data processing apparatus, or other device to cause the computer, other programmable apparatus, or other device to perform a series of operational steps to create a computer-implemented process, such that the instructions executing on the computer, other programmable apparatus, or other device implement the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0077] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may in fact be executed substantially concurrently, or the blocks may be executed in the reverse order, depending on the functionality involved. It should also be noted that each block in the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by a dedicated hardware-based system that performs the specified functions or operations or executes a combination of dedicated hardware and computer instructions.

[0078] The description of various embodiments of the present invention has been presented for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein have been selected to best explain the principles of the embodiments, practical applications, or technical improvements over technologies found in the market, or to enable others skilled in the art to understand the embodiments described herein.

Claims

1. 1. A computer-implemented method for performing a store drain merge operation to wake up a sleeping load entry on a dependent store entry, comprising: detecting, by a processor, a call to perform said store-drain-merge operation; generating a pair of store tags having a first store tag corresponding to the first store entry to be drained and a second store tag corresponding to the second store entry to be drained; determining that the pair of store tags is one of an even-type store tag and an odd-type store tag, wherein the pair of even-type store tags includes the first store tag as an even store tag and the second store tag as an odd store tag, and the pair of odd-type store tags includes the first store tag as an odd store tag and the second store tag as an even store tag; In response to the determination of the pair of even-type store tags, invalidating the odd-type store tags included in the pair of even-type store tags; waking up a first load entry dependent on the even store tag and a second load entry dependent on the odd store tag based on the even store tag included in the pair of even store tags while the odd store tag is invalidated; A computer-implemented method comprising:

2. 2. The computer-implemented method of claim 1, wherein the first load entry and the second load entry are woken up in a single given clock cycle of the processor.

3. The computer-implemented method of claim 1 or 2, wherein the even store tag and the odd store tag are defined as multiple bits.

4. A computer-implemented method as described in claim 3, wherein the step of invalidating the odd store tag included in the pair of even store tags includes the step of invalidating the least significant bit (LSB) of the odd store tag and comparing only the even store tag included in the pair of even store tags with the sleep state load entry.

5. 5. The computer-implemented method of claim 3, further comprising: responsive to determining the pair of odd-type store tags, waking up a first load entry dependent on the odd store tag during a first clock cycle of the processor; and delaying waking up a second load entry dependent on the even store tag until a subsequent clock cycle following the first clock cycle.

6. 6. The computer-implemented method of claim 5, wherein delaying the wakeup of the second load entry comprises invalidating a least significant bit of the even store tag in the pair of odd type store tags and using only the odd store tag in the pair of odd type store tags to compare with the sleeping load entry.

7. 7. The computer-implemented method of claim 6, further comprising delaying wake-up of the second load entry until the subsequent clock cycle removes a call to perform the store-drain-merge operation.

8. a store queue unit configured to hold at least one store entry to be completed; a load queue unit configured to hold at least one load entry in a sleeping state above a store entry included in said store queue unit; and detecting a call to perform a store drain merge operation; and generating a pair of store tags including a first store tag corresponding to a first store entry to be drained from the store queue unit and a second store tag corresponding to a second store entry to be drained from the store queue unit. Equipped with the processor determines that the pair of store tags is one of an even-type store tag and an odd-type store tag, the pair of even-type store tags including the first store tag as an even store tag and the second store tag as an odd store tag, and the odd-type store tags including the first store tag as an odd store tag and the second store tag as an even store tag; and in response to the determination of the pair of even-type store tags, invalidates the odd store tag included in the pair of even-type store tags, and wakes up a first load entry dependent on the even store tag and a second load entry dependent on the odd store tag based on the even store tag included in the pair of even-type store tags with the odd store tag invalidated.

9. 9. The computer system of claim 8, wherein the first load entry and the second load entry are woken up in a single given clock cycle of the processor.

10. 10. The computer system of claim 8, wherein the even store tag and the odd store tag are defined as multiple bits.

11. The computer system of claim 10, wherein the step of invalidating the odd store tag included in the pair of even store tags includes the step of invalidating the least significant bit (LSB) of the odd store tag and using only the even store tag included in the pair of even store tags to compare with the sleep state load entry.

12. 12. The computer system of claim 10, further comprising: a step of waking up a first load entry that depends on the odd store tag during a first clock cycle of the processor in response to determining the pair of odd store tags; and a step of delaying the wake-up of a second load entry that depends on the even store tag until a subsequent clock cycle following the first clock cycle.

13. 13. The computer system of claim 12, wherein delaying the wakeup of the second load entry comprises invalidating an LSB of the even store tag included in the pair of odd type store tags and using only the odd store tag included in the pair of odd type store tags to compare with the sleeping load entry.

14. 14. The computer system of claim 13, further comprising: delaying wake-up of said second load entry until said subsequent clock cycle removes a call to perform said store-drain-merge operation.

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