Embedded heaters in phase change memory materials

Abstract

A phase change memory cell for a semiconductor device includes a heater element on a first conductive layer with a spacer surrounding sides of the heater element. The phase change memory cell includes a first dielectric layer on the conductive layer and on a bottom of the spacer surrounding the heater element, and a second dielectric layer on the first dielectric layer surrounding a top of the heater element. The phase change memory cell includes a phase change material on a top surface of the heater element and on a second dielectric material.

Description

[Technical Field]

[0001] The present invention relates generally to the field of semiconductor device technology, and more particularly to embedded heaters in phase change materials in semiconductor chip applications, including phase change memory devices. [Background technology]

[0002] Phase change materials include various chalcogenide glass materials that can be used in semiconductor device applications such as phase change random access memory (PCRAM), sometimes known as PRAM, PCM, or PCME devices. PCRAM typically has at least two solid phases: crystalline and amorphous. The transition between these two phases can be achieved by changing the temperature of the phase change material. Generally, the transition of a phase change material (PCM) can be induced by heating with optical pulses, electrical heating, or Joule heating.

[0003] The optical and electronic properties can vary significantly between the amorphous and crystalline phases of PCMs. In typical memory applications, switching from a high-resistance or "reset" state, in which a phase-change material is partially or completely amorphous, occurs when a current pulse that heats the amorphous material above its crystallization temperature is applied long enough for the material to crystallize. At a given threshold voltage, switching occurs when a threshold electric field is exceeded, resulting in a threshold switching effect that causes a rapid and sudden (within nanoseconds) decrease in the resistance of the amorphous phase. Switching from a low-resistance or "set" state, in which the material is in a crystalline state, is achieved by a very short, high-current pulse at the tail end. In typical PCM semiconductor applications, the current pulse heats the material by Joule heating, melting it, and then allows for very rapid cooling (liquid quenching) so that the PCM material solidifies in the amorphous state.

[0004] Phase change materials exhibit different electrical properties depending on their state. In the amorphous state, they exhibit higher resistivity than their crystalline state. In semiconductor applications, phase change materials can switch between multiple electrically detectable resistivity states on nanosecond timescales with picojoule energy input. In a typical phase change random access memory device, the state of a memory bit can be identified by determining the state of the phase change material within the memory bit, since the phase change material is capable of reversible phase transitions. Summary of the Invention

[0005] An embodiment of the present invention provides a phase-change memory cell for a semiconductor device. The phase-change memory cell includes a heater element on a first conductive layer with a spacer surrounding the sides of the heater element. The phase-change memory cell includes a first dielectric layer on the conductive layer and on a bottom of the spacer surrounding the heater element, and a second dielectric layer on the first dielectric layer surrounding the top of the heater element. The phase-change memory cell includes a phase-change material on the top surface of the heater element and on the second dielectric material.

[0006] An embodiment of the present invention provides a method for forming a phase-change memory cell, comprising depositing a layer of heater material on a bottom electrode and selectively etching the layer of heater material to form a heater. The method includes depositing a layer of heater material on the bottom electrode and selectively etching the layer of heater material to form a heater. The method also includes forming spacers on sides of the heater and depositing a first dielectric material on the bottom electrode, the spacers, and a top surface of the heater. The method also includes removing an upper portion of the first dielectric material from the top surface of the heater, from above the spacers, and from above the bottom electrode, and depositing a second dielectric material on the top surface of the heater, above the spacers, and the first dielectric layer. The method also includes removing an upper portion of the second dielectric material, stopping at the top surface of the heater, and depositing a phase-change material on the top surface of the heater and the second dielectric material. The method also includes depositing a layer of top electrode material on the phase-change material.

[0007] Aspects, features, and advantages of various embodiments of the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view of an example phase change memory cell of a semiconductor structure having a heater element and PCM material after transforming a mushroom-shaped portion of the PCM to a crystalline state in accordance with an embodiment of the present invention. [Figure 2] 3 is a cross-sectional view of a phase change memory cell of a semiconductor structure after depositing a layer of heater material on a conductive layer according to one embodiment of the present invention. [Figure 3] 2 is a cross-sectional view of a semiconductor structure after forming a heater element according to one embodiment of the present invention. [Figure 4] 2 is a cross-sectional view of a semiconductor structure after depositing a layer of dielectric material over the semiconductor structure in accordance with one embodiment of the present invention. [Figure 5] 2 is a cross-sectional view of a semiconductor structure after etching a portion of the layer of dielectric material to form spacers, according to one embodiment of the present invention. [Figure 6] FIG. 2 is a cross-sectional view of a semiconductor structure after depositing a second dielectric layer according to one embodiment of the present invention. [Figure 7] FIG. 2 is a cross-sectional view of a semiconductor structure after chemical mechanical polishing (CMP) and etching of the top of a second dielectric material, in accordance with one embodiment of the present invention. [Figure 8] 2 is a cross-sectional view of a semiconductor structure after depositing a layer of a third dielectric material having a thermal conductivity similar to the PCM material, in accordance with one embodiment of the present invention. [Figure 9] 2 is a cross-sectional view of a semiconductor structure after performing CMP, according to one embodiment of the present invention. [Figure 10] 2 is a cross-sectional view of a semiconductor structure after depositing a layer of PCM material over the semiconductor structure, in accordance with one embodiment of the present invention. [Figure 11] 3 is a cross-sectional view of a phase change memory cell of a semiconductor structure after depositing a layer of conductive material over the semiconductor structure in accordance with one embodiment of the present invention. [Figure 12] FIG. 4 is a cross-sectional view of a semiconductor structure after depositing a first dielectric material over a heater element according to a second embodiment of the present invention. [Figure 13] FIG. 4 is a cross-sectional view of a semiconductor structure after depositing a second layer of dielectric material according to a second embodiment of the present invention. [Figure 14] FIG. 10 is a cross-sectional view of a semiconductor structure after forming spacers with portions of a second dielectric material on sides of a heater according to a second embodiment of the present invention. [Figure 15] FIG. 4 is a cross-sectional view of a semiconductor structure after depositing a sacrificial material on the semiconductor structure according to a second embodiment of the present invention. [Figure 16] FIG. 4 is a cross-sectional view of a semiconductor structure after CMP stopping on a top surface of a second dielectric material according to a second embodiment of the present invention. [Figure 17] FIG. 10 is a cross-sectional view of a semiconductor structure after CMP stop on top of a heater according to a second embodiment of the present invention. [Figure 18] FIG. 4 is a cross-sectional view of a semiconductor structure after removal of the sacrificial material according to a second embodiment of the present invention. [Figure 19] 4 is a cross-sectional view of a semiconductor structure after deposition of a layer of PCM material according to a second embodiment of the present invention. [Figure 20] 4 is a cross-sectional view of a semiconductor structure after depositing a layer of conductive material over the semiconductor structure in accordance with a second embodiment of the present invention. [Figure 21] FIG. 10 illustrates an example of the results of a thermal analysis of the effect of voltage versus temperature for various buried heater depths, in accordance with one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0009] Embodiments of the present invention recognize that heater elements in phase change memory cells of semiconductor devices utilizing phase change materials (PCMs) are critical for both memory device applications and analog computing applications. The heater elements provide the ability to effectively switch the PCM from a highly resistive amorphous state to a highly conductive crystalline state once a phase transition temperature, such as the PCM's melting point, is achieved. Embodiments of the present invention recognize that in analog synapse applications, the analog state and dynamic range depend on the heater element to affect the change in the PCM for efficient semiconductor device function. Embodiments of the present invention recognize that improved heating and cooling rates of heater elements and PCMs may be needed to improve the functionality of analog synapse devices and memory applications.

[0010] Embodiments of the present invention recognize that the ability of a heater element to more quickly and efficiently transfer thermal energy to a PCM is desirable to speed up state changes in the PCM. Embodiments of the present invention recognize that the ability to rapidly induce phase transitions in the mushroom-shaped portion of a PCM using improved heater element structures and materials provides improved functionality for semiconductor devices, and particularly for improving the dynamic range of analog devices used in deep neural networks. Embodiments of the present invention recognize that traditional methods of heater formation involve filling small holes in a dielectric material with heater material that is deposited in the small holes, typically by atomic layer deposition or chemical vapor deposition. Traditional hole formation methods create heaters with a uniform diameter or a tapered heater with a larger heater diameter at the top where the PCM contacts the heater and a smaller bottom heater diameter at the bottom electrode.

[0011] Embodiments of the present invention provide methods for forming heater elements with small top contact areas with the PCM, whether the heater is embedded in the PCM or not. Embodiments of the present invention provide heaters embedded in a dielectric material underlying the PCM. The dielectric material has a thermal conductivity similar to or matching that of the PCM. Embodiments of the present invention provide the ability to tape the heater to form a small top surface that contacts the PCM and a large bottom surface that contacts the bottom electrode. Heater structures that achieve tapered heaters with small top diameters allow heaters to be formed using well-developed metal-gate-first semiconductor manufacturing processes. The small heater top surface facilitates plasma deposition of the PCM. The method for forming tapered heaters with small top diameters also provides the ability to tailor the resistance of semiconductor devices by varying the height, shape, size, and spacer thickness of the embedded heater, depending on the material selection and semiconductor application needs.

[0012] Embodiments of the present invention provide the ability to more efficiently and uniformly heat and quench the mushroom-shaped phase change region of a PCM. By providing a layer of dielectric material surrounding all but a small top surface of the heater, the phase change region for melting and quenching the PCM is smaller, thereby enabling more efficient and faster initiation of the PCM phase change and using less power to initiate the PCM phase change.

[0013] Additionally, embodiments of the present invention provide the ability to embed a tapered heater into a portion of a PCM material. Thermal modeling of embedded tapered heaters has shown that the power level required to initiate a phase transition of the PCM decreases. Thermal modeling has shown that the power required to initiate a phase change of the PCM decreases as the heater penetrates deeper into the PCM material.

[0014] Detailed embodiments of the claimed structures and methods are disclosed herein. The methods described below do not constitute a complete process flow for fabricating integrated circuits, such as semiconductor devices. The embodiments include only those process steps commonly performed with integrated circuit fabrication techniques currently used in the art for semiconductor devices, and are necessary to understand the described embodiments. The figures show cross-sectional portions of heater elements embedded in PCM material in semiconductor devices, such as memory devices and analog devices. The figures are not drawn to scale and are provided to illustrate features of the described embodiments. Specific structural and functional details disclosed herein should not be construed as limiting, but merely as a representative basis for teaching those skilled in the art how to employ the disclosed methods and structures in various ways. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0015] References herein to "one embodiment," "other embodiment," "another embodiment," "an embodiment," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but not all embodiments necessarily include that particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is understood that it is within the knowledge of one of ordinary skill in the art to affect such feature, structure, or characteristic with respect to other embodiments, whether or not explicitly described.

[0016] For purposes of the following description, the terms "upper," "lower," "right," "left," "vertical," "horizontal," "top," "bottom," and derivatives thereof refer to the disclosed structures and methods oriented in the drawings. The terms "overlying," "atop," "over," "on," "positioned on," or "positioned atop" mean that a first element is present on a second element, and that intervening elements, such as interfacial structures, may be present between the first and second elements. The term "direct contact" means that a first element and a second element are connected without any intermediate conductive, insulating, or semiconducting layers at the interface between the two elements.

[0017] In the following detailed description, some process steps, materials, or operations known in the art are combined together for presentation and explanation purposes so as not to obscure the presentation of embodiments of the present invention, and in some instances may not be described in detail. Additionally, for the sake of brevity and to avoid distracting from the focus on the distinctive features of the elements of the present invention, descriptions of previously discussed materials, processes, and structures may not be repeated with respect to subsequent figures. In other instances, some process steps or operations that are well-known may not be described. It should be understood that the following description focuses, rather, on the distinctive features or elements of various embodiments of the present invention.

[0018] FIG. 1 is a cross-sectional view of an example of a phase-change memory cell in a semiconductor structure with a heater 11, according to an embodiment of the present invention. As shown, FIG. 1 includes a bottom electrode 10, a heater 11, a spacer 33, a dielectric layer 55, and a low-k dielectric material 77 having a thermal conductivity that closely matches the thermal conductivity of the PCM material of PCM 90a and PCM 90c. In some embodiments, the low-k dielectric material 77 is a material that closely matches the thermal conductivity of PCM 90a and PCM 90c, but is not a low-k dielectric material. FIG. 1 illustrates an example of PCM material (i.e., PCM 90a and PCM 90c) after a mushroom-shaped portion of the amorphous PCM material, represented as PCM 90a, has been transformed into a crystalline PCM 90c. For example, PCM 90a is a PCM structure that can be transformed into an amorphous state, i.e., a crystalline PCM 90c, when a heater 11 provides sufficient energy to heat PCM 90a to a phase transition temperature. A phase transition temperature, in this case the melting point of the PCM, causes a change in the atomic structure of the PCM material (not shown in FIG. 1 ), from PCM 90a to PCM 90c, or in other examples, from PCM 90c to PCM 90a. As shown in FIG. 1 , the heater 11 encapsulated by the spacer 33 may be embedded in a layer 77 of dielectric material. In various embodiments, the dielectric material 77 is a material, such as a low-k dielectric material, selected for its thermal conductivity that matches or nearly matches that of the PCM material (e.g., shown in FIG. 1 as PCM 90a and PCM 90c). In other embodiments, when the dielectric material 77 is not present, the heater 11 is embedded in the PCM material.

[0019] The modified cone shape of the heater 11 of FIG. 1 can be formed using negative patterning. The sides of the heater 11 can be vertical or, as in the case of the modified cone shape of the heater 11 of FIG. 1, tapered. The tapered sides of the heater 11 form an angle of greater than 90 degrees with the surface of the bottom electrode 10. Because the sides of the heater 11 are tapered, the diameter of the top of the heater 11 is smaller than the diameter of the bottom of the heater 11. The use of a modified cone-shaped, or tapered, heater 11 covered with a spacer 33 improves heat transfer from the heater 11 to the PCM 90a (e.g., reduces heat loss from the heater 11).

[0020] FIG. 2 is a cross-sectional view of a semiconductor structure after depositing a layer of heater material 11 on a bottom electrode 10 to form a phase-change memory cell according to an embodiment of the present invention. The semiconductor structure of FIG. 2 includes a layer of heater material 11 on a bottom electrode 10. The bottom electrode 10 may be composed of tungsten (W), copper (Cu), or any conductive material, metal, or metal alloy used in electrodes in semiconductor devices. In some embodiments, the bottom electrode 10 is part of a conductive layer of a semiconductor device and may be a wiring, via pad, contact, or other conductive feature of the semiconductor structure. The layer of heater material is deposited on the bottom electrode 10 using a semiconductor deposition process, such as plasma vapor deposition (PVD), chemical vapor deposition (CVD), spin-on process (spin-on-glass), or other suitable deposition process. Heater 11 may be constructed of titanium nitride (TiN), titanium tungsten (TiW), multilayer heater materials (e.g., tantalum nitride / titanium nitride), doped Si, doped silicon germanium (SiGe), or other materials commonly used for heater elements in PCRAM or other phase change memory cells in other types of semiconductor devices. The thickness of the layer of material for heater 11 may vary from 50 to 80 nm, but is not limited to these thicknesses.

[0021] FIG. 3 is a cross-sectional view of a semiconductor structure after forming heater 11 according to an embodiment of the present invention. The layer of material may be etched to form heater 11. The heater 11 may be etched using either a wet chemical etching process (e.g., using photolithographic patterning) or a dry etching process. For example, an etching process for forming a small diameter heater 11 may be a dry etch process, such as reactive ion etching (RIE). If a large diameter is to be formed in heater 11, wet chemical etching may be used. The etching process may be a double-patterning etching process for forming a very small diameter in heater 11. For example, a heater with a small bottom diameter of 15-30 nm may use a double-patterning etching process, such as double-patterning RIE. In one embodiment, an extreme ultraviolet etching process is used to form heater 11 with a very small diameter. The diameter of the bottom of the heater 11 after etching can vary between 15 and 50 nm, but is not limited to these diameters. The diameter of the heater 11 can vary depending on the height of the heater 11, the PCM, and the desired thermal and electrical properties of the heater 11 in the finished semiconductor chip application.

[0022] The heater 11 may have a tapered shape with a wider base, such as a cone, a modified cone with a flat top, a triangular prism (e.g., prism), or a tapered rectangular prism. For example, the flat top of the heater 11 may be 20 nm wide and the bottom of the heater 11 may be 30 nm wide. In one embodiment, the width of the bottom of the heater 11 is 100 nm or greater. In various embodiments, the heater 11 is etched into one of the following shapes: a cone, a modified cone with a flat top, a cylindrical or rectangular prism, an elliptical prism, or a triangular prism. The heater 11 may also have a uniform diameter, i.e., a cylindrical shape (e.g., a circular cylinder, an elliptical cylinder, a rectangular prism, a triangular prism).

[0023] The heater 11 is shown with an angle α between the side of the heater 11 and the top surface of the bottom electrode 10 parallel to the top surface of the semiconductor substrate (not shown). In various embodiments, the angle α is greater than 90 degrees. For example, the angle α is between 90 and 120 degrees, but is not limited to these angles. As shown, the angle α is greater than 90 degrees.

[0024] Using a tapered heater 11 with an angle α greater than 90 degrees can improve energy transfer to the PCM material deposited in a later step. For example, thermal modeling of a completed phase-change memory cell similar to that shown in Figure 1 without the dielectric material 77 estimates that the power required to initiate a phase change of the PCM is significantly reduced when using a tapered heater 11 versus a cylindrical, non-tapered heater with a uniform diameter (e.g., a heater with vertical sides). Thermal modeling confirmed that the Ponset required to initiate a phase change of the PCM using the tapered heater 11 is approximately 25% lower than the power (Ponset) required to initiate a phase change of the PCM using a non-tapered heater with vertical sides and a uniform diameter.

[0025] Using a tapered heater 11 embedded 30 nm into the PCM at a 95-degree angle with the bottom electrode 10, thermal modeling determined that the estimated current (i.e., I) required to initiate a phase change temperature of the PCM 90a was approximately 106 μA. Thermal modeling determined that the voltage (i.e., V) required to initiate a phase change of the PCM 90a material was approximately 0.95 V using the tapered heater 11, and the power (i.e., P) required to initiate a phase change from PCM 90a to PCM 90c was approximately 100.7 μW. Thermal modeling of a non-tapered heater embedded 30 nm into the PCM yielded a P of 133.5 μW, compared to the P of the tapered heater 11 of 100.7 μW. For the non-tapered heater, the thermal model estimated I of 178 μA and an estimated V of 0.75 μW.

[0026] Assumptions used in the thermal model included that the heater 11 was composed of TiN with a 10 nanometer thick layer of silicon nitride (SiN) as a spacer. The heater 11 was assumed to be embedded 30 nanometers into the PCM material (not shown in Figure 4). The PCM materials shown in Figure 1 are O, N, H, SiO2, SiN, Ti, and Ti. x O y The tapered heater 11 had a modified conical shape with a flat top. A non-tapered heater with a uniform diameter and vertical sides (non-tapered) was assumed to use the same materials.

[0027] 4 is a cross-sectional view of a semiconductor structure after depositing spacers 33 on the semiconductor structure, according to an embodiment of the present invention. The spacers 33 may be deposited as a layer of a dielectric material suitable for forming the spacers. In various embodiments, the dielectric material of the spacers 33 has a low thermal conductivity and a high thermal boundary resistance (G) relative to the PCM material. For example, the spacers 33 may be a silicon nitride (SiN) compound such as SiN (SiN x ), silicon dioxide (SiO2) and other silicon oxide compounds (SiO x ), nitride materials, hafnium oxide such as HfO2 (HfO x ) material or Al2O3 / O2 multilayer material. In various embodiments, SiN is deposited on the heater 11 and bottom electrode 10 for the spacer 33. The thickness of the spacer 33 for forming the spacer around the heater 11 can vary from 5 to 50 nm, but is not limited to this range.

[0028] FIG. 5 is a cross-sectional view of a semiconductor structure after etching away a portion of the dielectric material for the spacer 33, according to an embodiment of the present invention. Using a known spacer formation process, portions of the spacer 33 are removed from the horizontal surfaces of the bottom electrode 10 and heater 11 by etching. For example, RIE etching can be used to form the spacer, removing portions of the spacer 33 from the horizontal surfaces of the heater 11 and bottom electrode 10, but leaving portions of the spacer 33 on the sides of the heater 11. The spacer 33 can have a triangular or rounded triangular shape typical of spacers (e.g., for gates). In some cases, the spacer 33 can have a top width in the range of 5 to 25 nm and a bottom width in the range of 10 to 50 nm. The spacer 33 surrounding the heater 11 maintains the power efficiency of the heater 11 by using a material with low thermal conductivity for the spacer 33. In some cases, the spacer 33 can have a generally uniform thickness from the top to the bottom of the spacer 33. In other cases, spacers 33 may have a thick bottom region and a thin top region relative to the top surface of heater 11. Semiconductor processes developed for advanced metal-gate-first metallization and spacer formation may be utilized to fabricate spacers 33 and heater 11.

[0029] 6 is a cross-sectional view of a semiconductor structure after depositing a dielectric layer 55, according to an embodiment of the present invention. In various embodiments, the dielectric layer 55 is deposited on the exposed surfaces of the bottom electrode 10, the spacers 33, and the heater 11. The dielectric layer 55 may be composed of a second dielectric material that is different from the dielectric material used for the spacers 33. For example, the dielectric layer 55 may be composed of SiO2 when the spacers 33 are another dielectric material, such as SiN. In some cases, the dielectric layer 55 and the spacers 33 are composed of the same dielectric material.

[0030] 7 is a cross-sectional view of the semiconductor structure after CMP and etching of the top of dielectric layer 55, according to an embodiment of the present invention. The CMP removes the top surface of dielectric layer 55 using the top surface of heater 11 as a CMP stop. The CMP removes dielectric layer 55 above the top surface of heater 11.

[0031] After CMP, a selective overetch process, which can be a wet or dry etch process, removes the upper portion of the dielectric layer 55 around the heater 11. For example, to remove more of the dielectric layer 55 if it is thick, a wet subtractive etch using photolithography can be used to selectively remove portions of the dielectric layer 55 over the bottom electrode 10, spacers 33, and heater 11 while leaving the spacers 33 and heater 11. The bottom portion of the dielectric layer 55 remains around the heater 11 and on the top surface of the bottom electrode 10. The thickness of the remaining portion of the dielectric layer 55 can vary depending on the height of the heater 11 and the desired thickness of the next layer of material to be deposited on the semiconductor structure. For example, the thickness of the dielectric layer 55 remaining over the bottom electrode 10 can be between one-half the height of the heater 11 and approximately 90 percent of the height of the heater 11.

[0032] 8 is a cross-sectional view of a semiconductor structure after depositing a layer of low-k dielectric material 77 having a thermal conductivity similar to that of the PCM material, according to an embodiment of the present invention. A deposition process such as PVD, CVD, or a spin-on process may be used to deposit a layer of material with a thermal conductivity that matches or nearly matches that of the PCM material that will be deposited in one of the subsequent steps.

[0033] In various embodiments, the material deposited in this step is a low-k dielectric material with a thermal conductivity approximately equal to that of the PCM used in the semiconductor structure in one of the subsequent deposition processes. For example, low-k dielectric material 77 can be 100-500 nm. The specific low-k dielectric material selected for low-k dielectric material 77 can be tailored to the material selection of the PCM and is not limited to low-k dielectric materials. In other embodiments, the deposited material is not a low-k dielectric material, but rather another material with a thermal conductivity that matches or nearly matches that of the PCM. A typical thickness of low-k dielectric material 77 can be in the range of 100-200 nm, but is not limited to this range.

[0034] As shown in FIG. 10, a subsequently deposited layer of low-k dielectric material 77 with a thermal conductivity close to that of the selected PCM material reduces the energy or power required to initiate a phase change in the melting / quenching region of the PCM, as will be described in more detail below with respect to FIG. 11.

[0035] FIG. 9 is a cross-sectional view of a semiconductor structure after performing CMP, according to an embodiment of the present invention. The top portion of the low-k dielectric material 77 can be removed using CMP, stopping on the top surface of the heater 11. The thickness of the remaining low-k dielectric material 77 can vary depending on the thickness of the dielectric layer 55 after etching and the height of the heater 11. For example, the thickness of the low-k dielectric material 77 can be less than half the heater height when the selected PCM is GST (i.e., GST is germanium (Ge), antimony (Sb), or tellurium (Te)). In various embodiments, the combined thickness of the low-k dielectric material 77 and the dielectric layer 55 is equal to the height of the heater 11 (i.e., the top surface of the heater 11 is flush with the top surface of the low-k dielectric material 77). In some embodiments, the height of the heater 11 is slightly higher than the top surface of the low-k dielectric material 77 (e.g., the top of the heater 11 with the spacers 112 protrudes into the PCM 90). After CMP, the top surface of heater 11 is level or flush with the top surface of low-k dielectric material 77. Adding a layer of low-k dielectric material 77 to a completed phase change memory cell may result in a reduction in the amount of energy or power required to initiate a phase change of the PCM.

[0036] FIG. 10 is a cross-sectional view of a semiconductor structure after depositing a layer of PCM90 thereon, according to an embodiment of the present invention. The layer of PCM90 may be deposited on the exposed surfaces of the low-k dielectric material 77, the spacers 33 (if exposed), and the heater 11. The PCM90 may be deposited by known PCM material deposition processes (e.g., PVD, CVD, spin-on processes, etc.), and the thickness of the PCM90 deposition may range from 80 to 300 nm, but is not limited to these thicknesses. The PCM90 may be any known PCM material. In various embodiments, the PCM90 is a chalcogenide or chalcogenide glass material. For example, the PCM90 may be a GST, such as doped or undoped Ge2Sb2Te5. In various embodiments, the PCM90 is a GST. The GST of the PCM90 may be undoped or doped with, for example, O, N, H, SiO2, SiN, Ti, or Ti. x O y In other embodiments, PCM90 may be a reverse phase change material such as Cr2Ge2Te6. PCM90 may be deposited in a wide range of thicknesses. For example, PCM90 may be deposited between 80 and 300 nm, but is not limited to these thicknesses.

[0037] 11 is a cross-sectional view of a phase change memory cell in a semiconductor structure after depositing a layer of conductive material on the semiconductor structure in accordance with an embodiment of the present invention. As shown, FIG. 11 includes a bottom electrode 10, a dielectric layer 55, a spacer 33 on a heater 11, a PCM 90, and a top electrode 95. A conductive material, such as Al, W, Cu, or other known conductive material for semiconductor electrodes or interconnects, can be deposited on the PCM 90 to form the top electrode 95.

[0038] 11 with and without the layer of low-k dielectric material 77, it was determined that the presence of the layer of low-k dielectric material 77 below the PCM 90 reduces the power (e.g., Ponset) required to initiate a phase change in the PCM 90 by approximately 10%. The thermal model determined that the presence of the layer of low-k dielectric material 77 around the top of the embedded heater 11 reduces the power to initiate a phase change (Ponset) compared to the power required to initiate a phase change (Ponset) of the same semiconductor structure without the layer of low-k dielectric material 77.

[0039] The thermal model estimated the power required to transition the PCM 90 from an amorphous state to a crystalline state when the heater 11 is embedded in the low-k dielectric material 77 to a depth of 30 nm, and estimated that a higher power (Ponset) would be required to transition the PCM 90 using a similar semiconductor structure without a layer of low-k dielectric material 77 below the PCM 90.

[0040] Thermal modeling concluded that less power is required to initiate a phase change of the PCM 90 when a layer of low-k dielectric material 77 is present, as shown in Figure 11. The layer of low-k dielectric material 77 reduces the melting / quenching region that occurs during the phase transition of the PCM 90. For example, the melting / quenching region of the phase change of the PCM 90 can be represented as the mushroom-shaped region of PCM 90c in Figure 1.

[0041] When the heater 11 is embedded 30 nm into the PCM 90, the melting / quenching region is larger than when the low-k dielectric material 77 is present. When the heater 11 is embedded 30 nm into the PCM 90 without the low-k dielectric material 77, a larger melting / quenching region can extend around the sides of the embedded heater 11, not only above the top surface of the heater 11 but also below the top surface of the heater 11, especially with longer times at the transition or melting temperature. The melting / quenching region of the PCM 90 is larger without the low-k dielectric material 77 and therefore requires more power to initiate the phase change of the PCM 90.

[0042] The thermal model assumes an inverted tapered heater (the outer side of the heater 11 forms a 95-degree angle with the bottom electrode 10) with a flat top (e.g., a modified cone with a wider base), and a dielectric material surrounding the top electrode 95 and PCM 90, which is a GST material. The low-k dielectric material 77 in the model was assumed to be 30-40 nm thick, and the heater 11, with the SiN forming the spacer 33, was assumed to be TiN. For example, the thermal model estimated a Ponset of 93 μW with the low-k dielectric material 77, but 101 μW without the low-k dielectric material 77.

[0043] The processes used to form the semiconductor structure of FIG. 11 include advanced metal-gate-first metallization and spacer formation processes and techniques. The processes described for forming heater 11 can produce heater top shapes including circles, ellipses, squares, rectangles, or triangles. In addition, the semiconductor structure of FIG. 11 can realize heater 11 that can be embedded in PCM 90 or in another material (e.g., low-k dielectric material 77) selected for its thermal conductivity matching that of PCM 90. As known to those skilled in the art, the semiconductor structure shown in FIG. 11 can be further processed using known semiconductor fabrication processes and, in some cases, integrated into memory semiconductor chips such as PCRAM, analog synapses of semiconductor chips utilized in deep neural networks, or other semiconductor device applications.

[0044] FIG. 12 is a cross-sectional view of a semiconductor structure that will become a phase-change memory cell after depositing a dielectric material 111 on the heater 11 in accordance with a second embodiment of the present invention. As shown, FIG. 12 includes a heater 11 and bottom electrode 10 that are essentially the same as the heater 11 and bottom electrode 10 described with respect to FIG. 3, and a dielectric material 111 deposited on the heater 11 and bottom electrode 10. For example, the thickness of the dielectric material 111 varies between 20 nm and 100 nm. In various embodiments, the dielectric material 111 is SiN. The dielectric material 111 is not limited to SiN, but may also be SiON, Al2O3, HfO2, HfSiO, HfSiON, ZrO x It may be another dielectric material such as

[0045] FIG. 13 is a cross-sectional view of a semiconductor structure after depositing a layer of dielectric material for spacers 112 according to a second embodiment of the present invention. Known processes are used for spacer formation, and the deposited layer of dielectric material for spacers 112 can be composed of a different dielectric material than dielectric material 111. To selectively remove portions of the dielectric material to form spacers 112, as shown later in FIG. 14, the material used for the layer of dielectric material selected for spacers 112 has a high level of selectivity during RIE, i.e., a large etch rate during RIE (e.g., spacers 112 are more easily removed during RIE than dielectric material 111). For example, if dielectric material 111 is composed of SiN, spacers 112 can be composed of SiO2.

[0046] The thickness of the layer of dielectric material for spacers 112 is less than the thickness of dielectric material layer 111. For example, the thickness of spacers 112 may be less than half the thickness of dielectric material 111. The thickness of spacers 112 is less than the thickness of the dielectric material because the thin layer of dielectric material for spacers 112 can be more easily removed from horizontal surfaces of dielectric material 111 during an etching process such as RIE without removing most of dielectric material 111, as will be shown later in FIG.

[0047] 14 is a cross-sectional view of a semiconductor structure after forming spacers 112 on the sides of a heater according to a second embodiment of the present invention. Using known semiconductor spacer formation processes, an etching process, such as RIE, removes portions of the spacers 112 from the horizontal surfaces of the semiconductor structure. After etching, portions of the spacers 112 remain and surround the sides of the heater 11. The remaining portions of the spacers 112 on the vertical or near-vertical sides of the heater 11 become spacers around the heater 11.

[0048] 15 is a cross-sectional view of a semiconductor structure after depositing a sacrificial material 140 thereon, according to a second embodiment of the present invention. As shown in FIG. 15, a layer of sacrificial material 140 may be deposited on the exposed surfaces of the dielectric material 111 and the spacers 112. The sacrificial material 140 may be a soft material, such as amorphous carbon. For example, the sacrificial material 140 has a lower material hardness than the material forming the heater 11 and the material selected for the dielectric material 111.

[0049] 16 is a cross-sectional view of a semiconductor structure after CMP has stopped at the top surface of the dielectric material 111, in accordance with a second embodiment of the present invention. The first CMP removes the dielectric material 111 and the top portion of the sacrificial material 140 on the spacers 112. The CMP stops at the top surface of the dielectric material 111 that is on top of the heater 11. Remaining portions of the sacrificial material 140 reside on the spacers 112 and on the horizontal surfaces of the dielectric material 111 that are directly on the bottom electrode 10. For example, the CMP stops removing the sacrificial material 140 when it contacts the dielectric material 111 on top of the heater 11.

[0050] 17 is a cross-sectional view of a semiconductor structure after CMP is stopped on the top surface of heater 11, in accordance with a second embodiment of the present invention. The second CMP stops on the top surface of heater 11. The second CMP removes portions of sacrificial material 140 above the level of the top surface of heater 11, removes portions of spacers 112 above the level of the top surface of heater 11, and removes portions of dielectric material 111 above the level of the top surface of heater 11. Portions of sacrificial material 140 on dielectric material 111 and spacers 112 remain.

[0051] 18 is a cross-sectional view of a semiconductor structure after removal of sacrificial material 140, according to a second embodiment of the present invention. A photolithographically assisted wet chemical etching process or a dry etching process (e.g., RIE) can selectively remove the remaining portions of sacrificial material 140 from dielectric material 111 and spacers 112. In some embodiments, the etching process removes spacers 112 (e.g., optional spacer removal not shown in FIG. 18).

[0052] FIG. 19 is a cross-sectional view of a semiconductor structure after depositing a layer of PCM90 according to a second embodiment of the present invention. The layer of PCM90 is deposited on the dielectric material 111, the spacers 112, and the exposed surface of the heater 11. The thickness of the PCM90 can vary depending on the height of the heater 11. For example, the thickness of the PCM90 can vary between 15 nm and 50 nm, but is not limited to these thicknesses. As described with respect to FIG. 2, the PCM90 can be any PCM material. For example, the PCM90 can be a doped or undoped GST material. The PCM90 is essentially the same material as the PCM90 in FIG. 2. In various embodiments, the top surface of the heater 11 protrudes at least 5 nanometers above the top surface of the PCM90. In one embodiment, the top surface of the heater 11 is flush with the top surface of the PCM90 (i.e., the top surface of the heater 11 can be flush with the top surface of the PCM90).

[0053] 20 is a cross-sectional view of a semiconductor structure of a phase change memory cell according to a second embodiment of the present invention after depositing a layer of conductive material for a top electrode 95 thereon. The conductive material of the top electrode 95 can be any conductive material used in semiconductor devices. For example, the top electrode 95 can be Al, W, Cu, or other conductive material, metal, or suitable metal alloy used in electrodes or contacts in semiconductor devices. The thickness of the top electrode 95 can vary.

[0054] As known to those skilled in the art, the patterning and deposition of dielectric materials, i.e., ILDs (inter layer dielectrics) or other layers, or combinations thereof, around the top electrode 95 of the phase change memory cell shown in FIG. 20 can be performed according to typical semiconductor fabrication processes for completing a semiconductor chip or PCRAM memory device.

[0055] The difference between the height of the heater 11 above the bottom electrode 10 and the thickness of the dielectric material 111 can determine the depth to which the heater 11 is embedded in the PCM 90. Embedding the heater 11 in the PCM 90 as shown in FIG. 20 can improve the performance of semiconductor devices using the PCM 90.

[0056] FIG. 21 shows an example of the results of a thermal analysis of the effect of voltage (Volts) versus temperature (Kelvin) for various buried heater depths, according to an embodiment of the present invention. The graph shows the temperature of the PCM90 obtained at a probe adjacent to the top surface of the heater. The model assumes a tapered heater, with the heater sides forming a 95-degree angle with the top surface of the bottom electrode. Various heater depths P in the PCM90 are used in the thermal model.

[0057] Figure 21 shows the expected change in probe temperature for various applied voltages for four heater embedment depths in PCM 90. The melting point for the phase transition of the GST material used in PCM 90 is approximately 600 degrees Celsius or approximately 873 Kelvin.

[0058] The temperature versus voltage graph for various embedded heater depths (P) provides lines for heater protrusion depths into the PCM 90 of P=40 nm, P=30 nm, P=20 nm, P=10 nm, and P=0 nm (not embedded). An example of thermal model output, such as Vonset, Ionset, and Ponset, associated with the temperature versus voltage graph for four various heater depths embedded in the PCM is shown as model output in Figure 21. Vonset, Ionset, and Ponset are the voltage, current, and power, respectively, associated with the temperature that initiates a phase change in the PCM 90.

[0059] According to the thermal model and the temperature vs. voltage graph shown in Figure 21, the initiation of the phase change of PCM90 can occur with approximately 25% less power when the heater is embedded 40 nm into the PCM than when the heater is not embedded in the PCM. As shown in Figure 21, the Ponset required to achieve the phase transition temperature was determined to be 141 μW when P = 40 nm (i.e., when the heater is 40 nm protruding or embedded into the PCM90). Correspondingly, when P = 0 nm (no heater embedded), the model determined that the Ponset to achieve the phase transition of PCM90 is 170 μW.

[0060] The description of various embodiments of the present invention has been presented for purposes of illustration and is not intended to be exhaustive or limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used herein have been selected to best explain the principles of the embodiments, practical applications or technical improvements over technology found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

[0061] In a preferred embodiment of the present invention, a phase-change memory cell for a semiconductor device is provided, the phase-change memory cell comprising: a heater element on a first conductive layer, the heater element having a side surface at an angle greater than 90 degrees relative to the surface of the first conductive layer; a dielectric material on the side surface of the heater element and on the exposed surface of the first conductive layer; a spacer surrounding the dielectric material on the side surface of the heater element; and a phase-change material on the top surface of the heater element, on the spacer surrounding the dielectric material, and on the exposed portion of the dielectric material. The heater element may have one of the following shapes: a modified flat-topped cone, a cone, a tapered rectangular pillar, and a tapered triangular pillar. A portion of the heater element may protrude into a portion of the phase-change material along with the dielectric material on the side surface of the heater element and the spacer surrounding the dielectric material. The dielectric material and the spacer material may have different reactive ion etching selectivities. When the phase-change material is a doped germanium-antimony-tellurium material, the dielectric material may be silicon nitride surrounding a spacer made of silicon dioxide.

Claims

1. A phase change memory cell for a semiconductor device, comprising: a heater element on the first conductive layer; a spacer surrounding a side surface of the heater element; a first dielectric layer on a portion of the first conductive layer and on a bottom side of the spacer surrounding the heater element; a second dielectric layer on the first dielectric layer and on a side of the upper side of the spacer; a phase change material on the top surface of the heater element and on the second dielectric layer; Equipped with A phase change memory cell, wherein the second dielectric layer is composed of a material having a thermal conductivity similar to that of the phase change material.

2. The phase change memory cell of claim 1 further comprising a second conductive layer over the phase change material.

3. A phase change memory cell as described in claim 1 or 2, wherein the heater element on the first conductive layer forms an angle of 90 degrees or more with the surface of the first conductive layer.

4. The phase change memory cell of any one of claims 1 to 3, wherein the heater element has a conical shape with a flat top.

5. 5. The phase change memory cell of claim 1, wherein the heater element has one of a rectangular cylinder shape, a circular cylinder shape, an elliptical cylinder shape, or a triangular cylinder shape with either tapered or vertical sides.

6. The phase change memory cell of any one of claims 1 to 5, wherein the top surface of the heater element is smaller than the bottom surface of the heater element.

7. The phase change memory cell of any one of claims 1 to 6, wherein the top surface of the heater element is flush with the top surface of the second dielectric layer.

8. The phase change memory cell of any one of claims 1 to 7, wherein the second dielectric layer on the first dielectric layer is made of a low-k dielectric material.

9. The phase change memory cell of any one of claims 1 to 8, wherein the spacer extends to the top of the heater element.

10. The method includes, in place of the second dielectric layer on the first dielectric layer and on the upper side surface of the spacer, a material portion on the first conductive layer and surrounding the upper side surface of the spacer, The phase change memory cell of claim 1 , wherein the material portion is integrally formed of the same material as the phase change material.

11. The upper portion of the spacer includes a portion of dielectric material on the side of the heater element and a portion of spacer material surrounding the portion of dielectric material; the bottom of the spacer and the dielectric material portion are integrally formed of the same material as the first dielectric layer; 11. The phase change memory cell of claim 10, wherein the phase change material is formed over portions of the spacer material, over exposed portions of the dielectric material, and over exposed portions of the first dielectric layer.

12. 1. A method of forming a phase change memory cell in a semiconductor device, comprising: depositing a layer of heater material on the bottom electrode; selectively etching the layer of heater material to form a heater; forming spacers on sides of the heater; depositing a first dielectric material on the bottom electrode, on the spacer, and on a top surface of the heater; removing a top portion of a first dielectric material from the top surface of the heater, from the top of the spacer, and from above the bottom electrode; depositing a second dielectric material on the top surface of the heater, on the tops of the spacers, and on the first dielectric material; removing a top portion of the second dielectric material stopping at the top surface of the heater; depositing a phase change material on the top surface of the heater and on the second dielectric material; depositing a layer of top electrode material over the phase change material; Including, The method, wherein the second dielectric material has a thermal conductivity similar to that of the phase change material.

13. 13. The method of forming the phase change memory cell of claim 12, wherein selectively etching the layer of heater material forms the heater with heater sides that form an angle of 90 degrees or more with the top surface of the bottom electrode.

14. The method for forming the phase change memory cell of claim 12 or 13, wherein the second dielectric material is a low-k dielectric material.

15. 15. The method of forming the phase change memory cell of claim 12, wherein selectively etching the layer of heater material to form the heater comprises using either a double patterning process or an extreme ultraviolet etching process if the heater has a small diameter.

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