Templates for source-drain formation of nanosheets with bottom dielectrics

Abstract

A semiconductor device and a method for its manufacture are described. The method includes forming a bottom dielectric insulation (BDI) layer on a substrate and depositing a template material in source / drain trenches. The template material is crystallized. Epitaxial growth of source and drain regions then proceeds, advantageously on the bottom and sidewalls of the source and drain regions.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE

[0001] Embodiments of the present disclosure relate generally to semiconductor devices. More particularly, embodiments of the present disclosure are directed to gate-all-around (GAA) devices having source-drain regions with templates. [Background technology]

[0002]

[0002] Transistors are key components of most integrated circuits. Because a transistor's drive current, and therefore its speed, is proportional to its gate width, faster transistors generally require larger gate widths. As a result, there is a trade-off between transistor size and speed, and "fin" field-effect transistors (finFETs) have been developed to address the conflicting goals of maximum drive current and minimum size. FinFETs feature a fin-shaped channel region that significantly increases transistor size without significantly increasing the transistor's footprint, and are currently being applied in many integrated circuits. However, FinFETs also have drawbacks.

[0003]

[0003] As transistor device feature sizes continue to shrink to achieve increased circuit density and higher performance, improved transistor device structures are needed to improve electrostatic coupling and reduce adverse effects such as parasitic capacitance and off-state leakage. Examples of transistor device structures include planar structures, fin field-effect transistor (FinFET) structures, and horizontal gate-all-around (hGAA) structures. The hGAA device structure includes multiple lattice-matched channels suspended in a stacked configuration and connected by source / drain regions. The hGAA structure offers good electrostatic control and can be widely adopted in complementary metal-oxide-semiconductor (CMOS) wafer fabrication.

[0004]

[0004] The presence of a bottom dielectric insulating layer is becoming a key layer for improving the performance of nanosheet devices. However, when there is a bottom dielectric insulating (BDI) layer under the source / drain, the epitaxial source / drain can only grow from the sidewalls, not from the bottom, which causes numerous defects during the growth / formation of the source and drain regions. Therefore, an improved method for forming gate-all-around devices is needed. Summary of the Invention

[0005]

[0005] One or more embodiments of the present disclosure are directed to a method of forming a semiconductor device. In one or more embodiments, the method of forming the semiconductor device includes forming a superlattice structure on an upper surface of a bottom dielectric insulating layer on a substrate, the superlattice structure including a plurality of horizontal channel layers and a corresponding plurality of semiconductor material layers arranged alternately in a plurality of stacked pairs, forming source and drain trenches on the bottom dielectric insulating layer on the substrate adjacent to the superlattice structure, depositing a template material in the source and drain trenches, crystallizing the template material, and forming source and drain regions.

[0006]

[0006] Additional embodiments of the present disclosure are directed to methods of forming a semiconductor device. In one or more embodiments, the method of forming the semiconductor device includes forming a superlattice structure on an upper surface of a bottom dielectric insulating layer on a substrate, the superlattice structure including a plurality of horizontal channel layers and a corresponding plurality of semiconductor material layers arranged alternately in a plurality of stacked pairs, forming a gate structure on the upper surface of the superlattice structure, forming a dielectric layer on the gate structure and the superlattice structure, forming source and drain trenches on the bottom dielectric insulating layer on the substrate adjacent to the superlattice structure, depositing a template material in the source and drain trenches, annealing the substrate to crystallize the template material, and forming source and drain regions.

[0007]

[0007] So that the features of the present disclosure described above may be understood in detail, a more particular description of the present disclosure briefly summarized above will be had by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the present disclosure is susceptible to other equally effective embodiments, and therefore the accompanying drawings illustrate only typical embodiments of the present disclosure and should not be considered as limiting the scope of the present disclosure. [Brief explanation of the drawings]

[0008] [Figure 1] 8 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2A]

[0009] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2B]

[0010] 2B shows an enlarged cross-sectional view of a portion of the device of FIG. 2A according to one or more embodiments. [Figure 2C]

[0011] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2D]

[0012] 2D shows an enlarged cross-sectional view of a portion of the device of FIG. 2C according to one or more embodiments. [Figure 3A]

[0013] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 3B]

[0014] 1 shows a cross-sectional view of a device according to one or more alternative embodiments. [Figure 4A]

[0015] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 4B]

[0016] 1 shows a cross-sectional view of a device according to one or more alternative embodiments. [Figure 5]

[0017] 1 illustrates a process flow diagram of a method for forming a semiconductor device according to some embodiments of the present disclosure. [Figure 6]

[0018] 1 illustrates a cluster tool in accordance with one or more embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0009]

[0019] For ease of understanding, the same reference numerals have been used, where possible, to designate identical elements common to the figures. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated in other embodiments without further description.

[0010]

[0020] Before describing several example embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0011]

[0021] The term "substrate," as used herein and in the appended claims, refers to a surface or a portion of a surface upon which a process acts. Those skilled in the art will also understand that a reference to a substrate may refer to only a portion of a substrate unless the context clearly indicates otherwise. Furthermore, a reference to deposition on a substrate may refer to both a bare substrate and a substrate having one or more films or features deposited or formed on its surface.

[0012]

[0022] As used herein, "substrate" refers to any substrate or material surface formed on a substrate upon which film processing is performed during a manufacturing process. For example, substrate surfaces upon which processing may be performed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials, such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. Substrates may be exposed to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate (or otherwise create or graft target chemical moieties to impart chemical functionality), anneal, and / or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in the present disclosure, any of the disclosed film processing steps can also be performed on underlying layers formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include such underlying layers, as the context indicates. Thus, for example, if a film / layer or partial film / layer is being deposited on a substrate surface, the exposed surface of the newly deposited film / layer is the substrate surface. What a given substrate surface comprises will depend on what film is being deposited and the particular chemistry used.

[0013]

[0023] As used herein and in the appended claims, the terms "precursor," "reactant," "reactive gas," and the like are used interchangeably to refer to any gas species capable of reacting with the substrate surface.

[0014]

[0024] A transistor is a circuit component or element that is often formed on a semiconductor device. Depending on the circuit design, transistors may be formed on the semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive lines, or other elements. Generally, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source and drain regions include doped regions of a substrate and exhibit a doping profile suitable for a particular application. The gate is located over a channel region and includes a gate dielectric interposed between the gate electrode in the substrate and the channel region.

[0015]

[0025] As used herein, the term "field effect transistor" or "FET" refers to a transistor that uses an electric field to control the electrical behavior of the device. Enhancement-mode field-effect transistors generally exhibit very high input impedance at low temperatures. Conduction between the drain and source terminals is controlled by the electric field within the device, which is generated by a voltage difference between the body and gate of the device. The three terminals of a FET are the source (S), where carriers enter the channel, the drain (D), where carriers exit the channel, and the gate (G), which controls the conductivity of the channel. Conventionally, the current entering the channel from the source (S) is denoted IS, and the current entering the channel from the drain (D) is denoted ID. The voltage between the drain and source is denoted VDS. Applying a voltage to the gate (G) controls the current entering the channel at the drain (i.e., ID).

[0016]

[0026] A metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET). It has an insulated gate; the voltage across the gate determines the device's conductivity. This ability to change conductivity in response to an applied voltage is used to amplify or switch electronic signals. MOSFETs are based on modulation of charge concentration by a metal-oxide-semiconductor (MOS) capacitor between a body electrode and a gate electrode located above the body and insulated from all other device regions by a gate dielectric layer. Compared to a MOS capacitor, a MOSFET contains two additional terminals (source and drain), each connected to a separate highly doped region separated by a body region. These regions can be either p-type or n-type, but both are of the same type, opposite the body region. The source and drain (unlike the body) are highly doped, denoted by a "+" symbol after their doping type.

[0017]

[0027] If the MOSFET is an n-channel or nMOS FET, the source and drain are n+ regions and the body is p region. If the MOSFET is a p-channel or pMOS FET, the source and drain are p+ regions and the body is n region. The source is so named because it is the source of charge carriers (electrons for n-channel and holes for p-channel) that flow through the channel; similarly, the drain is so named because it is where the charge carriers exit the channel.

[0018]

[0028] As used herein, the term "fin field effect transistor (FinFET)" refers to a MOSFET transistor constructed on a substrate where the gates are located on two or three sides of the channel, forming a double-gate or triple-gate structure. FinFET devices are given the collective name FinFET because the channel region forms a "fin" on the substrate. FinFET devices have fast switching times and high current densities.

[0019]

[0029] As used herein, the term "gate-all-around (GAA)" is used to refer to an electronic device, such as a transistor, in which a gate material surrounds a channel region on all sides. The channel region of a GAA transistor may comprise a nanowire, nanoslab, or nanosheet, a rod-shaped channel, or other suitable channel configuration known to those skilled in the art. In one or more embodiments, the channel region of a GAA device comprises multiple vertically spaced horizontal nanowires or bars, making the GAA transistor a stacked horizontal gate-all-around (hGAA) transistor.

[0020]

[0030] As used herein, the term "nanowire" refers to a wire measuring 1 nanometer (10 -9 Nanowires refer to nanostructures having diameters on the order of 1000 to 10000 nm. Nanowires can also be defined as having a length-to-width ratio greater than 1000. Alternatively, nanowires can be defined as structures whose thickness or diameter is constrained to tens of nanometers or less, but whose length is not. Nanowires are used in transistor and some laser applications and, in one or more embodiments, are made of semiconducting, metallic, insulating, superconducting, or molecular materials. In one or more embodiments, nanowires are used in transistors for logic CPUs, GPUs, MPUs, and volatile (e.g., DRAM) and nonvolatile (e.g., NAND) devices. As used herein, the term "nanosheet" refers to a two-dimensional nanostructure having a thickness ranging from about 0.1 nm to about 1000 nm.

[0021]

[0031] Embodiments of the present disclosure are illustrated by diagrams that illustrate devices (e.g., transistors) and processes for forming transistors according to one or more embodiments of the present disclosure. The illustrated processes are merely exemplary of possible applications of the disclosed processes, and one of ordinary skill in the art will recognize that the disclosed processes are not limited to the applications illustrated.

[0022]

[0032] One or more embodiments of the present disclosure are described with reference to the figures. In one or more embodiment methods, a gate-all-around transistor with a bottom dielectric insulation (BDI) layer is fabricated using a standard process flow. After the source / drain regions are formed, a template material is deposited on the source / drain regions, and the template material is crystallized to form the source / drain. The crystallized template material allows epitaxial growth not only on the sidewalls but also on the bottom of the source / drain trenches.

[0023]

[0033] In some embodiments, the template material is deposited on one or more of the bottom surface of the source / drain trenches and the sidewalls of the source / drain trenches. In some embodiments, the template material is deposited conformally. As used herein, the term "conformal" means that a layer conforms to the contours of a feature or layer. The conformality of a layer is typically quantified by the ratio of the average thickness of a layer deposited on the sidewalls of a feature to the average thickness of the same deposited layer on the field (or top surface) of the substrate. In one or more embodiments, the template material is crystallized by rapid thermal processing (RTP) or laser annealing. Forming the source and drain regions includes growing an epitaxial layer.

[0024]

[0034] 1-4B illustrate stages in the fabrication of a semiconductor structure according to some embodiments of the present disclosure. FIG. 5 illustrates a process flow diagram of a method 200 for forming a semiconductor device according to some embodiments of the present disclosure. Method 200 is described below with reference to FIGS. 1-4B. FIGS. 1-4B illustrate cross-sectional views of an electronic device (e.g., a GAA) according to one or more embodiments. Method 200 may be part of a multi-step fabrication process for a semiconductor device. Thus, method 200 may be performed in any suitable process chamber connected to a cluster tool. The cluster tool may include process chambers for fabricating semiconductor devices, such as chambers configured for etching, deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), oxidation, or any other suitable chamber used in the fabrication of semiconductor devices.

[0025]

[0035] 1-4B illustrate the fabrication steps of steps 210-216 of FIG. 5. Referring to FIG. 5, a method 200 for forming a device 100 begins in step 202 by providing a substrate 102. In some embodiments, the substrate 102 may be a bulk semiconductor substrate. As used herein, the term "bulk semiconductor substrate" refers to a substrate that is entirely made of a semiconductor material. A bulk semiconductor substrate may include any suitable semiconductor material and / or combination of semiconductor materials for forming a semiconductor structure. For example, the semiconductor layer may be crystalline silicon (e.g., Si <100> or Si <111> The semiconductor substrate 102 may comprise one or more materials such as silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, gallium arsenide, or other suitable semiconductor materials. In some embodiments, the semiconductor material is silicon (Si). In one or more embodiments, the semiconductor substrate 102 comprises a semiconductor material, such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), other semiconductor materials, or any combination thereof. In one or more embodiments, the substrate 102 comprises one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), or phosphorus (P). Although several examples of materials that can form the substrate are described, any material that can serve as a foundation upon which passive and active electronic devices (e.g., transistors, memory, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic device) can be constructed is within the spirit and scope of the present disclosure.

[0026]

[0036] In some embodiments, the semiconductor material can be a doped material, such as n-type doped silicon (n-Si) or p-type doped silicon (p-Si). In some embodiments, the substrate can be doped using any suitable process, such as an ion implantation process. As used herein, the term "n-type" refers to a semiconductor made by doping an intrinsic semiconductor with an electron donor element during fabrication. The term n-type comes from the negative charge of electrons. In n-type semiconductors, electrons are the majority carriers and holes are the minority carriers. As used herein, the term "p-type" refers to the positive charge of wells (or holes). In contrast to n-type semiconductors, p-type semiconductors have a hole concentration that is greater than the electron concentration. In p-type semiconductors, holes are the majority carriers and electrons are the minority carriers. In one or more embodiments, the dopant is selected from one or more of boron (B), gallium (Ga), phosphorus (P), arsenic (As), other semiconductor dopants, or combinations thereof.

[0027]

[0037] In some embodiments, at step 204, a replacement gate structure (e.g., dummy gate structure 105) is formed on the superlattice structure 106. The dummy gate structure 105 defines a channel region of the transistor device. The dummy gate structure 105 may be formed using any suitable conventional deposition and patterning process known in the art. In one or more embodiments, the dummy gate structure 105 comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), and titanium aluminum (TiAl).

[0028]

[0038] In some embodiments, sidewall spacers are formed along the outer sidewalls of the dummy gate structure 105. The sidewall spacers may comprise any suitable insulating material known in the art, such as, for example, silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, etc. In some embodiments, the sidewall spacers are formed using any suitable conventional deposition and patterning process known in the art, such as atomic layer deposition, plasma-enhanced atomic layer deposition, plasma-enhanced chemical vapor deposition, or low-pressure chemical vapor deposition.

[0029]

[0039] Channel region 117 separates superlattice structure 106 from adjacent superlattice structures 106. In one or more embodiments, source trench 113 and drain trench 114 are formed adjacent to (i.e., on either side of) superlattice structure 106.

[0030]

[0040] 5, in step 206, in one or more embodiments, a bottom dielectric insulation (BDI) layer 104 may be formed on the substrate 102. The bottom dielectric insulation (BDI) layer 104 may comprise any suitable material known to those skilled in the art. In one or more embodiments, the bottom dielectric insulation (BDI) layer 104 comprises one or more of silicon oxide (SiOx), silicon nitride (SiN), silicon carbide (SiC), or a high-k material. In some embodiments, the high-k material is selected from one or more of aluminum oxide (Al2O3), hafnium oxide (HfO2), and the like. In one or more particular embodiments, the bottom dielectric insulation (BDI) layer 104 comprises silicon oxide.

[0031]

[0041] In some embodiments, bottom dielectric insulation (BDI) layer 104 is deposited on substrate 102 using conventional chemical vapor deposition techniques. In some embodiments, bottom dielectric insulation (BDI) layer 104 is recessed below the top surface of substrate 102 such that the bottom of superlattice structure 106 is formed from substrate 102.

[0032]

[0042] At least one superlattice structure 106 is formed on the top surface of the bottom dielectric insulation (BDI) layer 104. The superlattice structure 106 includes a plurality of stacked pairs of alternating semiconductor material layers 110 and corresponding nanosheet channel layers 108. In some embodiments, the plurality of stacked layers includes silicon (Si) and silicon germanium (SiGe). In some embodiments, the plurality of semiconductor material layers 110 includes silicon germanium (SiGe) and the plurality of nanosheet channel layers 108 includes silicon (Si). In other embodiments, the plurality of nanosheet channel layers 108 includes silicon germanium (SiGe) and the plurality of semiconductor material layers includes silicon (Si).

[0033]

[0043] In some embodiments, the plurality of semiconductor material layers 110 and the corresponding plurality of nanosheet channel layers 108 can include any number of pairs of lattice-matched materials suitable for forming the superlattice structure 106. In some embodiments, the plurality of semiconductor material layers 110 and the corresponding plurality of nanosheet channel layers 108 include from about 2 to about 50 pairs of lattice-matched materials.

[0034]

[0044] In one or more embodiments, the thickness t1 of the plurality of semiconductor material layers 110 and the plurality of nanosheet channel layers 108 is in the range of about 2 nm to about 50 nm, in the range of about 3 nm to about 20 nm, or in the range of about 2 nm to about 15 nm.

[0035]

[0045] 2B is an enlarged cross-sectional view of region 115 of FIG. 2A. Referring to FIGS. 2A-2B and 5, in step 212, a template material 116 is deposited in channel region 117 and on the bottom surfaces of source / drain trenches 113, 114. Template material 116 comprises any suitable material known to those skilled in the art. In some embodiments, template material 116 is amorphous. In one or more embodiments, template material 116 comprises one or more of silicon (Si), silicon germanium (SiGe), titanium (Ti), zirconium (Zr), and hafnium (Hf). In some embodiments, template material 116 comprises one or more of silicon (Si) and silicon germanium (SiGe).

[0036]

[0046] The template material 116 can be deposited using any suitable conventional deposition process known in the art, such as atomic layer deposition, plasma-enhanced atomic layer deposition, plasma-enhanced chemical vapor deposition, or low-pressure chemical vapor deposition.

[0037]

[0047] In one or more embodiments, the thickness of template material 116 is in the range of about 2 nm to about 50 nm, in the range of about 3 nm to about 20 nm, or in the range of about 2 nm to about 15 nm.

[0038]

[0048] Figure 2D is an enlarged cross-sectional view of region 115 of Figure 2C. Referring to Figures 2C-2D, in some embodiments, template material 116 can be deposited in channel region 117, on the bottom surfaces of source / drain trenches 113, 114, and on the sidewalls of superlattice structure 106.

[0039]

[0049] 3A-3B and 5, in step 214, the template material 116 is crystallized to form a crystalline template material 118.

[0040]

[0050] The template material 116 may be crystallized by any suitable means known to those skilled in the art. In one or more embodiments, the template material 116 is crystallized by rapid thermal processing (RTP) or laser annealing.

[0041]

[0051] In some embodiments, the rapid thermal processing (RTP) or laser annealing is performed at a temperature in the range of 500° C. to 900° C., in the range of 600° C. to 900° C., or in the range of 600° C. to 800° C. In some embodiments, the rapid thermal processing (RTP) or laser annealing is performed at a pressure in the range of 5 Torr to 20 Torr. In one or more embodiments, the rapid thermal processing or laser annealing is performed in an ambient atmosphere of hydrogen (H2) gas and oxygen (O2) gas at atmospheric pressure.

[0042]

[0052] 4A-4B and 5, in step 216, in some embodiments, the buried source region 120 and the drain region 122 are formed in the source trench 113 and the drain trench 114, respectively. In some embodiments, the source region 120 is formed adjacent to the first end of the superlattice structure 106, and the drain region 122 is formed adjacent a second opposite end of the superlattice structure. In some embodiments, the source and / or drain regions are formed from any suitable semiconductor material, such as, but not limited to, silicon, germanium, silicon germanium, silicon phosphide, or silicon arsenide. In some embodiments, the source region 120 and the drain region 122 may be formed using any suitable deposition process, such as an epitaxial deposition process. In some embodiments, the source region 120 and the drain region 122 is independently doped with one or more of phosphorus (P), arsenic (As), boron (B), and gallium (Ga).

[0043]

[0053] In some embodiments, an interlevel dielectric (ILD) layer (not shown) may be formed over the source region. 120 / Drain region 122 The ILD layer is blanket deposited on the substrate 102, including the dummy gate structure 105, and sidewall spacers. The ILD layer may be deposited using conventional chemical vapor deposition techniques (e.g., plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition). In one or more embodiments, the ILD layer is formed from any suitable dielectric material, such as, but not limited to, undoped silicon oxide, doped silicon oxide (e.g., BPSG, PSG), silicon nitride, and silicon oxynitride. In one or more embodiments, the ILD layer is then polished back using conventional chemical mechanical planarization techniques to expose the top surface of the dummy gate structure 105. In some embodiments, the ILD layer is polished back to expose the top surface of the dummy gate structure 105 and the top surfaces of the sidewall spacers 112.

[0044]

[0054] The dummy gate structure 105 may be removed to expose the channel region 117 of the superlattice structure 106. The ILD layer may be removed during the removal of the dummy gate structure 105 to expose the source region 117. 120 / Drain region 122 The dummy gate structure 105 may be removed using conventional etching methods, such as plasma dry etching or wet etching. In some embodiments, the dummy gate structure 105 comprises polysilicon, and the dummy gate structure 105 is removed by a selective etching process. In some embodiments, the dummy gate structure 105 comprises polysilicon, and the superlattice structure 106 comprises alternating layers of silicon (Si) and silicon germanium (SiGe).

[0045]

[0055] 5 , in step 218, the plurality of semiconductor material layers 110 are selectively etched between the plurality of nanosheet channel layers 108 in the superlattice structure 106. For example, if the superlattice structure 106 is composed of silicon (Si) and silicon germanium (SiGe) layers, the silicon germanium (SiGe) is selectively etched to form channel nanowires. The plurality of semiconductor material layers 110, e.g., silicon germanium (SiGe), may be removed using any well-known etchant that is selective to the plurality of nanosheet channel layers 108, where the etchant etches the plurality of semiconductor material layers 110 at a significantly higher rate than the plurality of nanosheet channel layers 108. In some embodiments, a selective dry etching or wet etching process may be used. In some embodiments, when the plurality of nanosheet channel layers 108 are silicon (Si) and the plurality of semiconductor material layers 110 are silicon germanium (SiGe), the silicon germanium layer can be selectively removed using a wet etchant, such as, but not limited to, a carboxylic acid / nitric acid / HF solution and a citric acid / nitric acid / HF solution. Removal of the plurality of semiconductor material layers 110 leaves voids between the plurality of nanosheet channel layers 108. The voids between the plurality of nanosheet channel layers 108 have a thickness of about 3 nm to about 20 nm. The remaining nanosheet channel layers 108 form a vertical array of channel nanowires connected to the source region 220 / drain region 222. The channel nanowires run parallel to the top surface of the substrate 102 and are aligned with each other to form a single row of channel nanowires.

[0046]

[0056] The isotropic etching process of Step 218 may include any suitable etching process that is selective to the semiconductor material of the plurality of nanosheet channel layers 108. In some embodiments, the isotropic etching process of Step 106 includes one or more of a wet etching process or a dry etching process. In some embodiments, the isotropic etching process of Step 106 includes a dry etching process.

[0047]

[0057] In such embodiments, the dry etching process may include conventional plasma etching or a remote plasma-assisted dry etching process, such as the SiCoNi™ etch process available from Applied Materials, Inc., Santa Clara, California. In the SiCoNi™ etch process, the device is exposed to H, NF, and / or NH plasma species, such as plasma-excited hydrogen and fluorine species. For example, in some embodiments, the device may be subjected to simultaneous exposure to H, NF, and NH plasma. The SiCoNi™ etch process is performed in a SiCoNi™ Preclean chamber and may be integrated into one of various multi-processing platforms, including the Centura™, Dual ACP, Producer™ GT, and Endura™ platforms available from Applied Materials. The wet etching process may include a hydrofluoric (HF) acid last process, or the so-called "HF last" process. In this process, an HF etch of the surface is performed, leaving the surface hydrogen-terminated. Alternatively, any other liquid-based pre-epitaxial pre-cleaning process can be used. In some embodiments, the process includes sublimation etching to remove native oxidation. The etching process can be plasma-based or thermal-based. The plasma process can be any suitable plasma (e.g., conductively coupled plasma, inductively coupled plasma, microwave plasma).

[0048]

[0058] In one or more embodiments, step 220 of method 200 represents one or more post-processing steps. The one or more post-processing steps can be any process known to those skilled in the art for device completion (e.g., formation of a replacement metal gate, etc.). For example, in one or more non-illustrated embodiments, a high-k dielectric is formed. The high-k dielectric can be any suitable high-k dielectric material deposited by any suitable deposition technique known to those skilled in the art. In some embodiments, the high-k dielectric comprises hafnium oxide. In some embodiments, a conductive material, such as titanium nitride (TiN), tungsten (W), cobalt (Co), or aluminum (Al), is deposited on the high-k dielectric. To ensure formation of a layer having a uniform thickness around each of the multiple channel layers, the conductive material can be formed using any suitable deposition process, such as, but not limited to, atomic layer deposition (ALD).

[0049]

[0059] In some embodiments, method 200 is integrated so as not to break vacuum. In one or more embodiments, deposition of template material (step 212), crystallization of template material (step 214), and source / drain epitaxial growth (step 216) can be integrated so as not to break vacuum between operations.

[0050]

[0060] In some embodiments, the apparatus or process tool is configured to maintain the substrate under vacuum conditions to prevent the formation of an oxide layer after deposition of template material 116. In such embodiments, the process tool is configured to move the substrate from the surface treatment chamber (e.g., annealing chamber) to a rapid thermal processing (RTP) chamber for step 214 (i.e., crystallization) without exposing the substrate to atmospheric conditions.

[0051]

[0061] One or more embodiments of the present disclosure are directed to a method of forming a semiconductor device, including forming a superlattice structure on an upper surface of a bottom dielectric insulating layer on a substrate, the superlattice structure including a plurality of horizontal channel layers and a corresponding plurality of semiconductor material layers arranged alternately in a plurality of stacked pairs, forming source and drain trenches on the bottom dielectric insulating layer on the substrate adjacent to the superlattice structure, depositing a template material in the source and drain trenches, crystallizing the template material, and forming source and drain regions.

[0052]

[0062] An additional embodiment of the present disclosure is directed to a processing tool 300 and described methods for forming GAA devices, as shown in FIG. 6. Various multi-processing platforms may be utilized, including Applied Materials' Centura, Dual ACP, Producer GT, and Endura platforms, as well as other processing systems. The cluster tool 300 includes at least one central transfer station 314 having multiple sides. A robot 316 is positioned within the central transfer station 314 and configured to move the robot blade and wafer to each of the multiple sides.

[0053]

[0063] The cluster tool 300 includes multiple processing chambers 308, 310, 312, also referred to as process stations, connected to a central transfer station. The various processing chambers provide distinct processing regions separate from adjacent processing stations. The processing chambers may be any suitable chamber, including, but not limited to, pre-clean chambers, deposition chambers, annealing chambers (i.e., template crystallization chambers), etch chambers, etc. The specific arrangement of processing chambers and components may vary depending on the cluster tool and should not be construed as limiting the scope of the present disclosure.

[0054]

[0064] 6, a factory interface 318 is connected to the front of the cluster tool 300. The factory interface 318 includes a loading and unloading chamber 302 at the front 319 of the factory interface 318.

[0055]

[0065] The size and shape of the loading and unloading chambers 302 can vary depending on, for example, the substrates to be processed in the cluster tool 300. In the illustrated embodiment, the loading and unloading chambers 302 are sized to hold a wafer cassette with multiple wafers positioned within the cassette.

[0056]

[0066] The robot 304 resides within a factory interface 318 and can move between the loading chamber 302 and the unloading chamber 302. The robot 304 can transfer wafers from a cassette in the loading chamber 302 through the factory interface 318 to a load lock chamber 320. The robot 304 can also transfer wafers from the load lock chamber 320 through the factory interface 318 to a cassette in the unloading chamber 302.

[0057]

[0067] In some embodiments, the robot 316 is a multi-arm robot capable of independently moving multiple wafers at a time. The robot 316 is configured to move wafers between chambers around the transfer chamber 314. Individual wafers are carried on a wafer transport blade located at the distal end of the first robotic mechanism.

[0058]

[0068] A system controller 357 is in communication with the robot 316 and the plurality of processing chambers 308, 310, 312. The system controller 357 can be any suitable component capable of controlling the processing chambers and robot. For example, the system controller 357 can be a computer including a central processing unit (CPU) 392, memory 394, input / output 396, appropriate circuitry 398, and storage.

[0059]

[0069] The processes may generally be stored in the memory of the system controller 357 as software routines that, when executed by a processor, cause the processing chamber to perform the processes of the present disclosure. The software routines may be stored and / or executed by a second processor (not shown) located remotely from the hardware controlled by the processor. Some or all of the methods of the present disclosure may also be performed in hardware. Thus, the processes may be implemented in software and executed using a computer system, for example, in hardware as an application-specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. The software routines, when executed by a processor, transform a general-purpose computer into a special-purpose computer (controller) that controls chamber operation to perform the processes.

[0060]

[0070] In some embodiments, the system controller 357 is configured to control the rapid thermal processing chamber to crystallize the template material.

[0061]

[0071] In one or more embodiments, the processing tool includes a central transfer station including a robot configured to move wafers; a plurality of process stations, each process station connected to the central transfer station and providing a processing area separated from the processing areas of adjacent process stations, including a template deposition chamber and a template crystallization chamber; and a controller connected to the central transfer station and the plurality of process stations, the controller configured to activate the robot to move wafers between the process stations and to control the process performed at each of the process stations.

[0062]

[0072] In the context of describing the materials and methods discussed herein (particularly in the context of the claims that follow), the use of "a" and "an," "the," and similar referents should be construed to encompass both the singular and the plural unless otherwise indicated herein or clearly contradicted by context. The recitation of ranges of values ​​herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or clearly contradicted by context. The use of any and all examples or exemplary language (e.g., "such as") provided herein is intended merely to better describe the materials and methods and does not limit the scope unless specifically claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[0063]

[0073] Throughout this specification, references to "one embodiment," "a particular embodiment," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one or more embodiments," "a particular embodiment," "in one embodiment," or "an embodiment" in various places throughout this specification do not necessarily refer to the same embodiment of the present disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0064]

[0074] Although the disclosure herein has been described with reference to particular embodiments, those skilled in the art will recognize that the described embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed method and apparatus without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure includes modifications and variations that come within the scope of the appended claims and their equivalents.

Claims

1. 1. A method of forming a semiconductor device, comprising: forming a superlattice structure on an upper surface of a bottom dielectric insulating layer on a substrate, the superlattice structure including a plurality of horizontal channel layers and a corresponding plurality of semiconductor material layers arranged alternately in a plurality of stacked pairs; forming source and drain trenches adjacent to the superlattice structure on the bottom dielectric insulating layer on the substrate; depositing a template material on a bottom surface of the source trench and on a bottom surface of the drain trench on the bottom dielectric insulating layer; crystallizing the template material by one or more of rapid thermal processing (RTP) annealing or laser annealing at a temperature ranging from 600°C to 900°C under an atmosphere of hydrogen (H2) gas and oxygen (O2) to form a crystallized template material on the bottom dielectric insulating layer; forming source and drain regions on the crystallized template material on the bottom dielectric insulating layer; A method comprising:

2. The method of claim 1 , wherein the template material is amorphous.

3. The method of claim 2 , wherein the template material comprises silicon (Si), silicon germanium (SiGe), titanium (Ti), zirconium (Zr), and hafnium (Hf).

4. The method of claim 2 , wherein the template material has a thickness in the range of 2 nm to 50 nm.

5. 10. The method of claim 1, wherein the plurality of semiconductor material layers and the plurality of horizontal channel layers independently comprise one or more of silicon germanium (SiGe) and silicon (Si).

6. The method of claim 1 , wherein forming the source and drain regions comprises growing an epitaxial layer.

7. 10. The method of claim 1, wherein the source and drain regions are independently doped with one or more of phosphorus (P), arsenic (As), boron (B), and gallium (Ga).

8. 10. The method of claim 1, wherein the bottom dielectric insulating layer comprises one or more of silicon oxide (SiOx), silicon nitride (SiN), silicon carbide (SiC), and a high-k material.

9. The method of claim 1 further comprising forming a gate structure on an upper surface of the superlattice structure.

10. 10. The method of claim 9, further comprising forming a dielectric layer over the gate structure and the superlattice structure.

11. 11. The method of claim 10, wherein the gate structure comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), and aluminum nitride (TiAl).

12. 1. A method of forming a semiconductor device, comprising: forming a superlattice structure on an upper surface of a bottom dielectric insulating layer on a substrate, the superlattice structure including a plurality of horizontal channel layers and a corresponding plurality of semiconductor material layers arranged alternately in a plurality of stacked pairs; forming a gate structure on an upper surface of the superlattice structure; forming a dielectric layer over the gate structure and the superlattice structure; forming source and drain trenches adjacent to the superlattice structure on the bottom dielectric insulating layer on the substrate; depositing a template material on a bottom surface of the source trench and on a bottom surface of the drain trench on the bottom dielectric insulating layer; annealing the substrate by one or more of rapid thermal processing (RTP) annealing or laser annealing at a temperature ranging from 600°C to 900°C in an atmosphere of hydrogen (H2) gas and oxygen (O2) to crystallize the template material and form a crystallized template material on the bottom dielectric insulating layer; forming source and drain regions on the crystallized template material on the bottom dielectric insulating layer; A method comprising:

13. The method of claim 12 , wherein the template material is amorphous and has a thickness in the range of 2 nm to 50 nm.

14. 14. The method of claim 13, wherein the template material comprises silicon (Si), silicon germanium (SiGe), titanium (Ti), zirconium (Zr), and hafnium (Hf).

15. 13. The method of claim 12, wherein the plurality of semiconductor material layers and the plurality of horizontal channel layers independently comprise one or more of silicon germanium (SiGe) and silicon (Si).

16. The method of claim 12 , wherein forming the source and drain regions comprises growing an epitaxial layer.

17. 13. The method of claim 12, wherein the source and drain regions are independently doped with one or more of phosphorus (P), arsenic (As), boron (B), and gallium (Ga).

18. 13. The method of claim 12, wherein the bottom dielectric insulating layer comprises one or more of silicon oxide (SiOx), silicon nitride (SiN), silicon carbide (SiC), and a high-k material.

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