Power conversion device and control method for power conversion device

Abstract

To provide a power conversion device capable of suppressing increase in a surge voltage and noise upon occurrence of off-resonance.SOLUTION: A power conversion device 101 comprises: a switching circuit RSC that has switching elements Q1 and Q2, a resonance capacitor Cr, and a transformer Tr with a primary coil Tr1 connected in series with the resonance capacitor Cr; a gate drive circuit 2 that outputs a gate drive current to gate terminals of the switching elements Q1 and Q2 to on / off-control the switching elements Q1 and Q2; a detection circuit 5 that detects a current I1 flowing in the switching circuit RSC; and a determination circuit 6 that determines inversion of a polarity of the current detected by the detection circuit 5. The gate drive circuit 2 comprises a gate adjustment circuit that adjusts the gate drive current on the basis of the determination results of the determination circuit 6.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a power conversion device and a control method thereof, and more particularly to a resonant power conversion device including a plurality of switching elements, a capacitor, and a transformer, and a control method thereof. [Background technology]

[0002] Resonant power conversion devices are described, for example, in Patent Documents 1 and 2. Patent Documents 1 and 2 describe resonant power conversion devices that can detect or determine fluctuations in the resonant frequency. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2017-184599 [Patent Document 2] Patent Publication No. 2019-201455 Summary of the Invention [Problem to be solved by the invention]

[0004] A resonant power converter includes a plurality of switching elements, a capacitor, and a transformer with a primary winding connected in series with the capacitor. The inventors' investigations have revealed that, when the load of the resonant power converter suddenly changes, for example to a high load, the resonant frequency of the series resonant circuit formed by the capacitor and the primary winding deviates from the frequency at which the plurality of switching elements are turned on and off (off-resonance), causing current to flow through the switching elements, resulting in increased surge voltage and noise. The inventors' investigations will be explained later with reference to the drawings.

[0005] An object of the present invention is to provide a power conversion device and a control method for a power conversion device that can suppress increases in surge voltage and noise when off-resonance occurs.

[0006] Other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] A brief summary of a representative embodiment of the present invention will be given below.

[0008] That is, the power conversion device includes a switching circuit including a plurality of switching elements, a capacitor, and a transformer including a primary winding connected in series with the capacitor, a gate drive circuit that outputs a gate drive current to the gates of the switching elements to control the on / off of the switching elements, a detection circuit that detects the current flowing in the switching circuit, and a determination circuit that determines whether the polarity of the current detected by the detection circuit is reversed.Here, the gate drive circuit includes a gate adjustment circuit that adjusts the gate drive current based on the result of the determination by the determination circuit. [Effects of the Invention]

[0009] To briefly explain the effect obtained by a representative embodiment of the invention disclosed in this application, it is possible to provide a power conversion device that can suppress increases in surge voltage and noise when off-resonance occurs. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a circuit diagram showing a configuration of a power conversion device according to a first embodiment. [Figure 2] 1 is a block diagram showing a configuration of a gate drive circuit according to a first embodiment. [Figure 3] 1 is a circuit diagram showing a configuration of a gate output circuit according to a first embodiment. [Figure 4] 4 is a flowchart illustrating a control method according to the first embodiment. [Figure 5] FIG. 3 is a waveform diagram for explaining the operation of the power conversion device according to the first embodiment. [Figure 6] FIG. 3 is a waveform diagram for explaining the operation of the power conversion device according to the first embodiment. [Figure 7] 1 is a cross-sectional view showing the structure of a GaN-HEMT used in a power conversion device according to a first embodiment. [Figure 8] FIG. 10 is a circuit diagram showing a configuration of a gate output circuit according to a second embodiment. [Figure 9] FIG. 10 is a circuit diagram showing a configuration of a power conversion device according to a third embodiment. [Figure 10] FIG. 10 is a circuit diagram showing a configuration of a power conversion device according to a fourth embodiment. [Figure 11] FIG. 10 is a plan view showing a part of a semiconductor chip according to a fourth embodiment. [Figure 12] FIG. 1 is a circuit diagram of a power conversion device for explaining the study by the present inventors. DETAILED DESCRIPTION OF THE INVENTION

[0011] The following description of the embodiments will be given with reference to the drawings. Note that the embodiments described below do not limit the scope of the invention as claimed, and not all of the elements and combinations thereof described in the embodiments are necessarily essential to the solution of the invention.

[0012] Before describing the embodiments of the present invention, a problem with the power conversion device studied by the present inventors will be described with reference to FIG.

[0013] Fig. 12 is a circuit diagram of a power conversion device for explaining the inventor's study. In the following, the present specification will explain the power conversion device by taking as an example a highly efficient LLC resonant power conversion device that uses a leakage inductor and an excitation inductor of a transformer and a capacitor coupled to the transformer.

[0014] In Fig. 12, reference numeral 100 denotes a power conversion device (hereinafter also referred to as a DC / DC converter). The DC / DC converter 100 includes a gate drive circuit 2 and primary and secondary circuitry, which will be described below. It converts the voltage of a DC power source Vi supplied to the primary circuit and supplies the converted DC voltage to a load 4 connected to the secondary circuit. The primary circuit includes a half-bridge circuit 1 formed by switching elements Q1 and Q2, a resonant capacitor (current resonant capacitor) Cr, and a transformer Tr. The secondary circuit includes a rectifier circuit 3 formed by diodes D1 and D2 and a smoothing capacitor Co.

[0015] The two switching elements Q1 and Q2 that make up the half-bridge circuit 1 are driven by a gate drive circuit 2. That is, the gate drive circuit 2 alternately switches the switching elements Q1 and Q2 at a predetermined cycle while providing a dead time (a time during which both switching elements are in the off state). The value of the voltage output from the secondary side circuit is adjusted by alternately switching the switching elements Q1 and Q2 at the predetermined cycle. In this case, the predetermined cycle for alternately switching the switching elements Q1 and Q2 is the operating cycle of the DC / DC converter 100 (in other words, the operating frequency of the DC / DC converter).

[0016] The LLC resonant DC / DC converter 100 uses a series resonant circuit formed by the resonant capacitor Cr and the leakage inductance (not shown) and magnetizing inductance included in the transformer Tr to perform zero voltage (current) switching, which switches the switching elements Q1 and Q2 on and off when at least one of the voltage and current of the switching elements Q1 and Q2 becomes zero ("0"). By performing zero voltage switching, it is possible to reduce power loss and switching noise when the switching elements are switched.

[0017] However, if the voltage value of the DC power supply Vi on the input side or the load 4 on the output side deviates from the design value, the resonant frequency of the series resonant circuit described above may fluctuate, causing the operating frequency of the DC / DC converter 100 to deviate from the resonant frequency. In this case, zero voltage switching is no longer established, resulting in increased power loss, generation of switching noise, destruction of switching elements, etc. In the following explanation, the deviation of the operating frequency of the DC / DC converter from the resonant frequency of the series resonant circuit is also referred to as "off-resonance."

[0018] Techniques for dealing with fluctuations in the resonant frequency of a series resonant circuit are described in Patent Documents 1 and 2. For example, Patent Document 1 provides a current detection circuit that detects the value of a current flowing through a switching element, and if the detected value of the current detection circuit is greater than zero at the timing of outputting a control signal to turn on the switching element, it is determined that the resonant frequency has fluctuated and an abnormality has occurred. Furthermore, Patent Document 2 detects current values ​​at two or more points within the same resonant period that are symmetrical with respect to a half-period of the resonant period as the midpoint, and if the current values ​​differ by more than a predetermined value, it is determined that the resonant frequency has fluctuated and an abnormality has occurred.

[0019] The technologies described in Patent Documents 1 and 2 detect the occurrence of an abnormality, and when an abnormality is detected, it is possible to avoid off-resonance by, for example, forcibly turning off a switching element and increasing the operating frequency of the DC / DC converter.

[0020] However, in this case, the switching element must be forcibly turned off continuously during the period when the resonance is off, i.e., the period when the voltage of the DC power supply Vi and the load 4 on the output side remain high, and during this period the DC / DC converter cannot perform appropriate power conversion.

[0021] Unless a configuration that forcibly turns off the switching elements is adopted to avoid out-of-resonance, power loss increases. That is, when out-of-resonance occurs in a DC / DC converter, the current flowing through one of the switching elements (e.g., Q1) that is on reverses from positive to negative, and after this reversal, the switching element (Q1) turns off, causing the switching element (Q1) to enter a reverse conduction state. When the other switching element (Q2) is turned on after the dead time has elapsed, a recovery current flows through the switching elements Q1 and Q2, resulting in large power loss and possibly damaging the switching elements.

[0022] By using a switching element with a small recovery current during reverse conduction, it is possible to suppress an increase in power loss when off-resonance occurs and prevent breakdown of the switching element. Examples of switching elements with a small recovery current during reverse conduction include fast recovery metal-oxide-semiconductor field effect transistors (MOSFETs) and high electron mobility transistors (HEMTs) using gallium nitride (GaN)-based materials. Hereinafter, HEMTs using GaN-based materials will be referred to as GaN-HEMTs.

[0023] In particular, GaN-HEMTs do not include a body diode inside the device, so in principle the recovery current is zero. Therefore, in a DC / DC converter that uses GaN-HEMTs as switching elements, even if off-resonance occurs, no loss due to recovery current occurs and the risk of breakdown of the switching element can be reduced, making it possible to operate the DC / DC converter even when the voltage value of the DC power supply Vi or the load on the output side is high.

[0024] Using a GaN-HEMT as a switching element can eliminate the aforementioned effects of the body diode, but because GaN-HEMTs also have output capacitance like MOSFETs, there is still an effect from the GaN-HEMT's output capacitance. That is, when an out-of-resonance condition occurs and one of the switching elements (e.g., Q1) enters a reverse conduction state, the output capacitance of the switching element (Q1) is discharged, and when the other switching element (Q2) is turned on, the output capacitance of the switching element (Q1) is recharged. At this time, a current flows through the switching elements (Q2) and (Q1) to recharge the output capacitance.

[0025] GaN-HEMTs have a small output capacitance, and the amount of stored charge is small compared to the recovery current, so there is little risk of increased power loss or damage to the switching element. However, because power conversion devices that use GaN-HEMTs as switching elements often operate at high frequencies, the amount of change in current over time due to the recharging of the output capacitance (dI / dt: I is the current that flows through the output capacitance during recharging) becomes large. This large amount of change in current over time (dI / dr) can cause surge voltages and increased noise, interfering with the normal operation of power conversion equipment.

[0026] Patent Documents 1 and 2 do not mention or recognize the surge voltage or increase in noise caused by the time change in the current that recharges the output capacitance of the switching element when off-resonance occurs.

[0027] In order to solve the above-mentioned problems, the present inventors have conducted extensive research and have come up with the configuration of the present embodiment. Hereinafter, the present embodiment will be described with reference to the drawings.

[0028] (Embodiment 1) <Overall configuration of power conversion device> Fig. 1 is a circuit diagram showing the configuration of a power conversion device according to embodiment 1. In Fig. 1, reference numeral 101 indicates the power conversion device. The power conversion device 101 is a DC / DC converter of LLC resonant type, including a half-bridge circuit 1 using two switching elements.

[0029] The power conversion device 101 includes a half-bridge circuit 1, a gate drive circuit 2, a current detection circuit (hereinafter also referred to as a detection circuit) 5, a current polarity reversal determination circuit (hereinafter also referred to as a determination circuit) 6, a resonance capacitor Cr, a transformer Tr formed by a primary winding Tr1 and secondary windings Tr2-1 and Tr2-2, and a rectifier circuit 3 formed by diodes D1 and D2 and a smoothing capacitor Co. In FIG. 1, T1 and T2 indicate input terminals of the power conversion device 101, and T3 and T4 indicate output terminals of the power conversion device 101. As shown in FIG. 1, an external DC power supply Vi is connected to the input terminals T1 and T2 of the power conversion device 101, and a load 4 is connected to the output terminals T3 and T4. The DC power supply Vi is, for example, a battery, an AC / DC (alternating current / direct current) converter, etc.

[0030] As shown in Fig. 1, the half-bridge circuit 1 is connected between both terminals of a DC power supply Vi. The half-bridge circuit 1 includes switching elements Q1 and Q2 connected in series between both terminals of the DC power supply Vi (between input terminals T1 and T2). Although not particularly limited, the switching elements Q1 and Q2 are configured by GaN-HEMTs formed on the silicon substrate of a single semiconductor chip (the same semiconductor chip).

[0031] In FIG. 1, Cp1 and Cp2 indicated by dashed lines represent the parasitic capacitors of the switching elements Q1 and Q2. One terminal of the parasitic capacitor Cp1 is connected to the source terminal of the switching element Q1, and the other terminal is connected to the drain terminal of the switching element Q1. This parasitic capacitor Cp1 corresponds to the output capacitance of the switching element Q1. Similarly, the parasitic capacitor Cp2 is connected between the source terminal and drain terminal of the switching element Q2, and corresponds to the output capacitance of the switching element Q2. Hereinafter, the parasitic capacitors Cp1 and Cp2 are also referred to as output capacitances Cp1 and Cp2.

[0032] In the half-bridge circuit 1, the drain terminal of the switching element Q1 is connected to the DC power supply Vi via the input terminal T1. The source terminal of the switching element Q1 is connected to the drain terminal of the switching element Q2. The source terminal of the switching element Q2 is connected to the DC power supply Vi via the input terminal T2. The gate terminals of the switching elements Q1 and Q2 are connected to the gate drive circuit 2. A detection circuit 5, a resonant capacitor Cr, and a primary winding Tr1 of a transformer Tr are connected in series between the node where the source terminal of the switching element Q1 and the drain terminal of the switching element Q2 are connected and the source terminal of the switching element Q2. The secondary side of the transformer Tr is composed of secondary windings Tr2-1 and Tr2-2. Although not particularly limited, the secondary windings Tr2-1 and Tr2-2 have the same number of turns and are connected in series so that they are wound in the same direction. Note that the black circles in Figure 1 indicate the polarity of the transformer Tr.

[0033] The rectifier circuit 3 is composed of diodes D1 and D2 and a smoothing capacitor Co, and the cathode terminals of the diodes D1 and D2 are connected to one terminal of the smoothing capacitor Co. The other terminal of the smoothing capacitor Co is connected to the node where one terminal of the secondary windings Tr2-1 and Tr2-2 of the transformer Tr is connected to each other. The other terminals of the secondary windings Tr1 and Tr2-2 of the transformer Tr are connected to the anode terminals of the diodes D1 and D2, respectively. The terminals of the smoothing capacitor Co are connected to the load 4 via output terminals T3 and T4.

[0034] The detection circuit 5 is configured with a current sensor. The current sensor is configured with, for example, a shunt resistor, a Hall element, or a Rogowski coil. The detection circuit 5 detects the current value of a current I1 flowing through a resonant switching circuit RSC (hereinafter simply referred to as a switching circuit) that includes switching elements Q1 and Q2, a resonant capacitor Cr, and a primary winding Tr1 of a transformer Tr. The current value detected by the detection circuit 5 is output as an analog value to the determination circuit 6. In the first embodiment, the detection circuit 5 is also provided in the resonant switching circuit RSC to detect the current value of the current I1.

[0035] The judgment circuit 6 is not particularly limited and is composed of a comparator and an edge detector (not shown). The comparator is composed of, for example, a comparator, and the edge detector is composed of, for example, an edge detection circuit formed by combining logic circuits or an edge detector using a microprocessor. The comparator receives an input (analog current value) from the detection circuit 5 and a reference value corresponding to a current value of "0 (zero)." The comparator compares the analog current value with the reference value and outputs the comparison result as a digital value to the edge detector. The edge detector detects changes in the input digital value as rising and falling edges of a signal and outputs a judgment signal indicating the polarity (current polarity) of the current I1 of the resonant switching circuit flowing through the detection circuit 5 to the gate drive circuit 2.

[0036] For example, if the analog current value from the detection circuit 5 drops from a high current value to below the reference value, the comparator in the decision circuit 6 changes the digital value from "1" to "0." The edge detector in the decision circuit 6 recognizes the change from the digital value "1" to "0" as a falling edge of the signal and outputs a decision signal indicating that the polarity of the current I1 in the resonant switching circuit RSC has reversed from positive to negative. In contrast, if the analog current value from the detection circuit 5 changes from a value lower than the reference value to above the reference value, the comparator in the decision circuit 6 changes the digital value from "0" to "1." The edge detector in the decision circuit 6 recognizes the change from the digital value "0" to "1" as a rising edge of the signal and outputs a decision signal indicating that the polarity of the current I1 in the resonant switching circuit RSC has reversed from negative to positive.

[0037] A Schmitt trigger or a low-pass filter may be provided on the input side of the comparator in the decision circuit 6. Noise contained in the output from the detection circuit 5 can be removed by this Schmitt trigger or low-pass filter.

[0038] The gate drive circuit 2 drives the switching elements Q1 and Q2 to alternately turn on and off in an operating cycle determined by the operating frequency of the power conversion device 101. When driving the switching elements Q1 and Q2, the gate drive circuit 2 adjusts the drive capacity based on a determination signal from a determination circuit 6. The gate drive circuit 2 will be described in detail below with reference to the drawings.

[0039] <<Gate drive circuit configuration>> Fig. 2 is a block diagram showing the configuration of the gate drive circuit according to embodiment 1. As shown in Fig. 2, the gate drive circuit 2 includes a control circuit 21 and two gate output circuits 22 corresponding to the switching elements Q1 and Q2.

[0040] The control circuit 21 is configured with, for example, a microprocessor or a programmable gate array (e.g., a so-called FPGA), and generates gate signals required to alternately turn on and off the switching elements Q1 and Q2 at the operating frequency of the power conversion device 101. The control circuit 21 also receives, via input terminals T21 and T22, the determination signals (current inversion positive / negative and current inversion negative / positive) output from the determination circuit 6, and generates output switching signals for switching the gate drive currents of the switching elements Q1 and Q2. The gate drive currents of the switching elements Q1 and Q2 are adjusted by switching the gate drive currents, and therefore the control circuit 21 that generates the output switching signals can be considered a gate adjustment circuit.

[0041] A gate output circuit 22 is provided for each of the switching elements Q1 and Q2, and outputs a gate output signal corresponding to the gate signal and output switching signal input from the control circuit 21. The gate output signal output from the gate output circuit 22 is supplied to the gate terminals of the switching elements Q1 and Q2 via output terminals T23 and T24. In Fig. 2, reference numeral 22-1 denotes a gate output circuit that supplies gate output signal 1 to the gate terminal of the switching element Q1, and reference numeral 22-2 denotes a gate output circuit that supplies gate output signal 2 to the gate terminal of the switching element Q2.

[0042] <<<Gate output circuit configuration>>> Next, the configuration of the gate output circuit will be described with reference to the drawings. The gate output circuit 22-1 corresponding to the switching element Q1 and the gate output circuit 22-2 corresponding to the switching element Q2 have similar configurations, and therefore will be described below as gate output circuit 22.

[0043] FIG. 3 is a circuit diagram showing a configuration of the gate output circuit according to the first embodiment.

[0044] The gate output circuit 22 includes P-channel field-effect (hereinafter also referred to as PMOS) transistors PTr1 and PTr2, an N-channel field-effect (hereinafter also referred to as NMOS) transistor NTr, resistance elements Rgon1, Rgon2, and Rgoff, inverter gates inv1 and inv2, and OR gates or1 and or2. Here, the electrical resistance value of the resistance element Rgon2 is set larger than the electrical resistance value of the resistance element Rgon1.

[0045] The source terminals of the PMOS transistors PTr1 and PTr2 are connected to a voltage line Vgon. The voltage (Vg,on) applied to the voltage line Vgon is a predetermined voltage applied to the gate terminals of the switching elements Q1 and Q2 to turn them on. The source terminal of the NMOS transistor NTr is connected to a voltage line Vgoff. The voltage (Vg,off) applied to the voltage line Vgoff is a voltage applied to the gate terminals of the switching elements Q1 and Q2 to turn them off. The voltages (Vg,on) and (Vg,off) are generated by the DC power supply Vi shown in FIG. 1, although there are no particular limitations on these voltages.

[0046] The drain terminals of the PMOS transistors PTr1 and PTr2 are connected to one terminal of the resistor elements Rgon1 and Rgon2, respectively, and the other terminals of the resistor elements Rgon1 and Rgon2 are connected to the output terminal T223. The drain terminal of the NMOS transistor NTr is connected to one terminal of the resistor element Rgoff, and the other terminal of the resistor element Rgoff is connected to the output terminal T223.

[0047] The gate signal output from the control circuit 21 is supplied to the input of the inverter gate inv2 via the input terminal T222. The output of the inverter gate inv2 is connected to one input of the OR gates or1 and or2 and also to the gate terminal of the NMOS transistor NTr. The output switching signal output from the control circuit 21 is connected to the other input of the OR gate or1 via the input terminal T221 and also to the other input of the OR gate or2 via the inverter gate inv1. The outputs of the OR gates or1 and or2 are connected to the gate terminals of the PMOS transistors PTr1 and PTr2, respectively.

[0048] Therefore, while the gate signal is at a low level ("0"), the PMOS transistors PTr1 and PTr2 are turned off. Meanwhile, during this period, the NMOS transistor NTr is turned on. In this case, the resistive element Rgoff is connected between the voltage line Vgoff and the gate terminal of the switching element Q1 or Q2 via the NMOS transistor NTr and the output terminal T223. That is, the resistive element Rgoff corresponds to the gate resistance of the switching element, and the voltage (Vg,off) via the gate resistance (resistive element Rgoff) is applied to the switching element Q1 or Q2 as a gate-off voltage, turning the switching element Q1 or Q2 off.

[0049] On the other hand, when the gate signal is at a high level ("1"), the NMOS transistor NTr is turned off. During this period, when the output switching signal is at a low level ("0"), the PMOS transistor PTr1 is turned on, and when the output switching signal is at a high level ("1"), the PMOS transistor PTr2 is turned on. Therefore, when the gate signal is at a high level, if the output switching signal is at a low level, the resistive element Rgon1 corresponds to the gate resistance of the switching element, and a voltage (Vg,on) via the gate resistor (resistive element Rgon1) is applied to the switching element Q1 or Q2 as a gate-on voltage, turning the switching element Q1 or Q2 on. At this time, in the switching element Q1 or Q2 that is in the on state, a drain current corresponding to the current (high-level gate drive current) of the gate output signal supplied to the gate terminal of the switching element Q1 or Q2 flows via the gate resistor (resistive element Rgon1).

[0050] Also, when the output switching signal is high level ("1") during the period when the gate signal is high level ("1"), the resistance element Rgon2 corresponds to the gate resistance of the switching element, and the voltage (Vg,on) via the gate resistance (resistance element Rgon2) is applied to the switching element Q1 or Q2 as a gate-on voltage. In this case, the switching element Q1 or Q2 is also in the on state. However, at this time, the current (gate drive current) of the gate output signal supplied to the gate terminal of the switching element Q1 or Q2 becomes the current (low-level gate drive current) of the gate output signal determined by the resistance element Rgon2, because the resistance element Rgon2 functions as a gate resistance. Therefore, at this time, in the switching element Q1 or Q2 that is in the on state, a drain current corresponding to the gate drive current determined by the resistance element Rgon2 will flow.

[0051] In the gate output circuit 22 according to the first embodiment, the gate resistances of the switching elements Q1 and Q2 that are turned on can be switched by an output switching signal. By switching the gate resistances, a gate drive current determined by the switched gate resistance is supplied to the gate terminals of the switching elements Q1 and Q2. A drain current corresponding to the gate drive current flows through the switching elements that are turned on. That is, a gate drive current of a level corresponding to the resistance element Rgon1 or Rgon2, which corresponds to the gate resistance, is supplied to the gate terminals of the switching elements, and a drain current corresponding to the gate drive current is output from the switching elements. As described above, since the electrical resistance of the resistance element Rgon2 is greater than the electrical resistance of the resistance element Rgon1, when the output switching signal is high, the gate output circuit 22 outputs a low-level gate drive current to the gate terminals of the switching elements Q1 and Q2, thereby switching the drain current of the switching elements Q1 and Q2 to a low level.

[0052] When the gate signal is at a high level, the inverter gate inv1, OR gates or1 and or2, and PMOS transistors PTr1 and PTr2 can be considered to constitute a switching circuit that selects a resistor element from resistor elements Rgon1 and Rgon2 according to the output signal. In this case, the selected resistor element is connected between a predetermined voltage (Vg,on) and the gate terminal of the switching element.

[0053] <Power conversion device operation> First, a control method executed in the power conversion device according to the first embodiment will be described with reference to the drawings. Fig. 4 is a flowchart for explaining the control method according to the first embodiment.

[0054] In step S1, the control circuit 21 shown in Fig. 2 outputs gate output signal 1 and gate output signal 2 to turn on and off the switching elements Q1 and Q2 shown in Fig. 1. Next, steps S2, S3, and S4 are executed in sequence, and these steps S2 to S4 are performed during the period in which the switching element Q1 or Q2 is in the on state.

[0055] Step S2 is a current detection step in which the detection circuit 5 of FIG. 1 detects the current I1 flowing through the resonant switching circuit RSC.

[0056] In step S3, the determination circuit 6 determines the polarity of the current I1 based on the current I1 detected in step S2, and supplies the determination result as a determination signal to the control circuit 21. That is, step S3 is a polarity determination step.

[0057] If it is determined in step S3 that the polarity is reversed (Y), the control circuit 21 generates an output switching signal and switches the gate drive current of the switching element. Since the gate drive current is adjusted by switching this gate drive current, step S4 is a drive current adjustment step.

[0058] If it is determined in step S3 that the polarity has not been inverted (N) and step S4 is completed, step S1 is executed again, that is, steps S1 to S3 are repeated.

[0059] In the power conversion device according to the first embodiment, if it is determined in step S3 that the polarity is reversed, processing is performed assuming that off-resonance has occurred. On the other hand, if it is determined in step S3 that the polarity is not reversed, processing is performed assuming that off-resonance has not occurred.

[0060] Although not particularly limited, step S4 (adjustment step) according to the first embodiment includes two steps: a step of adjusting (switching) the gate drive current to a low level when it is determined that the polarity is reversed, and a step of adjusting (switching) the gate drive current to a higher level than the low level after a predetermined period (output switching period) has elapsed since the gate drive current was switched to the low level.

[0061] Next, the cases where off-resonance does not occur and where it does occur will be described.

[0062] <<When resonance is not occurring>> First, a case will be described in which the load on the power conversion device 101 is not high and no off-resonance state occurs. Fig. 5 is a waveform diagram for explaining the operation of the power conversion device according to embodiment 1. The following description will be given with reference to Figs. 1 to 3 and 5.

[0063] 5 shows the waveforms of gate output signal 1 and gate output signal 2 output by gate drive circuit 2 to control half-bridge circuit 1, and the waveform of current I1 flowing through resonant switching circuit RSC including primary winding Tr1 of transformer Tr, detected by detection circuit 5. Furthermore, Fig. 5 shows the waveforms of voltages Vds1 and Vds2 applied between the drain and source terminals of switching elements Q1 and Q2, and the waveforms of currents Id1 and Id2 flowing from the drain terminals to the source terminals of switching elements Q1 and Q2 (drain currents). Voltage Vds1 and current Id1 are the voltage and current of switching element Q1, and voltage Vds2 and current Id2 are the voltage and current of switching element Q2.

[0064] The detection circuit 5 detects current with positive (+) polarity flowing from left to right, as indicated by the arrow in FIG. 1. Gate output signal 1 output from gate drive circuit 2 controls the on / off state of switching element Q1, and gate output signal 2 controls the on / off state of switching element Q2. A control circuit 21 constituting gate drive circuit 2 generates gate signals to complementarily drive switching elements Q1 and Q2, including dead times td1 and td2. Note that dead times td1 and td2 are periods during which both switching elements Q1 and Q2 are in the off state.

[0065] First, at time t1, when the gate output signal turns on the switching element Q1 while the switching element Q2 is in the off state, a positive (+) current I1 flows through the resonant switching circuit RSC, which includes the DC power supply Vi, the switching element Q1, the detection circuit 5, the resonant capacitor Cr, and the primary winding Tr1 of the transformer Tr.

[0066] At time t2, when switching element Q1 is turned off and dead time td1 begins, switching element Q2 enters reverse conduction, and the current flowing through transformer Tr's primary winding Tr1 is commutated to switching element Q2. Switching element Q2 is then turned on in reverse conduction, performing so-called zero-voltage switching, in which switching is performed while the voltage applied between the source and drain terminals of switching element Q2 is nearly zero. Then, due to LC resonance caused by the inductance included in transformer Tr and the capacitance of resonant capacitor Cr, the polarity of current I1 flowing through resonant switching circuit RSC, which includes transformer Tr's primary winding Tr1, reverses from positive (+) to negative (-).

[0067] Next, at time t3, when switching element Q2 is turned off and dead time td2 begins, switching element Q1 becomes reverse conductive and the current flowing in the primary winding Tr1 of the transformer Tr is commutated to switching element Q1, and then switching element Q1 is turned on in the reverse conductive state to perform zero voltage switching, and then LC resonance causes the current I1 flowing in the resonant switching circuit RSC, which includes the primary winding Tr1 of the transformer Tr, to reverse from negative (-) to positive (+).

[0068] The gate output signal is generated periodically at a cycle determined by the operating frequency of the power conversion device 101, and the operation from time t1 to time t3 is repeated. In response to a change in the current I1 flowing through the primary winding Tr1 of the transformer Tr, a current is generated in the secondary winding Tr2-1 or Tr2-2, which is converted to a direct current by the rectifier circuit 3 and supplied to the load 4.

[0069] <<When resonance is off>> Fig. 6 is a waveform diagram for explaining the operation of the power conversion device according to embodiment 1. Fig. 6 is similar to Fig. 5, and like Fig. 5, Fig. 6 also shows gate output signal 1 and gate output signal 2, current I1 flowing through resonant switching circuit RSC, voltages Vds1 and Vds2 between the drain terminal and source terminal of switching elements Q1 and Q2, and drain currents Id1 and Id2 of switching elements Q1 and Q2. Fig. 6 differs from Fig. 5 in that Fig. 6 illustrates a case where load 4 suddenly changes to a high load during the period in which power conversion device 101 is operating, causing off-resonance.

[0070] Under heavy load conditions, during the period (times t1 to t2) when switching element Q1 is in the on state, at a certain time (e.g., time t12), due to LC resonance caused by the inductance included in transformer Tr and the capacitance of resonant capacitor Cr, the polarity of the current flowing through resonant switching circuit RSC, including primary winding Tr1 of transformer Tr, reverses from positive to negative, as shown in Figure 6, causing switching element Q1 to enter a reverse conduction state. After that, when switching element Q1 is turned off and dead time td1 begins, switching element Q2 is off, so no current flows, and switching element Q1 continues to conduct current, remaining in a reverse conduction state. At this time, the output capacitance Cp1 (Figure 1) of switching element Q1 enters a discharged state.

[0071] At a later time t2, when switching element Q2 is changed (transitioned) to the on state, the current flowing through switching element Q1 is commutated to switching element Q2, at which time the output capacitance Cp1 of switching element Q1 is recharged. Because output capacitance Cp1 is a capacitor connected between the source terminal and drain terminal of switching element Q1, during the recharge period in which output capacitance Cp1 is being recharged, current (current for recharging output capacitance Cp1) flows between the drain terminal and source terminal of switching element Q1. At this time, switching element Q2 transitions to the on state, causing a through current to flow through switching elements Q1 and Q2.

[0072] Since this through current is a current that flows through the switching elements Q1 and Q2, the change in the current value of the through current over time is determined by the speed at which the switching element Q2 is transitioned to the ON state.

[0073] Next, the operation of turning on switching element Q1 after the dead time td2 has elapsed after switching element Q2 off is complementary to the above. That is, at time t23 before switching element Q2 transitions to the off state, the polarity of current I1 flowing through resonant switching circuit RSC, including primary winding Tr1 of transformer Tr, reverses from negative to positive due to the LC resonance. In this case, switching element Q2 enters a reverse conduction state, discharging output capacitance Cp2 of switching element Q2. When switching element Q1 transitions to the on state, output capacitance Cp2 is recharged. Therefore, when switching element Q1 transitions to the on state, a through current flows through switching elements Q1 and Q2. The time change in the value of this through current is also determined by the speed at which switching element Q1 transitions to the on state.

[0074] In the first embodiment, the control circuit 21 constituting the gate drive circuit 2 executes steps S2 to S4 shown in FIG. 4 during the ON period of the switching element Q1. That is, when the control circuit 21 receives a determination signal from the determination circuit 6 indicating that the polarity of the current I1 has reversed (in this case, from positive to negative), the control circuit 21 outputs an output switching signal to the gate output circuit 22-2 connected to the switching element Q2 to be transitioned to the ON state. When the output switching signal is received, the gate output circuit 22-2 switches the gate resistance used when driving the switching element Q2 to the ON state from the resistance element Rgon1 to the resistance element Rgon2, thereby increasing the value of the gate resistance. As a result, the gate drive current for the switching element Q2 decreases, and the drain current of the switching element Q2 also decreases, and the drive current of the switching element Q2 is adjusted to decrease.

[0075] This adjustment reduces the drain current, thereby slowing down the speed at which switching element Q2 transitions to the ON state. Therefore, even if the load 4 becomes heavy while switching element Q1 is in the ON state, the amount of change over time in the through current that occurs when switching element Q2 transitions to the ON state is reduced, making it possible to suppress surge voltages and noise.

[0076] 4 during the ON period of switching element Q2. That is, when a determination signal indicating a reversal of the polarity of current I1 (in this case, a reversal from negative to positive) is input to control circuit 21, control circuit 21 outputs an output switching signal to gate output circuit 22-1 connected to switching element Q1. When gate output circuit 22-1 inputs the output switching signal, it switches the gate resistance used when driving switching element Q1 to the ON state from resistance element Rgon1 to resistance element Rgon2, thereby increasing the value of the gate resistance. As a result, the gate drive current for switching element Q1 decreases, and the drain current of switching element Q1 also decreases, and the drive current of switching element Q1 is adjusted to decrease.

[0077] The adjustment reduces the drain current, slowing down the rate at which switching element Q1 transitions to the ON state. Therefore, even if load 4 becomes heavy while switching element Q2 is in the ON state, the amount of change over time in the through current that occurs when switching element Q1 transitions to the ON state is reduced, making it possible to suppress surge voltages and noise.

[0078] 6, the drain current change Id_1 indicated by the dashed line represents the change in drain current when the resistive element Rgon1 is used as the gate resistor without switching the resistive element, and the drain current change Id_2 indicated by the solid line represents the change in drain current when the gate resistor is switched to the resistive element Rgon2 according to the first embodiment. Furthermore, the voltage change Vsg_1 indicated by the dashed line represents the change in voltages Vds1 and Vds2 when the resistive element Rgon1 is used as the gate resistor without switching the resistive element, and the voltage change Vsg_2 indicated by the solid line represents the change in voltages Vds1 and Vds2 when the gate resistor is switched to the resistive element Rgon2 according to the first embodiment. These voltage changes Vsg_1 and Vsg_2 become surge voltages and noise.

[0079] According to the first embodiment, the time during which the drain current change occurs becomes longer, but the peak value can be reduced. As a result, as shown in FIG. 6, the voltage change Vsg_2 becomes smaller than the voltage change Vsg_1, and the surge voltage and noise that occur can be suppressed.

[0080] In the control circuit 21 according to the first embodiment, a period (output switching period) during which an output switching signal is output to the gate output circuits 22 (22-1, 22-2) is set in advance. During this set output switching period, the gate output circuit 22 uses the resistive element Rgon as a gate resistor and outputs a low gate drive current. In the first embodiment, the output switching period is set to be longer than the time from when the polarity reversal of the current I1 is determined to when the switching elements Q1 and Q2 are turned on and off, and shorter than half the period (half period) during which the switching elements Q1 and Q2 are turned on and off.

[0081] 6 as an example, the output switching period is set to be longer than the time from time t12 to time t2 and shorter than the time from time t1 to time t2. By setting the output switching period, in the period in which a high load on load 4 is detected as a polarity reversal of current I1, the gate drive current output from the output circuit is suppressed to a low value (low level) when the switching element is transitioned to the on state, and next time when the switching element is turned on or off, the resistive element Rgon1 is used as the gate resistor to raise the gate drive current to a high level, enabling high-speed switching.

[0082] <<Switching element structure>> In the first embodiment, as described above, GaN-HEMTs are used as switching elements Q1 and Q2. An example of a GaN-HEMT will now be described. Fig. 7 is a cross-sectional view showing the structure of a GaN-HEMT used in the power conversion device according to the first embodiment.

[0083] 7, 500 denotes a GaN-HEMT. The GaN-HEMT includes a substrate 501, a buffer layer 502 formed on the substrate 501, a gallium nitride (GaN) layer 503 formed on the buffer layer 502, an aluminum gallium nitride (AlGaN) layer 504 formed on the gallium nitride layer 503, a gate electrode 507 formed at a predetermined position on the aluminum gallium nitride layer 504 via a p-type gallium nitride (P-GaN) layer 505, and a source electrode 506 and a drain electrode 508 formed on the aluminum gallium nitride layer 504 at positions separated from the gate electrode 507.

[0084] The gate electrode 507 corresponds to the gate terminals of the switching elements Q1 and Q2, and the source electrode 506 and drain electrode 508 correspond to the source terminals and drain terminals of the switching elements Q1 and Q2. The output capacitance (Cp1) of a switching element (e.g., Q1) is a parasitic capacitor with the source electrode 506 as one terminal and the drain electrode 508 as the other terminal. That is, the output capacitance (Cp1) is connected between the source terminal and drain terminal of the switching element (Q1).

[0085] 7, a GaN-HEMT does not form a body diode, so it is possible to prevent loss due to recovery current flowing through the body diode. Therefore, according to the first embodiment, even if the load 4 becomes high and off-resonance occurs, loss due to recovery current does not occur, so it is possible to reduce the possibility of the element (GaN-HEMT) being destroyed.

[0086] According to the first embodiment, even if the load 4 is in a high load state and off-resonance occurs, it is possible to suppress the time change dI / dt of the current flowing through the switching elements Q1 and Q2 constituting the half-bridge circuit 1, thereby suppressing increases in surge voltage and noise, thereby enabling stable operation of the power conversion device 101.

[0087] In the first embodiment, a configuration has been described in which a field-effect transistor is used as the gate output circuit 22 as shown in FIG. 3, but a GaN-HEMT may be used instead of the field-effect transistor, similar to the switching element.

[0088] Furthermore, the GaN-HEMTs that constitute the switching elements Q1 and Q2 and the detection circuit 5 may be formed on the semiconductor substrate of the same semiconductor chip.

[0089] (Embodiment 2) In the second embodiment, the gate output circuit 22 shown in Fig. 2 is modified. Fig. 8 is a circuit diagram showing the configuration of the gate output circuit according to the second embodiment. The power conversion device according to the second embodiment differs from the power conversion device according to the first embodiment in that the configuration of the gate output circuit is changed from that shown in Fig. 3 to that shown in Fig. 8. Therefore, hereinafter, only the gate output circuit will be described unless otherwise necessary for the explanation.

[0090] The gate output circuit according to the second embodiment differs from that of the first embodiment in that a current mirror circuit is used to switch the gate drive current.

[0091] 8, 22a denotes a gate output circuit, which includes a PMOS transistor PTr1, a current mirror circuit CM configured by PMOS transistors PTr-CM1 and PTr-CM2, a voltage generating circuit Vref that outputs a voltage value according to an input, an operational amplifier OPref, NMOS transistors NTr and NTr-ref, resistors Rref and Rgoff, and an inverter gate inv.

[0092] The source terminals of the PMOS transistors PTr-CM1 and PTr-CM2 that make up the current mirror circuit CM are connected to a voltage line Vgon. The voltage applied to the voltage line Vgon is the voltage applied to the gate terminals of the switching elements Q1 and Q2 (Figure 1) to turn them on. The gate terminals of the PMOS transistors PTr-CM1 and PTr-CM2 are connected to each other and to the drain terminal of the PMOS transistor PTr-CM1. The drain terminal of the PMOS transistor PTr-CM1 is connected to the drain terminal of the PMOS transistor NTr-ref. The drain terminal of the PMOS transistor PTr-CM2 is connected to the output terminal T223.

[0093] The source terminal of the PMOS transistor PTr1 is connected to the voltage line Vgon, and its drain terminal is connected to the drain terminal of the NMOS transistor NTr-ref. The source terminal of the NMOS transistor NTr is connected to the voltage line Vgoff. The voltage applied to the voltage line Vgoff is the voltage applied to the gate terminals of the switching elements Q1 and Q2 to turn them off. The drain terminal of the NMOS transistor NTr is connected to one terminal of the resistor Rgoff, and the other terminal of the resistor Rgoff is connected to the output terminal T223.

[0094] The output of the voltage generator circuit Vref is connected to the non-inverting input terminal (+) of the operational amplifier OPref. The inverting input terminal (-) of the operational amplifier OPref is connected to the source terminal of the NMOS transistor NTr-ref, and its output terminal is connected to the gate terminal of the NMOS transistor NTr-ref. In addition, the source terminal of the NMOS transistor NTr-ref is connected to one terminal of the resistor element Rref, and the other terminal of the resistor element Rref is connected to the voltage line Vgoff. Therefore, the current flowing from the drain terminal to the source terminal of the NMOS transistor NTr-ref is equal to the ratio of the output voltage of the voltage generator circuit Vref to the resistance value of the resistor element Rref (output voltage / Rref). Because the resistance value of the resistor element Rref is fixed, the current flowing from the drain terminal to the source terminal of the NMOS transistor NTr-ref is proportional to the output voltage of the voltage generator circuit Vref.

[0095] The gate signal output from the control circuit 21 (FIG. 2) is supplied to the gate terminal of the PMOS transistor PTr1 via the input terminal T222, and also to the input of the inverter gate inv. The output of the inverter gate inv is connected to the gate terminal of the NMOS transistor NTr. The output switching signal output from the control circuit 21 is supplied as an input to the voltage generation circuit Vref via the input terminal T221. Because the output switching signal is supplied as an input, the voltage generation circuit Vref operates so as to output a lower voltage when the output switching signal is high level (“1”) compared to when the output switching signal is low level (“0”).

[0096] When the gate signal output from the control circuit 21 (Figure 2) is low level ("0"), the PMOS transistor PTr1 is on, and the voltage between the drain and source terminals of the PMOS transistor PTr-CM1 is almost zero. Because the drain and gate terminals of the PMOS transistor PTr-CM1 are connected, the PMOS transistor PTr-CM1 is off, and no current flows between the source and drain terminals of the PMOS transistor PTr-CM2 that makes up the current mirror circuit CM. At this time, the output of the inverter gate inv is high level ("1"), and the NMOS transistor NTr is on. Therefore, the resistor Rgoff functions as a gate resistor, and a gate-off voltage that turns off the switching element Q1 or Q2 is output.

[0097] On the other hand, while the gate signal output from the control circuit 21 is at a high level ("1"), the output of the inverter gate inv is at a low level ("0"), so that the NMOS transistor NTr is turned off. At this time, the high-level gate signal turns the PMOS transistor PTr off, so that the current mirror circuit CM operates, and a current proportional to the current flowing from the source terminal to the drain terminal of the PMOS transistor PTr-CM1 flows from the source terminal to the drain terminal of the PMOS transistor PTr-CM2. Because the PMOS transistor PTr-CM1 and the NMOS transistor NTr-ref are connected in series, the current flowing from the source terminal to the drain terminal of the PMOS transistor PTr-CM1 is equal to the current flowing from the drain terminal to the source terminal of the NMOS transistor NTr-ref. Therefore, a current proportional to the output voltage of the voltage generation circuit Vref is output to the gate terminal of the switching element Q1 or Q2 via the output terminal T223. When the output switching signal is at a high level ("1"), the output voltage of the voltage generating circuit Vref is lower than when the output switching signal is at a low level ("0"), and therefore the output of the gate driving current output from the gate driving circuit 2 (Figure 2) equipped with the gate output circuit 22a according to embodiment 2 is switched to a low level.

[0098] 8, the voltage generating circuit Vref, the operational amplifier OPref, the NMOS transistor NTr-ref, and the resistor element Rref can be regarded as configuring a current circuit that outputs a current according to the level of the output switching signal supplied to the input terminal T221. In this case, a current proportional to the current output from the current circuit is output from the current mirror circuit CM to the gate terminal of the switching element Q1 or Q2 as a gate drive current.

[0099] According to the second embodiment, the level of the gate drive current output from the gate output circuit 22a can be switched in response to an output switching signal. As in the first embodiment, when an off-resonance state occurs in the power conversion device, the control circuit 21 of the gate drive circuit 2 generates an output switching signal in response to the output of the determination circuit 6 (FIG. 1), thereby suppressing the amount of change over time in the through current and making it possible to suppress the occurrence of surge voltages and noise. Furthermore, according to the second embodiment, there is no longer a need for resistance elements corresponding to the resistance elements Rgon1 and Rgon2 shown in FIG. 3, and it is possible to reduce the occurrence of power loss in these resistance elements.

[0100] Furthermore, when the number of levels of the gate drive current output from the gate output circuit is increased beyond two, the gate output circuit 22 shown in FIG. 3 needs to increase the number of PMOS transistors (corresponding to PTr1 and PTr2 in FIG. 3 ) that drive the output when the gate is on, resistive elements (corresponding to Rgon1 and Rgon2), and OR gates (corresponding to or1 and or2) that control the gates of the PMOS transistors, depending on the number of levels of the gate drive current. In contrast, according to the second embodiment, it is only necessary to set the output voltage of the voltage generating circuit Vref to multiple levels (three or more levels), thereby enabling a simple configuration. Furthermore, it is possible to quickly switch the output of the gate drive current in response to an output switching signal, thereby enabling the power conversion device to operate at a high operating frequency. Note that, even in the second embodiment, the transistors constituting the gate output circuit 22 a are not limited to field-effect transistors and may be, for example, GaN-HEMTs.

[0101] (Embodiment 3) Fig. 9 is a circuit diagram showing the configuration of a power conversion device according to embodiment 3. Fig. 9 is similar to Fig. 1, so differences will be mainly described. The main difference is that the power conversion device shown in Fig. 9 uses a full-bridge circuit instead of a half-bridge circuit.

[0102] In FIG. 9, reference numeral 101a denotes a power conversion device according to a third embodiment. The power conversion device 101a includes a full-bridge circuit 7 instead of the half-bridge circuit 1 (FIG. 1). That is, the power conversion device 101a includes the full-bridge circuit 7, a gate drive circuit 2, a detection circuit 5, a determination circuit 6, a resonance capacitor Cr, a transformer Tr configured with a primary winding Tr1 and secondary windings Tr2-1 and Tr2-2, and a rectifier circuit 3 configured with diodes D1 and D2 and a smoothing capacitor Co. An external DC power supply Vi is connected to input terminals T1 and T2, and a load 4 is connected to output terminals T3 and T4. In the third embodiment as well, the DC power supply Vi is a device that supplies DC power, such as a battery or an AC / DC converter.

[0103] A full-bridge circuit 7 is connected between both terminals of a DC power supply Vi via input terminals T1 and T2. In the full-bridge circuit 7, switching elements Q1 and Q2 are connected in series, and switching elements Q3 and Q4 are connected in series. The switching elements Q1 to Q4 are configured, for example, by GaN-HEMTs formed on the silicon substrate of a semiconductor chip. In the full-bridge circuit 7, the drain terminals of the switching elements Q1 and Q3 are connected to the DC power supply Vi via input terminal T1. The source terminal of the switching element Q1 is connected to the drain terminal of the switching element Q2, and the source terminal of the switching element Q3 is connected to the drain terminal of the switching element Q4. The source terminals of the switching elements Q2 and Q4 are connected to the DC power supply Vi via input terminal T2.

[0104] The gate terminals of switching elements Q1 and Q4 are connected to one gate output of gate drive circuit 2, for example, T23 in FIG. 2. The gate terminals of switching elements Q2 and Q3 are connected to the other gate output of gate drive circuit 2 (T24 in FIG. 2). A detection circuit 5, a resonant capacitor Cr, and a primary winding Tr1 of a transformer Tr are connected in series between a node connecting the source terminal of switching element Q1 and the drain terminal of switching element Q2, and a node connecting the source terminal of switching element Q3 and the drain terminal of switching element Q4. Therefore, in full-bridge circuit 7, diagonally positioned switching elements (switching element pair) Q1 and Q4 are simultaneously turned on and off, and similarly, diagonally positioned switching elements (switching element pair) Q2 and Q3 are simultaneously turned on and off.

[0105] During the period when switching elements Q1 and Q4 are on, the voltage between the drain terminal and source terminal of switching element Q4 is almost zero, so the operation is equivalent to that of the circuit using half-bridge circuit 1 in embodiment 1, and the same operation as embodiment 1 is performed. That is, current I1 flows through a resonant switching circuit including DC power supply Vi, switching elements Q1 and Q4, detection circuit 5, resonant capacitor Cr, and primary winding Tr1 of transformer Tr.

[0106] Meanwhile, unlike in the first embodiment, the operation during the period when switching elements Q2 and Q3 are on includes DC power supply Vi in the path of current I2 flowing through the resonant switching circuit including primary winding Tr1 of transformer Tr. Therefore, according to the third embodiment using the full bridge circuit 7, current is supplied from DC power supply Vi not only during the period when switching elements Q1 and Q4 are on, but also during the period when switching elements Q2 and Q3 are on. This increases the current that can be output from power conversion device 101a compared to when the same amount of current is passed through switching elements Q1 to Q4 as in the first embodiment. This enables operation suitable for a power conversion device that outputs a large current.

[0107] In the third embodiment, too, when the load 4 becomes, for example, a high load, it is possible to suppress the amount of change over time in the through current flowing between the switching elements Q1 and Q4 and between the switching elements Q3 and Q2, as in the first embodiment, and to suppress the occurrence of surge voltages and noise.

[0108] In the third embodiment, the gate output circuit may also adopt the configuration described in the second embodiment.

[0109] (Fourth embodiment) Fig. 10 is a circuit diagram showing the configuration of a power conversion device according to embodiment 4. Fig. 10 is similar to Fig. 1, so the differences will be mainly explained below. The main differences are that in Fig. 10, two sense elements are added, two sense circuits corresponding to the sense elements are provided as sense circuits, and outputs of the two sense circuits are supplied to a determination circuit.

[0110] 10, reference numeral 101b denotes a power conversion device according to the fourth embodiment. The power conversion device 101b includes a half-bridge circuit 1a, a gate drive circuit 2, two detection circuits 5-1 and 5-2, a determination circuit 6a, a resonance capacitor Cr, a transformer Tr formed by a primary winding Tr1 and secondary windings Tr2-1 and Tr2-2, and a rectifier circuit 3 formed by diodes D1 and D2 and a smoothing capacitor Co. An external DC power supply Vi is connected to input terminals T1 and T2, and a load 4 is connected to output terminals T3 and T4.

[0111] The half-bridge circuit 1a includes switching elements Q1a and Q2a connected in series. The switching elements Q1a and Q2a are configured, for example, by GaN-HEMTs formed on the silicon substrate of a semiconductor chip. The switching elements Q1a and Q2a include switching elements (main switching elements) Q1a-f and Q2a-f that pass the main current, and switching elements (sensing switching elements) Q1a-s and Q2a-s that split the current flowing through the switching elements Q1a and Q2a and send it.

[0112] The drain terminals of switching elements Q1a-f and Q1a-s are connected to each other, and the gate terminals of switching elements Q1a-f and Q1a-s are also connected to each other. Similarly, the drain terminals of switching elements Q2a-f and Q2a-s are connected to each other, and the gate terminals of switching elements Q2a-f and Q2a-s are also connected to each other.

[0113] The main switching element and the sense switching element used in the fourth embodiment are formed on the semiconductor substrate (silicon substrate) of the same semiconductor chip. Fig. 11 is a plan view showing a part of the semiconductor chip according to the fourth embodiment. Fig. 11 shows the part of the switching element Q1a formed on the semiconductor substrate (silicon substrate) of the semiconductor chip.

[0114] The switching elements Q1a-f and Q1a-s included in the switching element Q1a are integrated on the same substrate. In FIG. 11, the symbol Q1a-Td denotes a common drain terminal of the switching elements Q1a-f and Q1a-s. The symbol Q1a-Tg denotes a common gate terminal of the switching elements Q1a-f and Q1a-s. The symbol Q1a-Ts-f denotes a source terminal of the switching element Q1a-f, and the symbol Q1a-Ts-s denotes a source terminal of the switching element Q1a-s. The drain and gate terminals of the switching elements Q1a-f and Q1a-s are connected to each other to connect the switching elements Q1a-f and Q1a-s in parallel. By operating the switching elements Q1a-f and Q1a-s in parallel, a portion of the current flowing through the switching element Q1a is diverted to the switching element Q1a-s, allowing the switching element Q1a-s to be used as a sense element.

[0115] As shown in Fig. 11, the device area of ​​switching element Q1a-s is smaller than the device area of ​​switching element Q1a-f. Although Fig. 11 shows only switching element Q1a, switching element Q2a is configured similarly to switching element Q1a. In the fourth embodiment, switching elements Q1a and Q2a are formed on the same semiconductor substrate.

[0116] Returning to Figure 10, the explanation will be given below. The source terminal of switching element Q1a-f is connected to the drain terminal of switching element Q2a. The source terminal of switching element Q2a-f is connected to DC power supply Vi via input terminal T2. The gate terminals of switching elements Q1a and Q2a are connected to gate drive circuit 2. A resonance capacitor Cr and a primary winding Tr1 of a transformer Tr are connected in series between the node connecting the source terminal of switching element Q1a-f and the drain terminal of switching element Q2a and the source terminal of switching element Q2a-f.

[0117] A detection circuit 5-1 is connected between the source terminals of switching elements Q1a-f and Q1a-s, and a detection circuit 5-2 is connected between the source terminals of switching elements Q2a-f and Q2a-s. The detection circuits 5-1 and 5-2 are current sensors that use, for example, shunt resistors, Hall elements, Rogowski coils, etc. The detection circuits 5-1 and 5-2 detect the current values ​​of the currents flowing through the switching elements Q1a-s and Q2a-s, respectively. The current values ​​detected by the detection circuits 5-1 and 5-2 are output as analog values ​​to a determination circuit 6a.

[0118] The decision circuit 6a is composed of a comparator, for example, and an edge detector using an edge detection circuit or a microprocessor. The comparator compares the inputs from the current detection circuits 5-1 and 5-2 with the detected value when the current value is zero, and outputs the result as a digital value. The signal output from the comparator is input to the edge detector, which outputs a signal corresponding to the falling edge of the signal from the comparator to the gate drive circuit 2.

[0119] Since the switching elements Q1 and Q2 described in the first embodiment correspond to the switching elements Q1a and Q2a in the fourth embodiment, the currents output from the detection circuits 5-1 and 5-2 correspond to the currents Id1 and Id2 shown in FIGS. 5 and 6. Therefore, the current output from the detection circuit 5-1 is used as a determination signal when the polarity of the current I1 flowing through the primary winding Tr1 of the transformer Tr reverses from positive to negative. That is, when the current output from the detection circuit 5-1 reverses from positive to negative, the determination circuit 6a outputs a determination signal indicating that the polarity of the current I1 has reversed from positive to negative.

[0120] On the other hand, the current output from the detection circuit 5-2 is used as a determination signal when the polarity of the current I1 flowing through the primary winding Tr1 of the transformer Tr reverses from negative to positive. That is, when the current output from the detection circuit 5-2 reverses from positive to negative, the determination circuit 6a outputs a determination signal indicating that the polarity of the current I1 has reversed from negative to positive. The gate drive circuit 2 performs the same operation as in the first embodiment based on the determination signal from the determination circuit 6a.

[0121] According to the fourth embodiment, the currents diverted from the currents flowing through the switching elements Q1a and Q2a are detected by the detection circuits 5-1 and 5-2, respectively, so that the absolute values ​​of the detected currents are smaller than the absolute value of the current I1 flowing through the primary winding Tr1 of the transformer Tr. This makes it possible to reduce the size of the detection circuits 5-1 and 5-2.

[0122] Furthermore, according to the fourth embodiment, the detection circuits 5-1 and 5-2 are provided at a location separate from the resonant switching circuit including the primary winding Tr1 of the transformer Tr, which is a path through which a large current flows, and therefore it is possible to reduce the parasitic inductance of the resonant switching circuit.

[0123] Furthermore, when using a switching element with an integrated sense element, the current sense ratio generally fluctuates due to the influence of temperature distribution inside the element, etc. However, according to the fourth embodiment, the sense element is used only to determine the reversal of the polarity (positive, negative) of the current, and therefore fluctuations in the ratio of the currents detected by the sense element (current sense ratio) do not affect the operation of the power conversion device, making it possible to use the integrated sense element.

[0124] The detection circuit 5-1 shown in FIG. 10 may be formed on the same semiconductor substrate as the switching element Q1a, and the detection circuit 5-2 may also be formed on the same semiconductor substrate as the switching element Q2a.

[0125] Although the fourth embodiment has been described based on the power conversion device described in the first embodiment, the present invention is not limited to this example. That is, the fourth embodiment may be based on the power conversion devices described in the second and third embodiments.

[0126] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0127] 1 Half-bridge circuit 2 Gate drive circuit 3 Rectifier circuit 4. Load 5, 5-1, 5-2 Detection circuit 6 Judgment circuit 7 Full-bridge circuit 100, 101, 101a, 101b Power conversion device Cp1, Cp2 output capacitance Q1, Q2, Q3, Q4, Q1a, Q2a switching elements RSC switching circuit

Claims

1. a switching circuit including a transformer having a plurality of switching elements, a capacitor, and a primary winding connected in series with the capacitor; a gate drive circuit that outputs a gate drive current to the gate of the switching element to control the on / off of the switching element; a detection circuit for detecting a current flowing through the switching circuit; a determination circuit for determining whether the polarity of the current detected by the detection circuit is reversed; Equipped with the gate drive circuit includes a gate adjustment circuit that adjusts the gate drive current based on the result of the determination by the determination circuit; the gate adjustment circuit outputs an output switching signal for switching the gate drive current between at least two levels in both of which a current flows; the gate adjustment circuit outputs the output switching signal for switching the gate drive current output by the gate drive circuit to a low level when the polarity reversal is determined by the determination circuit. Power conversion device.

2. The power conversion device according to claim 1, the gate adjustment circuit outputs the output switching signal for switching the gate drive current to a high level after a predetermined period of time has elapsed since the gate drive current was switched to a low level; Power conversion device.

3. The power conversion device according to claim 2, the gate drive circuit includes a plurality of gate resistors having different resistance values, and a switch circuit that selects a gate resistor from the plurality of gate resistors in accordance with the output switching signal and connects the selected gate resistor between a predetermined voltage and the gate terminal of the switching element. Power conversion device.

4. The power conversion device according to claim 2, The gate drive circuit includes a current circuit whose current value changes in response to the output switching signal, and a current mirror circuit that outputs a current proportional to the current flowing through the current circuit. Power conversion device.

5. The power conversion device according to any one of claims 1 to 4, the plurality of switching elements includes two switching elements, the gate adjustment circuit adjusts the gate drive current of one of the two switching elements to a low level when the other switching element is in an on state; Power conversion device.

6. The power conversion device according to any one of claims 1 to 4, the plurality of switching elements include two pairs of switching elements positioned diagonally opposite each other; the gate adjustment circuit adjusts the gate drive current of one switching element of the pair of switching elements to a low level when the other switching element is in an on state; Power conversion device.

7. 7. The power conversion device according to claim 1, At least one of the plurality of switching elements includes a main switching element that supplies current to the capacitor and a primary winding connected in series with the capacitor when in an on state, and a sense element that shunts a part of the current flowing through the one switching element, the detection circuit detects a current flowing through the sense element; The main switching element and the sense element are formed on the same semiconductor chip. Power conversion device.

8. The power conversion device according to claim 7, the detection circuit is formed on the same semiconductor chip as at least one of the plurality of switching elements; Power conversion device.

9. The power conversion device according to any one of claims 1 to 8, At least one switching element among the plurality of switching elements uses a gallium nitride-based material. Power conversion device.

10. a switching circuit including a transformer having a plurality of switching elements, a capacitor, and a primary winding connected in series with the capacitor; a gate drive circuit that outputs a gate drive current to a gate terminal of the switching element to control the on / off of the switching element; A power conversion device comprising: the gate drive circuit includes a gate adjustment circuit that outputs an output switching signal for switching the gate drive current between at least two levels, both of which are in a state where a current flows; Detecting a current flowing through the switching circuit; determining whether the polarity of the detected current has reversed; When it is determined that the polarity has been reversed, the gate adjustment circuit outputs the output switching signal that switches the gate drive current output by the gate drive circuit to a low level. A method for controlling a power conversion device.

11. The method for controlling a power conversion device according to claim 10, the gate adjustment circuit outputs the output switching signal for switching the gate drive current to a high level after a predetermined period of time has elapsed since the gate drive current was switched to a low level; A method for controlling a power conversion device.

12. The method for controlling a power conversion device according to claim 11, the predetermined period is longer than the time from when it is determined that the polarity has reversed until the on / off state of the switching element is switched, and is shorter than half the on / off cycle of the switching element. A method for controlling a power conversion device.

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