Complementary semiconductor devices using halide perovskite thin films

Abstract

A conductor device structure and method for fabricating the same is provided that utilizes the vacancy properties of two-dimensional materials to selectively control the semiconductor type of halide perovskite thin films. [Solution] A halide perovskite-based complementary semiconductor device 100 according to an embodiment of the present invention includes a substrate 120, a two-dimensional material layer 140 formed on the upper surface side of the substrate and including a hole injection layer and an electron injection layer, a halide perovskite layer 150 formed on the two-dimensional material layer, and an electrode layer 160 formed on the halide perovskite layer and including a drain electrode 160-1, output electrodes 160-2, 160-3 and a source electrode 160-4.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to and the benefit of Korean Patent Application No. 10-2025-0034438, filed on March 18, 2025, the entire disclosure of which is incorporated herein by reference. The present invention relates to the fields of electronics and semiconductor engineering, and more particularly to semiconductor device structures comprising two-dimensional materials and halide perovskite materials, and methods for fabricating the same. [Background technology]

[0002] Thin film transistors (TFTs) are widely used as display drivers. Currently, commercialized technology is limited to n-channel TFTs that use InGaZnO materials as the channel, which are limited from a circuit perspective. To overcome these limitations, active research is being conducted into the development of p-channel TFT devices. However, commercialization is difficult due to the lack of oxide semiconductor thin films with p-channel (hole-driving) properties.

[0003] Halide perovskite thin films have high field-effect mobility (>50 cm 2 / Vs), they have attracted attention as channel materials for p-channel TFT devices. In particular, they have the advantage of being easily applicable to glass and flexible substrates because they can be fabricated at low process temperatures. However, while halide perovskite thin films have excellent p-channel characteristics, it is difficult to achieve n-channel characteristics due to the energy band structure characteristics of the material, which limits the fabrication of complementary semiconductor devices using only a single material. As a result, most complementary semiconductor devices reported to date employ a method combining a p-channel TFT based on a halide perovskite material and an n-channel TFT based on an InGaZnO material.

[0004] Halide perovskite materials have various advantages, such as excellent photoresponse characteristics, high charge mobility, the possibility of low-cost mass production, and inherent flexibility. However, the following problems exist in the actual device fabrication and application processes.

[0005] 1) Limited control of electrical properties: Conversion of perovskite conductivity type (p-type / n-type) mainly depends on the change of chemical composition, which limits device design and property control.

[0006] 2) Process compatibility issues: Low compatibility with existing semiconductor processes such as photolithography makes it difficult to apply fine processes.

[0007] 3) Stability issues: vulnerability to atmospheric conditions such as moisture and oxygen leads to degradation of material properties during processing, making it difficult to ensure device reliability and stability.

[0008] These technical limitations have delayed the practical application and commercialization of halide perovskite-based electronic devices, necessitating technological development and research into halide perovskite-based devices. Summary of the Invention

[0009] The problem to be solved by the present invention is to provide a semiconductor device having a novel structure that can selectively control the semiconductor type of a halide perovskite thin film by utilizing the vacancy properties of two-dimensional materials.

[0010] The problem to be solved by the present invention is to realize a semiconductor device in which p-type and n-type regions can be simultaneously formed within a single halide perovskite thin film by controlling M vacancies and X vacancies in an MX2 (M: transition metal, X: chalcogenide) based two-dimensional material.

[0011] The problem to be solved by the present invention is to provide a complementary semiconductor device that can be manufactured in a single process via a multilayer structure of a two-dimensional material layer and a halide perovskite layer, and that operates stably.

[0012] The problems to be solved by the present invention are not limited to the above problems, and undescribed problems will also be clearly understood by those skilled in the art from this specification and the accompanying drawings.

[0013] A halide perovskite-based complementary semiconductor device according to an embodiment of the present invention may include a substrate, a two-dimensional material layer formed on a top side of the substrate and including a hole injection layer and an electron injection layer, a halide perovskite layer formed on the two-dimensional material layer, and an electrode layer formed on the halide perovskite layer and including a drain electrode, an output electrode, and a source electrode.

[0014] The means for solving the problems of the present invention are not limited to the above-mentioned means for solving the problems, and will be clearly understood by those skilled in the art from this specification and the accompanying drawings.

[0015] According to embodiments of the present invention, halide perovskite-based complementary semiconductor devices can selectively control the conductivity type of halide perovskite by utilizing the inherent vacancy properties of two-dimensional materials. Specifically, S vacancies act as an electron-rich (e-rich) electron injection layer, and W vacancies act as an electron-poor (e-poor) hole injection layer, effectively inducing semiconductor-type inversion. Furthermore, the charge injection control method utilizing the vacancy properties of two-dimensional materials enables very precise conductivity type tuning. Because S vacancies and W vacancies act as donors and acceptors, respectively, the charge transport properties of the perovskite layer can be locally and precisely tuned, enabling the realization of various logic devices, including inverters.

[0016] The halide perovskite-based complementary semiconductor device according to the present invention, unlike conventional heterogeneous material combination methods, can realize a complementary semiconductor device using a single halide perovskite material. This allows for simultaneous formation of p-type and n-type regions within a single material, simplifying the process and improving the uniformity of device characteristics. This device structure allows for low-temperature processing and is applicable to various substrate materials, such as glass and plastic substrates. It is particularly suitable for flexible substrates, enabling its use as a flexible electronic device. Furthermore, compatibility with existing semiconductor processes such as photolithography can be improved, and moisture stability can be enhanced, thereby improving device reliability and stability.

[0017] The effects of the present invention are not limited to those described above, and other effects not mentioned will be apparent to those skilled in the art from this specification and the accompanying drawings. [Brief explanation of the drawings]

[0018] The above and other objects, features and advantages of the present invention will become more apparent to those skilled in the art from the following detailed description of exemplary embodiments of the present invention taken in conjunction with the accompanying drawings. [Figure 1] 1A and 1B are schematic diagrams illustrating a top view and a cross-sectional side view, respectively, of a halide perovskite-based complementary semiconductor device including a two-dimensional material according to an embodiment of the present invention; [Figure 2] FIG. 1 is an enlarged schematic diagram of the two-dimensional material shown in FIGS. 1(a) and 1(b) as viewed from above. [Figure 3] 1(a) and 1(b) show a process sequence for fabricating the semiconductor device shown in FIG. [Figure 4] 4(a) and 4(b) are schematic diagrams of a device for an embodiment in which a passivation layer is added to improve the stability of the device shown in FIG. [Figure 5]5 shows a process sequence for the embodiment of FIG. [Figure 6] 6(a) and 6(b) are schematic diagrams of a device fabricated with additional processes to improve integration density in another embodiment. [Figure 7] 7 shows a process sequence for the embodiment of FIG. 6. [Figure 8] 8(a) and 8(b) are schematic diagrams showing top and cross-sectional views of a device for fabricating a top-gate complementary semiconductor device in another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0019] The above objects, features, and advantages of the present application will become more apparent through the following detailed description taken in conjunction with the accompanying drawings. However, since the present application can be modified in various ways and can have various embodiments, specific embodiments are shown in the drawings and will be described in detail below.

[0020] Throughout this specification, the same reference numerals generally refer to the same components. Furthermore, components having the same function within the same concept that appear in the drawings of each embodiment will be described using the same reference numerals, and redundant description will be omitted.

[0021] If it is determined that a detailed description of well-known functions or configurations in the present application may unnecessarily obscure the gist of the present application, such detailed description will be omitted. Furthermore, numbers (e.g., first, second, etc.) used in the description of this specification are merely identification symbols for distinguishing one component from another.

[0022] Furthermore, the suffixes "module" and "unit" for components used in the following embodiments are given or used interchangeably only to facilitate the preparation of the specification, and do not have meanings or roles that are clearly distinguished from each other.

[0023] In the following embodiments, singular expressions include plural expressions unless the context clearly dictates otherwise.

[0024] In the following embodiments, terms such as "comprise" or "have" mean the presence of features or components described in this specification, without precluding the possibility of adding one or more other features or components.

[0025] In the drawings, the size of components may be exaggerated or reduced for the sake of convenience of explanation. For example, the size and thickness of each component shown in the drawings are arbitrarily shown for the sake of convenience of explanation, and the present invention is not necessarily limited to those shown in the drawings.

[0026] When an embodiment can be implemented differently, the order of certain processes may be performed differently from the order described. For example, two processes described in succession may be performed substantially simultaneously or may proceed in the reverse order from that described. In the following embodiments, when components are said to be connected, it includes not only the case where the components are directly connected, but also the case where the components are indirectly connected with another component interposed between them. For example, in this specification, when components are said to be electrically connected, it includes not only the case where the components are directly electrically connected, but also the case where the components are indirectly electrically connected with another component interposed between them.

[0027] A halide perovskite based semiconductor device according to an embodiment of the present application may include a substrate, a two-dimensional material layer formed on an upper surface side of the substrate and including a hole injection layer and an electron injection layer, a halide perovskite layer formed on the two-dimensional material layer, and an electrode layer formed on the halide perovskite layer and including a drain electrode, an output electrode, and a source electrode.

[0028] According to one embodiment of the present application, the hole injection layer of the two-dimensional material layer injects holes into the halide perovskite layer such that a first region of the halide perovskite layer has p-type semiconductor properties, and the electron injection layer of the two-dimensional material layer injects electrons into the halide perovskite layer such that a second region of the halide perovskite layer has n-type semiconductor properties.

[0029] According to one embodiment of the present application, the hole injection layer forms a first contact potential at the interface with the halide perovskite layer, and the electron injection layer forms a second contact potential at the interface with the halide perovskite layer, so that a first region having p-type semiconductor properties and a second region having n-type semiconductor properties are locally formed in the halide perovskite layer due to the difference between the first contact potential and the second contact potential.

[0030] According to one embodiment of the present application, the two-dimensional material layer can be characterized as including a transition metal chalcogenide material including any one of WS2, MoS2, WSe2, MoSe2, NbSe2, TaS2, and Bi2Se3.

[0031] According to one embodiment of the present application, the two-dimensional material layer comprises WS2, the hole injection layer comprises W vacancies WS2, and the electron injection layer comprises S vacancies WS2.

[0032] According to one embodiment of the present application, the halide perovskite layer is selected from the group consisting of MAPbI3, MAPbBr3, MAPbCl3, FAPbI3, FAPbBr3, FAPbCl3, CsPbI3, CsPbBr3, CsPbCl3, RbPbI3, RbPbBr3, RbPbCl3, CsPb(I 1-x Br x )3, MASnI3, MASnBr3, MASnCl3, FASnI3, FASnBr3, FASnCl3, CsSnI3, CsSnBr3, CsSnCl3, MAGeI3, FAGeI3, CsGeI3, Cs2AgBiBr6, Cs2AgBiCl6, Cs2AgSbBr6, MAPb(I 1-x Br x )3, CsPb(Br 1-x Clx )3, FAPb(I 1-x Br x )3, (PEA)2PbI4 (phenethylammonium lead iodide), (FPEA)2PbI4 (4-fluoro-phenethylammonium lead iodide), (PEA)2SnI4 (phenethylammonium tin iodide), (FPEA)2SnI4 (4-fluoro-phenethylammonium tin iodide), (BA)2(MA) n-1 Pb n I 3n+1 (butylammonium-based), Cs2AgBiBr6, Cs2InBiCl6, Cs2SnI6, Cs2TiI6, and combinations thereof.

[0033] According to one embodiment of the present application, the two-dimensional material layer may be formed to have at least one two-dimensional material having at least one hexagonal structural pattern.

[0034] According to one embodiment of the present application, the hexagonal structural pattern can be characterized by being divided into hole injection regions corresponding to the hole injection layers and electron injection regions corresponding to the electron injection layers, which are alternately arranged about the center.

[0035] According to one embodiment of the present application, the drain electrode may be connected to a power supply voltage (VDD), the source electrode may be connected to a ground voltage (VSS), and the output electrode may be configured to provide an output voltage (Vout).

[0036] According to an embodiment of the present application, the semiconductor device may further include a backside input electrode layer formed on a backside of the substrate, and the backside input electrode layer may be configured to provide an input voltage (Vin).

[0037] According to one embodiment of the present application, the semiconductor device may further include a passivation layer formed on at least a portion of the halide perovskite layer and the electrode layer, and the passivation layer may be characterized by protecting devices included in the semiconductor device from an external environment to improve stability.

[0038] According to an embodiment of the present application, the semiconductor device may further include a gate insulating layer formed between the substrate and the two-dimensional material layer, and the two-dimensional material layer may be formed on at least a portion of a surface of the gate insulating layer.

[0039] According to one embodiment of the present application, a two-dimensional material layer may be formed having a pattern of patterned tetragonal structures by etching a material having a pattern of hexagonal structures by mechanical or laser scribing.

[0040] According to one embodiment of the present application, the substrate may be formed of glass or a flexible substrate, and may further include a gate insulating layer formed on the halide perovskite layer or the electrode layer. A gate electrode may be formed on the gate insulating layer and configured to provide an input electrode (Vin).

[0041] According to one embodiment of the present application, the halide perovskite layer may be characterized by being composed of any one of a three-dimensional thin film structure, a two-dimensional thin film structure, and a mixed form thereof.

[0042] Hereinafter, a semiconductor device using a halide perovskite thin film according to an embodiment of the present application and a manufacturing process thereof will be described in more detail with reference to FIGS.

[0043] Embodiment 1: Basic complementary semiconductor device structure FIG. 1(a) is a schematic diagram of a top view of a halide perovskite-based complementary semiconductor device 100 including a two-dimensional material according to one embodiment of the present invention. FIG. 1(b) is a schematic diagram of a cross-section of a halide perovskite-based complementary semiconductor device 100 including a two-dimensional material according to one embodiment of the present invention, viewed from the side. Specifically, FIG. 1(b) is a schematic diagram showing a cross-section of the semiconductor device 100 of FIG. 1(a) taken along line A-A'. FIG. 2 is an enlarged schematic diagram of the two-dimensional material shown in FIGS. 1(a) and 1(b) viewed from the top.

[0044] 1(a) and 1(b), there is shown a halide perovskite-based complementary semiconductor device 100 according to a first embodiment of the present invention. The semiconductor device 100 may include a substrate 120, a gate insulating layer 130, a two-dimensional material layer 140, a halide perovskite layer 150, and an electrode layer 160.

[0045] Substrate 120 is a structure that serves as the foundation of semiconductor device 100 and may be made of a variety of materials, such as a silicon substrate, a glass substrate, or a flexible substrate. For example, substrate 120 may be a silicon substrate in the form of a silicon wafer. The gate insulating layer 130 may be formed on the substrate 120 and may be made of an oxide insulator or the like. Specifically, the gate insulating layer 130 may be formed on the upper surface side of the substrate 120.

[0046] The two-dimensional material layer 140 may be formed on the gate insulating layer 130. Specifically, the two-dimensional material layer 140 may be formed on at least a portion of the surface of the gate insulating layer 130. Furthermore, the two-dimensional material layer 140 may be composed of a transition metal chalcogenide material (e.g., a transition metal dichalcogenide (TMD) material). The two-dimensional material layer 140 may be composed of a transition metal chalcogenide material including any one of WS2, MoS2, WSe2, or MoSe2. In this embodiment, WS2 will be described as an example. However, this is merely for convenience of description and should not be construed as limiting.

[0047] 2, the two-dimensional material layer 140 may be formed to have at least one hexagonal structure pattern composed of a region having a large number of W vacancies 140-1 and a large number of S vacancies 140-2, which are alternately arranged with respect to the center. Here, the region having a large number of W vacancies 140-1 acts as a hole injection region that functions as a hole injection layer, and the region having a large number of S vacancies 140-2 acts as an electron injection region that functions as an electron injection layer.

[0048] The halide perovskite layer 150 is formed on the two-dimensional material layer 140 and may be composed of a halide perovskite material selected from the group consisting of organic-inorganic hybrid halide perovskite materials, all-inorganic halide perovskite materials, Pb-free halide perovskite materials, mixed halide materials, two-dimensional halide perovskite materials, dual perovskite materials, vacancy-ordered halide perovskite materials, and combinations thereof.

[0049] The organic-inorganic hybrid halide perovskite material may be MAPbI3, MAPbBr3, MAPbCl3, FAPbI3, FAPbBr3, or FAPbCl3.

[0050] All-inorganic halide perovskite materials are CsPbI3, CsPbBr3, CsPbCl3, RbPbI3, RbPbBr3, RbPbCl3, or CsPb(I 1-x Br x )3 may also be used.

[0051] The Pb-free halide perovskite material may be MASnI3, MASnBr3, MASnCl3, FASnI3, FASnBr3, FASnCl3, CsSnI3, CsSnBr3, CsSnCl3, MAGeI3, FAGeI3, CsGeI3, Cs2AgBiBr6, Cs2AgBiCl6, or Cs2AgSbBr6.

[0052] The mixed halide perovskite material is MAPb(I 1-x Brx )3, CsPb(Br 1-x Cl x )3, or FAPb(I 1-x Br x )3 may also be used.

[0053] Two-dimensional halide perovskite materials include (PEA)2PbI4 (phenethylammonium lead iodide), (FPEA)2PbI4 (4-fluoro-phenethylammonium lead iodide), (PEA)2SnI4 (phenethylammonium tin iodide), (FPEA)2SnI4 (4-fluoro-phenethylammonium tin iodide), or (R-NH3)2(A) n-1 (BX3) n It has the structure (BA)2(MA) n-1 Pb n I 3n+1 (butylammonium type) may also be used.

[0054] The double perovskite material may be Cs2AgBiBr6 or Cs2InBiCl6.

[0055] The vacancy-ordered halide perovskite material may be Cs2SnI6 or Cs2TiI6.

[0056] Thus, according to one embodiment of the present application, the halide perovskite layer may be MAPbI3, MAPbBr3, MAPbCl3, FAPbI3, FAPbBr3, FAPbCl3, CsPbI3, CsPbBr3, CsPbCl3, RbPbI3, RbPbBr3, RbPbCl3, CsPb(I 1-x Br x )3, MASnI3, MASnBr3, MASnCl3, FASnI3, FASnBr3, FASnCl3, CsSnI3, CsSnBr3, CsSnCl3, MAGeI3, FAGeI3, CsGeI3, Cs2AgBiBr6, Cs2AgBiCl6, Cs2AgSbBr6, MAPb(I 1-x Br x )3, CsPb(Br 1-x Cl x )3, FAPb(I 1-x Brx )3, (PEA)2PbI4 (phenethylammonium lead iodide), (FPEA)2PbI4 (4-fluoro-phenethylammonium lead iodide), (PEA)2SnI4 (phenethylammonium tin iodide), (FPEA)2SnI4 (4-fluoro-phenethylammonium tin iodide), (BA)2(MA) n-1 Pb n I 3n+1 (butylammonium-based), Cs2AgBiBr6, Cs2InBiCl6, Cs2SnI6, Cs2TiI6, and combinations thereof.

[0057] However, this is merely an example, and any suitable material may be selected as the halide perovskite material of the halide perovskite layer.

[0058] The halide perovskite layer 150 is preferably formed to a thickness within the range of 1 nm to 100 nm. If it is thicker than 100 nm, the underlying two-dimensional material will not be visible after lamination, resulting in difficulty in aligning electrodes, high electrical resistance, and reduced device performance. If it is thinner than 1 nm, it may not function as a channel, which may result in the inability to operate a complementary semiconductor device.

[0059] The electrode layer 160 may be formed on the halide perovskite layer 150 and may include a drain electrode 160-1, output electrodes 160-2 and 160-3, and a source electrode 160-4. The drain electrode 160-1 is connected to a power supply voltage (VDD), the source electrode 160-4 is connected to a ground voltage (VSS), and each of the output electrodes 160-2 and 160-3 is configured to provide an output voltage (Vout). In addition, a backside input electrode layer 110 may be formed on the backside of the substrate 120 (i.e., the side opposite to the substrate 120 on which the gate insulating layer 130 is formed), and the backside input electrode layer 110 may provide an input voltage (Vin).

[0060] The hole injection layer 140-1 corresponding to the region having a large number of W vacancies in the two-dimensional material layer 140 functions as a hole injection layer that removes electrons from the halide perovskite layer 150, allowing the corresponding region of the halide perovskite layer 150 to have p-type semiconductor properties. On the other hand, the electron injection layer 140-2 corresponding to the region having a large number of S vacancies functions to inject electrons into the halide perovskite layer 150, allowing the corresponding region of the halide perovskite layer 150 to have n-type semiconductor properties.

[0061] Specifically, the hole injection layer 140-1 forms a first contact potential at the interface with the halide perovskite layer 150, and the electron injection layer 140-2 forms a second contact potential at the interface with the halide perovskite layer 150. Due to the difference between the first and second contact potentials, a first region having p-type semiconductor properties and a second region having n-type semiconductor properties are locally formed in the halide perovskite layer 150, enabling the operation of a complementary semiconductor device.

[0062] A method for manufacturing a semiconductor device 100 according to embodiment 1 of the present application will be described below with reference to Fig. 3. In describing the method for manufacturing the semiconductor device 100, content that overlaps with the content described with reference to Figs. 1 and 2 may be omitted. However, this is merely for the convenience of description and should not be construed as a limitation.

[0063] FIG. 3 illustrates a process sequence for fabricating the semiconductor device 100 shown in FIGS. 1(a) and 1(b).

[0064] A method for manufacturing a semiconductor device 100 according to an embodiment of the present application may include steps of preparing and cleaning a substrate 120 (S110), depositing a gate insulating layer 130 (S120), forming a two-dimensional material layer 140 (S130), forming a halide perovskite layer 150 (S140), and forming electrodes 110, 160 (S150).

[0065] In step S110, a substrate 120, which is a structure that serves as the basis for the semiconductor device 100, may be provided and cleaned. The substrate 120 may be made of a variety of materials, such as a silicon substrate (e.g., a silicon wafer), a glass substrate, or a flexible substrate.

[0066] In step S120, a gate insulating layer 130 may be deposited on the substrate 120 prepared in step S110.

[0067] In step S130, a two-dimensional material layer 140 may be formed on the gate insulating layer 130 deposited in step S120. Here, the two-dimensional material layer 140 may be composed of a material including any one of WS2, MoS2, WSe2, or MoSe2 as described above, and may be formed to have at least one hexagonal structural pattern composed of regions having a large number of W vacancies 140-1 and regions having a large number of S vacancies 140-2, which are alternately arranged about the center. Here, the region having a large number of W vacancies 140-1 acts as a hole injection layer, and the region having a large number of S vacancies 140-2 acts as an electron injection layer.

[0068] In step S140, a halide perovskite layer 150 may be formed on the two-dimensional material layer 140 formed in step S130. The halide perovskite layer 150 may be formed in any one of a three-dimensional thin film structure, a two-dimensional thin film structure, and a mixture thereof. The three-dimensional (3D) thin film structure may be in the form of an ABX structure (A: organic or inorganic cation, B: metal cation, X: halogen anion). Examples of halide perovskite-based materials having a three-dimensional thin film structure include MAPbI, FAPbI, CsPbI, RbPbI, MASnI, FASnI, CsSnI, MAPbBr, FAPbBr, CsPbBr, RbPbBr, MASnBr, FASnBr, CsSnBr, etc. The three-dimensional thin film structure has the advantage of excellent charge mobility, allowing electrons and holes to move easily in all directions. The two-dimensional (2D) thin film structure may be in the form of a layered structure of the form (R-NH3)2BX4 or A2BX4, and examples of halide perovskite-based materials having a two-dimensional thin film structure may include PEASnI3, PEAPbI3, PEASnBr3, PEAPbBr3, etc. The two-dimensional thin film structure has the characteristics of being more stable than a three-dimensional structure, having an adjustable band gap due to the quantum confinement effect, and having smooth charge transport in the planar direction but limited charge transport in the vertical direction.

[0069] In step S150, an electrode layer 160 including a drain electrode 160-1, output electrodes 160-2 and 160-3, and a source electrode 160-4 may be formed on at least a portion of the halide perovskite layer 150 formed in step S140. Furthermore, in step S150, a back surface input electrode layer 110 may be formed on the back surface side of the substrate 120.

[0070] Embodiment 2: Complementary semiconductor device with additional passivation layer 170

[0071] Figures 4(a) and 4(b) are schematic diagrams of devices for an embodiment in which a passivation layer 170 is added to improve the stability of the device shown in Figure 1. Specifically, Figure 4(b) is a schematic diagram showing a cross section of the semiconductor device 100 of Figure 4(a) taken along line A-A'.

[0072] 4(a) and 4(b), there is shown a halide perovskite-based complementary semiconductor device 100 according to a second embodiment of the present invention. The second embodiment has the same structure as the first embodiment, but with a passivation layer 170 added.

[0073] A passivation layer 170 may be formed on at least a portion of the halide perovskite layer 150 and the electrode layer 160. The passivation layer 170 may function to protect the semiconductor device from the external environment to improve stability. In particular, halide perovskite materials are vulnerable to moisture, so protecting the device from moisture via the passivation layer 170 can ensure long-term stability.

[0074] A method for manufacturing a semiconductor device 100 according to a second embodiment of the present application will be described below with reference to Figure 5. In describing the method for manufacturing a semiconductor device 100, content that overlaps with the content described with reference to Figures 1 to 4 may be omitted. However, this is merely for the convenience of description and should not be construed as a limitation.

[0075] FIG. 5 shows a process sequence for the embodiment of FIG.

[0076] A method for manufacturing a semiconductor device 100 according to an embodiment of the present application may include a step 120 (S210) of preparing and cleaning a substrate, a step (S220) of depositing a gate insulating layer 130, a step (S230) of forming a two-dimensional material layer 140, a step (S240) of forming a halide perovskite layer 150, a step (S250) of forming electrodes 110 and 160, and a step (S260) of forming a passivation layer 170. Among these, steps S110, S120, S130, S140, and S150 described in embodiment 1 can be substantially identically applied to steps S210, S220, S230, S240, and S250 according to embodiment 2 described below, and therefore, descriptions thereof will be omitted and step S260 will be mainly described.

[0077] In step S260, a passivation layer 170 may be formed on at least a portion of the halide perovskite layer 150 formed in step S240 and the electrode layer 160 formed in step S250. As mentioned above, the passivation layer 170 may function to protect the semiconductor device from the external environment to improve stability.

[0078] Embodiment 3: Square pattern structure for improving device integration density 6(a) and 6(b) are schematic diagrams of devices fabricated with additional processes to increase device integration density in another embodiment.

[0079] 6(a) and 6(b), a halide perovskite-based complementary semiconductor device 100 according to a third embodiment of the present invention is shown. In the third embodiment, a two-dimensional material having a hexagonal structure pattern is patterned into a square structure pattern by mechanical or laser scribing to improve device integration density. The square structure pattern can provide the advantage of increasing space utilization in integrated circuit designs and improving compatibility with existing semiconductor process technologies.

[0080] A method for manufacturing a semiconductor device 100 according to a third embodiment of the present application will now be described with reference to Figure 7. In describing the method for manufacturing a semiconductor device 100, content that overlaps with the content described with reference to Figures 1 to 6 may be omitted. However, this is merely for the convenience of description and should not be construed as a limitation.

[0081] FIG. 7 shows a manufacturing process sequence for a device having a square pattern structure, which may further include, after forming the two-dimensional material layer 140, a process of etching at least one two-dimensional material (e.g., TMD) included in the two-dimensional material layer 140 into a square shape.

[0082] Specifically, a method for manufacturing a semiconductor device 100 according to an embodiment of the present application may include the steps of preparing and cleaning a substrate 120 (S310), depositing a gate insulating layer 130 (S320), forming a two-dimensional material layer 140 (S330), etching the two-dimensional material layer 140 (S335), forming a halide perovskite layer 150 (S340), and forming electrodes 110, 160 (S350). Among them, steps S110, S120, S130, S140, and S150 described in embodiment 1 are substantially similarly applicable to steps S310, S320, S330, S340, and S350 according to embodiment 3 described below, and therefore descriptions thereof will be omitted and step S335 will be mainly described.

[0083] In step S335, at least one two-dimensional material included in the two-dimensional material layer 140 formed in step S330 may be etched by mechanical scribing or laser scribing. Specifically, at least one two-dimensional material included in the two-dimensional material layer 140 formed in step S330 may be formed to have a structure pattern other than a square (e.g., a hexagonal structure pattern (see FIG. 2 )). Specifically, the two-dimensional material may be formed on a substrate via a direct growth method (e.g., chemical vapor deposition (CVD)) or a dry transfer method in which the two-dimensional material is attached to the substrate. In this case, in step S335 of the semiconductor device manufacturing method according to an embodiment of the present application, a process may be performed in which the two-dimensional material having the hexagonal structure pattern is etched to have a square structure pattern (e.g., a square structure pattern) by mechanical scribing or laser scribing. As described above, a square structure pattern can provide the advantage of increasing space utilization in integrated circuit design and improving compatibility with existing semiconductor process technologies.

[0084] Meanwhile, although not shown in Fig. 7, the method for manufacturing the semiconductor device 100 according to the third embodiment of the present application may further include, after the step (S350) of forming the electrodes 160, 110, a step (S360) of forming a passivation layer 170, which is essentially the same as step S260 described in Fig. 5. The above-mentioned description of the passivation layer 170 and step S260 is applicable mutatis mutandis to this case, and therefore will not be repeated for convenience.

[0085] Embodiment 4: Complementary semiconductor device with top gate structure

[0086] Hereinafter, the semiconductor device 200 according to the fourth embodiment of the present application will be described in more detail with reference to Fig. 8. Meanwhile, the two-dimensional material layer 140, the halide perovskite layer 150, and the electrode layer 160 described in the first to third embodiments can be applied in substantially the same manner as the two-dimensional material layer 240, the halide perovskite layer 250, and the electrode layer 260 according to the fourth embodiment described below. Therefore, their description will be omitted, and the description will focus on the substrate 220, the gate insulating layer 270, and the gate electrode 280, which are modified compared to the first to third embodiments.

[0087] 8(a) and 8(b) are schematic diagrams showing top and cross-sectional views of a device for fabricating a top-gate complementary semiconductor device in another embodiment.

[0088] 8(a) and 8(b), there is shown a halide perovskite-based top-gate complementary semiconductor device 200 according to a fourth embodiment of the present invention. The semiconductor device 200 according to the fourth embodiment has a structure in which a glass substrate or a flexible substrate 220 is used instead of the substrate 120 in the form of a silicon wafer, and a gate electrode 280 is disposed on top of the semiconductor device 200.

[0089] In the top-gate structure, the two-dimensional material layer 240, the halide perovskite layer 250, and the electrode layer 260 are sequentially formed on the substrate 220, and a gate insulating layer 270 may be formed on at least a portion of the halide perovskite layer 250 and / or the electrode layer 260. Furthermore, a gate electrode 280 may be formed on the gate insulating layer 270, and the gate electrode 280 may be configured to provide an input electrode (Vin). The semiconductor device 200 according to this embodiment does not require the use of a substrate in the form of a silicon wafer, and is therefore applicable to a variety of substrates, and is particularly suitable for realizing flexible electronic devices.

[0090] As in the first embodiment, the two-dimensional material layer 240 is composed of a region having a large number of W vacancies 240-1 (i.e., a hole injection layer) and a region having a large number of S vacancies 240-2 (i.e., an electron injection layer), and regions having p-type and n-type properties can be formed by injecting holes and electrons, respectively, into the halide perovskite layer 250. In addition, the electrode layer 260 includes a drain electrode 260-1, output electrodes 260-2 and 260-3, and a source electrode 260-4, and the gate electrode 280 may provide an input voltage (Vin).

[0091] The present invention described above utilizes the inherent vacancy properties of two-dimensional materials to locally control the semiconducting properties of halide perovskite layers, thereby realizing complementary semiconductor devices in a single material system, which offers significant advantages in terms of process simplification, performance uniformity, and device stability compared to conventional methods that combine different materials.

[0092] The W and S vacancies in the 2D material layer, particularly WS2, play an important role in this invention. These vacancies can be naturally formed during the chemical vapor deposition (CVD) growth process, and precise control of these vacancy structures can effectively control the charge distribution in the halide perovskite layer. The W vacancy regions in the 2D material layer induce a p-type doping effect by attracting electrons from the halide perovskite layer, increasing the hole concentration, while the S vacancy regions induce an n-type doping effect by supplying electrons to the halide perovskite layer.

[0093] By utilizing this principle, the present invention can realize a CMOS (complementary metal-oxide semiconductor) circuit, which is the basic structure of a complementary semiconductor device, by locally forming p-type and n-type regions in the same halide perovskite layer. This can be effectively used in realizing logic circuits such as inverters, NAND gates, and NOR gates.

[0094] Furthermore, the structure proposed in this invention, combined with the excellent optoelectronic properties of halide perovskite materials, offers the potential for application in various optoelectronic devices such as photodetectors, solar cells, and light-emitting diodes. The absorption wavelength band can be controlled by adjusting the thickness and composition of the halide perovskite layer, and the charge transport properties can be optimized through the pore structure of the two-dimensional material layer.

[0095] The passivation layer, square patterning structure, top gate structure, etc. shown in various embodiments of the present invention can be selectively applied according to the actual application environment and purpose, thereby improving the stability, integration density, and applicability to various substrates of the device.

[0096] In conclusion, the halide perovskite-based complementary semiconductor devices according to the present invention can overcome the limitations of existing technologies and present new possibilities for the development of next-generation electronic and optoelectronic devices through an innovative approach that exploits the vacancy properties of two-dimensional materials.

[0097] The features, structures, effects, etc. described in the above embodiments are included in at least one embodiment of the present invention, but are not necessarily limited to one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified for other embodiments by a person skilled in the art to which the embodiment belongs. Therefore, the contents relating to such combinations and modifications should also be interpreted as being included within the scope of the present invention.

[0098] Furthermore, while the above description has focused on the embodiments, these are merely examples and do not limit the present invention. Those skilled in the art will understand that various modifications and applications other than those illustrated above are possible without departing from the essential features of the present invention. In other words, each component specifically illustrated in the embodiments can be modified and implemented. Differences regarding such modifications and applications should be construed as being included within the scope of the present invention as defined in the appended claims. [Explanation of symbols]

[0099] 100: Semiconductor devices 120: Circuit board 140: Two-dimensional material layer 150: Halide perovskite layer 160: Electrode layer

Claims

1. A semiconductor device comprising: A substrate; a two-dimensional material layer formed on the upper surface side of the substrate, the two-dimensional material layer including a hole injection layer and an electron injection layer; a halide perovskite layer formed on the two-dimensional material layer; an electrode layer formed on the halide perovskite layer, the electrode layer including a drain electrode, an output electrode, and a source electrode; the hole injection layer of the two-dimensional material layer injects holes into the halide perovskite layer such that a first region of the halide perovskite layer has p-type semiconductor properties; 1. A semiconductor device comprising: a first region of the halide perovskite layer having n-type semiconductor properties; a second region of the halide perovskite layer having n-type semiconductor properties; and a second region of the halide perovskite layer having n-type semiconductor properties.

2. the hole injection layer forms a first contact potential at an interface with the halide perovskite layer; the electron injection layer forms a second contact potential at an interface with the halide perovskite layer; 2. The semiconductor device of claim 1, wherein the first region having p-type semiconductor properties and the second region having n-type semiconductor properties are locally formed in the halide perovskite layer due to a difference between the first contact potential and the second contact potential.

3. The two-dimensional material layer is WS 2 , MoS 2 , WSe 2 , and MoSe 2 10. The semiconductor device of claim 1, further comprising a transition metal chalcogenide material comprising any one of:

4. The two-dimensional material layer is WS 2 Including, The hole injection layer has W vacancies WS 2 Including, The electron injection layer has S vacancies WS 2 10. The semiconductor device of claim 1, comprising:

5. The halide perovskite layer is MAPbI 3 , MAPbBr 3 , MAPbCl 3 , FAPbI 3 , FAPbBr 3 , FAPbCl 3 , CsPbI 3 , CsPbBr 3 , CsPbCl 3 , RbPbI 3 , RbPbBr 3 , RbPbCl 3 , CsPb(I 1-ｘ Br ｘ ) 3 , MASnI 3 , MASnBr 3 , MASnCl 3 , FASnI 3 , FASnBr 3 , FASnCl 3 , CsSnI 3 , CsSnBr 3 , CsSnCl 3 , MAGeI 3 , FAGeI 3 , CsGeI 3 , Cs 2 AgBiBr 6 , Cs 2 AgBiCl 6 , Cs 2 AgSbBr 6 , MAPb(I 1-ｘ Br ｘ ) 3 , CsPb(Br 1-ｘ Cl ｘ ) 3 , FAPb(I 1-ｘ Br ｘ ) 3 , (PEA) 2 PbI 4 (Phenethylammonium lead iodide), (FPEA) 2 PbI 4 (4-fluoro-phenethylammonium lead iodide), (PEA) 2 SnI 4 (Phenethylammonium tin iodide), (FPEA) 2 SnI 4 (4-fluoro-phenethylammonium tin iodide), (BA) 2 (MA) ｎ-1 Pb ｎ I 3ｎ+1 (butylammonium type), Cs 2 InBiCl 6 , Cs 2 SnI 6 , Cs 2 TiI 6 10. The semiconductor device of claim 1, wherein the first and second electrodes are selected from the group consisting of:

6. 10. The semiconductor device of claim 1, wherein the two-dimensional material layer is formed to include at least one two-dimensional material having at least one hexagonal structural pattern.

7. 7. The semiconductor device according to claim 6, wherein the hexagonal structural pattern is divided into hole injection regions corresponding to the hole injection layer and electron injection regions corresponding to the electron injection layer, which are arranged alternately with respect to the center.

8. The drain electrode is connected to a power supply voltage (VDD); The source electrode is connected to a ground voltage (VSS), 10. The semiconductor device of claim 1, wherein the output electrode is configured to provide an output voltage (Vout).

9. a rear input electrode layer formed on the rear surface side of the substrate; 9. The semiconductor device of claim 8, wherein the backside input electrode layer is configured to provide an input voltage (Vin).

10. a passivation layer formed on at least a portion of the halide perovskite layer and the electrode layer; 10. The semiconductor device of claim 1, wherein the passivation layer protects devices contained in the semiconductor device from an external environment and improves stability.

11. further comprising a gate insulating layer formed between the substrate and the two-dimensional material layer; 2. The semiconductor device of claim 1, wherein the two-dimensional material layer is formed on at least a portion of a surface of the gate insulating layer.

12. the substrate is formed of glass or a flexible substrate; the semiconductor device further includes a gate insulating layer formed on the halide perovskite layer or the electrode layer; 10. The semiconductor device of claim 1, wherein a gate electrode is formed on the gate insulating layer and configured to provide an input electrode (Vin).

13. 2. The semiconductor device according to claim 1, wherein the halide perovskite layer has one of a three-dimensional thin film structure, a two-dimensional thin film structure, and a mixed form thereof.

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