package

Abstract

To provide a package capable of suppressing occurrence of crack from a via hole caused by a stress which is generated during manufacture or use of the package.SOLUTION: A ceramic frame part 120 is disposed on a ceramic substrate part 110, in which a substrate wiring part 200 is provided, and encloses a cavity CV. A metallized layer 600 is provided on the ceramic frame part 120. A via electrode 510 connects the metallized layer 600 and the substrate wiring part 200 and is disposed in a via hole VH. The via hole VH includes a frame penetration part VH1, a wiring penetration part VH2 and a protruding part VH3. The frame penetration part VH1 penetrates the ceramic frame part 120 and is filled with the via electrode 510. The wiring penetration part VH2 extends from the frame penetration part VH1, penetrates the substrate wiring part 200 and is filled with the via electrode 510. The protruding part VH3 protrudes from the wiring penetration part into the ceramic substrate part 110.SELECTED DRAWING: Figure 11

Description

[Technical Field]

[0001] The present invention relates to a package, and more particularly to a package provided with a cavity for hermetically sealing an electronic component by attaching a lid. [Background technology]

[0002] Packages for quartz crystal resonators are known as ceramic components manufactured using ceramic green sheets. A typical quartz crystal resonator includes a quartz crystal blank, a package with a cavity that houses the quartz crystal blank, and a lid for sealing the cavity. The package includes a substrate that forms the bottom of the cavity, a frame that surrounds the cavity, and a metallized layer provided on the frame. The lid is bonded to the metallized layer using a bonding material (typically, a brazing material).

[0003] During use of a module using the package, such as the above-described crystal unit, the potential of the metallization layer often needs to be appropriately controlled for purposes such as noise prevention, and is typically set to ground potential. For this purpose, the metallization layer is electrically shorted to, for example, an electrode pad for ground potential. This electrical path is typically ensured through a via electrode that penetrates the frame. Specifically, the wiring portion electrically connected to the electrode pad for ground potential and the metallization layer are connected to each other by a via electrode embedded in the frame.

[0004] However, as packages become smaller, the width of the frame material (the dimension between the inner and outer wall surfaces of the frame) becomes smaller, making it difficult to form fine via electrodes that correspond to this. Specifically, it is becoming difficult to form fine via holes in the green sheet that will become the frame after firing in order to place the fine via electrodes.

[0005] When a pin-shaped mold is used as a typical method for forming a via hole, the mechanical strength of the pin tends to be insufficient when the pin shape is made finer to make the via hole finer. Therefore, in mold processing, as the via hole becomes finer, it becomes more difficult to ensure processing efficiency in mass production.

[0006] Therefore, for example, according to the technology disclosed in Japanese Patent Laid-Open Publication No. 2007-27592 (Patent Document 1), instead of via electrodes, castellation electrodes with a roughly crescent shape are provided on the inner wall surface of the frame. However, when castellation electrodes are provided on the side walls of the cavity instead of via electrodes as in the technology of the above publication, the brazing material is likely to flow into the cavity along the castellation electrodes during the process of joining the lid using brazing material. Contact between the flowing brazing material and the crystal blank can adversely affect the performance of the crystal unit. Note that the adverse effect on mechanical characteristics caused by the flowing brazing material is a particular concern when the element mounted in the package is a crystal blank, but it can also occur in other piezoelectric elements, not just crystal blanks. Furthermore, there are concerns about adverse effects on electrical characteristics, such as unintended short circuits, not only for piezoelectric elements but also for other electronic components.

[0007] On the other hand, Japanese Patent Laid-Open Publication No. 2009-234074 (Patent Document 2) discloses a method for forming minute through-holes as via holes in a ceramic green sheet by laser processing technology. Specifically, through-holes with a diameter of 30 μm to 50 μm are formed in a ceramic green sheet having a thickness of 250 μm or less using an ultraviolet laser. By using such laser processing instead of the above-mentioned mold processing, it is possible to ensure the processing efficiency of via holes in the mass production of small packages. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-27592 [Patent Document 2] Japanese Patent Application Laid-Open No. 2009-234074 Summary of the Invention [Problem to be solved by the invention]

[0009] By using laser processing as described above, through holes (via holes) can be formed with sufficient processing efficiency. However, according to the studies of the present inventors, as described above, the smaller the material width of the frame portion becomes with the progress of miniaturization of packages, the greater the concern that cracks will occur in the via holes due to stresses that occur during the manufacture or use of the package.

[0010] The present invention has been made to solve the above-mentioned problems, and its purpose is to provide a package that can suppress the occurrence of cracks in via holes due to stresses that occur during the manufacture or use of the package. [Means for solving the problem]

[0011] A package according to one embodiment has a cavity for hermetically sealing an electronic component by attaching a lid. The package includes a ceramic substrate portion, a substrate wiring portion, a ceramic frame portion, a metallization layer, and a via electrode. The substrate wiring portion is provided on the ceramic substrate portion. The ceramic frame portion has a first surface and a second surface opposite to the first surface and disposed on the ceramic substrate portion on which the substrate wiring portion is provided, and surrounds the cavity. The metallization layer is provided on the first surface of the ceramic frame portion. The via electrode connects the metallization layer and the substrate wiring portion to each other and is disposed in a via hole. The via hole has a frame penetration portion, a wiring penetration portion, and a protrusion portion. The frame penetration portion penetrates the ceramic frame and is filled with the via electrode. The wiring penetration portion extends from the frame penetration portion to penetrate the substrate wiring portion and is filled with the via electrode. The protrusion portion protrudes from the wiring penetration portion into the ceramic substrate portion. [Effects of the Invention]

[0012] According to the above aspect, the via hole has a protruding portion that protrudes into the ceramic substrate portion. As a result, the via electrode disposed in the via hole does not have a bottom surface on the substrate wiring portion, and therefore does not have a corner on the substrate wiring portion. This prevents stress from concentrating on the corner due to at least one of the difference in sintering shrinkage rate between the via electrode and the ceramic substrate portion during the firing process for manufacturing the package and the difference in thermal expansion coefficient between the via electrode and the ceramic substrate portion during use of the package. This prevents cracks from occurring due to stress concentration.

[0013] The protruding portion of the via hole may be tapered, in which case stress in the vicinity of the protruding portion can be reduced.

[0014] The protruding portion of the via hole may be a blind hole provided in the ceramic substrate portion, thereby reducing the depth of the via hole and thus preventing a decrease in the mechanical strength of the ceramic substrate portion due to the via hole.

[0015] The ceramic frame may have a minimum width of 200 μm or less. When the ceramic frame has such minute dimensions, cracks are particularly likely to occur. According to the above aspect, the occurrence of such cracks can be prevented.

[0016] The via electrodes have a diameter of 50 μm or less. Such fine via electrodes allow the ceramic frame to have a fine width. When the ceramic frame has such fine dimensions, cracks are particularly likely to occur. According to the above-described aspect, the occurrence of such cracks can be prevented.

[0017] The package may further include electrode pads onto which a crystal blank serving as the electronic component is mounted. Packages onto which crystal blanks are mounted often have minute design dimensions, making them particularly susceptible to cracking. According to the above aspect, the occurrence of such cracks can be prevented.

[0018] The protruding portion of the via hole may be at least partially filled with the via electrode, thereby more reliably filling the wiring penetration portion, which is a portion of the via hole located shallower than the protruding portion, with the via electrode, thereby more reliably electrically connecting the via electrode to the substrate wiring portion.

[0019] The protruding portion of the via hole may be partially filled with the via electrode so that the protruding portion has a void, which can further relieve stress.

[0020] The via electrode may have a bottom surface that contacts the protruding portion of the via hole, and the bottom surface of the via electrode may be a convex curved surface. In this case, the bottom surface of the via electrode does not have any angular portions. This prevents stress concentration in such angular portions. Therefore, it is possible to prevent cracks from occurring due to the stress concentration.

[0021] The objects, features, aspects, and advantages of the present invention will become more apparent from the following detailed description and the accompanying drawings. [Brief explanation of the drawings]

[0022] [Figure 1] 1 is a plan view schematically illustrating a configuration of a quartz crystal resonator according to a first embodiment. [Figure 2] FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG. [Figure 3] 2 is a plan view schematically showing one step of a method for manufacturing the quartz crystal resonator of FIG. 1. FIG. [Figure 4] FIG. 4 is a schematic cross-sectional view taken along line IV-IV in FIG. 3. [Figure 5] FIG. 1 is a plan view schematically showing a configuration of a package in a first embodiment. [Figure 6] FIG. 6 is a schematic cross-sectional view taken along line VI-VI in FIG. 5. [Figure 7] FIG. 6 is a plan view in which the metallized layer, the ceramic frame, and the via electrodes in FIG. 5 are omitted. [Figure 8] 8 is a plan view schematically showing the substrate portion and substrate via electrodes in FIG. 7, with package electrode pads indicated by dashed lines. FIG. [Figure 9] 6 is a plan view in which the metallized layer on the ceramic frame in FIG. 5 is omitted. [Figure 10] FIG. 6 is a schematic partial cross-sectional view taken along line XX in FIG. 5. [Figure 11] FIG. 11 is a partially enlarged view of FIG. [Figure 12] 3 is a flow chart schematically showing a method for manufacturing a package according to the first embodiment. [Figure 13] 3 is a plan view schematically showing a step of the method for manufacturing the package in the first embodiment. FIG. [Figure 14] 14 is a plan view schematically showing the substrate portion and substrate via electrodes in FIG. 13, with package electrode pads indicated by dashed lines. FIG. [Figure 15] FIG. 15 is a schematic partial cross-sectional view taken along line XV-XV in FIGS. 13 and 14. [Figure 16] 3 is a partial cross-sectional view schematically showing a step in the method for manufacturing the package in the first embodiment. FIG. [Figure 17] 3 is a partial cross-sectional view schematically showing a step in the method for manufacturing the package in the first embodiment. FIG. [Figure 18] 3 is a partial cross-sectional view schematically showing a step in the method for manufacturing the package in the first embodiment. FIG. [Figure 19] 3 is a partial cross-sectional view schematically showing a step in the method for manufacturing the package in the first embodiment. FIG. [Figure 20] 3 is a partial cross-sectional view schematically showing a step in the method for manufacturing the package in the first embodiment. FIG. [Figure 21] 3 is a partial cross-sectional view schematically showing a step in the method for manufacturing the package in the first embodiment. FIG. [Figure 22] FIG. 2 is a partial cross-sectional view showing the configuration of a package in a first comparative example. [Figure 23] FIG. 23 is a partially enlarged view of FIG. 22. [Figure 24] 10 is a partial cross-sectional view showing a step in a method for manufacturing a package in a first comparative example. FIG. [Figure 25] 10 is a partial cross-sectional view showing a step in a method for manufacturing a package in a first comparative example. FIG. [Figure 26] 10 is a partial cross-sectional view showing a step in a method for manufacturing a package in a first comparative example. FIG. [Figure 27] 10 is a partial cross-sectional view showing a step in a method for manufacturing a package in a first comparative example. FIG. [Figure 28] 10 is a partial cross-sectional view showing a step in a method for manufacturing a package in a first comparative example. FIG. [Figure 29] FIG. 10 is a partial cross-sectional view showing a step in a method for manufacturing a package in a second comparative example. [Figure 30] 21A-21C are photomicrographs showing an example of the process shown in FIG. 20. [Figure 31] 12 is a partial cross-sectional view schematically showing the configuration of a package in a second embodiment in a field of view corresponding to FIG. 11. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0023] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0024] <First Embodiment> Fig. 1 is a plan view schematically showing the configuration of a quartz crystal resonator 900 as a module in the first embodiment. Fig. 2 is a schematic cross-sectional view taken along line II-II in Fig. 1. Fig. 3 is a plan view schematically showing the configuration immediately after mounting a quartz crystal blank 890 (electronic component) in a manufacturing method for the quartz crystal resonator 900 (Fig. 1). Fig. 4 is a schematic cross-sectional view taken along line IV-IV in Fig. 3.

[0025] The quartz crystal unit 900 includes a package 701, a quartz crystal blank 890, a brazing material 960, and a lid 980. The package 701 includes a cavity CV for hermetically sealing the quartz crystal blank 890 (electronic component) when the lid 980 is attached. The quartz crystal blank 890 is housed within the cavity CV and mounted on the device electrode pads 211 and 212 of the package 701. The lid 980 is bonded to the metallized layer 600 of the package 701 with the brazing material 960, thereby sealing the cavity CV. The brazing material 960 is typically preferably made of an alloy containing gold, such as an alloy containing gold and tin, or in other words, an Au-Sn alloy. The lid 980 is made of a metal, such as an alloy containing iron and nickel. Note that, in this specification, an alloy is considered to be a type of metal.

[0026] The metallization layer 600 is made of, for example, a metal containing at least one of molybdenum and tungsten. A plating layer, typically a gold plating layer, may be provided on the surface of the metallization layer 600 (the surface facing the brazing material 960). A nickel plating layer may be provided as a base for the gold plating layer. The metallization layer 600, which is provided directly on the frame top surface SF1 of the ceramic frame 120 of the package 701, and the lid 980 may be joined only by the brazing material 960.

[0027] Fig. 5 is a plan view schematically showing the configuration of a package 701. Fig. 6 is a schematic cross-sectional view taken along line VI-VI in Fig. 5. The package 701 includes a ceramic part 100, an element electrode pad 211, an element electrode pad 212, and package electrode pads 301 to 304.

[0028] The ceramic portion 100 is made of ceramic, preferably containing an oxide as a primary component, more preferably containing alumina as a primary component, e.g., substantially consisting of alumina. The ceramic portion 100 includes a ceramic substrate portion 110 and a ceramic frame portion 120 that surrounds a cavity CV on the ceramic substrate portion 110. The ceramic substrate portion 110 and the ceramic frame portion 120 may be made of the same material. The ceramic frame portion 120 is laminated on the ceramic substrate portion 110 in the thickness direction (the vertical direction in FIG. 6). Thus, the ceramic frame portion 120 is disposed on the ceramic substrate portion 110 and surrounds the cavity CV. The ceramic frame portion 120 has a frame upper surface SF1 (first surface) and a frame lower surface SF2 (second surface opposite the first surface in the thickness direction). The ceramic frame portion 120 also has an inner wall surface that connects the frame upper surface SF1 and the frame lower surface SF2 to each other, and this inner wall surface forms the side wall of the cavity CV. The ceramic substrate portion 110 has a substrate upper surface SF3 (third surface). The substrate upper surface SF3 has a support surface portion SF3S that supports the frame lower surface SF2 of the ceramic frame portion 120, and a cavity surface portion SF3C that faces the cavity CV. The cavity surface portion SF3C forms the bottom surface of the cavity CV.

[0029] The package 701 also has a metallized layer 600, to which a lid 980 (FIGS. 1 and 2) is to be bonded, on the top frame surface SF1 of the ceramic frame 120. The package 701 also includes a configuration for electrical wiring provided in the ceramic portion 100, as described below.

[0030] The element electrode pads 211 and 212 (FIG. 5) are arranged on the ceramic part 100 (FIG. 6) facing the cavity CV. Specifically, the element electrode pads 211 and 212 are arranged on the cavity surface portion SF3C of the substrate upper surface SF3 of the ceramic substrate part 110 (FIG. 6). A crystal blank 890 (FIGS. 3 and 4) serving as an electronic component is mounted on the element electrode pads 211 and 212. The package electrode pads 301-304 (FIG. 5) are arranged on the ceramic part 100 (FIG. 6) outside the cavity CV. Specifically, the package electrode pads 301-304 are arranged on the lower surface (the surface opposite to the substrate upper surface SF3) of the ceramic substrate part 110 (FIG. 6).

[0031] The relay electrode 220 (FIG. 5) is provided on the substrate upper surface SF3 of the ceramic substrate portion 110 (FIG. 6). The relay electrode 220 is at least partially disposed on the support surface portion SF3S (FIG. 6). Thus, the relay electrode 220 (FIG. 5) is at least partially covered by the ceramic frame portion 120. The relay electrode 220 may further have a portion that is not covered by the ceramic frame portion 120 and is disposed on the bottom surface of the cavity CV. In other words, the relay electrode 220 may be only partially covered by the ceramic frame portion 120.

[0032] Fig. 7 is a plan view in which the metallized layer 600, the ceramic frame portion 120, and the via electrodes 510 (see Fig. 9) in Fig. 5 are omitted. Fig. 8 is a plan view that schematically shows the ceramic substrate portion 110 and the substrate via electrodes 411-414 in Fig. 7, with the package electrode pads 301-304 indicated by dashed lines.

[0033] Wiring layers 401 to 403 are embedded in the ceramic substrate part 110 of the ceramic part 100 near its upper surface. The wiring layer 401 is in contact with the element electrode pad 211, the wiring layer 402 is in contact with the element electrode pad 212, and the wiring layer 403 is in contact with the relay electrode 220. The wiring layers 401 to 403 may be covered with an insulating film 110i (see FIG. 10) as part of the ceramic substrate part 110 to the extent that this contact is not hindered, and in particular, the element electrode pad 211 and the wiring layer 403 are insulated by the insulating film 110i. The wiring layer 403 and the relay electrode 220 form a substrate wiring part 200. The substrate wiring part 200 is part of the package 701 and is provided on the ceramic substrate part 110. The thickness of the substrate wiring part 200 is, for example, 5 μm or more and 20 μm or less.

[0034] The package 701 has substrate via electrodes 411 to 414 embedded in the ceramic substrate portion 110. The substrate via electrode 411 connects the wiring layer 402 and the package electrode pad 301 to each other. The substrate via electrode 412 connects the wiring layer 403 and the package electrode pad 302 to each other. The substrate via electrode 413 connects the wiring layer 401 and the package electrode pad 303 to each other. The substrate via electrode 414 connects the wiring layer 403 and the package electrode pad 304 to each other.

[0035] With the above configuration, the element electrode pad 211 is electrically connected to the package electrode pad 303, the element electrode pad 212 is electrically connected to the package electrode pad 301, and the relay electrode 220 is electrically connected to the package electrode pad 302 and the package electrode pad 304.

[0036] Fig. 9 is a plan view in which the metallization layer 600 in Fig. 5 is omitted. Fig. 10 is a schematic partial cross-sectional view taken along line XX in each of Fig. 5 and Fig. 7 to Fig. 9. Fig. 11 is a partially enlarged view of Fig. 10.

[0037] Referring to FIG. 9, the minimum width of the ceramic frame 120, i.e., the minimum dimension between the inner wall surface EI (the surface facing the cavity CV) and the outer wall surface EO (the surface opposite to the inner wall surface EI) of the ceramic frame 120, may be 200 μm or less, and is typically 20 μm or more and 110 μm or less.

[0038] As described above, the wiring layer 403 and the relay electrode 220 form the substrate wiring portion 200 on the substrate upper surface SF3 of the ceramic substrate portion 110. Also, as described above, the ceramic substrate portion 110 has an insulating film 110i (FIG. 10) as a part thereof. The frame lower surface SF2 (FIG. 10) of the ceramic frame portion 120 is disposed on the ceramic substrate portion 110 on which the substrate wiring portion 200 is provided.

[0039] As a modification, the insulating film 110i may be omitted depending on the package design. The substrate wiring unit 200 may be configured with only either the wiring layer 403 or the relay electrode 220. For example, the substrate wiring unit 200 may have the wiring layer 403 but omit the relay electrode 220. In this case, the boundary position between the wiring layer 403 and the insulating film 110i (the right end position of the wiring layer 403 in FIG. 10 ) may be shifted to the end position of the relay electrode 220 on the support surface portion SF3S (the right end position of the relay electrode 220 in FIG. 10 ), and the relay electrode 220 may be omitted. The end of the insulating film 110i facing the cavity CV may be deformed to reach the ceramic frame 120. In this case, the substrate wiring unit 200 may be separated from the cavity CV by the insulating film 110i. 10, substrate wiring portion 200 typically spans support surface portion SF3S and cavity surface portion SF3C, but as a variant, it may be disposed only on support surface portion SF3S. In the present embodiment, substrate wiring portion 200 has an end away from the outer edge of frame lower surface SF2 of ceramic frame 120 (the right end of frame lower surface SF2 in FIG. 10), but this end may reach the outer edge.

[0040] The package 701 has a via electrode 510. The via electrode 510 has an end face SFA on the frame top surface SF1 and a bottom face SFB on the opposite side of the end face SFA. The end face SFA of the via electrode 510 may be substantially circular in shape, and the approximate circle of this shape may have a diameter of 10 μm to 50 μm. The thickness of the via electrode 510 (the vertical dimension in FIG. 10) is, for example, 50 μm to 250 μm.

[0041] As shown in FIG. 10 , the via electrode 510 penetrates the ceramic frame 120 between the frame upper surface SF1 and the frame lower surface SF2 and reaches the substrate wiring portion 200; specifically, it reaches the relay electrode 220 of the substrate wiring portion 200. As a result, the via electrode 510 connects the metallized layer 600 and the substrate wiring portion 200 to each other. The via electrode 510 electrically shorts the metallized layer 600 to the substrate wiring portion 200. As described above, the relay electrode 220 is in contact with the wiring layer 403, and the substrate via electrode 412 and the substrate via electrode 414 are connected to the wiring layer 403 ( FIG. 7 ). Therefore, the substrate via electrode 412 and the substrate via electrode 414 are electrically connected to the via electrode 510. Furthermore, the end face SFA of the via electrode 510 is in contact with the metallized layer 600. 8, the metallization layer 600 is electrically connected to the package electrode pad 302 and the package electrode pad 304 via the substrate via electrode 412 and the substrate via electrode 414, respectively. Therefore, by setting the potentials of the package electrode pad 302 and the package electrode pad 304 as a reference potential, the potential of the metallization layer 600 can also be set as a reference potential. The reference potential is typically the ground potential.

[0042] As described above, the via electrode 510 is disposed in the via hole VH (FIG. 11) so as to penetrate the ceramic frame 120 and reach the substrate wiring part 200. The thickness of the via hole VH (the vertical dimension in FIG. 11) is, for example, not less than 50 μm and not more than 250 μm.

[0043] As shown in FIG. 11 , the via hole VH has a frame-penetrating portion VH1, a wiring-penetrating portion VH2, and a protruding portion VH3. The frame-penetrating portion VH1 penetrates the ceramic frame portion 120 and is filled with a via electrode 510. The wiring-penetrating portion VH2 extends from the frame-penetrating portion VH1 and penetrates the substrate wiring portion 200 and is filled with a via electrode 510. The protruding portion VH3 protrudes from the wiring-penetrating portion VH2 into the ceramic substrate portion 110. In this embodiment, the protruding portion VH3 of the via hole VH is tapered in the protruding direction of the protruding portion VH3 (downward in FIG. 11 ). The protruding portion VH3 is a blind hole provided in the ceramic substrate portion 110. The protruding portion VH3 is at least partially filled with the via electrode 510, and in the configuration shown in FIG. 11 , the protruding portion VH3 is substantially entirely filled. In this configuration, the via electrode 510 has a bottom surface SFB that contacts the protrusion VH3, and the bottom surface SFB is a convex curved surface.

[0044] Fig. 12 is a flow diagram schematically showing a method for manufacturing package 701 in accordance with the first embodiment. Fig. 13 is a plan view schematically showing one step in the method for manufacturing package 701 in accordance with the first embodiment. Fig. 14 is a plan view schematically showing ceramic substrate portion 110 and substrate via electrodes 411-414 in Fig. 13 with package electrode pads 301-304 indicated by dashed lines. Fig. 15 is a schematic partial cross-sectional view taken along line XV-XV in Figs. 13 and 14. Figs. 16 to 21 are partial cross-sectional views schematically showing one step in the method for manufacturing the package in accordance with the first embodiment.

[0045] 13 to 15, in step ST100 (FIG. 12), the ceramic substrate portion 110 provided with the substrate wiring portion 200 is formed as a substrate green body GS. In this specification, "green body" refers to a configuration that becomes a ceramic body when fired. The green body is typically a powder compact. To facilitate powder molding and handling, the green body may contain a glass component and an organic component as additives in addition to the main component. The organic component may include, for example, polyvinyl butyral or acrylic. The green body may be formed by any method, but a green sheet as the green body may be formed by, for example, a doctor blade method. Another green body may be added to this green sheet, and this addition is typically performed by printing on the green sheet or laminating another green sheet. The printing is typically performed by a screen printing method. The main component of the green body that becomes the ceramic portion 100 when fired may be, for example, alumina powder. The main component of the green body that becomes the substrate wiring portion 200 and the via electrode 510 by firing may be, for example, tungsten (W) powder, molybdenum (Mo) powder, a mixed powder of W powder and Mo powder, or a W-Mo alloy powder.

[0046] Specifically, first, a green sheet that will become the ceramic substrate portion 110 is formed. Via holes are formed in this green sheet by punching, and an electrode paste is printed into the via holes to form a green body that will become the substrate via electrodes 411-414. The electrode paste contains, for example, a powder of at least one of tungsten and molybdenum dispersed therein. Next, an electrode paste is printed on this green sheet to form a green body that will become the wiring layers 401-403. Next, a ceramic paste is printed on this green sheet to form a green body that will become the insulating film 110i. Next, an electrode paste is printed on this green sheet to form a green body that will become the element electrode pads 211 and 212 and the relay electrode 220. Furthermore, at any timing after the green body that will become the substrate via electrodes 411-414 is formed as described above, an electrode paste is printed on this green sheet to form a green body that will become the package electrode pads 301-304.

[0047] 16 and 17, in step ST200 (FIG. 12), the ceramic frame 120 is formed as a frame-shaped green sheet GF having a frame shape surrounding a cavity CV. Specifically, first, as shown in FIG. 16, a green sheet that will become the ceramic frame 120 is formed. Next, as shown in FIG. 17, the cavity CV is formed by punching. Note that the order of steps ST100 and ST200 (FIG. 12) is arbitrary.

[0048] 18, in step ST300 (FIG. 12), a frame-shaped green sheet GF (see FIG. 17) is laminated on a substrate green body GS (see FIG. 15).

[0049] 19 in addition to FIG. 18, in step ST400 (FIG. 12), via holes VH are formed by performing laser processing. A laser processing system, which is a system for performing laser processing, includes a table that supports a workpiece to be irradiated with laser light, a laser device that irradiates the workpiece with the desired laser light, and a control unit that controls the table and the laser device.

[0050] The laser device includes a laser oscillator, a collimator lens, a mask, a bent mirror, a scan head, a table, and a camera. The laser oscillator, for example, a CO2 laser oscillator, generates laser light. The generated laser light is collimated by a collimator lens. The collimated light passes through a mask to form a laser beam with an adjusted beam width. The direction of the laser beam may be adjusted by a bent mirror, if necessary. The scan head, to which the laser beam is supplied, focuses the laser beam at a desired position on a workpiece supported on the table. To control this position, the scan head may have a galvanometer scanner that can adjust the position where the laser beam is irradiated to any position in two dimensions parallel to the table. The scan head may also have a focusing lens between the galvanometer scanner and the workpiece to focus the laser beam.

[0051] The control unit may be configured by a general computer having electrical circuits, which includes a central processing unit (CPU), read only memory (ROM), random access memory (RAM), storage device, input unit, display unit, and communication unit, as well as a bus line connecting these units together.

[0052] In this embodiment, step ST400 includes steps ST411, ST412, and ST421. In step ST411 (FIG. 12), the position of the cavity CV in the frame-shaped green sheet GF is recognized. Specifically, the laser processing system recognizes the position of the cavity CV in the frame-shaped green sheet GF using its camera. This recognition may be performed using a normal image recognition technique. In step ST412 (FIG. 12), the position where laser processing will be performed is determined based on the position recognized in step ST411 (FIG. 12). For example, the control unit of the laser processing system determines a predetermined relative position from the recognized position as the position where laser processing will be performed. In step ST421 (FIG. 12), a via hole VH (FIG. 19) is formed by irradiating laser light, as shown in FIG. 19. For example, a process of irradiating two pulses of laser light with a wavelength of 9.3 μm or more and 10.7 μm or less from a CO 2 laser oscillator with an average output of 10 W or more and 250 W or less for an irradiation time of 6 μs is repeated five times.

[0053] 19, the via hole VH is formed so as to penetrate through the substrate wiring part 200 and also into the ceramic substrate part 110. The via hole VH may have a substantially circular shape in a cross section along the upper surface of the substrate wiring part 200 (the surface facing the frame upper surface SF1), and the approximate circle of this shape has a diameter of, for example, 10 μm or more and 40 μm or less.

[0054] 20, in step ST500 (FIG. 12), via electrodes 510 (see FIG. 10) are formed as electrode green bodies G510 in the via holes VH (FIG. 19) of the frame-shaped green sheet GF. The electrode green bodies G510 are green bodies that will become the via electrodes 510 (see FIG. 10) when fired. The electrode green bodies G510 may be formed by filling the via holes VH with an electrode paste by screen printing.

[0055] 21, the metallized layer (see FIG. 10) is formed as a metallized green body G600. The metallized green body G600 is a green body that becomes the metallized layer 600 (see FIG. 10) when fired. The metallized green body G600 is formed by applying an electrode paste, and the application is performed by, for example, a screen printing method.

[0056] In step ST600 (FIG. 12), the substrate green body GS, the frame-shaped green sheet GF, the electrode green body G510, and the metallized green body G600 are fired. If necessary, a plating process may be performed after firing. This completes the process to obtain package 701 (FIG. 10).

[0057] 13 to 21, a method for manufacturing one package has been described for the sake of simplicity. However, for efficient mass production, a sintered body having a configuration in which multiple packages are connected to each other in the in-plane direction is formed, and then the sintered body is divided to obtain multiple packages. This technique is well known, and may be applied to the present embodiment. In this case, the outer wall surface SF4 of the package 701 may be formed by a dividing step after firing.

[0058] Fig. 22 is a partial cross-sectional view showing the configuration of a package 711 in a first comparative example, and Fig. 23 is a partial enlarged view of Fig. 22. The via hole VH0 (Fig. 23) of the package 711 has a portion corresponding to the frame-penetrating portion VH1 of the via hole VH (Fig. 11), but does not have portions corresponding to the wiring-penetrating portion VH2 and the protruding portion VH3 of the via hole VH (Fig. 11).

[0059] 24 to 28 are partial cross-sectional views showing steps in a manufacturing method of a package 711 in the first comparative example. First, a frame-shaped green sheet GFc is formed by the steps of FIGS. 24 to 27. Specifically, with reference to FIG. 24, a via hole VH0 is formed before the cavity CV (Embodiment 1: FIG. 17) is formed. With reference to FIG. 25, a via electrode 510 (see FIG. 22) is formed as an electrode green body G510 in the via hole VH0. With reference to FIG. 26, a metallized layer (see FIG. 22) is formed as a metallized green body G600. With reference to FIG. 27, a cavity CV is then formed. At this time, unnecessary portions of the metallized green body G600 are removed. In this manner, a frame-shaped green sheet GFc is formed. With reference to FIG. 28, the frame-shaped green sheet GFc (see FIG. 27) is stacked on the substrate green body GS (see FIG. 15). This stack is fired to obtain a package 711 (FIG. 22).

[0060] The first drawback of the first comparative example is that when the via hole VH0 is formed (FIG. 24), the cavity CV (FIG. 27) has not yet been formed, so the position of the cavity CV (FIG. 27) cannot be used as a reference. As a result, it is difficult to ensure sufficient positional accuracy of the via hole VH0 relative to the cavity CV and the substrate wiring portion 200. The second drawback is that stress tends to concentrate at the corners CN (FIG. 23) of the via electrode 510 due to differences in sintering shrinkage between the via electrode 510 and the ceramic substrate portion 110 during the firing process. This stress concentration can cause cracks.

[0061] FIG. 29 is a partial cross-sectional view schematically illustrating a step in a package manufacturing method according to the second comparative example. In this comparative example, after the same steps as those of the first embodiment are performed up to the step shown in FIG. 18, a via hole VH0 having the shape described in the first comparative example 1 is formed by laser processing, instead of the via hole VH (first embodiment: FIG. 19). In this case, the first drawback described above can be resolved, but the second drawback cannot be resolved. Furthermore, a third drawback is that precise control of the laser processing is required to accurately stop the bottom surface SH (FIG. 29) of the via hole VH0 on the board wiring portion 200 without penetrating the board wiring portion 200. As a result, manufacturing efficiency is likely to be sacrificed.

[0062] 30 is a micrograph showing a state in which the via hole VH (see FIG. 19) is filled with the electrode green body G510 (see FIG. 20) in an example of the manufacturing method of the package 701 according to the present embodiment 1. As described above, the inventors conducted experiments on the manufacturing method according to the present embodiment 1 and confirmed that the manufacturing method is practical.

[0063] According to this embodiment, the via hole VH (FIG. 11) has a protrusion VH3 that protrudes into the ceramic substrate portion 110. As a result, the via electrode 510 disposed in the via hole VH does not have a bottom surface SFB on the substrate wiring portion 200 (see FIG. 11), and therefore does not have a corner CN (FIG. 23) on the substrate wiring portion 200. This prevents stress from concentrating on the corner CN due to at least one of the difference in sintering shrinkage rate between the via electrode 510 and the ceramic substrate portion 110 during the firing process for manufacturing the package 701 and the difference in thermal expansion coefficient between the via electrode 510 and the ceramic substrate portion 110 during use of the package 701. This prevents cracks from occurring due to stress concentration.

[0064] Furthermore, since the via hole VH (FIG. 11) has the protruding portion VH3 protruding into the ceramic substrate portion 110 as described above, the via hole VH can be formed so as to penetrate the ceramic frame portion 120 and the substrate wiring portion 200 and protrude into the ceramic substrate portion 110 in the via hole VH formation step (FIG. 19) before the firing step in manufacturing the package 701. Therefore, the via hole VH can be formed based on the position of the cavity CV, which is the area surrounded by the ceramic frame portion 120. This improves the positional accuracy of the via hole VH in the package 701.

[0065] Specifically, when the via hole VH is formed, the position of the cavity CV is recognized in step ST411 (FIG. 12), and the position to be laser processed is determined in step ST412 (FIG. 12) based on the recognized position. This increases the accuracy of the relative position between the cavity CV and the via hole VH. Furthermore, since the cavity CV has a relatively large dimension, the recognition (typically image recognition) can be easily performed. The accuracy of the relative position between the via hole VH and the substrate wiring portion 200 (see FIG. 7) is usually sufficiently ensured by ensuring the accuracy of the relative position by referring to the position of the cavity CV and the position of the substrate wiring portion 200 (or a position corresponding thereto) in the lamination process of the substrate green body GS (FIG. 15) and the frame-shaped green sheet GF (FIG. 17). However, if particular accuracy in the relative position between the via hole VH and the substrate wiring portion 200 is required, in addition to recognizing the position of the cavity CV (step ST411), the position of the substrate wiring portion 200 (or a position corresponding thereto) may also be recognized, and then laser processing of the via hole VH may be performed using both of these positions as references.

[0066] Furthermore, when the via hole VH (FIG. 11) has a protruding portion VH3 that protrudes into the ceramic substrate portion 110 as described above, there is no need to precisely stop the bottom surface of the via hole VH on the substrate wiring portion 200 during laser processing without penetrating the substrate wiring portion 200. This makes it easier to control the laser processing, thereby improving the efficiency of the laser processing.

[0067] The protruding portion VH3 of the via hole VH may be tapered. In this case, first, stress in the vicinity of the protruding portion VH3 can be reduced. Second, laser processing can be easily applied as a method for forming the via hole VH.

[0068] The protruding portion VH3 of the via hole VH may be a blind hole provided in the ceramic substrate portion 110. This makes it possible, firstly, to reduce the depth of the via hole VH, thereby suppressing a decrease in the mechanical strength of the ceramic substrate portion 110 due to the via hole VH.

[0069] The ceramic frame 120 may have a minimum width of 200 μm or less. When the ceramic frame 120 has such minute dimensions, first, cracks are particularly likely to occur. According to this embodiment, the occurrence of such cracks can be prevented. Second, there is a particularly high need to improve the relative positional accuracy between the ceramic frame 120 and the via holes VH. According to this embodiment, this need can be met.

[0070] The via electrode 510 has a diameter of 50 μm or less. Such a fine via electrode 510 allows the ceramic frame 120 to have a fine width. When the ceramic frame 120 has such fine dimensions, firstly, cracks are particularly likely to occur. According to this embodiment, such cracks can be prevented. Secondly, there is a particularly high need to improve the relative positional accuracy between the ceramic frame 120 and the via hole VH. According to this embodiment, this need can be met.

[0071] The package 701 may further include a metallization layer 600 on the ceramic frame 120, to which the lid 980 will be bonded. The metallization layer 600 is electrically shorted to the substrate wiring portion 200 by a via electrode 510. In this case, the potential of the metallization layer 600 can be controlled to the potential of the substrate wiring portion 200.

[0072] The package 701 may further include element electrode pads 211, 212 on which a crystal blank 890 serving as an electronic component 890 is mounted. The package 701 on which the crystal blank 890 is mounted often has minute design dimensions. In such cases, firstly, cracks are particularly likely to occur. This embodiment can prevent such cracks from occurring. Secondly, there is a particularly high need to improve the positional accuracy of the via holes VH in the package 701. This embodiment can fulfill this need.

[0073] The protruding portion VH3 of the via hole VH may be at least partially filled with the via electrode 510. This allows the wiring penetrating portion VH2, which is a portion of the via hole VH located shallower than the protruding portion VH3, to be more reliably filled with the via electrode 510. This allows the via electrode 510 to be electrically connected to the substrate wiring portion 200 more reliably.

[0074] The via electrode 510 may have a bottom surface SFB that contacts the protruding portion VH3 of the via hole VH, and the bottom surface SFB of the via electrode 510 may be a convex curved surface. In this case, the bottom surface SFB of the via electrode 510 does not have any angular portions. This prevents stress from concentrating on such angular portions. Therefore, it is possible to prevent cracks from occurring due to the stress concentration.

[0075] <Embodiment 2> FIG. 31 is a partial cross-sectional view schematically illustrating the configuration of a package 702 according to the second embodiment, in a field of view corresponding to FIG. 11. In this embodiment, the protruding portion VH3 of the via hole VH is partially filled with the via electrode 510 so that the protruding portion VH3 has a gap GP. The gap GP does not reach the wiring penetration portion VH2. In other words, the gap GP in the via hole VH is located lower than the substrate wiring portion 200 in the figure. The bottom surface SFB of the via electrode 510 is separated from the ceramic substrate portion 110 by the gap GP. The gap GP is obtained by incompletely filling the via hole VH with the electrode paste for forming the electrode green body G510 (see FIG. 20). Other than these features, the second embodiment is substantially the same as the first embodiment, and therefore description thereof will not be repeated.

[0076] According to the present embodiment, the protrusion VH3 of the via hole VH is partially filled with the via electrode 510 so that the protrusion VH3 has a gap GP. This gap GP can further relieve the stress described in the first embodiment.

[0077] The first and second embodiments and their modifications of the present invention have been described above. These embodiments and modifications may be freely combined with each other as long as they do not contradict each other. [Explanation of symbols]

[0078] 110: Ceramic substrate section 110i: insulating film 120: Ceramic frame 200: PCB wiring section 211, 212: Element electrode pads 220: Relay electrode 510: Via electrode 600: Metallized layer 701, 702: Package 890: Crystal blank (electronic component) 900: Crystal oscillator 980: Lid CN: Corner CV: Cavity GP: void VH: Via hole VH1: Frame penetration part VH2: Wiring penetration part VH3:Protrusion

Claims

1. A package having a cavity for hermetically sealing an electronic component by attaching a lid, a ceramic substrate portion; a substrate wiring portion provided on the ceramic substrate portion; a ceramic frame portion having a first surface and a second surface opposite to the first surface and disposed on the ceramic substrate portion on which the substrate wiring portion is provided, the ceramic frame portion surrounding the cavity; a metallized layer disposed on the first surface of the ceramic frame; a via electrode that connects the metallized layer and the substrate wiring portion to each other and is disposed in the via hole; Equipped with The via hole is a frame penetration portion that penetrates the ceramic frame portion and is filled with the via electrode; a wiring penetration portion that extends from the frame penetration portion, penetrates the substrate wiring portion, and is filled with the via electrode; a protruding portion protruding from the wiring penetration portion into the ceramic substrate portion; It has package.

2. The package of claim 1 , wherein the protruding portion of the via hole is tapered.

3. 3. The package according to claim 1, wherein the protruding portion of the via hole is a blind hole provided in the ceramic substrate portion.

4. 4. The package of claim 1, wherein the ceramic frame has a minimum width of 200 [mu]m or less.

5. The package according to claim 1 , wherein the via electrode has a diameter of 50 μm or less.

6. The package according to claim 1 , further comprising electrode pads onto which a crystal blank serving as the electronic component is to be mounted.

7. The package according to claim 1 , wherein the protruding portion of the via hole is at least partially filled with the via electrode.

8. The package according to claim 1 , wherein the protruding portion of the via hole is partially filled with the via electrode such that the protruding portion has a void.

9. The package according to claim 1 , wherein the via electrode has a bottom surface that contacts the protruding portion of the via hole, and the bottom surface of the via electrode is a convex curved surface.

10. A package described in any one of claims 1 to 9, wherein the material of the ceramic substrate portion and the material of the ceramic frame portion are primarily composed of alumina.

11. A package described in any one of claims 1 to 10, wherein the material of the ceramic substrate portion and the material of the ceramic frame portion are the same.

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