Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device capable of efficiently discharging carriers to an emitter side at turning off, and a manufacturing method of the same.SOLUTION: In a region of a semiconductor substrate SUB positioned between a trench gate electrode TGE and a trench emitter electrode TEE which are arranged with a distance therebetween, a source diffusion layer SDR and a base diffusion layer BDR are formed. On the trench emitter electrode TEE, base diffusion layer BDR, and an insulation film EIF, a recess section RCS is formed while retracting from a first main surface to a second main surface. A shared contact member CCN projects from the first main surface toward the second main surface in a mode being brought into contact with the recess section RCS.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and can be suitably used, for example, in a semiconductor device including an electron injection enhanced trench insulated gate bipolar transistor. [Background technology]

[0002] Among power semiconductor devices, there are semiconductor devices equipped with trench insulated gate bipolar transistors (IGBTs) as switching elements, and some of these semiconductor devices have an enhanced injection enhancement (IE) effect to reduce on-state voltage.

[0003] In this type of semiconductor device, a region is formed that prevents holes injected from the collector side from escaping to the emitter (electrode) side. This increases the concentration of holes accumulated in the drift layer in the semiconductor substrate, promoting the injection of electrons from the emitter side and increasing the electron concentration. The increased concentration of carriers (electrons and holes) causes conductivity modulation, which can reduce the on-state voltage. For this type of semiconductor device, various arrangement patterns of trench gate electrodes and the like have been proposed depending on the application (Patent Document 1 and Patent Document 2). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2019-29434 [Patent Document 2] Japanese Patent Application Laid-Open No. 2013-140885 Summary of the Invention [Problem to be solved by the invention]

[0005] In semiconductor devices, it is necessary to shorten the time it takes to turn off in order to reduce turn-off loss when switching from the on state to the off state, i.e., to efficiently discharge carriers (holes) accumulated in the drift layer to the emitter (electrode).

[0006] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] A semiconductor device according to one embodiment includes a trench insulated gate bipolar transistor having an emitter electrode, a collector electrode, and a gate electrode. The semiconductor device includes a first conductivity type semiconductor substrate, multiple trench electrodes, multiple impurity regions, an interlayer insulating film, and multiple contact members. The first conductivity type semiconductor substrate has opposing first and second main surfaces. A gate electrode and an emitter electrode are formed on the first main surface, and a collector electrode is formed on the second main surface. The multiple trench electrodes are formed from the first main surface toward the second main surface of the semiconductor substrate, and include first trench emitter electrodes electrically connected to the emitter electrode and first trench gate electrodes electrically connected to the gate electrode. The multiple impurity regions include first impurity regions of a second conductivity type having a first impurity concentration formed in a first region of the semiconductor substrate. The interlayer insulating film is formed to cover the first main surface of the semiconductor substrate. The multiple contact members are formed to penetrate the interlayer insulating film and include first contact members electrically connected to the emitter electrode. The first trench emitter electrode is formed in the emitter trench with a trench insulating film interposed therebetween. The trench insulating film is interposed between the first region and the first trench emitter electrode, with the first region in the semiconductor substrate in contact with the trench insulating film. The first impurity region is formed in the first region of the semiconductor substrate at a position whose depth from the first main surface is shallower than the first depth. A recess portion is formed in the first trench emitter electrode, the trench insulating film, and the first impurity region, spanning between the first trench emitter electrode and the first impurity region and recessed from the first main surface toward the second main surface. The recess portion includes a first recess portion, a second recess portion, and a third recess portion. The first recess portion is formed in the first impurity region and is located at a second depth from the first main surface that is shallower than the first depth. The second recess portion is formed in the first trench emitter electrode and is located at a third depth from the first main surface that is deeper than the second depth but shallower than the first depth. The third recess portion is formed in the trench insulating film and is located at a fourth depth from the first main surface that is deeper than the third depth but shallower than the first depth. The first contact member protrudes from the first main surface toward the second main surface in contact with the recess portion.

[0008] A method for manufacturing a semiconductor device according to another embodiment includes the steps of: preparing a semiconductor substrate of a first conductivity type having a first main surface and a second main surface facing each other; forming a plurality of trenches; forming trench electrodes in each of the plurality of trenches; forming a plurality of impurity regions; forming an interlayer insulating film covering the first main surface of the semiconductor substrate; forming a plurality of contact openings; forming contact members in each of the plurality of contact openings; and forming a plurality of conductive layers. The step of forming the plurality of trenches includes forming first emitter trenches and first gate trenches from the first main surface toward the second main surface of the semiconductor substrate. The step of forming the plurality of impurity regions includes forming a first impurity region of a second conductivity type in a first region of the semiconductor substrate that is in contact with the trench insulating film and on the side opposite to the side where the first trench emitter electrode is located. The step of forming the plurality of contact openings includes forming first contact openings that penetrate the interlayer insulating film and straddle the first trench emitter electrode, the trench insulating film, and the first impurity region. The step of forming contact members in each of the plurality of contact openings includes forming first contact members in the first contact openings. The step of forming the plurality of conductive layers includes forming a first conductive layer on the interlayer insulating film, the first conductive layer being electrically connected to the first contact members. In the step of forming the first contact openings, recesses are formed in the first trench emitter electrode, the trench insulating film, and the first impurity region, recessed from the first main surface toward the second main surface. In the step of forming the first contact members, the first contact members are formed to protrude from the first main surface toward the second main surface and in contact with the first trench emitter electrode and the first impurity region in which the recesses are formed. In the step of forming the first conductive layer, the first conductive layer is formed as an emitter electrode. [Effects of the Invention]

[0009] According to the semiconductor device of the embodiment, accumulated carriers can be efficiently discharged to the emitter electrode.

[0010] According to the method for manufacturing a semiconductor device according to another embodiment, it is possible to manufacture a semiconductor device that can efficiently discharge accumulated carriers to the emitter electrode. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a plan view illustrating an example of a semiconductor device according to each embodiment. [Figure 2] 1 is a partial plan view showing an example of a planar structure of a semiconductor device according to a first embodiment. [Figure 3] 3 is a cross-sectional view showing the cross-sectional structures along the cross-sectional lines IIIa-IIIa, IIIb-IIIb, and IIIc-IIIc shown in FIG. 2 in the embodiment. [Figure 4] FIG. 2 is a partially enlarged cross-sectional view showing the structure of a recess portion and a common contact member in the embodiment. [Figure 5] 2 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device in the embodiment. FIG. [Figure 6] 6 is a cross-sectional view showing a step performed after the step shown in FIG. 5 in the embodiment. [Figure 7] 7 is a cross-sectional view showing a step performed after the step shown in FIG. 6 in the embodiment. [Figure 8] 8 is a cross-sectional view showing a step performed after the step shown in FIG. 7 in the embodiment. [Figure 9] 9 is a cross-sectional view showing a step performed after the step shown in FIG. 8 in the embodiment. [Figure 10] 10 is a cross-sectional view showing a step performed after the step shown in FIG. 9 in the embodiment. [Figure 11] 11 is a cross-sectional view showing a step performed after the step shown in FIG. 10 in the embodiment. [Figure 12]12 is a cross-sectional view showing a step performed after the step shown in FIG. 11 in the embodiment. [Figure 13] 13 is a cross-sectional view showing a step performed after the step shown in FIG. 12 in the embodiment. [Figure 14] 14 is a cross-sectional view showing a step performed after the step shown in FIG. 13 in the embodiment. [Figure 15] 15 is a cross-sectional view showing a step performed after the step shown in FIG. 14 in the embodiment. [Figure 16] FIG. 16 is a partially enlarged cross-sectional view of the step shown in FIG. 15 in the embodiment. [Figure 17] 17 is a cross-sectional view showing a step performed after the step shown in FIGS. 15 and 16 in the embodiment. FIG. [Figure 18] 18 is a cross-sectional view showing a step performed after the step shown in FIG. 17 in the embodiment. [Figure 19] 10 is a graph qualitatively showing the dependency of on-voltage on the relationship between the depth of the base diffusion layer and the position of the insulating film in the embodiment. [Figure 20] FIG. 10 is a partial plan view showing an example of the planar structure of a semiconductor device according to a second embodiment. [Figure 21] 21 is a cross-sectional view showing the cross-sectional structures along the cross-sectional lines XXIa-XXIa, XXIb-XXIb, and XXIc-XXIc shown in FIG. 20 in the embodiment. [Figure 22] FIG. 2 is a partially enlarged cross-sectional view showing the structure of a recess portion and a common contact member in the embodiment. [Figure 23] 2 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device in the embodiment. FIG. [Figure 24] 24 is a cross-sectional view showing a step performed after the step shown in FIG. 23 in the embodiment. [Figure 25] 25 is a cross-sectional view showing a step performed after the step shown in FIG. 24 in the embodiment. [Figure 26]26 is a cross-sectional view showing a step performed after the step shown in FIG. 25 in the embodiment. [Figure 27] 27 is a cross-sectional view showing a step performed after the step shown in FIG. 26 in the embodiment. [Figure 28] FIG. 28 is a partially enlarged cross-sectional view of the step shown in FIG. 27 in the embodiment. [Figure 29] 29 is a cross-sectional view showing a step performed after the step shown in FIGS. 27 and 28 in the embodiment. FIG. [Figure 30] FIG. 30 is a cross-sectional view showing a step performed after the step shown in FIG. 29 in this embodiment. [Figure 31] FIG. 11 is a cross-sectional view showing an example of a cross-sectional structure of a semiconductor device according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] As mentioned above, semiconductor devices with IE-type trench insulated gate bipolar transistors have various trench gate electrode arrangement patterns depending on the application. For example, there is a GE-type semiconductor device that prioritizes reducing on-state voltage. The GE-type has a structure in which a trench gate electrode electrically connected to the gate electrode and a trench emitter electrode electrically connected to the emitter electrode are arranged at a distance from each other.

[0013] Furthermore, a semiconductor device that emphasizes operational stability and balance is the GGEE type semiconductor device. The GGEE type has a structure in which one trench emitter electrode and another trench emitter electrode are arranged at a distance from each other, and one trench gate electrode and another trench gate electrode are arranged at a distance from each other. The one trench emitter electrode and another trench emitter electrode, and the one trench gate electrode and another trench gate electrode are arranged at a predetermined distance from each other.

[0014] Furthermore, semiconductor devices that prioritize high-speed performance include EGE type semiconductor devices. The EGE type has a structure in which one trench emitter electrode, a trench gate electrode, and another trench emitter electrode are arranged with a gap between them. This will be explained in detail below.

[0015] First, an example of the overall structure of a semiconductor device including an IE-type trench insulated gate bipolar transistor will be described. As shown in Figure 1, a semiconductor device SED (semiconductor substrate SUB) includes a cell region CER and a gate wiring lead-out region MGR.

[0016] An IE-type trench insulated gate bipolar transistor is formed in the cell region CER. An emitter electrode MEE is formed in the cell region CER so as to cover the cell region CER. The emitter electrode MEE is exposed at the bottom of an opening HK1 formed in an insulating film (not shown) covering the emitter electrode MEE (semiconductor substrate SUB).

[0017] The gate wiring lead-out region MGR is arranged to surround the cell region CER. Gate wiring lead-out lines MGI and gate electrodes MGE are formed in the gate wiring lead-out region MGR. The gate wiring lead-out lines MGI are electrically connected to the gate electrodes MGE. The gate electrodes MGE are exposed at the bottom of openings HK2 formed in an insulating film (not shown) covering the gate electrodes MGE (semiconductor substrate SUB).

[0018] Furthermore, the semiconductor device SED (semiconductor substrate SUB) has defined therein a peripheral element region PDR in which peripheral elements such as protection diodes or temperature sensing diodes are formed.

[0019] Embodiment 1 Here, an example of a GE type semiconductor device SED will be described. First, the cell region CER will be described. As shown in Figures 2 and 3, in the cell region CER, a trench gate electrode TGE (first trench gate electrode) and a trench emitter electrode TEE (first trench emitter electrode) are arranged in one direction with an interval therebetween. The trench gate electrode TGE and the trench emitter electrode TEE each extend in another direction intersecting the one direction.

[0020] The trench gate electrode TGE is a trench TRC (first 2 To Wrench) inside the insulating film GIF (Second insulating film) The trench emitter electrode TEE is formed by interposing a trench TRC (first 1 To The insulating film EIF (first 1st The trench TRC is formed with an insulating film (insulating film) interposed therebetween. The trench TRC is formed from the first main surface toward the second main surface of the semiconductor substrate SUB having an N-type region NSR (drift layer).

[0021] In a region (first region) of the semiconductor substrate SUB located between the trench gate electrode TGE and the trench emitter electrode TEE, an N+ type source diffusion layer SDR (second impurity region) is formed from the first main surface to a predetermined depth. A P type base diffusion layer BDR (first impurity region) is formed from the bottom of the source diffusion layer SDR to a further predetermined depth. The base diffusion layer BDR includes a P+ layer PPR ( No. 2 The impurity region (BDR) is formed. Bottom? An N-type hole barrier layer HBR is formed from the trench gate electrode TGE to a predetermined depth. The hole barrier layer HBR is formed to reach the bottoms (lower ends) of the trench gate electrode TGE and the trench emitter electrode TEE. The region where the hole barrier layer HBR is formed is called an active region.

[0022] In a region of the semiconductor substrate SUB located on the opposite side of the trench gate electrode TGE from the side on which the trench emitter electrode TEE is located, a P-type floating diffusion layer FPR is formed from the first main surface to a position deeper than the bottom (lower end) of the trench gate electrode TGE. Also, in a region of the semiconductor substrate SUB located on the opposite side of the trench emitter electrode TGE from the side on which the trench gate electrode TGE is located, a P-type floating diffusion layer FPR is formed from the first main surface to a position deeper than the bottom (lower end) of the trench emitter electrode TEE. The floating diffusion layer FPR is called an inactive region.

[0023] An interlayer insulating film CIL is formed so as to cover the trench gate electrode TGE, the trench emitter electrode TEE, the source diffusion layer SDR, etc. A common contact member CCN is formed through the interlayer insulating film CIL so as to be in contact with the trench emitter electrode TEE, the base diffusion layer BDR (P+ layer PPR), the source diffusion layer SDR, etc. The common contact member CCN includes a barrier metal film BME and a tungsten plug WPG.

[0024] A recess portion RCS recessed from the first main surface toward the second main surface is formed in the trench emitter electrode TEE, the base diffusion layer BDR, and the insulating film EIF. The shared contact member CCN protrudes from the first main surface toward the second main surface in contact with the recess portion RCS. A distance L1 between the trench emitter electrode TEE and the trench gate electrode TGE is set to a distance such that the shared contact member CCN does not contact the trench gate electrode TGE. This structure will be described later.

[0025] The emitter electrode ME is formed so as to be in contact with the surface (upper surface) of the interlayer insulating film CIL. E is The common contact member CCN is electrically connected to the emitter electrode MEE, which is made of, for example, an aluminum film.

[0026] On the other hand, a P-type collector diffusion layer CDR and an N-type buffer layer NBR are formed on the second main surface side of the semiconductor substrate SUB. An N-type region NSR serving as a drift layer is located between the floating diffusion layer FPR and the buffer layer NBR. A collector electrode BEL (back electrode) is formed so as to be in contact with the collector diffusion layer CDR (the second main surface of the semiconductor substrate SUB).

[0027] Next, the gate wiring lead-out region MGR will be described. In the gate wiring lead-out region MGR, a trench gate lead-out electrode TG I The trench gate lead-out electrode TGI is formed in the trench TRCW with an insulating film GIF interposed therebetween. As shown in FIGS. 2 and 3, the trench gate lead-out electrode TGI is electrically connected to the trench gate electrode TGE. The trench gate lead-out electrode TGI (trench TRC W) has a first part TGN set to a first width W1 that is the same as the width of the trench gate electrode TGE (trench TRC), and a second part TGW set to a second width W2 that is wider than the first width W1.

[0028] A gate lead-out contact member GCN is formed so as to penetrate the interlayer insulating film CIL and contact the second part TGW of the trench gate lead-out electrode TGI. The gate lead-out contact member GCN includes a barrier metal film BME and a tungsten plug WPG. A gate lead-out wiring MGI (second conductive layer) is formed so as to contact the surface (upper surface) of the interlayer insulating film CIL. The gate lead-out contact member GCN is electrically connected to the gate lead-out wiring MGI. The gate lead-out wiring MGI is formed of, for example, an aluminum film or the like.

[0029] Next, the peripheral element region PDR will be described. In the peripheral element region PDR, wiring PIC is formed on the first main surface of the semiconductor substrate SUB with an insulating film IF and a silicon oxide film HDL interposed therebetween. The wiring PIC is electrically connected to a peripheral element (not shown), such as a protection diode or a temperature sensing diode. A contact member DCN is formed so as to penetrate the interlayer insulating film CIL and make contact with the wiring PIC. A conductive layer MPL (third conductive layer) is formed on the surface of the interlayer insulating film CIL and is electrically connected to the wiring PIC via the contact member DCN.

[0030] Next, the structure of the common contact member CCN will be described in more detail. As shown in Fig. 4, a recess portion RCS recessed from the first main surface toward the second main surface is formed in the trench emitter electrode TEE, the base diffusion layer BDR (source diffusion layer SDR), and the insulating film EIF located between the trench emitter electrode TEE and the base diffusion layer BDR (source diffusion layer SDR).

[0031] The recess portion RCS is formed so as to extend between the trench emitter electrode TEE and the base diffusion layer BDR (source diffusion layer SDR). The recess portion RCS is a first recess portion RCS1 formed in the base diffusion layer BDR (source diffusion layer SDR). (Part 1) and a second recess portion RCS2 formed in the trench emitter electrode TEE. (Second part) and a third recess portion RCS3 formed in the insulating film EIF. (3rd part) It has the following features.

[0032] The first recess portion RCS1 is formed at a depth D1 (the 1 The second recess portion RCS2 is located at a depth D2 (first recess portion RCS3) that is deeper than the depth D1 from the first main surface. 2 The third recess portion RCS3 is located at a depth D from the first main surface that is deeper than the depth D2. 4 The shallow depth D3 ( 3The common contact member CCN has a protruding structure that protrudes from the first main surface toward the second main surface in a manner that makes contact with the first recess portion RCS1, the second recess portion RCS2, and the third recess portion RCS3.

[0033] The depth D3 of the third recess portion RCS3 formed in the insulating film EIF is deeper than the depth D2 of the second recess portion RCS2 formed in the trench emitter electrode TEE, so that the contact area between the common contact member CCN and the base diffusion layer BDR (P+ layer PPR) is expanded, and carriers (holes) can be efficiently removed. The GE type semiconductor device SED is configured as described above.

[0034] Next, an example of a method for manufacturing the above-mentioned semiconductor device SED will be described. As shown in Fig. 5, a silicon oxide film SOF1 is formed so as to cover the first main surface of the semiconductor substrate SUB. Next, with the silicon oxide film SOF1 formed, a P-type region PR that will become a floating diffusion layer is formed by injecting P-type impurities. Furthermore, an N-type region NR that will become a hole barrier layer is formed by injecting N-type impurities.

[0035] Next, a hard mask (not shown) is formed to form trenches. Next, the semiconductor substrate SUB is etched using the hard mask as an etching mask to form trenches TRC (first emitter trench, first gate trench) and trenches TRCW (third gate trench) (see FIG. 6). Thereafter, the hard mask is removed. As a result, as shown in FIG. 6, the first main surface of the semiconductor substrate SUB in which trenches TRC and TRCW are formed is exposed. Trench TRCW is formed to have a width wider than that of trench TRC.

[0036] Next, a predetermined heat treatment is performed to diffuse the P-type impurities in the P-type region PR, thereby forming a floating diffusion layer FPR. Also, the N-type impurities in the N-type region NR are diffused to form a hole barrier layer HBR (see FIG. 7). Next, as shown in FIG. 7, a thermal oxidation treatment is performed to form an insulating film IF on the first main surface of the semiconductor substrate SUB, including the inner wall surfaces of the trenches TRC and TRCW.

[0037] Next, a polysilicon film PSF is formed to cover the semiconductor substrate SUB and to fill the trenches TRC and TRCW, respectively. At this time, the position of the polysilicon film PSF covering the relatively wide trench TRCW is lower than the position of the polysilicon film PSF covering the relatively narrow trench TRC.

[0038] Next, the entire surface of the polysilicon film PSF is etched to remove the portion of the polysilicon film PSF located on the first main surface of the semiconductor substrate SUB. Furthermore, the polysilicon film PSF is over-etched. As a result, as shown in FIG. 8, the upper surfaces of the polysilicon film PSF remaining in the trenches TRC and TRCW are positioned lower than the first main surface of the semiconductor substrate SUB.

[0039] At this time, when the polysilicon film PSF is formed, the position of the polysilicon film PSF covering the trench TRCW is lower than the position of the polysilicon film PSF covering the trench TRC. Therefore, after the entire surface etching process is performed, the position of the upper surface of the polysilicon film PSF left in the trench TRCW is lower than the position of the upper surface of the polysilicon film PSF left in the trench TRC. Here, the thickness corresponding to this difference in height (thickness) is defined as thickness TK.

[0040] 9, a silicon oxide film HDL is formed to cover the insulating film IF. Next, a polysilicon film PSF2 is formed to cover the silicon oxide film HDL. Next, a photolithography process is performed to form a photoresist pattern PHR1 for patterning wiring.

[0041] 10, the polysilicon film PSF2 is etched using the photoresist pattern PHR1 as an etching mask, thereby forming the wiring PIC. Next, the silicon oxide film HDL is etched using the photoresist pattern PHR1 as an etching mask, and further, the insulating film IF is etched, thereby removing the portions of the silicon oxide film HDL and the insulating film IF located on the first main surface of the semiconductor substrate SUB.

[0042] As a result, a trench emitter electrode TEE is formed in the trench TRC with an insulating film EIF (insulating film IF) interposed therebetween. Also, a trench gate electrode TGE is formed in the trench TRC with an insulating film GIF (insulating film IF) interposed therebetween. Furthermore, a trench gate lead electrode TGI is formed in the trench TRCW with an insulating film GIF (insulating film IF) interposed therebetween. Thereafter, the photoresist pattern PHR1 is removed.

[0043] 11, a silicon oxide film SOF2 is formed to cover the first main surface of the semiconductor substrate SUB. Next, a predetermined photolithography process is performed to form a photoresist pattern (not shown) for forming a source diffusion layer and a base diffusion layer. Next, P-type impurities are implanted using the photoresist pattern as an implantation mask. Furthermore, N-type impurities are implanted. Thereafter, the photoresist pattern is removed.

[0044] As a result, a source diffusion layer SDR and a base diffusion layer BDR are formed in a region of the semiconductor substrate SUB located between the trench emitter electrode TEE and the trench gate electrode TGE. The base diffusion layer BDR is formed at a predetermined depth from the first main surface. GoodbyeThe source diffusion layer SDR is formed at a position shallower than the base diffusion layer BDR. The bottom After that, the silicon oxide film SOF2 is removed.

[0045] Next, an interlayer insulating film CIL is formed so as to cover the first main surface of the semiconductor substrate SUB (see FIG. 12). As the interlayer insulating film CIL, for example, a PSG film (Phospho Silicate Glass) is formed. Next, a predetermined photolithography process is performed to form a photoresist pattern PHR2 for forming contact openings in the interlayer insulating film CIL (see FIG. 12).

[0046] 12, the interlayer insulating film CIL is etched using the photoresist pattern PHR2 as an etching mask. By this etching, contact openings CH 1、 Contact opening CH 2O and contact opening CH 3 is , are formed simultaneously.

[0047] Here, since the contact opening depth is large relative to its width and the aspect ratio (opening depth DC / opening width WC: approximately 1.4 to 2.5) is high, an anisotropic etching process is applied as the etching process. In this anisotropic etching, conditions are set such that the etching selectivity ratio of the etching rate of the interlayer insulating film CIL (insulating film EIF) to the etching rate of the semiconductor substrate SUB (trench emitter electrode TEE) is high. By this anisotropic etching process, the contact openings CH1 and the like are formed in a tapered shape.

[0048] Furthermore, as described above, the position of the upper surface of the trench gate extraction electrode TGI (polysilicon film PSF) formed in the trench TRCW is lower by the thickness TK than the position of the upper surface of the trench emitter electrode TEE (polysilicon film PSF) formed in the trench TRC.

[0049] Therefore, in this anisotropic etching, when the upper surface of the trench emitter electrode TEE is exposed, the trench gate extraction electrode TGI is still covered with the interlayer insulating film CIL having a thickness of TK. Then, after the trench emitter electrode TEE is exposed, the insulating film EIF interposed between the trench emitter electrode TEE and the base diffusion layer BDR (semiconductor substrate SUB) is also etched before the trench gate extraction electrode TGI is exposed. This causes the upper surface of the insulating film EIF to recede, forming a third recess portion RCS3 and increasing the area of ​​the exposed base diffusion layer BDR. Then, the photoresist pattern PHR2 is removed.

[0050] 13, an anisotropic etching process is performed on the trench emitter electrode TEE, the base diffusion layer BDR, and the source diffusion layer SDR exposed at the bottom of the contact opening CH1. As a result, a part of the upper surface of the trench emitter electrode TEE is recessed, and a part of the upper surface of the base diffusion layer BDR is also recessed. At this time, since the upper surface of the trench emitter electrode TEE is initially located lower than the first main surface of the semiconductor substrate SUB (the upper surface of the base diffusion layer BDR), the recessed upper surface of the trench emitter electrode TEE is located lower than the upper surface of the recessed base diffusion layer BDR.

[0051] This series of anisotropic etching steps leaves a residue RES at the bottom of the contact opening CH1, including a part of the insulating film EIF and a part of the silicon (semiconductor substrate SUB, polysilicon). Next, a dry etching process is performed to remove the residue RES. In this way, a recess portion RCS is formed (see FIG. 14).

[0052] 14, P+ type impurities are implanted through the contact openings CH1 to CH3. At this time, a P+ layer PPR having an impurity concentration higher than the impurity concentration of the base diffusion layer BDR is formed in the P-type base diffusion layer BDR exposed at the bottom (recess portion RCS) of the contact opening CH1. This reduces the contact resistance between the shared contact member CCN and the P+ layer PPR (base diffusion layer BDR).

[0053] On the other hand, at the bottom of the contact opening CH1, the P+ type impurities are also implanted into the side surface of the N-type source diffusion layer SDR exposed in the recess portion RCS. As a result, the N-type impurities in the source diffusion layer SDR, which comes into contact with the shared contact member CCN, are neutralized by the P+ type impurities, which may increase the contact resistance between the source diffusion layer SDR and the shared contact member CCN.

[0054] 15, the interlayer insulating film CIL is subjected to a wet etching process to widen the opening width of the contact opening CH1 and the like. As shown in FIG. 16, widening the opening width of the contact opening CH1 exposes the upper surface of the source diffusion layer SDR into which the P+ type impurity PM has not been implanted. This reduces the contact resistance between the shared contact member CCN and the source diffusion layer SDR.

[0055] 17, a barrier metal film BME is formed so as to cover the interlayer insulating film CIL including the inner wall surfaces of the contact openings CH1 to CH3. As the barrier metal film BME, for example, a stacked film of titanium nitride (TiN) and titanium (Ti) is formed. Next, a tungsten film WF is formed so as to cover the barrier metal film BME. Next, the tungsten film WF and the barrier metal film BME located on the upper surface of the interlayer insulating film CIL are removed by performing an etch-back process on the entire surface of the tungsten film WF and the like.

[0056] 18, the tungsten film WF and the barrier metal film BME left in the contact opening CHI form a common contact member CCN. The tungsten film WF and the barrier metal film BME left in the contact opening CH2 form a gate lead-out contact member GCN. The tungsten film WF and the barrier metal film BME left in the contact opening CH3 form a contact member DCN.

[0057] Thereafter, for example, an aluminum film (not shown) is formed so as to cover the interlayer insulating film CIL, and the aluminum film is patterned to form the emitter electrode MEE, gate lead wiring MGI, gate electrode MGE, etc. (See FIG. 3, etc.). Next, an N-type buffer layer NBR and a P-type collector diffusion layer CDR are formed on the second main surface side of the semiconductor substrate SUB. Furthermore, a collector electrode BEL (back surface electrode) is formed, completing the semiconductor device.

[0058] Next, the operation of the semiconductor device SED described above will be explained. First, when the trench insulated gate bipolar transistor is turned on, a voltage equal to or higher than the threshold voltage is applied to the gate electrode MGE. As a result, electrons are injected from the source diffusion layer SDR through the channel into the N-type region NSR (drift layer) in the semiconductor substrate SUB, the PN junction between the N-type region NSR and the collector diffusion layer CDR is forward biased, and holes are injected from the collector diffusion layer CDR into the N-type region NSR.

[0059] The injected holes are prevented from escaping to the source diffusion layer SDR (emitter) side by the P-type floating diffusion layer FPR, and holes accumulate in the N-type region NSR and floating diffusion layer FPR, increasing the hole concentration. When the hole concentration in the N-type region NSR etc. increases, the injection of electrons from the source diffusion layer SDR is promoted, and the electron concentration also increases. In this way, the increase in the carrier concentration in the N-type region NSR etc. causes conductivity modulation, resulting in an on-state.

[0060] Next, to turn off the trench insulated gate bipolar transistor, a voltage lower than the threshold voltage is applied to the gate electrode MGE. This causes the channel to disappear. The carriers (holes) accumulated in the N-type region NSR and other regions are discharged to the emitter electrode MEE by the parasitic P-channel MOSFET (floating diffusion layer FPR, trench emitter electrode TEE at the emitter potential, base diffusion layer BDR, etc.) formed on the trench emitter electrode TEE side, turning the transistor off.

[0061] In the above-described semiconductor device SED, the common contact member CCN, which electrically connects the base diffusion layer BDR etc. and the emitter electrode MEE, contacts the recess portion RCS. The recess portion RCS is formed so as to straddle the trench emitter electrode TEE, the insulating film EIF, the base diffusion layer BDR etc. The recess portion RCS has a first recess portion RCS1 formed in the base diffusion layer BDR, a second recess portion RCS2 formed in the trench emitter electrode TEE, and a third recess portion RCS3 formed in the insulating film EIF.

[0062] Of the first recess portion RCS1, the second recess portion RCS2, and the third recess portion RCS3, the third recess portion RCS3 is at the deepest position (fourth depth) with respect to the first recess portion RCS1 and the second recess portion RCS2. Therefore, since the upper surface of the insulating film EIF is lowered (set back), the contact area between the common contact member CCN and the base diffusion layer BDR is increased and the contact area between the common contact member CCN and the trench emitter electrode TEE is also increased, thereby reducing the contact resistance.

[0063] This allows carriers (holes) accumulated in the N-type region NSR and other regions to be efficiently discharged from the base diffusion layer BDR to the emitter electrode MEE via the common contact member CCN, shortening the time it takes to turn off and contributing to a reduction in turn-off loss.

[0064] In addition, the position of the third recess portion RCS3 formed in the insulating film EIF can be recessed to a position deeper than the positions of the first recess portion RCS1 and the second recess portion RCS2 by over-etching when forming a contact opening in the interlayer insulating film CIL.

[0065] As described above, in the process shown in FIG. 18, the position of the upper surface of the trench gate extraction electrode TGI (polysilicon film PSF) is lower by the thickness TK than the position of the upper surface of the trench emitter electrode TEE (polysilicon film PSF).

[0066] As a result, after the trench emitter electrode TEE is exposed, the insulating film EIF is also etched before the trench gate extraction electrode TGI is exposed, and the position of the upper surface of the insulating film EIF can be lowered (set back) without adding a new process.

[0067] As described above, the common contact member CCN includes a portion that is in contact with the N-type source diffusion layer SDR on the upper surface of the source diffusion layer SDR. In the process shown in Fig. 14, when the P+ layer PPR is formed, P-type impurities are implanted into the exposed side surface of the N-type source diffusion layer SDR, and the N-type impurities are neutralized by the P-type impurities.

[0068] Therefore, in the process shown in FIG. 15, by widening the opening width of the contact opening CH1, etc., the upper surface of the source diffusion layer SDR into which P-type impurities have not been implanted is exposed, and the common contact member CCN comes into contact with the upper surface of the source diffusion layer SDR, thereby reducing the contact resistance.

[0069] As shown in Fig. 4, the position (depth D3) of the upper end of the insulating film EIF needs to be adjusted to be shallower than the bottom (depth D4) of the base diffusion layer BDR. This will be explained below. Fig. 19 shows a graph qualitatively illustrating the relationship between the depths D3 and D4 and the on-voltage Vsat.

[0070] As shown in Figure 19, when the position (depth D3) of the upper end of the insulating film EIF is shallower than the bottom (depth D4) of the base diffusion layer BDR (depth D3 < depth D4), the on-voltage (collector voltage required to pass the rated current when the gate electrode is on) becomes a constant value.

[0071] However, when the position (depth D3) of the upper end of the insulating film EIF is deeper than the bottom (depth D4) of the base diffusion layer BDR (depth D3>D4), the on-voltage Vsat gradually increases as the position (depth D3) of the upper end of the insulating film EIF increases. That is, holes pass directly through the shared contact member CCN.

[0072] Since a lower on-state voltage Vsat is desirable, when etching the insulating film EIF, it is necessary to ensure that the position of the upper end of the insulating film EIF (depth D3) does not become deeper than the bottom of the base diffusion layer BDR (depth D4). In this case, since the variation in etching is greater than the variation in ion implantation, it is necessary to control the depth of the base diffusion layer BDR.

[0073] Embodiment 2 Here, an example of a GGEE-type semiconductor device will be described. The GGEE-type semiconductor device is applied to applications requiring stable operation, etc. First, the cell region CER will be described. As shown in FIGS. 20 and 21, one trench emitter electrode TEE (first trench emitter electrode) and another trench emitter electrode TEE (second trench emitter electrode) are arranged at a distance in one direction. The distance between the one trench emitter electrode TEE and the other trench emitter electrode TEE is distance L2. The one trench emitter electrode TEE and the other trench emitter electrode TEE each extend in another direction intersecting the one direction.

[0074] One trench gate electrode TGE (first trench gate electrode) and another trench gate electrode TGE (second trench gate electrode) are arranged at a distance in one direction. The distance between the one trench gate electrode TGE and the other trench gate electrode TGE is distance L3. The one trench gate electrode TGE and the other trench gate electrode TGE each extend in another direction intersecting the one direction.

[0075] Moreover, the one trench emitter electrode TEE and the other trench emitter electrode TEE, and the one trench gate electrode TGE and the other trench gate electrode TGE are arranged at a distance in one direction.

[0076] In a region (first region) of the semiconductor substrate SUB located between one trench emitter electrode TEE and another trench emitter electrode TEE, a predetermined depth from the first main surface is provided. Sani P-type base diffusion layer BDR (1st impurity region) In the base diffusion layer BDR, a P+ layer PPR having a higher P-type impurity concentration is formed.

[0077] In a region (second region) of the semiconductor substrate SUB located between the first trench gate electrode TGE and the other trench gate electrode TGE, an N+ type source diffusion layer SDR (third impurity region) is formed from the first main surface to a predetermined depth. Sani A P-type base diffusion layer BDR (fourth impurity region) is formed across the region.

[0078] An interlayer insulating film CIL is formed to cover the first main surface of the semiconductor substrate SUB. A common contact member CCN and a gate contact member GDC are formed to penetrate the interlayer insulating film CIL. As shown in FIG. 22 , a recess portion RCS recessed from the first main surface toward the second main surface is formed in one trench emitter electrode TEE, the base diffusion layer BDR, and the insulating film EIF.

[0079] The recess portion RCS is formed so as to straddle between the trench emitter electrode TEE and the base diffusion layer BDR. The recess portion RCS has a first recess portion RCS1 formed in the base diffusion layer BDR, a second recess portion RCS2 formed in the trench emitter electrode TEE, and a third recess portion RCS3 formed in the insulating film EIF.

[0080] As shown in FIG. 22, the first recess portion RCS1 has a depth D1 (the 1The second recess portion RCS2 is located at a depth D2 (first recess portion RCS3) that is deeper than the depth D1 from the first main surface. 2 The third recess portion RCS3 is located at a depth D from the first main surface that is deeper than the depth D2. 4 The shallow depth D3 ( 3 The common contact member CCN has a protruding structure that protrudes from the first main surface toward the second main surface in a manner that makes contact with the first recess portion RCS1, the second recess portion RCS2, and the third recess portion RCS3.

[0081] On the other hand, as shown in FIG. 21, the gate contact member GDC is formed so as to be in contact with the source diffusion layer SDR and the base diffusion layer BDR formed in a region (second region) of the semiconductor substrate SUB.

[0082] Furthermore, the distance L2 between adjacent trench emitter electrodes TEE and another trench emitter electrode TEE may be narrower than the distance L1 between the trench gate electrode TGE and the trench emitter electrode TEE in the semiconductor device SED described above. This is because the common contact member CCN may be in contact with the other trench emitter electrodes TEE. The remaining configuration is similar to that of the semiconductor device SED shown in Figures 2 and 3, so the same members are designated by the same reference numerals and their description will not be repeated unless necessary.

[0083] Next, an example of a manufacturing method of the above-mentioned semiconductor device SED will be described. The semiconductor device SED is manufactured by substantially the same manufacturing method as the manufacturing method of the above-mentioned semiconductor device SED, except that the arrangement pattern of the trench gate electrodes TGE (trench TRC (first gate trench, second gate trench, third gate trench)) and the trench emitter electrodes TEE (trench TRC (first emitter trench, second emitter trench)) is different from the arrangement pattern of the trench gate electrodes TGE and the trench emitter electrodes TEE in the above-mentioned semiconductor device SED.

[0084] 5 to 10, a silicon oxide film SOF2 is formed to cover the first main surface of the semiconductor substrate SUB, as shown in Fig. 23. Next, a predetermined photolithography process is performed to form a photoresist pattern (not shown) for forming the base diffusion layer BDR. Next, using the photoresist pattern as an implantation mask, P-type impurities are implanted to form the base diffusion layer BDR.

[0085] Next, after the photoresist pattern is removed, a photoresist pattern (not shown) for forming the source diffusion layer SDR is formed by performing a predetermined photolithography process. Next, using the photoresist pattern as an implantation mask, N-type impurities are implanted to form the source diffusion layer SDR. Thereafter, the photoresist pattern is removed.

[0086] As a result, a base diffusion layer BDR is formed in a region of the semiconductor substrate SUB located between the adjacent trench emitter electrodes TEE and the other trench emitter electrodes. Furthermore, a base diffusion layer BDR and a source diffusion layer SDR are formed in a region of the semiconductor substrate SUB located between the adjacent trench gate electrodes TGE and the other trench gate electrodes TGE. Then, the silicon oxide film SOF2 is removed.

[0087] Next, an interlayer insulating film CIL is formed so as to cover the first main surface of the semiconductor substrate SUB (see FIG. 24). Next, a predetermined photolithography process is performed to form a photoresist pattern PHR2 for forming contact openings in the interlayer insulating film CIL. Next, as shown in FIG. 24, the interlayer insulating film CIL is etched using the photoresist pattern PHR2 as an etching mask. This etching process forms contact openings CH 1、 Contact opening CH 2、 Contact opening CH 3O and contact opening CH 4 is , are formed simultaneously.

[0088] At this time, as explained for the step shown in FIG. 12, an anisotropic etching process is applied as the etching process because the aspect ratio (opening depth DC / opening width WC: approximately 1.4 to 2.5) is high. By this anisotropic etching process, the contact openings CH1 and the like are formed in a tapered shape. Furthermore, since the position of the upper surface of the trench gate extraction electrode TGI (polysilicon film PSF) is lower by the thickness TK than the position of the upper surface of the trench emitter electrode TEE (polysilicon film PSF), while etching the amount corresponding to the thickness TK, the upper surface of the insulating film EIF drops (retreats), and the area of ​​the exposed base diffusion layer BDR increases. Thereafter, the photoresist pattern PHR2 is removed.

[0089] Next, an anisotropic etching process is performed similarly to the process shown in Fig. 13. As a result, as shown in Fig. 25, the upper surface of the trench emitter electrode TEE exposed at the bottom of the contact opening CH1 is recessed, and the upper surface of the base diffusion layer BDR is also recessed. At this time, the source diffusion layer SDR is etched at the bottom of the contact opening CH4, and the base diffusion layer BDR is also exposed. Thereafter, a dry etching process is performed to remove the residue RES remaining at the bottom of the contact opening CH1.

[0090] Next, similarly to the process shown in FIG. 14, P+ type impurities are implanted. As a result, a P+ layer PPR is formed in the P-type base diffusion layer BDR as shown in FIG. 26. Next, similarly to the process shown in FIG. 15, a wet etching process is performed on the interlayer insulating film CIL. As a result, the opening widths of the contact openings CH1 and CH4 are increased as shown in FIG. 27. As shown in FIG. 28, a recess portion RCS with which the shared contact member CCN comes into contact is formed at the bottom of the contact opening CH1. At this time, the opening width is increased at the bottom of the contact opening CH4, thereby exposing the upper surface of the source diffusion layer SDR into which the P+ type impurities have not been implanted.

[0091] 17, a barrier metal film BME is formed to cover the interlayer insulating film CIL including the inner wall surfaces of the contact openings CH1 to CH4, as shown in Fig. 29. Next, a tungsten film WF is formed to cover the barrier metal film BME. Next, an etch-back process is performed on the entire surface of the tungsten film WF, etc., to remove the tungsten film WF and the barrier metal film BME located on the upper surface of the interlayer insulating film CIL.

[0092] 30, a common contact member CCN is formed in the contact opening CHI. A gate lead-out contact member GCN is formed in the contact opening CH2. A contact member DCN is formed in the contact opening CH3. A gate contact member GDC is formed in the contact opening CH4. Thereafter, the semiconductor device SED is completed through steps of forming the emitter electrode MEE, the gate lead-out wiring MGI, the gate electrode MGE, etc.

[0093] 22, in the semiconductor device SED described above, the recess portion RCS has a first recess portion RCS1 formed in the base diffusion layer BDR, a second recess portion RCS2 formed in the trench emitter electrode TEE, and a third recess portion RCS3 formed in the insulating film EIF. The third recess portion RCS3 is located at the deepest position compared to the first recess portion RCS1 and the second recess portion RCS2. Place be.

[0094] As a result, the upper surface of the insulating film EIF is lowered (set back), thereby increasing the contact area between the common contact member CCN and the base diffusion layer BDR, and also increasing the contact area between the common contact member CCN and the trench emitter electrode TEE, thereby reducing the contact resistance.

[0095] This allows carriers (holes) accumulated in the N-type region NSR and other regions to be efficiently discharged from the base diffusion layer BDR to the emitter electrode MEE via the common contact member CCN, shortening the time it takes to turn off and contributing to a reduction in turn-off loss.

[0096] In addition, by widening the opening width at the bottom of the contact opening CH4, the upper surface of the source diffusion layer SDR into which P+ type impurities have not been implanted is exposed, thereby reducing the contact resistance between the gate contact member GDC and the source diffusion layer SDR.

[0097] Embodiment 3 Here, an example of an EGE type semiconductor device will be described. The EGE type semiconductor device SED is applied to applications requiring high speed. As shown in FIG. 31, in the cell region CER, one trench emitter electrode TEE (first trench emitter electrode), a trench gate electrode TGE (first trench gate electrode), and another trench emitter electrode TEE (second trench gate electrode) are arranged. 2 A trench emitter electrode is formed.

[0098] The one trench emitter electrode TEE, the trench gate electrode TGE and the other trench emitter electrode TEE are formed at a distance (interval L1) from each other, with the trench gate electrode TGE being located between the one trench emitter electrode TEE and the other trench emitter electrode TEE.

[0099] One recess portion RCS is formed in one trench emitter electrode TEE, base diffusion layer BDR, and insulating film EIF. Another recess portion RCS is formed in another trench emitter electrode TEE, base diffusion layer BDR, and insulating film EIF. The one recess portion RCS and the other recess portion RCS are formed almost symmetrically (line symmetrically) with respect to the trench gate electrode TGE. The one recess portion RCS and the other recess portion RCS have the same structure as the recess portion RCS shown in FIG.

[0100] The rest of the configuration is similar to that of the semiconductor device SED shown in FIG. 3 etc., so the same members are given the same reference numerals and the description thereof will not be repeated unless necessary.

[0101] Next, a method for manufacturing the semiconductor device SED described above will be described. The semiconductor device SED is manufactured by substantially the same manufacturing method as the manufacturing method for the semiconductor device SED described in the first embodiment, except that the layout pattern of the trench gate electrodes TGE and the trench emitter electrodes TEE is different from the layout pattern of the trench gate electrodes TGE and the trench emitter electrodes TEE in the semiconductor device SED shown in FIG.

[0102] In the above-described semiconductor device SED, as in the first embodiment, a recessed portion RCS is formed that is recessed from the first main surface toward the second main surface, and a common contact member CCN is in contact with the recessed portion RCS.

[0103] This increases the contact area between the shared contact member CCN and the base diffusion layer BDR, reducing the contact resistance. This allows carriers (holes) accumulated in the N-type region NSR and other regions to be efficiently discharged from the base diffusion layer BDR to the emitter electrode MEE via the shared contact member CCN. As a result, the time required for turn-off is shortened, contributing to a reduction in turn-off loss.

[0104] The semiconductor device and the manufacturing method thereof described in each embodiment can be variously combined as necessary, and the dependent claims are intended to correspond to such combinations.

[0105] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0106] SED semiconductor device, CER cell region, MGR gate wiring lead-out region, PDR peripheral element region, MEE emitter electrode, MGE gate electrode, MGI gate lead-out line, SUB semiconductor substrate, TRC trench, GIF insulating film, TGE trench gate electrode, EIF insulating film, TEE trench emitter electrode, SDR source diffusion layer, BDR base diffusion layer, PPR P+ layer, HBR hole barrier layer, FPR floating diffusion layer, NBR N buffer layer, CDR collector diffusion layer, NSR N-type region, BEL collector electrode, CIL interlayer insulating film, CH1 contact opening, CCN common contact material, WPG tungsten plug, BME barrier metal film, RCS recess portion, RCS1 first recess portion, RCS2 second recess portion, RCS3 third recess portion, GDC gate contact material, CH2 contact opening, GCN gate lead-out contact material, TGI trench gate lead-out electrode, TGN first portion, TGW Part 2, TRCW trench, CH3 contact opening, DCN contact material, PIC wiring, MPL conductive layer, SOF1 silicon oxide film, NR N-type region, PR P-type region, IF insulating film, PSF polysilicon film, TK thickness, HDL silicon oxide film, PSF2 polysilicon film, PHR1 photoresist, SOF2 silicon oxide film, PHR2 photoresist, RES residue, PM P-type impurity, WF tungsten film, W1 first width, W2 second width, L1, L2, L3 spacing, WC opening width, DC opening depth.

Claims

1. a semiconductor substrate of a first conductivity type having a first main surface and a second main surface opposite to the first main surface; a first trench formed in the semiconductor substrate; a first trench emitter electrode embedded in the first trench via a first insulating film; a first impurity region of a second conductivity type opposite to the first conductivity type, the first impurity region being formed in the first region of the semiconductor substrate and contacting the first trench; a recess formed in the semiconductor substrate and spanning between the first trench emitter electrode and the first impurity region in a plan view; an interlayer insulating film formed on the first main surface; a first contact member that penetrates the interlayer insulating film and is embedded in the interlayer insulating film and the recess; The recess is a first portion formed in the first impurity region and having a first depth that is a depth from the first main surface; a second portion formed on the first trench emitter electrode and having a second depth that is a depth from the first main surface; a third portion formed on the first insulating film, located at a position deeper than the first depth and the second depth, and having a third depth that is a depth from the first main surface; The first contact member has, at the third portion, contacting the first trench emitter electrode on one side; the other side of the semiconductor device is in contact with the first impurity region over the entirety thereof.

2. a second impurity region of the second conductivity type formed in the first region and in contact with the first contact member; 2. The semiconductor device according to claim 1, wherein the impurity concentration of said second impurity region is higher than the impurity concentration of said first impurity region.

3. a third impurity region of the first conductivity type formed in the first region and exposed to the first main surface on the first impurity region; The semiconductor device according to claim 2 , wherein said first contact member is in contact with said third impurity region on said first main surface.

4. a second trench formed in the semiconductor substrate; a first trench gate electrode embedded in the second trench and formed with a second insulating film interposed therebetween; 2. The semiconductor device according to claim 1, wherein the first trench gate electrode is formed at a distance from the first trench emitter electrode so that the first region is located between the first trench gate electrode and the first trench emitter electrode.

5. an emitter electrode formed on the first main surface and electrically connected to the first trench emitter electrode; a gate electrode formed on the first main surface and electrically connected to the first trench gate electrode; a collector electrode formed on the second main surface, 5. The semiconductor device according to claim 4, wherein said emitter electrode, said gate electrode and said collector electrode constitute a trench insulated gate bipolar transistor.

6. a third trench formed in the semiconductor substrate; a second trench emitter electrode embedded in the third trench and formed via a third insulating film, 5. The semiconductor device according to claim 4, wherein the first trench emitter electrode, the first trench gate electrode, and the second trench emitter electrode are formed at a distance from each other such that the first trench gate electrode is located between the first trench emitter electrode and the second trench emitter electrode.

7. a semiconductor substrate of a first conductivity type having a first main surface; a first trench, a second trench, a third trench, and a fourth trench formed in the semiconductor substrate; a first trench emitter electrode embedded in the first trench with a first insulating film interposed therebetween; a second trench emitter electrode embedded in the second trench via a second insulating film; a first trench gate electrode embedded in the third trench via a third insulating film; a second trench gate electrode embedded in the fourth trench with a fourth insulating film interposed therebetween; a first impurity region of a second conductivity type opposite to the first conductivity type, the first impurity region being formed in a first region of the semiconductor substrate and contacting the first trench and the second trench; a recess formed in the semiconductor substrate and spanning between the first trench emitter electrode and the first impurity region in a plan view; an interlayer insulating film formed on the first main surface; a first contact member that penetrates the interlayer insulating film and is embedded in the interlayer insulating film and the recess; Equipped with the second trench emitter electrode is formed at a distance from the first trench emitter electrode such that the first region is located between the first trench emitter electrode and the second trench emitter electrode; the second trench gate electrode is formed at a distance from the first trench gate electrode such that a second region is located between the first trench gate electrode and the second trench gate electrode; The recess is a first portion formed in the first impurity region and having a first depth that is a depth from the first main surface; a second portion formed on the first trench emitter electrode and having a second depth that is a depth from the first main surface; a third portion formed on the first insulating film, located at a position deeper than the first depth and the second depth, and having a third depth that is a depth from the first main surface; a third impurity region of the first conductivity type formed in the second region so as to be exposed to the first main surface; a fourth impurity region of the second conductivity type formed in the second region at a position deeper than the third impurity region; a second contact member that penetrates the interlayer insulating film and is embedded in a portion of the second region; the second contact member is in contact with the third impurity region and the fourth impurity region; The first contact member has, at the third portion, contacting the first trench emitter electrode on one side; the other side of the semiconductor device is in contact with the first impurity region over the entirety thereof.

8. (a) forming a first trench in a semiconductor substrate of a first conductivity type having a first main surface; (b) forming a first trench emitter electrode embedded in the first trench with a first insulating film interposed therebetween; (c) forming a first impurity region of a second conductivity type opposite to the first conductivity type in contact with the first trench in a first region of the semiconductor substrate; (d) forming an interlayer insulating film on the first main surface; (e) forming an opening in the semiconductor substrate, the opening including a recess that penetrates the interlayer insulating film, exposes a portion of the first impurity region, and straddles the first trench emitter electrode and the first impurity region; (f) embedding a first contact member in the opening including the recess; The recess is a first portion formed in the first impurity region and having a first depth that is a depth from the first main surface; a second portion formed on the first trench emitter electrode and having a second depth that is a depth from the first main surface; a third portion formed on the first insulating film, located at a position deeper than the first depth and the second depth, and having a third depth that is a depth from the first main surface; In the step (f), the first contact member embedded in the opening is In the third part, contacting the first trench emitter electrode on one side; The other side of the second impurity region is in contact with the first impurity region over the entirety thereof.

9. (g) forming a second impurity region of the second conductivity type in the first region so as to be in contact with the first contact member; 9. The method for manufacturing a semiconductor device according to claim 8, wherein the second impurity region has a higher impurity concentration than the first impurity region.

10. (h) forming a third impurity region of the first conductivity type in the first impurity region formed in the first region so as to be exposed to the first major surface; 9. The method for manufacturing a semiconductor device according to claim 8, wherein the first contact member is in contact with the third impurity region at the first main surface.

11. (i) forming a second trench in the semiconductor substrate; (j) forming a first trench gate electrode embedded in the second trench with a second insulating film interposed therebetween; 9. The method for manufacturing a semiconductor device according to claim 8, wherein the first trench gate electrode is formed at a distance from the first trench emitter electrode so that the first region is located between the first trench gate electrode and the first trench emitter electrode.

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