Data transmission using continuous weighted PPM duration signals.

Abstract

A computer-implemented method for processing a signal is provided, the method comprising: generating a continuous-time weighted pulse position modulation (CW PPM) duration signal from an input analog signal; converting the CW PPM duration signal to a memory access signal; performing a multiply-accumulate (MAC) operation with the memory access signal; and advantageously generating the input analog signal from a result of the MAC operation by an activation function (AF).

Description

[Technical Field]

[0001] The present invention relates generally to data transmission techniques, and more particularly to data transfer using continuous weighted pulse position modulation (PPM) duration signals. [Background technology]

[0002] In electronics, modulation is the act of controlling or varying something. Modulation can also be described as changing the pitch, intensity, or frequency of a tone, such as a human voice. However, in terms of application, modulation techniques are sometimes used for controlling devices such as direct current (DC) motors or light-emitting diodes (LEDs). In such cases, the technique is called pulse-width modulation (PWM).

[0003] Modulation refers to the ability to apply control to a device or system. As such, it exists in countless applications within the field of electronics. One of the more common uses of modulation as a control method is PWM. PWM is widely used due to its adaptability. PWM is a technique that reduces the average amount of deliverable power of an applied electrical signal. Furthermore, the process is achieved by effectively dividing the signal into separate parts. In terms of functional operation, PWM achieves this control by controlling the average current and voltage delivered to the load. This is achieved by rapidly switching on and off a switch between the load and the source. However, when comparing the on and off periods of the switch, increasing the on time relative to the off time increases the total power delivered to the load.

[0004] Furthermore, the PWM switching frequency must be high enough so as not to affect the load, but the resulting waveform perceived by the load must also be smooth. The frequency at which power must be switched typically varies widely depending on the device and its application. For example, switching may occur several times per minute, reaching tens or even hundreds of kilohertz for PC power supplies and audio amplifiers. One of the advantages of using PWM is that the power losses in the switching device are substantially low. In fact, there is virtually no current during the switch's off phase. Also, there is virtually no voltage drop across the switch during the switch's on phase, while it transmits power to the load. Because power losses are the result of both voltage and current, this translates to virtually zero power loss for PWM. As a result, PWM can be used continuously for data transmission applications.

[0005] In particular, hardware neural network processor cores can use analog memory to achieve data transmission using PWM signals. The output of such neural network processor cores is analog data, but the signal level is the same as that of digital signals. Data transmission using PWM signals enables analog data transmission without analog-to-digital (ADC) conversion or digital-to-analog (DAC) conversion. However, because the duration of PWM signals corresponds to the data value, transmitting large data values ​​requires a long period. Unless the data transmission period is shortened, it is difficult to improve system performance (operating speed). Therefore, other methods are needed to achieve efficient data transmission. Summary of the Invention

[0006] According to an embodiment, a computer-implemented method for processing a signal is provided, the computer-implemented method including generating a continuous-time weighted pulse-position modulation (CW PPM) duration signal from an input analog signal, converting the CW PPM duration signal to a memory access signal, performing a multiply-accumulate (MAC) operation with the memory access signal, and generating the input analog signal from a result of the MAC operation by an activation function (AF).

[0007] According to another embodiment, a computer program product for processing a signal is provided, the computer program product including a computer-readable storage medium having program instructions embodied therein that are executable by the computer to cause the computer to generate a continuous-time weighted pulse-position modulated (CW PPM) duration signal from an input analog signal, convert the CW PPM duration signal to a memory access signal, perform a multiply-accumulate (MAC) operation with the memory access signal, and generate the input analog signal from a result of the MAC operation via an activation function (AF).

[0008] According to yet another embodiment, there is provided a signal processing system for an analog neural network device, comprising: a signal generator for generating a continuous-time weighted pulse-position modulated (CW PPM) duration signal from an input analog signal, a converter for converting the CW PPM duration signal to a memory access signal, a multiply-accumulate (MAC) calculator for processing by accessing a memory using the memory access signal, and an activation function (AF) calculator for processing a result of the MAC calculator and generating an input analog signal for the signal generator.

[0009] According to another embodiment, an array structure is provided that includes a plurality of memory cells interposed between a plurality of bit lines and a plurality of word lines, each memory cell including a field effect transistor (FET) including a gate contact, a source contact, and a drain contact, and a variable resistor having one end electrically connected to the drain contact of the FET and the other end electrically connected to one of the plurality of word lines, wherein a slope signal is provided to the word line and a window signal is provided to the gate contact of the FET, such that the slope signal and the window signal combine to form a memory access signal derived from a continuous weighted pulse position modulated (CW PPM) duration signal.

[0010] According to yet another embodiment, a method for configuring an array structure is provided, the method including incorporating a plurality of memory cells between a plurality of bit lines and a plurality of word lines, each memory cell including a field effect transistor (FET) including a gate contact, a source contact, and a drain contact, and a variable resistor having one end electrically connected to the drain contact of the FET and the other end electrically connected to one of the plurality of word lines, and providing a slope signal to the word lines and a window signal to the gate contact of the FET, such that the slope signal and the window signal combine to form a memory access signal derived from a continuous weighted pulse position modulated (CW PPM) duration signal.

[0011] Advantages of the present invention include providing efficient data transmission of large amounts of data. Advantages of the present invention further include more efficient central processing unit (CPU) utilization and more efficient input / output (I / O) bandwidth utilization due to the efficient data transmission of large amounts of data. Further advantages include higher quality, cost reduction, better coverage, faster performance, fewer application errors, and fewer data errors.

[0012] In one preferred embodiment, a CW PPM duration signal is transmitted from a pre-neuron to a post-neuron via a network pathway.

[0013] In another preferred embodiment, the CW PPM duration signal is an exponentially decaying weighted signal.

[0014] In yet another preferred embodiment, the exponentially decaying weighting signal is based on the time since the synchronization pulse immediately preceding the exponentially decaying weighting signal was applied.

[0015] In yet another preferred embodiment, the steps are repeated by using a CW PPM duration signal generated from input analog values ​​that are the output of the MAC and AF.

[0016] In yet another preferred embodiment, the CW PPM duration signal allows for data transmission by shortening the duration pulses.

[0017] In yet another preferred embodiment, the memory access signal is divided into a slope signal and a window signal.

[0018] In yet another preferred embodiment, the slope signal and the window signal determine the amount of memory access for controlling data transmission.

[0019] It should be noted that exemplary embodiments are described with reference to different subject matters. In particular, some embodiments are described with reference to method-type claims, and other embodiments are described with reference to apparatus-type claims. However, those skilled in the art will infer from the above and following description that, unless otherwise specified, any combination of features belonging to one type of subject matter, as well as any combination of features relating to different subject matters, in particular any combination of features from a method-type claim with a feature from an apparatus-type claim, is also considered to be described herein.

[0020] These and other features and advantages will become apparent from the following detailed description of illustrative embodiments, which should be read in connection with the accompanying drawings.

[0021] The present invention is provided in more detail in the following description of preferred embodiments with reference to the following drawings. [Brief explanation of the drawings]

[0022] [Figure 1] FIG. 2 illustrates an exemplary continuous weighted pulse position modulation (PPM) duration scheme, in accordance with an embodiment of the present invention. [Figure 2] FIG. 2 illustrates an exemplary memory access signal for memory access volume, according to an embodiment of the present invention. [Figure 3] FIG. 10 is a block / flow diagram of an exemplary data process flow for a continuous weighted PPM duration scheme, in accordance with an embodiment of the present invention. [Figure 4] FIG. 2 illustrates an exemplary current-to-voltage converter in accordance with an embodiment of the present invention. [Figure 5] FIG. 1 illustrates an exemplary signal processing system for a continuous weighted PPM duration scheme, in accordance with an embodiment of the present invention. [Figure 6] FIG. 2 illustrates an exemplary continuous weighted PPM duration signal generator according to an embodiment of the present invention. [Figure 7] FIG. 2 illustrates an exemplary continuous weighted PPM duration signal to access signal converter according to an embodiment of the present invention. [Figure 8] 1 illustrates an exemplary cell and array structure using memory access signals, according to an embodiment of the present invention. [Figure 9] FIG. 1 is a block / flow diagram of an exemplary processing system using a continuous weighted PPM duration scheme in accordance with an embodiment of the present invention. [Figure 10] FIG. 1 is a block / flow diagram of an exemplary cloud computing environment, according to an embodiment of the present invention. [Figure 11]FIG. 2 is a schematic diagram of exemplary abstraction model layers, according to an embodiment of the present invention. [Figure 12] FIG. 1 illustrates a practical application using a continuous weighted PPM duration scheme according to an embodiment of the present invention. [Figure 13] 1 is a block / flow diagram of an exemplary method for using a continuous weighted PPM duration scheme, according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0023] Throughout the drawings, the same or similar reference numbers represent the same or similar elements.

[0024] Embodiments of the present invention provide a method and device for shortening a duration pulse using continuous weighting of the duration pulse's position. The added continuous weighting allows the duration pulse to be shortened by converting a continuously weighted pulse position modulated (PPM) signal into a memory access signal. After accessing an analog memory using the converted signal, a multiply-accumulate (MAC) operation is implemented using a memory array and a current-to-voltage converter. The MAC result is sent to an activation function (AF) to generate a duration signal pulse. The duration signal pulse is then converted into a continuously weighted PPM duration signal.

[0025] PPM is a signal modulation technique that allows computers to share data by measuring the time it takes for each data packet to reach the computer. PPM works by sending electrical, electromagnetic, or optical pulses to a computer or other device to communicate data. PPM requires both devices to be synchronized to the same clock, so once a series of pulses is sent, the device decodes the information based on when the pulses were broadcast. Herein, PPM can be used to advantageously transmit large amounts of data.

[0026] In today's competitive marketplace, the ability to execute quickly and decisively is critical to an organization's success. The amount of information available to businesses is growing rapidly and is often overwhelming. Organizations that effectively and efficiently manage these vast amounts of data and use the information to make business decisions realize a competitive advantage in the marketplace. Such a competitive advantage can be achieved by using the continuously weighted (CW) PPM duration method presented herein, which transmits large amounts of data quickly and efficiently.

[0027] While the present invention is described with respect to a given example architecture, it should be understood that other architectures, structures, substrate materials, process features, and steps / blocks can vary within the scope of the present invention. Note that for clarity, some features may not be shown in all figures. This is not intended to be construed as limiting any particular embodiment, or illustration, or the scope of the claims.

[0028] FIG. 1 is a diagram illustrating an exemplary continuous weighted pulse position modulation (PPM) duration scheme in accordance with an embodiment of the present invention.

[0029] Waveform 5 shows the input of the duration-to-access signal conversion, and waveform 5' shows the output of the duration-to-access signal conversion. An exemplary embodiment converts waveform 5 into a memory access amount. The maximum duration data period for both waveforms is 2 n From (ln2 n +α) or less.

[0030] FIG. 2 is a diagram illustrating exemplary memory access signals for memory access volume according to an embodiment of the present invention.

[0031] The memory access amount can be advantageously divided into a "slope" signal and a "window" signal. The first memory access amount signal 10 can be divided into a slope signal 12 and a window signal 14. The window signal 14 can have a width w1. The second memory access amount signal 20 can be divided into a slope signal 22 and a window signal 24. The window signal 24 can have a width w2, and w2 < w1. The third memory access amount signal 30 can be divided into a slope signal 32 and a window signal 34. The window signal 34 can have a width w3, and w3 < w2 < w1.

[0032] This correspondence can be explained by the following description. The memory access amount signal 10 (memory access amount 1) can be a signal that exponentially decays without delay from the start point timing. The memory access amount signal 20 (memory access amount 2) can be a signal that exponentially decays with a delay x1 from the start point timing, and the memory access amount signal 30 (memory access amount 3) can be the same signal with a delay x2 from the start point timing. The memory access amount can be controlled by the effective waveform period of the exponentially decaying signal. i In this case, i x + i+1 w is constant, so the effective waveform period i+1 w is determined. Therefore, the memory access amount can be determined by the start point timing of the exponentially decaying signal and the effective waveform period ( i+1 w). Therefore, the data transmission speed can be controlled by the CW PPM duration signal.

[0033] PPM is an analog modulation method in which the amplitude and width of the pulses remain constant, and the position of each pulse relative to the position of a reference pulse varies according to the instantaneous sampled value of the message signal. The transmitter must send a synchronization pulse to synchronize the transmitter and receiver. This synchronization pulse helps maintain the pulse position. Pulse position modulation is performed according to a pulse-width modulated signal. Each trailing edge of the pulse-width modulated signal becomes the starting point of a pulse in the PPM signal. The position of these pulses is therefore proportional to the width of the PWM pulse.

[0034] FIG. 3 is a block / flow diagram of an exemplary data process flow for a continuous weighted PPM duration scheme, in accordance with an embodiment of the present invention.

[0035] In block 40, a duration-to-access signal conversion is performed.

[0036] At block 42, a multiply-accumulate (MAC) operation is performed on the memory cells.

[0037] In block 44, a current-to-voltage conversion is performed.

[0038] In block 46, the activation function is implemented.

[0039] At block 48, duration generation is performed.

[0040] At block 49, a network router is advantageously used.

[0041] FIG. 4 is a diagram illustrating an exemplary current-to-voltage converter in accordance with an embodiment of the present invention.

[0042] Current-to-voltage converter 50 includes a first field-effect transistor (FET) 52 and a second FET 54, with second FET 54 connected to a third FET 56. Third FET 56 is connected to a fourth FET 58, which is connected to a capacitor 59. Third FET 56 and fourth FET 58 may be p-type metal-oxide-semiconductor (PMOS) transistors, and first FET 52 and second FET 54 may be n-type metal-oxide-semiconductor (NMOS) transistors. One skilled in the art can consider several different FET configurations to achieve the current-to-voltage conversion.

[0043] FIG. 5 is a diagram illustrating an exemplary signal processing system for a continuous weighted PPM duration scheme, in accordance with an embodiment of the present invention.

[0044] The signal processing system 60 may advantageously include a signal generator 62, a converter 64, a MAC computation unit 66, an activation function computation unit 68, and an output 69. Thus, the signal processing system 60 for an analog neural network device may include a signal generator 62 for generating a continuous-time weighted pulse-position modulation (CW PPM) duration signal from an input analog signal, a converter 64 for converting the CW PPM duration signal into a memory access signal, a multiply-accumulate (MAC) computation unit 66 for processing by accessing a memory using said memory access signal, and an activation function (AF) computation unit 68 for processing a result 69 of the MAC computation unit and generating an input analog signal for the signal generator.

[0045] FIG. 6 is a diagram illustrating an exemplary continuous weighted PPM duration signal generator according to an embodiment of the present invention.

[0046] The input signal vdg_level_in (70) is received by the positive terminal of a comparator 88. An operational amplifier in the form of a comparator 88 can be advantageously used to find values ​​of the input voltage that are greater than a specified range. In another embodiment, an operational amplifier in the form of a comparator 88 can be advantageously used to find values ​​of positive and negative voltages when a fixed value of the reference voltage source is associated with the inverting input.

[0047] The signal vdg_sync_in (72) is received by the synchronization timing controller 74. The synchronization timing controller 74 outputs four signals. The first signal, vdg_delayed_sync (76), is received by the waveform integrator 90. The vdg_delayed_sync (76) is also provided to a comparator 88 as an en_trig input, which triggers the enablement of the comparator 88. The second signal, vdg_duration_end (78), is provided to the comparator 88 as a reset trigger signal (rst_trig), which resets the output, vdg_cmp_result (89), of the comparator 88 to zero. The third signal, vdg_sync1 (80), is provided to a transmission gate (T-gate) 81, which functions as an on / off switch depending on the signal provided. The fourth signal, vdg_sync2 (82), is received by a T-gate 83 in a circuit configuration 85 having a resistor R and a capacitor C. The output of circuitry 85 is signal vdg_rc_slope (84), which is fed to an analog buffer 87 connected to the negative terminal of comparator 88. Comparator 88 advantageously outputs the result of the comparison as signal vdg_cmp_result (89), which is fed to waveform synthesizer 90 along with signal vdg_delayed_sync (76).

[0048] The signal vdg_rc_slope (84) fed to the negative terminal of comparator 88 is an exponentially decaying signal, and the input signal vdg_level_in (70) fed to the positive terminal of comparator 88 is an analog level signal. Comparator 88 compares these signals and advantageously provides an output signal vdg_out (92). The output of waveform integrator 90, the continuous weighted PPM duration signal (92), is shown in the lower right corner.

[0049] FIG. 7 is a diagram illustrating an exemplary continuous weighted PPM duration signal to access signal converter according to an embodiment of the present invention.

[0050] The signal vdasc_in (100) is received by the sync duration separator 102. The signal vdasc_in (100) is the signal (92) generated by the CW PPM duration signal generator of FIG.

[0051] The sync duration separator 102 advantageously outputs three signals. The first signal is vdasc_window_out (104). The second signal, vdasc_sync1 (106), is provided to a T-gate 107. The third signal, vdasc_sync2 (108), is provided to a T-gate 109 of circuitry 115 having a resistor R and a capacitor C. An analog buffer 112 receives a signal, vdasc_rc_slope (110), generated from the signals vdasc_sync1 (106) and vdasc_sync2 (108). The output of the analog buffer 112 is a signal, vdasc_slope_out (114). Because the analog buffer 112 simply drives the input analog signal to generate the output analog signal, the waveforms of the input signal, vdasc_rc_slope (110) and the output signal, vdasc_slope_out (114), are substantially identical. The signal vdasc_slope_out (114) is an exponentially decaying signal, so the signal vdasc_in (100) is advantageously transformed into the memory access signal vdasc_slope_out (114).

[0052] FIG. 8 is a diagram illustrating an exemplary cell and array structure using memory access signals, according to an embodiment of the present invention.

[0053] The array structure 190 includes a plurality of cells. The first cell 130 includes a FET 132 and a variable resistor 134. The variable resistor 134 may be connected to the drain (D) of the FET 132. The source (S) of the FET 132 may be connected to a bit line 192. The bit line 192 may connect the sources (S) of several FETs of various cells. For example, cell 150 and cell 170 are vertically aligned with cell 130. Cell 150 includes a variable resistor 154 and a FET 152, and cell 170 includes a variable resistor 174 and a FET 172. Similarly, cell 140 may be horizontally aligned with cell 130, cell 160 may be horizontally aligned with cell 150, and cell 180 may be horizontally aligned with cell 170. For example, cell 140 includes a variable resistor 144 and a FET 142. The source (S) of the FET 140 may be connected to a bit line 194. The bit line 194 may connect the sources (S) of several FETs of different cells, i.e., cells 160, 180.

[0054] Signal vdasc_slope_out_0 (120) is advantageously received by one of the word lines 136 of the first series of horizontal cells 130, 140, etc. Signal vdasc_window_out_0 (122) is advantageously received by another word line 138 connected to the gates of FETs 132 of cell 130 and 142 of cell 140, etc. Signal 120 may be an exponentially decaying signal, and signal 122 may be a pulsed signal. The pulsed signal may have a width w4. The memory access volume may be represented by w4. vdasc_slope_out_0 (120) is a full exponentially decaying signal, and vdasc_window_out_0 (122) is high for a limited period (w4). These two signals ensure that the access current from memory cell 130 is proportional to the level of vdasc_slope_out_0 (120) only during w4. This is because FET 132 is turned on when vdasc_window_out_0 (122) is high. In other words, no read current flows from cell 130 when vdasc_window_out_0 (122) is low.

[0055] Signal vdasc_slope_out_1 (124) is advantageously received by one of word lines 156 of the first series of horizontal cells 150, 160, etc. Signal vdasc_window_out_1 (126) is advantageously received by another word line 158 connected to the gates of FETs 152 of cell 150 and 162 of cell 160, etc. Signal 124 may be an exponentially decaying signal, and signal 126 may be a pulsed signal. The pulsed signal may have a width w5. The memory access volume may be represented by w5. vdasc_slope_out_1 (124) is a full exponentially decaying signal, and vdasc_window_out_1 (126) is high for a limited period (w5). These two signals ensure that the access current from memory cell 150 is proportional to the level of vdasc_slope_out_1 (124) only during w5. This is because FET 152 is on when vdasc_window_out_1 (126) is high. In other words, no read current flows out of cell 150 when vdasc_window_out_1 (126) is low.

[0056] Signal vdasc_slope_out_n-1 (128) is advantageously received by one of the word lines 176 of the first series of horizontal cells 170, 180, etc. Signal vdasc_window_out_n-1 (129) is advantageously received by another word line 178 connected to the gates of FETs 172 of cell 170 and 182 of cell 189, etc. Signal 128 may be an exponentially decaying signal, and signal 129 may be a pulse signal. The pulse signal may have a width w6. The amount of memory access may be represented by w6. vdasc_slope_out_n-1 (128) is a full exponentially decaying signal, and vdasc_window_out_n-1 (129) goes high for a finite period (w6). These two signals ensure that the access current from memory cell 170 is proportional to the level of vdasc_slope_out_n-1 (128) only during w6. This is because FET 172 is on when vdasc_window_out_n-1 (129) is high. In other words, no read current flows from cell 170 when vdasc_window_out_n-1 (129) is low. Therefore, vdasc_slope_out_0 (120), vdasc_slope_out_1 (124), ..., and vdasc_slope_out_n-1 (128) all have the same shape, but vdasc_window_out_0 (122), vdasc_window_out_1 (124), ..., and vdasc_window_out_n-1 (129) vary from word to word.

[0057] Therefore, data transmission can be achieved using CW PPM duration signals. Data transmission rate is a measurement of the amount of data sent between two points on a network in a given period of time. High data transmission rates, enabling networks to be used for complex tasks like online streaming, are an important concept in modern business networking. Understanding data transmission rate can help improve the performance of your business's own network. Data transmission rate is typically measured in bits per second (bps), where one "bit" is equal to an individual binary digit. This is similar to the networking concept of bandwidth, which is also measured in bps. However, transmission rate and bandwidth are two different things. Transmission rate focuses on the amount of data actually transmitted between two different points, while bandwidth is a measure of the theoretical maximum transmission capacity of a point on a network.

[0058] Every network application requires a certain amount of data to function effectively. For example, a web browser must receive the necessary web page data each time a user navigates to a new page. A low transmission rate effectively prevents this data from being delivered to the application, typically resulting in slower performance, such as slower speeds or stuttering. In addition, very low transmission rates can cause some applications to stop functioning entirely. Some online tasks require higher data transmission rates than others. For example, online streaming essentially requires a computer to download a new image every fraction of a second. This consumes much more data than, say, sending an email. Therefore, the impact of low data transmission rates is most readily felt by organizations and individuals who regularly work with data-intensive applications. The CW PPM duration signals used herein, shown in Figures 1 through 8, can advantageously achieve fast and efficient data transmission rates.

[0059] FIG. 9 is a block / flow diagram of an exemplary processing system using a continuous weighted PPM duration scheme in accordance with an embodiment of the present invention.

[0060] 9 is a block diagram of components of a system 200 including a computing device 205. It should be understood that FIG. 9 is merely provided as an illustration of one implementation and is not intended to imply any limitation with regard to the environments in which different embodiments may be implemented. Many modifications to the depicted environment may be made.

[0061] Computing device 205 includes communications fabric 202, which provides communication between computer processor 204, memory 206, persistent storage 208, communications unit 210, and input / output (I / O) interface 212. Communications fabric 202 may be implemented with any architecture designed to pass data and / or control information between processors (such as microprocessors, communications and network processors), system memory, peripheral devices, and any other hardware components in the system. For example, communications fabric 202 may be implemented with one or more buses.

[0062] Memory 206, cache memory 216, and persistent storage 208 are computer-readable storage media. In this embodiment, memory 206 includes random access memory (RAM) 214. In another embodiment, memory 206 may be flash memory. In general, memory 206 may include any suitable volatile or non-volatile computer-readable storage medium.

[0063] In some embodiments of the present invention, a program 225 is included and operated by an AI accelerator chip 222 as a component of a computing device 205. In other embodiments, the program 225 is stored in persistent storage 208 and executed by the AI ​​accelerator chip 222 in conjunction with one or more of the respective computer processors 204 via one or more of the memories 206. The AI ​​accelerator chip 222 can advantageously power the neural network device 250 via CW PPM duration signal processing 496. In this embodiment, the persistent storage 208 includes a magnetic hard disk drive. Instead of or in addition to a magnetic hard disk drive, the persistent storage 208 can include a solid-state hard drive, a semiconductor storage device, a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, or any other computer-readable storage medium capable of storing program instructions or digital information.

[0064] The media used by persistent storage 208 may be removable. For example, a removable hard drive may be used for persistent storage 208. Other examples include optical and magnetic disks, thumb drives, and smart cards that are inserted into a drive for transfer to another computer-readable storage medium that is also part of persistent storage 208.

[0065] In these examples, the communications unit 210 provides communication with other data processing systems or devices, including resources of the distributed data processing environment. In these examples, the communications unit 210 includes one or more network interface cards. The communications unit 210 can provide communication using either or both physical and wireless communications links. The deep learning program 225 can be downloaded to the persistent storage 208 through the communications unit 210.

[0066] I / O interface 212 allows for the input and output of data with other devices that may be connected to computing system 200. For example, I / O interface 212 may provide connection to external devices 218, such as a keyboard, keypad, touch screen, or other suitable input device, or a combination thereof. External devices 218 may also include portable computer-readable storage media, such as, for example, thumb drives, portable optical or magnetic disks, and memory cards.

[0067] Display 220 provides a mechanism for displaying data to a user and may be, for example, a computer monitor.

[0068] FIG. 10 is a block / flow diagram of an exemplary cloud computing environment, according to an embodiment of the present invention.

[0069] Although the present invention includes detailed descriptions relating to cloud computing, it should be understood that implementation of the teachings described herein is not limited to cloud computing environments. Rather, embodiments of the present invention may be implemented in conjunction with any other type of computing environment now known or later developed.

[0070] Cloud computing is a service delivery model for enabling convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) that can be rapidly provisioned and released with minimal administrative effort or interaction with the service provider. This cloud model can include at least five characteristics, at least three service models, and at least four deployment models.

[0071] The features are as follows:

[0072] On-Demand Self-Service: Cloud consumers can unilaterally provision computing capacity, such as server time and network storage, automatically as needed, without the need for human interaction with the provider of the service.

[0073] Broadband Network Access: Functionality is available over the network and accessed through standard mechanisms that facilitate use by heterogeneous thin or thick client platforms (e.g., cell phones, laptops, and PDAs).

[0074] Resource Pooling: To accommodate multiple consumers using a multi-tenant model, a provider's computing resources are pooled, with different physical and virtual resources dynamically allocated and reallocated according to demand. Consumers generally have no control or knowledge of the exact location of the resources provided, but there is a sense of location independence in that they can specify a higher level of abstraction (e.g., country, state, or data center).

[0075] Rapid Elasticity: Capabilities are quickly and elastically provisioned, sometimes automatically, so they can be quickly scaled out, and quickly released so they can be quickly scaled in. To the consumer, the capabilities available for provisioning often appear unlimited, and any amount can be purchased at any time.

[0076] Metered Services: Cloud systems automatically control and optimize resource usage by leveraging metering capabilities at some level of abstraction appropriate to the type of service (e.g., storage, processing, bandwidth, and active user accounts). Resource usage can be monitored, controlled, and reported to provide transparency to both providers and consumers of utilized services.

[0077] The service model is as follows:

[0078] Software as a Service (SaaS): The functionality offered to the consumer is the use of a provider's applications running on a cloud infrastructure. The applications are accessible from a variety of client devices through a thin-client interface such as a web browser (e.g., web-based email). The consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, storage, or individual application functions, except for limited user-specific application configuration settings.

[0079] Platform as a Service (PaaS): The capability offered to consumers is the deployment of consumer-created or consumer-acquired applications, written using programming languages ​​and tools supported by the provider, on a cloud infrastructure. The consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, or storage, but has control over the deployed applications and, in some cases, the application hosting environment configuration.

[0080] Infrastructure as a Service (IaaS): The functionality offered to consumers is the provisioning of processing, storage, networking, and other basic computing resources, upon which the consumer can deploy and run any software, which may include operating systems and applications. The consumer does not manage or control the underlying cloud infrastructure, but does have control over the operating system, storage, deployed applications, and possibly limited control over selected networking components (e.g., host firewalls).

[0081] The deployment models are as follows:

[0082] Private Cloud: This cloud infrastructure is operated solely for the organization. It may be managed by the organization or a third party and may reside on-premise or off-premise.

[0083] Community Cloud: This cloud infrastructure is shared by several organizations to support a specific community with common concerns (e.g., mission, security requirements, policies, and compliance issues). It may be managed by the organization or a third party and may reside on-premises or off-premises.

[0084] Public Cloud: This cloud infrastructure is available to the general public or large industry organizations and is owned by an organization that sells cloud services.

[0085] Hybrid Cloud: This cloud infrastructure is a composite of two or more clouds (private, community, or public) that remain unique entities but are bound together by standardized or proprietary technologies that allow for data and application portability (e.g., cloud bursting for load balancing between clouds).

[0086] Cloud computing environments are service-oriented, focusing on statelessness, loose coupling, modularity, and semantic interoperability. At the heart of cloud computing is an infrastructure that includes a network of interconnected nodes.

[0087] Referring now to FIG. 10 , a cloud computing environment 350 that enables use cases of the present invention is illustrated. As shown, the cloud computing environment 350 includes one or more cloud computing nodes 310 that can communicate with local computing devices used by cloud consumers, such as, for example, a personal digital assistant (PDA) or mobile phone 354 a, a desktop computer 354 b, a laptop computer 354 c, or an automotive computer system 354 n, or combinations thereof. The nodes 310 can communicate with each other. The nodes 310 can be physically or virtually grouped (not shown) in one or more networks, such as the aforementioned private cloud, community cloud, public cloud, or hybrid cloud, or combinations thereof. This enables the cloud computing environment 350 to provide infrastructure, platform, and / or software as a service for which the cloud consumer does not need to maintain resources on their local computing device. The types of computing devices 354a-354n shown in FIG. 10 are merely exemplary, and it is understood that computing node 310 and cloud computing environment 350 can communicate (e.g., using a web browser) with any type of computerized device over any type of network and / or network-addressable connection.

[0088] 11 is a schematic diagram of exemplary abstract model layers according to an embodiment of the present invention. It should be understood in advance that the components, layers, and functions shown in FIG. 11 are merely exemplary, and embodiments of the present invention are not limited thereto. As shown, the following layers and corresponding functions are provided:

[0089] Hardware and software layer 460 includes hardware and software components. Examples of hardware components include mainframes 461, reduced instruction set computer (RISC) architecture-based servers 462, servers 463, blade servers 464, storage devices 465, and networks and networking components 466. In some embodiments, software components include network application server software 467 and database software 468.

[0090] Virtualization layer 470 provides an abstraction layer from which the following examples of virtual entities can be provided: virtual servers 471, virtual storage 472, virtual networks including virtual private networks 473, virtual applications and operating systems 474, and virtual clients 475.

[0091] In one example, management layer 480 can provide the following functions: Resource provisioning 481 dynamically procures computing and other resources utilized to execute tasks within the cloud computing environment. Metering and pricing 482 tracks costs as resources are utilized within the cloud computing environment and bills or invoices for the consumption of these resources. In one example, these resources can include application software licenses. Security verifies the identity of cloud consumers and tasks and protects data and other resources. User portal 483 provides consumers and system administrators with access to the cloud computing environment. Service level management 484 allocates and manages cloud computing resources to ensure required service levels are met. Service level agreement (SLA) planning and fulfillment 485 pre-arranges and procures cloud computing resources where future requirements are forecasted according to SLAs.

[0092] Workload layer 490 provides examples of functions for which a cloud computing environment can be utilized. Examples of workloads and functions that can be provided from this layer include mapping and navigation 491, software development and lifecycle management 492, virtual classroom instruction delivery 493, data analytics processing 494, transaction processing 495, and CW PPM duration signal processing 496.

[0093] FIG. 12 is a diagram illustrating a practical application using a continuous weighted PPM duration scheme according to an embodiment of the present invention.

[0094] The artificial intelligence (AI) accelerator chip 501 can implement or power neural network devices 250 via CW PPM duration signal processing 496 and can be used in a wide variety of real-world applications including, but not limited to, robotics 510, industrial applications 512, mobile or Internet of Things (IoT) 514, personal computers 516, consumer electronics 518, server data centers 520, physical and chemical applications 522, medical applications 524, and financial applications 526.

[0095] For example, Robotic Process Automation (RPA) 510 enables organizations to automate tasks, streamline processes, improve employee productivity, and ultimately deliver a satisfying customer experience. Through the use of RPA 510, robots can perform high-volume, repetitive tasks, freeing up company resources to work on higher-value activities. RPA robots 510 emulate humans performing manual, repetitive tasks, making decisions based on a prescribed set of rules, and integrating with existing applications. All of this is done while maintaining compliance, reducing errors, and improving customer experience and employee engagement.

[0096] FIG. 13 is a block / flow diagram of an exemplary method for using a continuous weighted PPM duration scheme, according to an embodiment of the present invention.

[0097] In block 602, a continuous-time weighted pulse-position modulated (CW PPM) duration signal is generated from an input analog signal.

[0098] At block 604, the CW PPM duration signal is transmitted from the pre-neuron to the post-neuron via the network paths.

[0099] At block 606, the CW PPM duration signal is converted into a memory access signal.

[0100] At block 608, a multiply-accumulate (MAC) operation is performed using the memory access signals.

[0101] In block 610, the activation function (AF) generates the input analog signal from the result of the MAC operation.

[0102] The present invention may be a system, a method, and / or a computer program product, which may include one or more computer-readable storage media having computer-readable program instructions for causing a processor to perform aspects of the present invention.

[0103] A computer-readable storage medium may be a tangible device capable of retaining and storing instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the above. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: portable computer diskettes, hard disks, random access memory, read-only memory, erasable programmable read-only memory (EPROM or flash memory), static random access memory, portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanically encoded devices such as punch cards or ridge structures in grooves on which instructions are recorded, and any suitable combination of the above. As used herein, computer-readable storage media should not be construed as being ephemeral signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses passing through fiber optic cable), or electrical signals transmitted over electrical wires.

[0104] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or can be downloaded to an external computer or external storage device over a network, such as the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage on a computer-readable storage medium within the respective computing / processing device.

[0105] Computer-readable program instructions for carrying out the operations of the present invention may be source or object code written in any combination of one or more programming languages, including assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, or conventional procedural programming languages, such as object-oriented programming languages ​​like Smalltalk®, C++, and the like, and traditional procedural programming languages, such as the "C" programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) may execute computer-readable program instructions by utilizing state information of the computer-readable program instructions to personalize the electronic circuitry to carry out aspects of the present invention.

[0106] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0107] These computer-readable program instructions may be provided to at least one processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to create a machine, such that the instructions, executed by the processor of the computer or other programmable data processing apparatus, create means for performing the functions / acts specified in one or more blocks or modules of the flowcharts and / or block diagrams. These computer-readable program instructions may be stored on a computer-readable storage medium, such that the computer-readable storage medium on which the instructions are stored comprises an article of manufacture containing instructions for implementing aspects of the functions / acts specified in one or more blocks or modules of the flowcharts and / or block diagrams, instructing a computer, programmable data processing apparatus, or other device, or combination thereof, to function in a particular manner.

[0108] The computer-readable program instructions may be loaded into a computer, other programmable data processing apparatus, or other device and cause the computer, other programmable apparatus, or other device to perform a series of operational blocks / steps to create a computer-implemented process, such that the instructions, which execute on the computer, other programmable apparatus, or other device, perform the functions / operations specified in one or more blocks or modules of the flowcharts and / or block diagrams.

[0109] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing specified logical functions. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending on the functionality involved. It should also be noted that each block in the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by a dedicated hardware-based system that performs the specified functions or operations or executes a combination of dedicated hardware and computer instructions.

[0110] References herein to "one embodiment" or "an embodiment" of the present principles, as well as other variations thereof, mean that a particular feature, structure, or characteristic, etc., described in connection with the embodiment is included in at least one embodiment of the present principles. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment," as well as any other variations thereof, in various places throughout this specification do not necessarily all refer to the same embodiment.

[0111] It should be understood that the use of any of " / ", "or or both", "at least one of", for example, "A / B", "A or B or both", "at least one of A and B", is intended to encompass the selection of only the first listed alternative (A), or the selection of only the second listed alternative (B), or the selection of both alternatives (A and B). As a further example, "A, B, or C, or a combination thereof" and "at least one of A, B, and C", such language is intended to encompass the selection of only the first listed alternative (A), or the selection of only the second listed alternative (B), or the selection of only the third listed alternative (C), or the selection of only the first listed alternative and the second listed alternative (A and B), or the selection of only the first listed alternative and the third listed alternative (A and C), or the selection of only the second listed alternative and the third listed alternative (B and C), or the selection of all three alternatives (A, B, and C). This can be extended to many of the items listed, as would be readily apparent to one of ordinary skill in this and related arts.

[0112] Having described a preferred embodiment of a method for data transmission using a continuous weighted pulse position modulated (PPM) duration signal, which is intended to be illustrative and not limiting, it should be noted that modifications and variations can be made by those skilled in the art in light of the above teachings. It is therefore understood that changes can be made in the particular embodiments described and are within the scope of the invention as outlined by the appended claims. Having thus described aspects of the invention with the detail and particularity required by the patent laws, what is claimed and desired to be protected by Letters Patent is set forth in the appended claims.

Claims

1. 1. A computer-implemented method for processing a signal, comprising: generating a continuous-time weighted pulse-position modulated (CW PPM) duration signal from an input analog signal; converting said CW PPM duration signal into a memory access signal; performing a multiply-accumulate (MAC) operation using the memory access signals; generating the input analog signal from the result of the MAC operation by an activation function (AF); 11. A computer-implemented method comprising:

2. The computer-implemented method of claim 1 , wherein the CW PPM duration signal is transmitted from pre-neurons to post-neurons through a network.

3. The computer-implemented method of claim 1 , wherein the CW PPM duration signal is an exponentially decaying weighted signal.

4. 4. The computer-implemented method of claim 3, wherein the exponentially decaying weighted signal is based on the time since a synchronization pulse was applied immediately preceding the exponentially decaying weighted signal.

5. 2. The computer-implemented method of claim 1, further comprising repeating each step of the method by using the CW PPM duration signal generated from an input analog value that is the output of the MAC and the AF.

6. The computer-implemented method of claim 1 , wherein the CW PPM duration signal enables data transmission by shortening the duration pulses.

7. 2. The computer-implemented method of claim 1, wherein the memory access signal is divided into a slope signal and a window signal.

8. 8. The computer-implemented method of claim 7, wherein the slope signal and the window signal determine an amount of memory access for controlling data transmission.

9. A computer program for processing a signal, the computer program causing a computer to carry out the steps of the method according to any one of claims 1 to 8.

10. 1. A signal processing system for an analog neural network device, comprising: a signal generator for generating a continuous-time weighted pulse-position modulated (CW PPM) duration signal from an input analog signal; a converter for converting the CW PPM duration signal into a memory access signal; a multiply-accumulate (MAC) calculator for processing by accessing a memory using the memory access signal; an activation function (AF) calculator for processing the result of the MAC calculator and generating the input analog signal for the signal generator; A signal processing system comprising:

11. 11. The system of claim 10, wherein the CW PPM duration signal is transmitted from pre-neurons to post-neurons via a network router.

12. 11. The system of claim 10, wherein the CW PPM duration signal is an exponentially decaying weighted signal.

13. 13. The system of claim 12, wherein the exponentially decaying weighted signal is based on the time since a synchronization pulse was applied immediately preceding the exponentially decaying weighted signal.

14. 11. The system of claim 10, wherein the CW PPM duration signal enables data transmission by shortening the duration pulses.

15. 11. The system of claim 10, wherein the memory access signal is divided into a slope signal and a window signal.

16. 16. The system of claim 15, wherein the slope signal and the window signal determine the amount of memory access for controlling data transmission.

17. An array structure, A plurality of memory cells interposed between a plurality of bit lines and a plurality of word lines, each memory cell comprising: a field effect transistor (FET) including a gate contact, a source contact, and a drain contact; a variable resistor having one end electrically connected to the drain contact of the FET and the other end electrically connected to one of two word lines of a memory cell; Including, a slope signal is provided to one of the word lines and a window signal is provided to another word line connected to the gate contact of the FET, such that the slope signal and the window signal combine to form a memory access signal derived from a continuous weighted pulse position modulated (CW PPM) duration signal.

18. 1. A method for constructing an array structure, comprising: Incorporating a plurality of memory cells between a plurality of bit lines and a plurality of word lines, each memory cell comprising: a field effect transistor (FET) including a gate contact, a source contact, and a drain contact; a variable resistor having one end electrically connected to the drain contact of the FET and the other end electrically connected to one of two word lines of a memory cell; incorporating a plurality of memory cells, providing a slope signal to one of the word lines and a window signal to another word line connected to the gate contact of the FET, such that the slope signal and the window signal combine to form a memory access signal derived from a continuous weighted pulse position modulated (CW PPM) duration signal; A method comprising:

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