Semiconductor device, power conversion device, and method for manufacturing the semiconductor device

Abstract

The description of the present application discloses a technology for enhancing the reliability of a semiconductor device. A semiconductor device according to the technology disclosed in the description of the present application is provided with: a semiconductor layer; a first electrode layer which covers a part of the upper surface of the semiconductor layer; and an insulating film which covers another part of the upper surface of the semiconductor layer and a part of the upper surface of the first electrode layer. With respect to this semiconductor device, the arithmetic mean roughness of the upper surface of the insulating film is lower than the arithmetic mean roughness of the interface between the insulating film and the first electrode layer.

Description

[Technical Field]

[0001] The technology disclosed in the present specification relates to a technology for improving the reliability of a semiconductor device. [Background technology]

[0002] For example, semiconductor devices such as those disclosed in Patent Document 1, particularly power semiconductor devices such as insulated gate bipolar transistors (IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), or Schottky barrier diodes (SBDs), are widely used as inverter circuits for industrial motors or automotive motors, power supplies for large-capacity servers, or semiconductor switches for uninterruptible power supplies. In recent years, semiconductor devices have been miniaturized by increasing the current density of the semiconductor devices, and the manufacturing costs of the semiconductor devices have been reduced. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-50358 Summary of the Invention [Problem to be solved by the invention]

[0004] As the current density of a semiconductor device increases, the temperature of the components during operation also increases, increasing the temperature difference between when the components are not operating. Therefore, due to the stress caused by thermal expansion and contraction due to differences in the linear expansion coefficients of the components, the electrode layer or mold resin surrounding the protective insulating film that constitutes the semiconductor device may peel off or crack in the protective insulating film that ensures the semiconductor device's insulation performance from the outside. In this case, the insulating performance of the semiconductor device becomes insufficient, resulting in a problem of a loss of reliability of the semiconductor device.

[0005] The technology disclosed in the present specification has been made in consideration of the problems described above, and is a technology for improving the reliability of semiconductor devices. [Means for solving the problem]

[0006] A semiconductor device that is a first aspect of the technology disclosed in the present specification comprises a semiconductor layer, a first electrode layer covering a portion of an upper surface of the semiconductor layer, and an insulating film covering another portion of the upper surface of the semiconductor layer and a portion of an upper surface of the first electrode layer, wherein the arithmetic mean roughness of the upper surface of the insulating film is smaller than the arithmetic mean roughness of the interface between the insulating film and the first electrode layer. [Effects of the Invention]

[0007] According to at least the first aspect of the technology disclosed in the present specification, the connection between the protective insulating film and the components below can be made stronger than the connection between the protective insulating film and the components above it, thereby making it possible to suppress peeling of the protective insulating film during operation, etc. With this configuration, the reliability of the semiconductor device can be improved.

[0008] Furthermore, objects, features, aspects, and advantages associated with the technology disclosed herein will become more apparent from the detailed description set forth below and the accompanying drawings. [Brief explanation of the drawings]

[0009] [Figure 1]1A and 1B are diagrams schematically illustrating an example of the configuration of a semiconductor device manufactured by a manufacturing method described in an embodiment. [Figure 2] 1A and 1B are diagrams schematically illustrating an example of the configuration of a semiconductor device manufactured by a manufacturing method described in an embodiment. [Figure 3] 1A and 1B are diagrams schematically illustrating an example of the configuration of a semiconductor device manufactured by a manufacturing method described in an embodiment. [Figure 4] 1 is a flowchart illustrating an example of a manufacturing process for a SiC-SBD according to an embodiment. [Figure 5] 1A to 1C are cross-sectional views showing an example of a manufacturing process for a SiC-SBD according to an embodiment. [Figure 6] 1A to 1C are cross-sectional views showing an example of a manufacturing process for a SiC-SBD according to an embodiment. [Figure 7] 1A to 1C are cross-sectional views showing an example of a manufacturing process for a SiC-SBD according to an embodiment. [Figure 8] 1A to 1C are cross-sectional views showing an example of a manufacturing process for a SiC-SBD according to an embodiment. [Figure 9] 1A to 1C are cross-sectional views showing an example of a manufacturing process for a SiC-SBD according to an embodiment. [Figure 10] 1A to 1C are cross-sectional views showing an example of a manufacturing process for a SiC-SBD according to an embodiment. [Figure 11] 1A to 1C are cross-sectional views showing an example of a manufacturing process for a SiC-SBD according to an embodiment. [Figure 12] 1A to 1C are cross-sectional views showing an example of a manufacturing process for a SiC-SBD according to an embodiment. [Figure 13] 2 is an enlarged view showing a configuration in the vicinity of a surface electrode and a protective insulating film of a semiconductor device according to an embodiment; FIG. [Figure 14] FIG. 1 is a diagram illustrating the definition of arithmetic mean roughness. [Figure 15] FIG. 10 is a graph showing the relationship between the ratio of the arithmetic mean roughness of the top and bottom surfaces of a protective insulating film and the peeling rate of the protective insulating film after a power cycle test of 100,000 times. [Figure 16]This figure shows the relationship between the angle of the vertex and the incidence of cracks when the ratio of the arithmetic mean roughness of the top and bottom surfaces of the protective insulating film is set to 0.7, focusing on the vertex with the smallest angle among the vertices formed at the end of the top surface of the protective insulating film. [Figure 17] 1A and 1B are diagrams schematically illustrating an example of the configuration of a semiconductor device manufactured by a manufacturing method described in an embodiment. [Figure 18] 1A and 1B are diagrams schematically illustrating an example of the configuration of a semiconductor device manufactured by a manufacturing method described in an embodiment. [Figure 19] 1A and 1B are diagrams schematically illustrating an example of the configuration of a semiconductor device manufactured by a manufacturing method described in an embodiment. [Figure 20] 1 is a flowchart illustrating an example of a manufacturing process for a SiC-SBD according to an embodiment. [Figure 21] 21 is a cross-sectional view showing an example of the structure of a semiconductor device in which steps up to step ST06 in FIG. 20 have been completed. [Figure 22] 1 is a flowchart showing an example of plating pretreatment and plating treatment. [Figure 23] 10 is a flowchart showing a modified example of zincate treatment. [Figure 24] 10 is a flowchart showing a modified example of zincate treatment. [Figure 25] 1A and 1B are diagrams illustrating an example of the structure of a semiconductor device. [Figure 26] 1A and 1B are diagrams illustrating an example of the structure of a semiconductor device. [Figure 27] 1A and 1B are diagrams illustrating an example of the structure of a semiconductor device. [Figure 28] 1A and 1B are diagrams illustrating an example of the structure of a semiconductor device. [Figure 29] FIG. 10 is a diagram showing the relationship between the difference between the interface between the surface electrodes and the interface between the surface electrode and the protective insulating film, and the defect rate after an assembly test. [Figure 30] 1 is a diagram illustrating a schematic configuration of a power conversion system to which a power conversion device according to an embodiment is applied; [Figure 31]1A and 1B are diagrams schematically illustrating an example of the configuration of a semiconductor device manufactured by a manufacturing method described in an embodiment. [Figure 32] 1A and 1B are diagrams schematically illustrating an example of the configuration of a semiconductor device manufactured by a manufacturing method described in an embodiment. [Figure 33] 1A and 1B are diagrams schematically illustrating an example of the configuration of a semiconductor device manufactured by a manufacturing method described in an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments will be described with reference to the accompanying drawings. In the following embodiments, detailed features will be shown for the purpose of explaining the technology, but these are merely examples and are not necessarily essential features for enabling the embodiments to be implemented.

[0011] The drawings are schematic, and for the sake of convenience, components may be omitted or simplified as appropriate. The relative sizes and positions of components shown in different drawings are not necessarily accurately depicted and may be changed as appropriate. Hatching may also be used in drawings such as plan views that are not cross-sectional views to facilitate understanding of the embodiments.

[0012] In the following description, the same components are denoted by the same reference numerals, and their names and functions are also the same. Therefore, detailed descriptions of them may be omitted to avoid duplication.

[0013] Furthermore, in the description given in this specification, when a certain component is described as "comprising," "including," or "having," unless otherwise specified, this is not an exclusive expression that excludes the presence of other components.

[0014] Furthermore, although ordinal numbers such as "first" or "second" may be used in the descriptions in this specification, these terms are used for convenience to facilitate understanding of the contents of the embodiments, and the contents of the embodiments are not limited to the order that may result from these ordinal numbers.

[0015] Furthermore, in the description given in this specification, expressions such as "positive direction of the ... axis" or "negative direction of the ... axis" refer to the direction along the arrow of the ... axis shown in the figure as the positive direction, and the direction opposite to the arrow of the ... axis shown in the figure as the negative direction.

[0016] Furthermore, in the explanations given in this specification, expressions indicating an equal state, such as "identical," "equal," "uniform," or "homogeneous," unless otherwise specified, include cases indicating a strictly equal state and cases where there is a difference within a tolerance or within a range where the same level of functionality is obtained.

[0017] Furthermore, in the description provided in this specification, terms that indicate specific positions or directions, such as "top," "bottom," "left," "right," "side," "bottom," "front," or "back," may be used, but these terms are used for convenience to facilitate understanding of the contents of the embodiments and have no relation to the positions or directions when the embodiments are actually implemented.

[0018] Furthermore, in the description of the present specification, when "the upper surface of ..." or "the lower surface of ..." is used, it is intended to include not only the upper surface or lower surface of the target component itself, but also a state in which another component is formed on the upper surface or lower surface of the target component. For example, when it is described as "B provided on the upper surface of A," it does not preclude another component "C" from being interposed between A and B.

[0019] First Embodiment A semiconductor device and a method for manufacturing the semiconductor device according to this embodiment will be described below.

[0020] <Configuration of semiconductor device> 1, 2, and 3 are diagrams schematically illustrating examples of the configuration of a semiconductor device manufactured by the manufacturing method described in this embodiment. In the example of Fig. 1, a SiC Schottky barrier diode (SBD) is shown.

[0021] Fig. 1 is a plan view of a SiC-SBD. As shown in Fig. 1, a surface electrode 2 is formed in the central current-carrying region, and a protective insulating film 4 is formed around it to ensure insulation from the surroundings.

[0022] FIG. 2 is a cross-sectional view corresponding to the A-A' cross section indicated by the dashed line in FIG. 1. In a front-back conduction type power semiconductor device, current flows in the Z-axis direction in FIG. 2. A front surface electrode 2 is provided on the top surface of a semiconductor substrate 1, and a back surface electrode 3 is provided on the bottom surface of the semiconductor substrate 1. The front surface electrode 2 and the back surface electrode 3 are each connected to the outside by appropriate means such as wire or soldering. In addition, a protective insulating film 4 is provided on the outer periphery of the front surface electrode 2 to prevent insulation failure of the semiconductor device due to discharge at the outer periphery of the chip.

[0023] Figure 3 is an enlarged view of the area surrounded by the dashed line in Figure 2. A surface electrode 2 is formed on the upper surface of a semiconductor substrate 1, and a protective insulating film 4 is further formed on the upper surface of the surface electrode 2. The arithmetic mean roughness of the upper surface of the protective insulating film 4 is smaller than the arithmetic mean roughness of the interface between the protective insulating film 4 and the surface electrode 2 (i.e., the lower surface of the protective insulating film 4). The upper end of the protective insulating film 4 has multiple vertices.

[0024] <About the manufacturing method of semiconductor devices> Fig. 4 is a flowchart showing an example of a manufacturing process for a SiC-SBD according to this embodiment. Fig. 5 to Fig. 12 are cross-sectional views showing an example of a manufacturing process for a SiC-SBD according to this embodiment. The manufacturing process for a SiC-SBD will be specifically described below with reference to Fig. 5 to Fig. 12.

[0025] As shown in Figure 5, drift layer 6 made of n-type SiC is formed as a first-layer epitaxial film on a first main surface (hereinafter referred to as the front surface) located on the positive side of the Z axis of n-type SiC substrate 5, and then drift layer 7 is formed as a second-layer epitaxial film by epitaxial crystal growth at a growth temperature lower than the growth temperature of drift layer 6 so as to be in contact with the upper surface of drift layer 6 (corresponding to step ST01 in Figure 4).

[0026] Next, as shown in FIG. 6, an interlayer insulating film 8 is formed on the upper surface of the drift layer 7 by a deposition method such as thermal oxidation or chemical vapor deposition.

[0027] Thereafter, as shown in FIG. 7, a mask (not shown here) made of resist or the like is formed using photolithography, and then the interlayer insulating film 8 in unnecessary regions is removed by dry etching using plasma or wet etching using a chemical solution, and further the mask is removed by plasma ashing or wet processing, or the like.

[0028] In addition, in the drift layer 7 facing the interlayer insulating film 8, an impurity layer is formed by appropriate ion implantation and activation using boron (B) or aluminum (Al) as a p-type impurity and phosphorus (P) or nitrogen (N) as an n-type impurity, so as to obtain the desired breakdown voltage of the SiC-SBD.

[0029] Next, after performing a wet process including hydrofluoric acid or cleaning with a mixture of ammonia and hydrogen peroxide, a mixture of sulfuric acid and hydrogen peroxide, or a mixture of hydrochloric acid and hydrogen peroxide as appropriate, a Schottky electrode layer 9 is formed so as to be in contact with the drift layer 7 (corresponding to step ST02 in FIG. 4).

[0030] In this case, the electrode material can be appropriately selected from titanium (Ti), nickel (Ni), iridium (Ir), platinum (Pt), etc. Then, the excess electrode material formed in the peripheral region is removed by photolithographic patterning and plasma or chemical etching, and heat treatment is performed as necessary to ensure electrical connection between the drift layer 7 and the Schottky electrode layer 9. This results in the cross-sectional structure shown in FIG.

[0031] Next, as shown in FIG. 9, a surface electrode 2 is formed by sputtering, vapor deposition, or the like using aluminum, an aluminum alloy made of aluminum and silicon, or nickel. This is then removed by patterning using photolithography and etching using plasma or a chemical solution. Then, for example, by heating at 150°C or higher and 400°C or lower for 15 minutes or longer, unevenness can be formed on the surface of the surface electrode 2 (corresponding to step ST03 in FIG. 4). The surface electrode 2 is formed on parts of the upper surfaces of the drift layer 6 and the drift layer 7 via a Schottky electrode layer 9, an interlayer insulating film 8, and the like.

[0032] 10, a protective insulating film 4 is then formed. The protective insulating film 4 is preferably made of polyimide or silicone resin, and is formed around the outermost periphery of the front surface of the SiC-SBD by using spin coating, photolithography, etching, or inkjet coating techniques (corresponding to step ST04 in FIG. 4). The protective insulating film 4 covers the portion of the top surface of the drift layer 7 that is not covered by the front electrode 2. The protective insulating film 4 also covers a portion of the top surface of the front electrode 2.

[0033] After the protective insulating film 4 is formed, a surface treatment is performed using a plasma containing oxygen and argon to form multiple vertices on the upper surface of the protective insulating film 4. At this time, if multiple vertices are also formed on the upper surface of the protective insulating film 4 on the outer periphery of the semiconductor device, reliability is further improved.

[0034] As a method for forming multiple vertices on the upper surface (upper end) of the protective insulating film 4, a suitable processing method can be selected as appropriate, such as repeating inkjet coating technology multiple times or subsequently applying a heat treatment at 250°C or higher.

[0035] Next, a heat treatment is performed at a temperature of, for example, 200° C. or higher and 400° C. or lower, more preferably, 250° C. or higher and 380° C. or lower, to form the slope of the protective insulating film 4 into an arc shape as shown in Fig. 13. The heat treatment performed after the formation of the surface electrode 2 can also serve as the heat treatment performed after the formation of the protective insulating film 4.

[0036] 11, in order to reduce loss during current flow, the SiC substrate 5 is thinned (reduced in thickness) from the lower surface side of the SiC substrate 5 by machining using a grinding wheel made of alumina abrasive grains or diamond abrasive grains (corresponding to step ST05 in FIG. 4). Note that the thinning of the SiC substrate 5 can be omitted as needed.

[0037] Thereafter, the back electrode 3 is formed using titanium, a titanium alloy, aluminum, an aluminum alloy made of aluminum and silicon, nickel, or the like (corresponding to step ST06 in FIG. 4). Regarding the back electrode 3, an anti-oxidation film made of gold, platinum, silver, a silver alloy containing palladium, or the like may be formed on the outermost surface of the back electrode 3 to prevent oxidation of the electrode material during soldering.

[0038] Thereafter, the plurality of semiconductor devices formed on the semiconductor wafer are diced into individual pieces using a dicing device, to obtain semiconductor devices such as those shown in FIGS. 1, 2 and 3.

[0039] Then, as illustrated in FIG. 12, the semiconductor device 10 manufactured as described above has its upper and lower surfaces connected to a lead frame 12 using, for example, solder 11 and wire 13, respectively, and is then sealed with molded resin 14 to complete the semiconductor module.

[0040] Fig. 13 is an enlarged view showing the configuration of the vicinity of the surface electrode 2 and the protective insulating film 4 of the semiconductor device 10 in this embodiment. Fig. 14 is a diagram showing the definition of arithmetic mean roughness. As shown in Fig. 14, according to the definition of surface roughness (JIS B 0601:1994, JIS B 0031:1994), the arithmetic mean roughness Ra can be calculated by extracting a reference length from a roughness curve 400 in the direction of its mean line 401, and using the formula in the figure, with the direction of the mean line of this extracted portion as the X-axis and the direction of longitudinal magnification as the Y-axis.

[0041] The inventors performed a 1 mm line scan using an atomic force microscope (AFM) SPM-9600 manufactured by Shimadzu Corporation, obtained the above roughness curve 400, and then calculated the arithmetic mean roughness Ra. Note that the method for calculating the arithmetic mean roughness Ra is not limited to the above, and any other method can be selected, such as a stylus-type step / surface roughness meter or a laser microscope capable of non-contact measurement.

[0042] 13, the arithmetic mean roughness of the upper surface of the protective insulating film 4 is smaller than the arithmetic mean roughness of the interface (i.e., the lower surface of the protective insulating film 4) between the protective insulating film 4 and the surface electrode 2. In FIG. 13, multiple protrusions 2a are formed on the upper surface of the surface electrode 2, which is one of the reasons why the arithmetic mean roughness of the interface between the protective insulating film 4 and the surface electrode 2 is large.

[0043] 13, multiple vertices are formed at the edge of the upper surface of the protective insulating film 4. Specifically, the edge of the upper surface of the protective insulating film 4 is an inclined surface, and the vertex formed at the upper end of the inclined surface has an obtuse angle θ1, and the vertex formed at the lower end of the inclined surface has an obtuse angle θ2.

[0044] Furthermore, the ridge 4a on the side surface of the protective insulating film 4 has a concave shape compared to the straight line drawn from the edge of the upper surface (specifically, the vertex formed at the lower end of the inclined surface) to the edge (vertex) of the lower surface.

[0045] The inventors conducted a power cycle test on the semiconductor module having the structure shown in FIG. 12, in which the semiconductor device was repeatedly switched between a powered state and a powered state.

[0046] The protective insulating film 4 is subjected to stress due to thermal expansion or thermal contraction from the upper surface due to the difference in linear expansion coefficient between it and the mold resin 14, and from the lower surface due to the difference in linear expansion coefficient between it and the surface electrode 2, respectively.

[0047] Fig. 15 is a diagram showing the relationship between the ratio of the arithmetic mean roughness of the upper and lower surfaces of the protective insulating film 4 and the peeling rate of the protective insulating film 4 after 100,000 power cycle tests. In Fig. 15, the vertical axis represents the peeling rate of the protective insulating film 4, and the horizontal axis represents the ratio of the arithmetic mean roughness of the upper and lower surfaces of the protective insulating film 4 (arithmetic mean roughness of the upper surface / arithmetic mean roughness of the lower surface).

[0048] 15, by setting the ratio of the arithmetic mean roughness of the upper and lower surfaces of the protective insulating film 4 (arithmetic mean roughness of the upper surface / arithmetic mean roughness of the lower surface) to 0.9 or less, the adhesive strength between the protective insulating film 4 and the surface electrode 2 can be made sufficient to withstand the stress that the protective insulating film 4 receives from the mold resin 14. As a result, peeling of the protective insulating film 4 can be suppressed.

[0049] When the semiconductor module was opened and analyzed after the above test, it was confirmed that a crack had occurred at the sharpest corner of the protective insulating film 4.

[0050] 16 focuses on the vertex with the smallest angle among the vertices formed at the edge of the top surface of the protective insulating film 4, and shows the relationship between the vertex angle and the crack incidence in the power cycle test described above when the ratio of the arithmetic mean roughness of the top and bottom surfaces of the protective insulating film 4 (arithmetic mean roughness of the top surface / arithmetic mean roughness of the bottom surface) is set to 0.7. In FIG. 16, the vertical axis represents the crack incidence of the protective insulating film 4, and the horizontal axis represents the angle [θ] of the vertex with the smallest angle among the vertices formed at the edge of the top surface of the protective insulating film 4. In FIG. 16, the case where there is one vertex (i.e., only the vertex with the smallest angle) is represented by a hollow circle, the case where there are two vertices is represented by a solid triangle, and the case where there are three vertices is represented by a solid square.

[0051] 16, it can be seen that by making the angle of the vertex formed at the end of the upper surface of the protective insulating film 4 equal to or greater than 90 degrees, it is possible to alleviate the stress from the molding resin 14. It can also be seen that by forming multiple vertices at the end of the upper surface of the protective insulating film 4, it is possible to reduce cracks that occur in the protective insulating film 4.

[0052] Furthermore, the inventors' verification has revealed that, as shown in the example of Figure 13, it is advantageous for suppressing cracks in the protective insulating film 4 when the ridge line 4a on the side of the protective insulating film 4 is recessed (has a concave shape) with respect to a straight line drawn from the vertex of the upper surface of the protective insulating film 4 to the vertex of the lower surface.

[0053] <Second embodiment> A semiconductor device and a method for manufacturing the semiconductor device according to the present embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0054] <Configuration of semiconductor device> 17, 18, and 19 are diagrams schematically showing examples of the configuration of a semiconductor device manufactured by the manufacturing method described in this embodiment. In the example of Fig. 1, a SiC Schottky barrier diode (SBD) is shown.

[0055] Fig. 17 is a plan view of a SiC-SBD. As shown in Fig. 17, a surface electrode 2 is formed in the central current-carrying region, and a protective insulating film 4 is formed around it to ensure insulation from the surroundings. The difference from the case shown in Fig. 1 is that a surface electrode 15 is formed to cover part of the upper surface of the surface electrode 2.

[0056] Fig. 18 is a cross-sectional view corresponding to the A-A' cross section indicated by the dashed line in Fig. 17. In a front-to-back conduction type power semiconductor device, current flows in the Z-axis direction in Fig. 18. In Fig. 18, compared to the configuration shown in Fig. 2, a front surface electrode 15 is formed, which makes it possible to connect wiring to the outside using solder on the top surface side of the power semiconductor device, and also makes it possible to pass a large current.

[0057] 19 is an enlarged view of the area surrounded by the dashed line in FIG. 18. A surface electrode 2 is formed on the upper surface of a semiconductor substrate 1, and a protective insulating film 4 and a surface electrode 15 are further formed on the upper surface of the surface electrode 2. The arithmetic mean roughness of the upper surface of the protective insulating film 4 is smaller than the arithmetic mean roughness of the interface between the protective insulating film 4 and the surface electrode 2. In addition, multiple vertices are provided at the upper end of the protective insulating film 4. In addition, the interface between the surface electrode 2 and the surface electrode 15 is located lower than the interface between the surface electrode 2 and the protective insulating film 4.

[0058] <About the manufacturing method of semiconductor devices> Fig. 20 is a flowchart showing an example of a manufacturing process for a SiC-SBD according to this embodiment. Fig. 5 to Fig. 12 are cross-sectional views showing an example of a manufacturing process for a SiC-SBD according to this embodiment. The manufacturing process for a SiC-SBD will be specifically described below with reference to Fig. 5 to Fig. 12.

[0059] Steps ST01 to ST06 in FIG. 20 are the same as steps ST01 to ST06 in FIG. 4, and therefore the description thereof will be omitted.

[0060] FIG. 21 is a cross-sectional view showing an example of the structure of a semiconductor device in which steps up to step ST06 in FIG. 20 have been completed.

[0061] Next, electrodes are formed on the surface of the semiconductor device by plating (steps ST07 and ST08 in FIG. 20). Even if plating is performed on the Al or Al alloy electrodes on the wafer after commonly known degreasing and pickling, strong organic residues and oxide films are formed on the surface of the Al or Al alloy (hereinafter, Al or Al alloy will also be referred to as Al alloy) on the wafer, preventing metal diffusion between the Al alloy and the plating metal, and making it impossible to form a plating layer with strong adhesion.

[0062] Therefore, in this process, the plating process for the Al alloy electrode on the wafer is carried out in the following order: plasma cleaning, degreasing, pickling, zincate treatment, and plating. Note that sufficient water rinsing time must be ensured between each process to prevent the processing solution or residue from the previous process from being carried over to the next process.

[0063] An outline of the plating pre-treatment and plating treatment will be described below with reference to Fig. 22. Fig. 22 is a flow chart showing an example of the plating pre-treatment and plating treatment.

[0064] First, a surface activation treatment is performed as a pre-plating treatment, for example, using plasma (corresponding to step ST11 in FIG. 22). Here, plasma cleaning is a treatment that uses plasma to clean the surface of the Al alloy electrode by using plasma to oxidatively decompose or drive out organic residues that are baked onto the Al alloy electrode and cannot be removed by general pre-plating treatments.

[0065] Next, degreasing and acid cleaning are performed as pre-plating treatments (corresponding to steps ST12 and ST13 in FIG. 22). The degreasing is performed to remove any slight organic contamination or oxide film remaining on the Al alloy surface. The acid cleaning is performed to neutralize the Al alloy surface and further etch the Al alloy surface to roughen it, increasing the reactivity of the treatment solution in the subsequent process and improving the adhesion of the plating.

[0066] Next, zincate treatment is performed as a pre-plating treatment (corresponding to step ST14 in FIG. 22). After that, plating is performed to form a plating film with strong adhesiveness. Specifically, electroless Ni plating is performed, followed by electroless Au plating (corresponding to steps ST15 and ST16 in FIG. 22).

[0067] Here, we will explain zincate treatment. Zincate treatment is a process that forms a zinc (Zn) film on the surface of an Al alloy while removing the Al oxide film. Specifically, when an Al alloy is immersed in an aqueous solution in which Zn is dissolved as ions, the Al dissolves as ions because Zn has a more noble standard oxidation-reduction potential than Al. The electrons generated during this process are then accepted by the Zn ions on the surface of the Al alloy, forming a Zn film on the surface of the Al. The Al oxide film is also removed during this process.

[0068] 23 and 24 are flow charts showing modified examples of the zincate treatment.

[0069] 23, first, a surface activation treatment such as plasma cleaning is performed (corresponding to step ST21 in FIG. 23), followed by a degreasing treatment and acid cleaning (corresponding to steps ST22 and ST23 in FIG. 23).

[0070] Next, a first zincate treatment is performed (corresponding to step ST24 in FIG. 23), and after zincate removal (corresponding to step ST25 in FIG. 23), a second zincate treatment is performed again (corresponding to step ST26 in FIG. 23).

[0071] Thereafter, a plating process is performed to form a plated film with strong adhesion. Specifically, electroless Ni plating is performed, followed by electroless Au plating (corresponding to steps ST27 and ST28 in FIG. 23).

[0072] 24, first, a surface activation treatment such as plasma cleaning is performed (corresponding to step ST31 in FIG. 24), followed by a degreasing treatment and acid cleaning (corresponding to steps ST32 and ST33 in FIG. 24).

[0073] Next, a first zincate treatment is performed (corresponding to step ST34 in FIG. 24). Then, after zincate stripping (corresponding to step ST35 in FIG. 24), a second zincate treatment is performed again (corresponding to step ST36 in FIG. 24). Furthermore, after zincate stripping (corresponding to step ST37 in FIG. 24), a third zincate treatment is performed again (corresponding to step ST38 in FIG. 24).

[0074] Thereafter, a plating process is performed to form a plated film with strong adhesiveness. Specifically, electroless Ni plating is performed, followed by electroless Au plating (corresponding to steps ST39 and ST40 in FIG. 24).

[0075] 23 and 24, when zincate treatment and zincate stripping are repeated, an Al alloy coated with Zn is immersed in concentrated nitric acid, whereby the Zn dissolves and a thin, uniform Al oxide film is formed on the Al surface. Then, the Al alloy is immersed again in a Zn treatment solution, whereby the Al alloy surface is coated with Zn and the Al oxide film is removed.

[0076] By this operation, the oxide layer on the surface of the aluminum alloy becomes thinner and smoother. The more times the above operation is performed, the more uniform the aluminum surface becomes and the better the plating film becomes. However, considering productivity, it is preferable to perform the zincate treatment twice as shown in Figure 23 or three times as shown in Figure 24.

[0077] In this way, by performing the zincate treatment and zincate peeling up to three times, it is possible to form an interface between the front surface electrode 2 and the front surface electrode 15 so that the interface is located lower than the interface between the front surface electrode 2 and the protective insulating film 4. When forming such an interface located lower, the surface activation treatment (corresponding to step ST11) shown in FIG.

[0078] 25, 26, 27, and 28 are diagrams showing examples of the structure of a semiconductor device manufactured by the above-described flow. Fig. 27 is an enlarged view of the area surrounded by the dashed line in Fig. 26. In Fig. 27, the interface between the protective insulating film 4 and the surface electrode 2 is taken as the reference plane, and the distance to the interface between the surface electrode 15 and the surface electrode 2, which is located below the reference plane, is defined as d.

[0079] The inventors then conducted an assembly test of a semiconductor module in which the upper and lower surfaces of the semiconductor device 10 were each joined to a lead frame 12 via solder 11, and further sealed with molding resin 14, as shown in the example of Figure 28.

[0080] In the above assembly test, as an accelerated test, the soldering process was repeated three times to create a situation in which more stress was applied to the protective insulating film 4 from the surface electrode 2, the surface electrode 15, the solder 11, or the lead frame 12.

[0081] 29 is a diagram showing the relationship between the difference between the interface between the surface electrode 2 and the surface electrode 15 and the interface between the surface electrode 2 and the protective insulating film 4, and the defect rate after an assembly test. In FIG. 29, the vertical axis represents the defect rate of the semiconductor module after the assembly test, and the horizontal axis represents the difference [nm] between the interface between the surface electrode 2 and the surface electrode 15 and the interface between the surface electrode 2 and the protective insulating film 4. In FIG. 29, the negative values ​​on the horizontal axis indicate that the interface between the surface electrode 2 and the surface electrode 15 protrudes relative to the interface between the surface electrode 2 and the protective insulating film 4.

[0082] According to FIG. 29, by making the difference between the interface between the surface electrode 2 and the surface electrode 15 and the interface between the surface electrode 2 and the protective insulating film 4 10 nm or more, the defect rate of the semiconductor module after assembly testing can be reduced.

[0083] Furthermore, when the semiconductor modules that were found to be defective after the above assembly test were analyzed, it was found that insulation defects had occurred due to peeling of the protective insulating film 4. Therefore, it can be said that by positioning the interface between the surface electrode 2 and the surface electrode 15 below the interface between the surface electrode 2 and the protective insulating film 4, stress on the protective insulating film 4 is alleviated, thereby suppressing the rate of defects in the semiconductor modules after the assembly test.

[0084] <Third embodiment> A power conversion device and a method for manufacturing the power conversion device according to this embodiment will be described. In the following description, components similar to those described in the above embodiment will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0085] <Configuration of power conversion device> In this embodiment, the semiconductor devices according to the first and second embodiments are applied to a power conversion device. The power conversion device according to this embodiment is not limited to a specific power conversion device, but the following describes a case where the power conversion device according to this embodiment is applied to a three-phase inverter.

[0086] 30 is a diagram schematically illustrating the configuration of a power conversion system to which a power conversion device 200 according to this embodiment is applied. The power conversion system illustrated in FIG. 30 includes a power supply 100, a power conversion device 200, and a load 300.

[0087] Power supply 100 is a DC power supply and supplies DC power to power conversion device 200. Power supply 100 can be configured with various power sources, for example, it may be configured with a DC system, a solar cell, a storage battery, or it may be configured with a rectifier circuit or an AC / DC converter connected to an AC system. Power supply 100 may also be configured with a DC / DC converter that converts DC power output from a DC system into a predetermined power.

[0088] The power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300. The power conversion device 200 converts DC power supplied from the power source 100 into AC power and supplies it to the load 300. The power conversion device 200 includes a main conversion circuit 201 and a control circuit 203. The main conversion circuit 201 converts input DC power into AC power and outputs the AC power. The control circuit 203 outputs a control signal to the main conversion circuit 201 to control the main conversion circuit 201.

[0089] The load 300 is a three-phase electric motor driven by AC power supplied from the power conversion device 200. The load 300 is not limited to a specific application, but is an electric motor mounted on various electric devices, and is used as an electric motor for, for example, a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioning device.

[0090] The power conversion device 200 will be described in detail below. The main conversion circuit 201 includes switching elements and freewheel diodes (not shown). By switching the switching elements, the main conversion circuit 201 converts DC power supplied from the power source 100 into AC power and supplies it to the load 300. There are various specific circuit configurations for the main conversion circuit 201, but the main conversion circuit 201 according to this embodiment is a two-level, three-phase full-bridge circuit that can be configured with six switching elements and six freewheel diodes connected in anti-parallel to each switching element. At least one of the switching elements and freewheel diodes of the main conversion circuit 201 is implemented using the semiconductor device 202 according to any of the first embodiment, second embodiment, and their modifications. Two of the six switching elements are connected in series to form upper and lower arms, and each upper and lower arm constitutes a respective phase (U phase, V phase, and W phase) of the full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0091] The main conversion circuit 201 includes a drive circuit (not shown) that drives each switching element. The drive circuit generates drive signals that drive the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, the drive circuit outputs, to the control electrodes of each switching element, a drive signal that turns the switching element on and a drive signal that turns the switching element off, in accordance with a control signal from a control circuit 203 (described later). When maintaining a switching element in the on state, the drive signal is a voltage signal (on signal) that is equal to or higher than the threshold voltage of the switching element, and when maintaining a switching element in the off state, the drive signal is a voltage signal (off signal) that is equal to or lower than the threshold voltage of the switching element.

[0092] The control circuit 203 controls the switching elements of the main conversion circuit 201 so that a desired power is supplied to the load 300. Specifically, the control circuit 203 calculates the time (on time) that each switching element of the main conversion circuit 201 should be in the on state, based on the power to be supplied to the load 300. For example, the control circuit 203 can control the main conversion circuit 201 by pulse width modulation (PWM) control, which modulates the on time of the switching elements according to the voltage to be output. The control circuit 203 then outputs a control command (control signal) to a drive circuit included in the main conversion circuit 201 so that, at each point in time, an on signal is output to a switching element that should be in the on state, and an off signal is output to a switching element that should be in the off state. In accordance with this control signal, the drive circuit outputs an on signal or an off signal as a drive signal to the control electrode of each switching element.

[0093] <About the manufacturing method of the power conversion device> The manufacturing method of the power conversion device 200 includes the following steps. A semiconductor device 202 is manufactured by the manufacturing method described in the first embodiment, the second embodiment, or their modifications. A main conversion circuit 201 having this semiconductor device 202 is formed. A control circuit 203 is also formed. This completes the power conversion device 200. When the main conversion circuit 201 is formed, for example, as shown in FIG. 12 , the back electrode 3 of the semiconductor device 10 is joined to a lead frame 12 via solder 11, and the front electrode 2 is joined to the lead frame 12 via a wire 13.

[0094] According to this embodiment, the semiconductor device 202 according to the first or second embodiment is used as at least one of the semiconductor devices 202 constituting the main conversion circuit 201. This makes it possible to suppress malfunctions caused by stress from peripheral components when the semiconductor device 202 is in operation and when it is not in operation. This improves the reliability of the main conversion circuit 201. This in turn improves the reliability of the power conversion device 200.

[0095] In the present embodiment, an example in which the semiconductor device 202 is applied to a two-level three-phase inverter has been described, but the present embodiment is not limited to this and can be applied to various power conversion devices. In the present embodiment, the power conversion device is described as a two-level power conversion device, but it may be a multi-level power conversion device such as a three-level power conversion device. Furthermore, when supplying power to a single-phase load, the above-mentioned power conversion device may be applied to a single-phase inverter. Furthermore, when supplying power to a DC load or the like, the above-mentioned power conversion device may be applied to a DC / DC converter or an AC / DC converter.

[0096] Furthermore, the power conversion device according to this embodiment is not limited to the case where the load is an electric motor, but can also be used as a power supply device for, for example, an electric discharge machine, a laser processing machine, an induction heating cooker, or a non-contact power supply system, and can also be used as a power conditioner for a solar power generation system or a power storage system.

[0097] <Fourth embodiment> A semiconductor device and a method for manufacturing the semiconductor device according to this embodiment will be described below.

[0098] <Configuration of semiconductor device> 1, 2, and 31 are diagrams schematically illustrating examples of the configuration of a semiconductor device manufactured by the manufacturing method described in this embodiment. In the example of Fig. 1, a SiC Schottky barrier diode (SBD) is shown.

[0099] Fig. 31 is a cross-sectional view corresponding to the region surrounded by the dashed line in Fig. 2. The difference from the case shown in Fig. 3 is that a recess 40a is provided in the side portion of the protective insulating film 40.

[0100] A surface electrode 2 is formed on the upper surface of the semiconductor substrate 1, and a protective insulating film 40 is further formed on the upper surface of the surface electrode 2. The arithmetic mean roughness of the upper surface of the protective insulating film 40 is smaller than that of the side surface of the protective insulating film 40. The arithmetic mean roughness of the side surface of the protective insulating film 40 is smaller than that of the interface between the protective insulating film 40 and the surface electrode 2 (i.e., the lower surface of the protective insulating film 40). In addition, the upper end of the protective insulating film 40 has multiple vertices.

[0101] <About the manufacturing method of semiconductor devices> Fig. 4 is a flowchart showing an example of a manufacturing process for a SiC-SBD according to this embodiment. In the flowchart shown in Fig. 4, the steps up to the formation of the surface electrode (step ST03) and the corresponding cross-sectional views in Fig. 5 to Fig. 9 are common to the first embodiment, and therefore description thereof will be omitted.

[0102] Thereafter, as shown in FIG. 10, a protective insulating film 4 (protective insulating film 40 in this embodiment) is formed. The protective insulating film is preferably made of polyimide or silicone resin, and the protective insulating film is formed on the outermost periphery of the front surface side of the SiC-SBD by using spin coating, photolithography and etching techniques, or inkjet coating techniques (corresponding to step ST04 in FIG. 4). The protective insulating film 4 (protective insulating film 40 in this embodiment) covers the portion of the top surface of the drift layer 7 that is not covered by the front electrode 2. The protective insulating film also covers a portion of the top surface of the front electrode 2.

[0103] After the protective insulating film 40 is formed, for example, a batch-type plasma processing apparatus is used to perform surface treatment with plasma containing oxygen and argon, thereby forming multiple vertices on the upper surface of the protective insulating film 40 and forming recesses 40a on the side surface of the protective insulating film 40. In this embodiment as well, reliability can be further improved by forming multiple vertices on the upper surface of the protective insulating film 40 on the outer periphery of the semiconductor device and forming unevenness (recesses 40a) on the side surface of the protective insulating film 40.

[0104] Thereafter, similarly to the first embodiment, the process of thinning the SiC substrate 5 (corresponding to step ST05 in FIG. 4) and subsequent steps are carried out to obtain a semiconductor device such as the example shown in FIG. 1, FIG. 2, and FIG. 31.

[0105] When the semiconductor device thus fabricated is assembled into a semiconductor module having the structure shown in FIG. 12 and a power cycle test is performed in which the semiconductor device is repeatedly switched between a powered state and a powered state, the protective insulating film 40 is subjected to stress due to thermal expansion or thermal contraction from the upper surface side due to the difference in the linear expansion coefficient between it and the mold resin 14, and from the lower surface side due to the difference in the linear expansion coefficient between it and the surface electrode 2.

[0106] In such a case, in the present embodiment, the arithmetic mean roughness of the upper surface of the protective insulating film 40 is smaller than that of the side surfaces of the protective insulating film 40, which in turn is smaller than that of the interface (i.e., the lower surface of the protective insulating film 40) between the protective insulating film 40 and the surface electrode 2. Therefore, the external force acting between the protective insulating film 40 and the surface electrode 2 in response to the stress that the protective insulating film 40 receives from the mold resin 14 can be alleviated compared to the first embodiment, and peeling of the protective insulating film 40 can be suppressed.

[0107] <Fifth embodiment> A semiconductor device and a method for manufacturing the semiconductor device according to this embodiment will be described below.

[0108] <Configuration of semiconductor device> 1, 32, and 33 are diagrams schematically illustrating examples of the configuration of a semiconductor device manufactured by the manufacturing method described in this embodiment. In the example of Fig. 1, a SiC Schottky barrier diode (SBD) is shown.

[0109] Fig. 32 is a cross-sectional view corresponding to the region surrounded by the dashed line in Fig. 33. The difference from the case shown in Fig. 3 is that an inclined portion 41b is provided on the upper surface of the protective insulating film 41.

[0110] <About the manufacturing method of semiconductor devices> Fig. 4 is a flowchart showing an example of a manufacturing process for a SiC-SBD according to this embodiment. In the flowchart shown in Fig. 4, the steps up to the formation of the surface electrode (step ST03) and the corresponding cross-sectional views in Fig. 5 to Fig. 9 are common to the first embodiment, and therefore description thereof will be omitted.

[0111] Thereafter, as shown in FIG. 10, a protective insulating film 4 (protective insulating film 41 in this embodiment) is formed. The protective insulating film is preferably made of polyimide or silicone resin, and the protective insulating film is formed on the outermost periphery of the front surface side of the SiC-SBD by using spin coating, photolithography and etching techniques, or inkjet coating techniques (corresponding to step ST04 in FIG. 4). The protective insulating film 4 (protective insulating film 41 in this embodiment) covers the portion of the top surface of the drift layer 7 that is not covered by the front electrode 2. The protective insulating film also covers a portion of the top surface of the front electrode 2.

[0112] After the protective insulating film 41 is formed, for example, a batch-type plasma processing apparatus is used to perform surface treatment with plasma containing oxygen and argon, thereby forming multiple vertices on the upper surface of the protective insulating film 41. At this time, if multiple vertices are also formed on the upper surface of the protective insulating film 41 on the outer periphery of the semiconductor device, reliability can be further improved.

[0113] Thereafter, by performing a heat treatment at a temperature of 250°C or higher and 350°C or lower, an inclined portion 41b having an angle of θ3 (i.e., inclined) with respect to a plane parallel to the semiconductor substrate (i.e., the upper surface of the protective insulating film 41) can be formed on the upper surface of the protective insulating film 41, as shown in Figures 32 and 33.

[0114] Next, similarly to the first embodiment, the process of thinning the SiC substrate 5 (corresponding to step ST05 in FIG. 4) and subsequent steps are carried out to obtain a semiconductor device such as the examples shown in FIGS. 1, 32, and 33.

[0115] 12, when a power cycle test is performed in which the semiconductor device is repeatedly switched between a powered state and a powered state, the edges of protective insulating film 41 are thicker than the center of protective insulating film 41, and therefore the edges of protective insulating film 41 can deform to absorb the stress that the semiconductor device receives from mold resin 14. This makes it possible to suppress cracks from occurring in protective insulating film 41.

[0116] <Effects Produced by the Multiple Embodiments Described Above> Next, examples of effects obtained by the above-described embodiments will be described. Note that in the following description, the effects will be described based on the specific configurations exemplified in the above-described embodiments, but these may be replaced with other specific configurations exemplified in the present specification as long as the same effects are obtained. In other words, for convenience, only one of the associated specific configurations may be described as a representative below, but the representatively described specific configuration may be replaced with another associated specific configuration.

[0117] Furthermore, the replacement may be made across multiple embodiments, i.e., configurations illustrated in different embodiments may be combined to produce the same effect.

[0118] According to the above-described embodiment, the semiconductor device includes a semiconductor layer, a first electrode layer, and an insulating film. Here, the semiconductor layer corresponds to, for example, the drift layer 6 or the drift layer 7. The first electrode layer corresponds to, for example, the surface electrode 2. The insulating film corresponds to, for example, the protective insulating film 4. The surface electrode 2 covers a part of the upper surface of the drift layer 7 via the drift layer 6, the Schottky electrode layer 9, etc. The protective insulating film 4 covers another part of the upper surface of the drift layer 7 via the drift layer 6, the Schottky electrode layer 9, etc. The protective insulating film 4 covers a part of the upper surface of the surface electrode 2. Here, the arithmetic mean roughness of the upper surface of the protective insulating film 4 is smaller than the arithmetic mean roughness of the interface between the protective insulating film 4 and the surface electrode 2.

[0119] With this configuration, the contact area between the protective insulating film 4 and the components above it is smaller than the contact area between the protective insulating film 4 and the components below it. Therefore, the connection between the protective insulating film 4 and the components below it can be made stronger than the connection between the protective insulating film 4 and the components above it, which makes it possible to suppress peeling of the protective insulating film 4 during operation, etc. With this configuration, the reliability of the semiconductor device can be improved.

[0120] Furthermore, even if other configurations shown as examples in this specification are appropriately added to the above configuration, that is, even if other configurations in this specification that were not mentioned as the above configuration are appropriately added, the same effect can be achieved.

[0121] Furthermore, according to the embodiment described above, the edge of the upper surface of the protective insulating film 4 is an inclined surface. The vertex formed at the upper end of the inclined surface and the vertex formed at the lower end of the inclined surface both have obtuse angles. With this configuration, by having multiple vertices at the upper and lower ends of the inclined surface, it is possible to distribute stress applied to the protective insulating film 4 from the surroundings. Furthermore, by making the angle of each vertex 90 degrees or more, it is possible to reduce the force applied to the vertices, thereby suppressing the occurrence of cracks in the protective insulating film 4.

[0122] Furthermore, according to the embodiment described above, the semiconductor device includes a second electrode layer that covers a portion of the surface electrode 2. Here, the second electrode layer corresponds to, for example, the surface electrode 15. The protective insulating film 4 covers a portion of the surface electrode 2. Furthermore, the interface between the surface electrode 15 and the surface electrode 2 is located lower than the interface between the protective insulating film 4 and the surface electrode 2. With this configuration, the force that the protective insulating film 4 receives from the surface electrode 15 can be reduced. As a result, peeling of the protective insulating film 4 can be suppressed.

[0123] Furthermore, according to the embodiment described above, the ridge 4a on the side surface of the protective insulating film 4 is concave. With this configuration, the occurrence of cracks in the protective insulating film 4 can be suppressed.

[0124] Furthermore, according to the embodiment described above, a power converter includes a main conversion circuit 201 that includes the semiconductor device and converts and outputs input power, and a control circuit 203 that outputs a control signal to the main conversion circuit 201 for controlling the main conversion circuit 201. With this configuration, the contact area between the protective insulating film 4 and the components above it is smaller than the contact area between the protective insulating film 4 and the components below it. This makes it possible to make the connection between the protective insulating film 4 and the components below it stronger than the connection between the protective insulating film 4 and the components above it, thereby preventing peeling of the protective insulating film 4 during operation, etc. With this configuration, the reliability of a power converter including a semiconductor device can be improved.

[0125] According to the embodiment described above, in the method for manufacturing a semiconductor device, the front surface electrode 2 is formed to cover part of the top surface of the drift layer 6. Then, the protective insulating film 4 is formed to cover another part of the top surface of the drift layer 6 and at least part of the top surface of the front electrode 2. Here, the arithmetic mean roughness of the top surface of the protective insulating film 4 is smaller than the arithmetic mean roughness of the interface between the protective insulating film 4 and the front surface electrode 2.

[0126] With this configuration, the contact area between the protective insulating film 4 and the components above it is smaller than the contact area between the protective insulating film 4 and the components below it. Therefore, the connection between the protective insulating film 4 and the components below it can be made stronger than the connection between the protective insulating film 4 and the components above it, which makes it possible to suppress peeling of the protective insulating film 4 during operation, etc. With this configuration, the reliability of the semiconductor device can be improved.

[0127] Furthermore, according to the above-described embodiment, a method for manufacturing a power converter includes providing a main conversion circuit 201 that includes a semiconductor device manufactured by the above-described manufacturing method and converts and outputs input power. A control circuit 203 is also provided that outputs a control signal to the main conversion circuit 201 for controlling the main conversion circuit 201. With this configuration, the contact area between the protective insulating film 4 and the components above it is smaller than the contact area between the protective insulating film 4 and the components below it. This allows for stronger connections between the components below the protective insulating film 4 than between the components above it, thereby preventing peeling of the protective insulating film 4 during operation. This configuration prevents defects caused by stress from peripheral components during operation and non-operation of the semiconductor device. This improves the reliability of the main conversion circuit and the power converter.

[0128] <Modifications of the above-described embodiments> In the multiple embodiments described above, the material, composition, dimensions, shape, relative positional relationship, or implementation conditions of each component may also be described, but these are merely examples in all aspects and are not limiting.

[0129] Therefore, countless modifications and equivalents not shown as examples are contemplated within the scope of the technology disclosed in the present specification, including, for example, modifying, adding, or omitting at least one component, and further, extracting at least one component in at least one embodiment and combining it with a component in another embodiment.

[0130] Furthermore, in at least one of the embodiments described above, when a material name or the like is stated without being specifically specified, unless a contradiction arises, it is assumed that the material in question includes other additives, such as alloys.

[0131] Furthermore, unless a contradiction arises, when it is stated in the above-described embodiments that "one" component is provided, it is also understood that "one or more" of that component may be provided.

[0132] Furthermore, each component in the embodiments described above is a conceptual unit, and the scope of the technology disclosed in this specification includes cases where one component is made up of multiple structures, cases where one component corresponds to part of a structure, and even cases where multiple components are provided in one structure.

[0133] Furthermore, each of the components in the embodiments described above includes structures having other structures or shapes as long as they perform the same function.

[0134] Furthermore, the descriptions in this specification are incorporated by reference for all purposes related to the present technology, and none of them are admitted to be prior art.

[0135] Various aspects of the present disclosure are summarized below as appendices.

[0136] (Appendix 1) a semiconductor layer; a first electrode layer covering a portion of an upper surface of the semiconductor layer; an insulating film covering another part of the upper surface of the semiconductor layer and a part of the upper surface of the first electrode layer; the arithmetic mean roughness of the upper surface of the insulating film is smaller than the arithmetic mean roughness of the interface between the insulating film and the first electrode layer; Semiconductor device.

[0137] (Appendix 2) 10. The semiconductor device according to claim 1, an end portion of the upper surface of the insulating film is an inclined surface, a vertex formed at the upper end of the inclined surface and a vertex formed at the lower end of the inclined surface both having an obtuse angle; Semiconductor device.

[0138] (Appendix 3) 3. The semiconductor device according to claim 1, the insulating film covers a portion of the first electrode layer; further comprising a second electrode layer covering a portion of the first electrode layer; an interface between the second electrode layer and the first electrode layer is located below an interface between the insulating film and the first electrode layer; Semiconductor device.

[0139] (Appendix 4) The semiconductor device according to any one of Supplementary Notes 1 to 3, a ridge line of a side surface of the insulating film is concave; Semiconductor device.

[0140] (Appendix 5) a main conversion circuit including the semiconductor device according to any one of Supplementary Notes 1 to 4, which converts input power and outputs the converted power; a control circuit that outputs a control signal to the main conversion circuit for controlling the main conversion circuit, Power conversion device.

[0141] (Appendix 6) forming a first electrode layer covering a portion of an upper surface of the semiconductor layer; forming an insulating film covering another part of the upper surface of the semiconductor layer and at least a part of the upper surface of the first electrode layer; the arithmetic mean roughness of the upper surface of the insulating film is smaller than the arithmetic mean roughness of the interface between the insulating film and the first electrode layer; A method for manufacturing a semiconductor device.

[0142] (Appendix 7) a semiconductor layer; a first electrode layer covering a portion of an upper surface of the semiconductor layer; an insulating film covering another part of the upper surface of the semiconductor layer and a part of the upper surface of the first electrode layer; the arithmetic mean roughness of the top surface of the insulating film is smaller than the arithmetic mean roughness of the side surface of the insulating film; the arithmetic mean roughness of the side surface of the insulating film is smaller than the arithmetic mean roughness of the interface between the insulating film and the first electrode layer; Semiconductor device.

[0143] (Appendix 8) a semiconductor layer; a first electrode layer covering a portion of an upper surface of the semiconductor layer; an insulating film covering another part of the upper surface of the semiconductor layer and a part of the upper surface of the first electrode layer; the arithmetic mean roughness of the top surface of the insulating film is smaller than the arithmetic mean roughness of the side surface of the insulating film; the arithmetic mean roughness of the side surface of the insulating film is smaller than the arithmetic mean roughness of the interface between the insulating film and the first electrode layer; A method for manufacturing a semiconductor device.

[0144] (Appendix 9) A semiconductor device according to any one of Supplementary Notes 1 to 4 and 7, an inclined portion inclined with respect to the upper surface of the insulating film is provided on the upper surface of the insulating film; Semiconductor device. [Explanation of symbols]

[0145] 1 semiconductor substrate, 2 surface electrode, 2a convex portion, 3 back electrode, 4 protective insulating film, 4a ridge line, 5 substrate, 6 drift layer, 7 drift layer, 8 interlayer insulating film, 9 Schottky electrode layer, 10 semiconductor device, 11 solder, 12 lead frame, 13 wire, 14 molding resin, 15 surface electrode, 40 protective insulating film, 40a concave portion, 41 protective insulating film, 41b inclined portion, 100 power supply, 200 power conversion device, 201 main conversion circuit, 202 semiconductor device, 203 control circuit, 300 load, 401 average line.

Claims

1. a semiconductor layer; a first electrode layer covering a portion of an upper surface of the semiconductor layer; an insulating film covering another part of the upper surface of the semiconductor layer and a part of the upper surface of the first electrode layer; an arithmetic mean roughness of the upper surface of the insulating film is smaller than an arithmetic mean roughness of the interface between the insulating film and the first electrode layer; Semiconductor device.

2. a semiconductor layer; a first electrode layer covering a portion of an upper surface of the semiconductor layer; an insulating film covering another part of the upper surface of the semiconductor layer and a part of the upper surface of the first electrode layer; the arithmetic mean roughness of the top surface of the insulating film is smaller than the arithmetic mean roughness of the side surface of the insulating film; an arithmetic mean roughness of a side surface of the insulating film is smaller than an arithmetic mean roughness of an interface between the insulating film and the first electrode layer; Semiconductor device.

3. 2. The semiconductor device according to claim 1, an end portion of the upper surface of the insulating film is an inclined surface, a vertex formed at the upper end of the inclined surface and a vertex formed at the lower end of the inclined surface both having an obtuse angle; Semiconductor device.

4. 3. The semiconductor device according to claim 1, the insulating film covers a portion of the first electrode layer; a second electrode layer covering a portion of the first electrode layer; an interface between the second electrode layer and the first electrode layer is located below an interface between the insulating film and the first electrode layer; Semiconductor device.

5. 3. The semiconductor device according to claim 1, a ridge line of a side surface of the insulating film is concave; Semiconductor device.

6. 3. The semiconductor device according to claim 1, an inclined portion inclined with respect to the upper surface of the insulating film is provided on the upper surface of the insulating film; Semiconductor device.

7. a main conversion circuit including the semiconductor device according to claim 1 or 2, which converts input power and outputs the converted power; a control circuit that outputs a control signal to the main conversion circuit for controlling the main conversion circuit, Power conversion device.

8. forming a first electrode layer covering a portion of an upper surface of the semiconductor layer; forming an insulating film covering another part of the upper surface of the semiconductor layer and at least a part of the upper surface of the first electrode layer; an arithmetic mean roughness of the upper surface of the insulating film is smaller than an arithmetic mean roughness of the interface between the insulating film and the first electrode layer; A method for manufacturing a semiconductor device.

9. 9. The method for manufacturing a semiconductor device according to claim 8, the arithmetic mean roughness of the top surface of the insulating film is smaller than the arithmetic mean roughness of the side surface of the insulating film; an arithmetic mean roughness of a side surface of the insulating film is smaller than an arithmetic mean roughness of an interface between the insulating film and the first electrode layer; A method for manufacturing a semiconductor device.

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