Control circuit, semiconductor memory device, and method for controlling semiconductor memory device

Abstract

Provided are a control circuit, a semiconductor memory device, and a control method thereof that are capable of efficiently estimating the amount of delay between a first signal and a second signal and generating an output signal according to the amount of delay. [Solution] The control circuit 30 comprises a delay line section 31 to which a start signal start_tdc is input, the delay line section including a plurality of delay units U1 to U8 connected in series; a detection section 32 to which an end signal end_tdc is input, the detection section detecting, when an end signal is input after the start signal is input to the delay line section, the number of delay units among the plurality of delay units through which the start signal has passed before the end signal is input; and a control section 33 that controls the transmission path of the start signal in the delay line section so that the number of delay units through which the start signal has passed before the start signal is output from the delay line section is equal to the number of delay units detected by the detection section.

Description

[Technical Field]

[0001] The present invention relates to a control circuit, a semiconductor memory device, and a method for controlling a semiconductor memory device. [Background technology]

[0002] A TDC (Time to Digital Converter) circuit is known that is configured to detect a delay amount (phase difference) between a first signal and a second signal and generate a digital value corresponding to this delay amount (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-87797 Summary of the Invention [Problem to be solved by the invention]

[0004] Such a circuit has a plurality of delay units, and can generate a digital value corresponding to a predetermined delay amount using some of the delay units. Here, it is desirable to efficiently estimate the delay amount between a first signal and a second signal (i.e., to estimate the number of delay units corresponding to the predetermined delay amount) and generate an output signal corresponding to the delay amount.

[0005] The present invention has been made in consideration of the above-mentioned problems, and aims to provide a control circuit, a semiconductor memory device, and a control method thereof that are capable of efficiently estimating the amount of delay between a first signal and a second signal and generating an output signal according to the amount of delay. [Means for solving the problem]

[0006] In order to solve the above problem, the present invention provides a control circuit comprising: a delay line section to which a first signal is input, the delay line section including a plurality of delay units connected in series, each of which delays the input first signal; a detection section to which a second signal, which is a delayed version of the first signal, is input, the detection section detecting, when the second signal is input after the first signal is input to the delay line section, the number of delay units among the plurality of delay units through which the first signal has passed before the second signal is input; and a control section controlling the transmission path of the first signal in the delay line section so that the number of delay units through which the first signal has passed before the first signal is output from the delay line section is equal to the number of delay units detected by the detection section.

[0007] According to this invention, the number of delay units through which the first signal has passed before the second signal is input is detected as the delay amount between the first signal and the second signal, so that the delay amount can be easily detected by inputting each of the first and second signals. Furthermore, according to this invention, the transmission path of the first signal in the delay line section is controlled so that the number of delay units through which the first signal has passed is equal to the number of delay units detected by the detection section (i.e., the delay amount between the first signal and the second signal). Therefore, it is possible to easily generate an output signal delayed by the delay amount from the input signal using this delay line section. This makes it possible to efficiently estimate the delay amount between the first signal and the second signal and generate an output signal according to the delay amount.

[0008] The present invention also provides a semiconductor memory device including the above control circuit.

[0009] Furthermore, the present invention provides a control method executed by a control circuit provided in a semiconductor memory device, the control method including: a delay line section to which a first signal is input, the delay line section including a plurality of delay units connected in series, each of the plurality of delay units delaying the input first signal; when a second signal, which is a delayed version of the first signal, is input to the control circuit after the first signal is input to the delay line section, detecting the number of delay units among the plurality of delay units through which the first signal has passed before the second signal is input; and controlling a transmission path of the first signal in the delay line section so that the number of delay units through which the first signal has passed before the first signal is output from the delay line section is equal to the detected number of delay units. [Effects of the Invention]

[0010] According to the control circuit, semiconductor memory device, and control method thereof of the present invention, it is possible to efficiently estimate the amount of delay between a first signal and a second signal and generate an output signal according to the amount of delay. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a diagram showing an example of the configuration of a semiconductor memory device according to an embodiment of the present invention; [Figure 2] FIG. 2 is a diagram illustrating an example of the configuration of a control circuit according to an embodiment of the present invention. [Figure 3] 4 is a time chart showing an example of transition of a voltage of a signal in a control circuit. [Figure 4] 10A and 10B are diagrams illustrating an example of a state of a signal in a control circuit during a delay amount estimation process. [Figure 5] 10A and 10B are diagrams illustrating an example of a state of a signal in a control circuit during a delay amount estimation process. [Figure 6] 10A and 10B are diagrams illustrating an example of the state of signals in a control circuit during output signal generation processing. [Figure 7] FIG. 10 is a diagram illustrating an example of the configuration of a part of a control circuit according to a modified example. [Figure 8] FIG. 10 is a diagram illustrating an example of the configuration of a part of a control circuit according to a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0012] 1 is a diagram showing an example of the configuration of a semiconductor memory device according to one embodiment of the present invention. As shown in FIG. 1, the semiconductor memory device includes an input buffer 10, a delay circuit 20, a control circuit 30, a replica unit 40, and an output buffer 50. In this embodiment, the semiconductor memory device is a DRAM (Dynamic Random Access Memory) as an example. In addition, in this embodiment, well-known components provided in the semiconductor memory device (e.g., a memory cell array, a power supply circuit, a clock generator, etc.) are not shown in order to simplify the explanation.

[0013] The input buffer 10 generates a reference clock signal clk_ref by buffering an external clock signal input to the input buffer 10. The generated reference clock signal clk_ref is output to a delay circuit 20 and a control circuit 30.

[0014] The delay circuit 20 is a delay locked loop (DLL) circuit that generates an output clock signal (delayed signal) dll_clk by delaying an input reference clock signal clk_ref. The delay circuit 20 outputs the generated output clock signal dll_clk to a replica unit 40 and an output buffer 50. The delay circuit 20 also has a delay line unit 31 and a detection unit 32 included in a control circuit 30, which will be described later.

[0015] The replica unit 40 outputs the output clock signal dll_clk generated by the delay circuit 20 to the control circuit 30 as a feedback signal clk_fb.

[0016] The output buffer 50 outputs the output clock signal dll_clk generated by the delay circuit 20 as an internal clock signal to other circuits (not shown) within the semiconductor memory device.

[0017] The control circuit 30 according to this embodiment will be described with reference to Fig. 2. The control circuit 30 includes a delay line unit 31, a detection unit 32, and a control unit 33.

[0018] The delay line section 31 is configured to receive a reference clock signal clk_ref or a start signal start_tdc (described later) and includes a plurality of delay units U1 to U8 (eight in this embodiment) connected in series. Here, each of the reference clock signal clk_ref and the start signal start_tdc is an example of a "first signal" in the present invention.

[0019] Each of the delay units U1 to U8 is configured to delay an input signal by a predetermined amount and output the delayed signal. In the example shown in Fig. 2, a signal (reference clock signal clk_ref or start signal start_tdc) is input to delay unit U1, which is the most upstream delay unit in delay line section 31, among the delay units U1 to U8, and signals output from the immediately preceding delay units U1 to U7 are input to the subsequent delay units U2 to U8.

[0020] Furthermore, each of the delay units U1 to U8 includes one or more delay elements that delay the input signal. Here, each of the delay units U1 to U8 may include an even number (two in this embodiment) of NAND circuits N1 to N16 as one or more delay elements. This makes it possible to align the logical level of the signal input to the delay line section 31 with the logical level of the signal output from each of the delay units U1 to U8. In the example shown in Figure 2, delay unit U1 includes two NAND circuits N1 and N2, delay unit U2 includes two NAND circuits N3 and N4, delay unit U3 includes two NAND circuits N5 and N6, delay unit U4 includes two NAND circuits N7 and N8, delay unit U5 includes two NAND circuits N9 and N10, delay unit U6 includes two NAND circuits N11 and N12, delay unit U7 includes two NAND circuits N13 and N14, and delay unit U8 includes two NAND circuits N15 and N16.

[0021] A signal (reference clock signal clk_ref or start signal start_tdc) is input to one input terminal of the NAND circuit N1, which is the most upstream of the plurality of NAND circuits N1 to N16 in the delay line unit 31, and a signal output from the output terminal of the preceding NAND circuit N1 to N15 is input to one input terminal of each of the succeeding NAND circuits N2 to N16. Furthermore, activation signals AS[1] to AS

[10] , AS

[12] , AS

[14] , and AS

[16] for activating the corresponding NAND circuits N1 to N10, N12, N14, and N16 are input to the other input terminal of each of the NAND circuits N1 to N10, N12, N14, and N16. For example, when the logical value of the activation signal AS[i] (in this embodiment, i is an integer between 1 and 16, inclusive, excluding 11, 13, and 15) is "1," the NAND circuit Ni is activated, and when the logical value of the activation signal AS[i] is "0," the NAND circuit Ni is deactivated. Note that in this embodiment, the logical value of the activation signal AS[i] is set by the control unit 33.

[0022] Furthermore, the delay line section 31 is formed with a plurality of (three in this embodiment) bypass paths BR1 to BR3, each of which has a different number of delay units through which an input signal (reference clock signal clk_ref or start signal start_tdc) passes before being output from the delay line section 31. In the example shown in FIG. 2, the bypass path BR1 is formed to shortcut between the delay unit U1 and the delay unit U8. As a result, the number of delay units through which the signal passes from the bypass path BR1 to the delay line section 31 to be output is two (delay units U1 and U8). Furthermore, the bypass path BR2 is formed to shortcut between the delay unit U2 and the delay unit U7. As a result, the number of delay units through which the signal passes from the bypass path BR2 to the delay line section 31 to be output is four (delay units U1, U2, U7, and U8). Furthermore, the bypass path BR3 is formed to shortcut between the delay unit U3 and the delay unit U6. As a result, the number of delay units through which the signal passes before passing through the bypass route BR3 and being output from the delay line section 31 is six (delay units U1, U2, U3, U6, U7, and U8).

[0023] In this embodiment, each of the plurality of bypass routes BR1 to BR3 is configured to include at least one delay unit, which makes it possible to delay signals in each of the bypass routes BR1 to BR3.

[0024] 2, the bypass path BR1 includes one NAND circuit BN1 as a delay unit, the bypass path BR2 includes one NAND circuit BN2 as a delay unit, and the bypass path BR3 includes one NAND circuit BN3 as a delay unit. One input terminal of the NAND circuit BN1 of the bypass path BR1 is connected to the output terminal of the NAND circuit N1 of the delay unit U1, and the output terminal of the NAND circuit BN1 is connected to the other input terminal of the NAND circuit N15 of the delay unit U8. One input terminal of the NAND circuit BN2 of the bypass path BR2 is connected to the output terminal of the NAND circuit N3 of the delay unit U2, and the output terminal of the NAND circuit BN2 is connected to the other input terminal of the NAND circuit N13 of the delay unit U7. Furthermore, one input terminal of the NAND circuit BN3 of the bypass path BR3 is connected to the output terminal of the NAND circuit N5 of the delay unit U3, and the output terminal of the NAND circuit BN3 is connected to the other input terminal of the NAND circuit N11 of the delay unit U6. Furthermore, the other input terminal of each of the NAND circuits BN1 to BN3 receives an activation signal AS[B1] to AS[B3] for activating the corresponding NAND circuit BN1 to BN3. For example, when the logic value of the activation signal AS[Bj] (in this embodiment, j is an integer between 1 and 3) is "1," the NAND circuit BNj is activated, and when the logic value of the activation signal AS[Bj] is "0," the NAND circuit BNj is deactivated. In this embodiment, the logic values ​​of the activation signals AS[B1] to AS[B3] are set by the control unit 33.

[0025] In this embodiment, the delay line section 31 is formed in a U-shape in plan view (i.e., a plurality of delay units U1 to U8 (more specifically, a plurality of NAND circuits N1 to N16) are arranged in a U-shape in plan view). This makes it possible to compact the area in which the delay line section 31 is formed. Furthermore, for example, by forming each of the bypass routes BR1 to BR3 so as to provide a shortcut connection between the delay units arranged opposite to each other in the U-shaped route, it is possible to shorten the length of each of the bypass routes BR1 to BR3.

[0026] The detector 32 is configured to receive an end signal end_tdc, which is a delayed version of the start signal start_tdc. When the end signal end_tdc is input after the start signal start_tdc is input to the delay line section 31, the detector 32 is configured to detect the number of delay units U1 to U8 through which the start signal start_tdc has passed before the end signal end_tdc is input. Here, the end signal end_tdc is an example of the "second signal" of the present invention.

[0027] In this embodiment, the detection unit 32 includes latch units corresponding to each of the delay units U1 to U8, which latch signals output from the corresponding delay units U1 to U8 when the end signal end_tdc is input. When the end signal end_tdc is input, the detection unit 32 is configured to detect the number of delay units among the delay units U1 to U8 whose corresponding latch units have latched signals with the same value as the start signal start_tdc as the number of delay units through which the start signal start_tdc passed before the end signal end_tdc was input. This makes it possible to easily detect the number of delay units through which the start signal start_tdc passed before the end signal end_tdc was input (i.e., the delay between the start signal start_tdc and the end signal end_tdc) by inputting the start signal start_tdc and the end signal end_tdc.

[0028] Here, the latch section may include a flip-flop circuit. The flip-flop circuit may include a D flip-flop circuit. This makes it possible to easily latch the signals output from the delay units U1 to U8.

[0029] 2, the detection unit 32 includes a plurality of (eight in this embodiment) D flip-flop circuits FF1 to FF8 corresponding to the plurality of delay units U1 to U8, respectively. The D terminal of the D flip-flop circuit FF1 is connected to the output terminal of the NAND circuit N2 of the delay unit U1, and the D terminal of the D flip-flop circuit FF2 is connected to the output terminal of the NAND circuit N4 of the delay unit U2. The D terminal of the D flip-flop circuit FF3 is connected to the output terminal of the NAND circuit N6 of the delay unit U3, and the D terminal of the D flip-flop circuit FF4 is connected to the output terminal of the NAND circuit N8 of the delay unit U4. The D terminal of the D flip-flop circuit FF5 is connected to the output terminal of the NAND circuit N10 of the delay unit U5, and the D terminal of the D flip-flop circuit FF6 is connected to the output terminal of the NAND circuit N12 of the delay unit U6. Furthermore, the D terminal of D flip-flop circuit FF7 is connected to the output terminal of NAND circuit N14 of delay unit U7, and the D terminal of D flip-flop circuit FF8 is connected to the output terminal of NAND circuit N16 of delay unit U8. An end signal end_tdc is input to the clock terminal of each of the plurality of D flip-flop circuits FF1 to FF8. Furthermore, the output of each of the plurality of D flip-flop circuits FF1 to FF8 is sent to control unit 33.

[0030] The control unit 33 is configured to control the transmission path of the reference clock signal clk_ref in the delay line unit 31 so that the number of delay units through which the reference clock signal clk_ref passes before it is output from the delay line unit 31 is equal to the number of delay units detected by the detection unit 32.

[0031] Furthermore, the control unit 33 may perform control so that the reference clock signal clk_ref is transmitted via a bypass path (any of the bypass paths BR1 to BR3) formed in the delay line unit 31 so that the number of delay units through which the reference clock signal clk_ref passes before being output from the delay line unit 31 is equal to the number of delay units detected by the detection unit 32. In this way, the reference clock signal clk_ref is output from the delay line unit 31 via the bypass path, so that an output signal delayed by the number of delay units detected by the detection unit 32 (i.e., the delay amount between the start signal start_tdc and the end signal end_tdc) can be easily output from the delay line unit 31.

[0032] Furthermore, the control unit 33 may select a bypass route from among the multiple bypass routes BR to BR3 such that the number of delay units through which the reference clock signal clk_ref passes before being output from the delay line unit 31 is equal to the number of delay units detected by the detection unit 32, and perform control so that the reference clock signal clk_ref is transmitted via the selected bypass route. This makes it possible to delay the input reference clock signal clk_ref via the optimal bypass route selected from the multiple bypass routes BR1 to BR3.

[0033] The control unit 33 is configured to receive the reference clock signal clk_ref output from the input buffer 10 and the feedback signal clk_fb output from the replica unit 40. In this embodiment, the control unit 33 asserts a start signal start_tdc (sets its logical value to "1") at the rising edge of the feedback signal clk_fb and outputs it to the delay line unit 31. In this embodiment, the control unit 33 also asserts an end signal end_tdc (sets its logical value to "1") at the rising edge of the reference clock signal clk_ref immediately after the rising edge of the feedback signal clk_fb and outputs it to the detection unit 32.

[0034] In addition, the control unit 33 controls the transmission path of the reference clock signal clk_ref in the delay line unit 31 by setting the logical values ​​of each of the activation signals AS[1] to AS

[10] , AS

[12] , AS

[14] , AS

[16] and the activation signals AS[B1] to AS[B3] to "1" or "0" depending on the number of delay units detected by the detection unit 32 (i.e., the amount of delay between the start signal start_tdc and the end signal end_tdc).

[0035] 3, an example of the relationship between signals and delay amounts in the control circuit 30 will be described. First, when the reference clock signal clk_ref output from the input buffer 10 is input to the delay circuit 20, the delay circuit 20 generates the output clock signal dll_clk by delaying the input reference clock signal clk_ref. Note that in this embodiment, it is assumed that when the control circuit 30 is not detecting the delay amount, the delay circuit 20 generates the output clock signal dll_clk without using the delay line unit 31. Then, the replica unit 40 outputs the output clock signal dll_clk generated by the delay circuit 20 to the control circuit 30 as a feedback signal clk_fb.

[0036] Here, when the delay of the output clock signal dll_clk is adjusted using a DLL circuit, a sequence is executed that includes a delay (lock) operation of the DLL circuit (for example, an operation of synchronizing the reference clock signal clk_ref and the output clock signal dll_clk while activating the delay lines one by one).

[0037] The lock time tDLL due to the delay operation of the DLL circuit can be expressed by the following equation (1). tINT+tDLL=N×tCK (1) In the above equation (1), tINT represents the inherent delay time in the DLL circuit, N represents the number of delay clock cycles between the reference clock signal clk_ref and the output clock signal dll_clk (feedback signal clk_fb), and tCK represents the clock cycle.

[0038] The lock time tDLL can be expressed by the following equation (2). tDLL = X × CDL + Y × FDL (2) In the above formula (2), CDL (coarse delay line) indicates the signal delay amount per delay unit in a CDL with a relatively large delay adjustment pitch, and FDL (fine delay line) indicates the signal delay amount per delay unit in an FDL with a relatively small delay adjustment pitch. Also, X and Y each indicate the number of delay units used to delay the signal.

[0039] 3, it is assumed that the period from the rising edge of the feedback signal clk_fb (and the corresponding start signal start_tdc) at time t1 to the rising edge of the reference clock signal clk_ref (and the corresponding end signal end_tdc) at time t2 is approximately equal to X×CDL in the above equation (2).The detector 32 detects the value of X (i.e., the number of delay units used to delay the signal in CDL (delay line section 31)).

[0040] An example of the operation of the control circuit 30 in this embodiment will be described with reference to FIGS. 4 to 6. FIG. 4 shows an example of the state of signals in the control circuit 30 during the delay amount estimation process, and more specifically, shows an example of the logical values ​​of signals in the control circuit 30 at time t1 in FIG. 3. When the rising edge of the feedback signal clk_fb is input to the control unit 33 at time t1, the control unit 33 asserts the start signal start_tdc (sets the logical value to "1") and outputs it to the delay line unit 31. The control unit 33 also sets the logical values ​​of each of the activation signals AS[1] to AS

[10] , AS

[12] , AS

[14] , and AS

[16] to "1," and sets the logical values ​​of each of the activation signals AS[B1] to AS[B3] to "0." As a result, the start signal start_tdc is transmitted through the delay units U1 to U8 in the delay line unit 31.

[0041] 5 shows an example of the state of signals in the control circuit 30 during the delay amount estimation process, and more specifically, shows an example of the logical values ​​of signals in the control circuit 30 at time t2 in FIG. 3. At time t2, when the rising edge of the reference clock signal clk_ref immediately after the rising edge of the feedback signal clk_fb is input to the control unit 33, the control unit 33 asserts the end signal end_tdc (sets the logical value to "1") and outputs it to the detection unit 32. At this time, each of the multiple D flip-flop circuits FF1 to FF8 in the detection unit 32 latches the signal output from the corresponding delay unit U1 to U8 and outputs the latched signal to the control unit 33. Here, as shown in FIG. 5, if the asserted start signal start_tdc has been transmitted to the delay unit U6 at time t2, the logical values ​​of the signals latched by the D flip-flop circuits FF1 to FF6 corresponding to each of the delay units U1 to U6 will be "1." On the other hand, the logical value of the signal latched by the D flip-flop circuits FF7 to FF8 corresponding to each of the delay units U7 to U8 to which the asserted start signal start_tdc has not been transmitted is “0.” This enables the detection unit 32 to detect (estimate) the number of D flip-flop circuits (six in the example shown in FIG. 5) among the multiple D flip-flop circuits FF1 to FF8 that latch a signal with a logical value of “1” when the asserted end signal end_tdc is input, as the number of delay units through which the start signal start_tdc has passed before the end signal end_tdc is input.

[0042] 6 shows an example of the state of signals in the control circuit 30 during the output signal generation process. Here, the control unit 33 may use, for example, a switch circuit (not shown) or the like to perform control so that the reference clock signal clk_ref is input to the delay line unit 31. The control unit 33 also controls the transmission path of the reference clock signal clk_ref in the delay line unit 31 so that the number of delay units through which the reference clock signal clk_ref passes before being output from the delay line unit 31 is equal to the number of delay units detected by the detection unit 32.

[0043] Specifically, the control unit 33 controls the transmission path of the reference clock signal clk_ref in the delay line unit 31 so that the reference clock signal clk_ref is transmitted via any one of the multiple bypass paths BR1 to BR3. The control unit 33 may negate (set the logical value to "0") each of the start signal start_tdc and the end signal end_tdc. For example, as shown in FIG. 5, when the number of delay units detected by the detection unit 32 is six (the number of NAND circuits is 12), the control unit 33 controls so that the reference clock signal clk_ref is transmitted via the bypass path BR3, of the multiple bypass paths BR1 to BR3, through which the reference clock signal clk_ref passes before being output from the delay line unit 31. In this case, the control unit 33 sets the logical value of each of the activation signals AS[1] to AS[5], AS

[12] , AS

[14] , AS

[16] , and AS[B3] to "1," and sets the logical value of each of the activation signals AS[6] to AS

[10] , AS[B1] to AS[B2] to "0." As a result, the reference clock signal clk_ref is transmitted through the delay units U1 to U3, the bypass path BR3, and the delay units U6 to U8 in the delay line unit 31. That is, the reference clock signal clk_ref is transmitted through the NAND circuits N1, N2, N3, N4, N5, BN3, N11, N12, N13, N14, N15, and N16.

[0044] In this way, it is possible to use the delay line section 31 to easily generate an output signal that is delayed from the input signal (reference clock signal clk_ref) by the delay amount detected by the detection section 32.

[0045] As described above, according to the control circuit 30, semiconductor memory device, and control method thereof of this embodiment, the number of delay units through which the start signal start_tdc (first signal) has passed before the end signal end_tdc (second signal) is input is detected as the delay amount between the start signal start_tdc and the end signal end_tdc, so that the delay amount can be easily detected by inputting each of the start signal start_tdc and the end signal end_tdc. Also, according to the control circuit 30, semiconductor memory device, and control method thereof of this embodiment, the transmission path of the reference clock signal clk_ref in the delay line unit 31 is controlled so that the number of delay units through which the reference clock signal clk_ref (first signal) has passed is equal to the number of delay units detected by the detection unit 32 (i.e., the delay amount between the start signal start_tdc and the end signal end_tdc). Therefore, it is possible to easily generate an output signal delayed by the delay amount from the input signal (reference clock signal clk_ref) using this delay line unit 31. This makes it possible to efficiently estimate the amount of delay between the start signal start_tdc and the end signal end_tdc and generate an output signal according to this amount of delay.

[0046] In the above-described embodiment, the delay unit Uk (k is an integer between 1 and 8) includes a NAND circuit N(2k-1) that delays the start signal start_tdc or the reference clock signal clk_ref (first signal) and a NAND circuit N(2k) connected to the output of the NAND circuit N(2k-1). However, the present invention is not limited to this. For example, as shown in FIG. 7, the delay unit Uk may include a NAND circuit N(2k-1), a NAND circuit N(2k), and a NAND circuit CNk connected between the NAND circuit N(2k-1) and a corresponding D flip-flop circuit FFk (latch unit). Here, the NAND circuit N(2k-1) is an example of the "first delay element" of the present invention, the NAND circuit N(2k) is an example of the "second delay element" of the present invention, and the NAND circuit CNk is an example of the "third delay element" of the present invention. This makes it possible to delay a signal using three NAND circuits (delay elements).

[0047] In the example shown in FIG. 7, one NAND circuit CN1 is provided between the NAND circuit N1 and the corresponding D flip-flop circuit FF1, and one NAND circuit CN2 is provided between the NAND circuit N3 and the corresponding D flip-flop circuit FF2. Furthermore, one NAND circuit CN3 is provided between the NAND circuit N5 and the corresponding D flip-flop circuit FF3, and one NAND circuit CN4 is provided between the NAND circuit N7 and the corresponding D flip-flop circuit FF4. Furthermore, one NAND circuit CN5 is provided between the NAND circuit N9 and the corresponding D flip-flop circuit FF5, and one NAND circuit CN6 is provided between the NAND circuit N11 and the corresponding D flip-flop circuit FF6. Furthermore, one NAND circuit CN7 is provided between the NAND circuit N13 and the corresponding D flip-flop circuit FF7, and one NAND circuit CN8 is provided between the NAND circuit N15 and the corresponding D flip-flop circuit FF8.

[0048] 7, one input terminal of NAND circuit CN1 is connected to the output terminal of NAND circuit N1, and the output terminal of NAND circuit CN1 is connected to the D terminal of D flip-flop circuit FF1. One input terminal of NAND circuit CN2 is connected to the output terminal of NAND circuit N3, and the output terminal of NAND circuit CN2 is connected to the D terminal of D flip-flop circuit FF2. One input terminal of NAND circuit CN3 is connected to the output terminal of NAND circuit N5, and the output terminal of NAND circuit CN3 is connected to the D terminal of D flip-flop circuit FF3. One input terminal of NAND circuit CN4 is connected to the output terminal of NAND circuit N7, and the output terminal of NAND circuit CN4 is connected to the D terminal of D flip-flop circuit FF4. One input terminal of NAND circuit CN5 is connected to the output terminal of NAND circuit N9, and the output terminal of NAND circuit CN5 is connected to the D terminal of D flip-flop circuit FF5. Furthermore, one input terminal of NAND circuit CN6 is connected to the output terminal of NAND circuit N11, and the output terminal of NAND circuit CN6 is connected to the D terminal of D flip-flop circuit FF6. Furthermore, one input terminal of NAND circuit CN7 is connected to the output terminal of NAND circuit N13, and the output terminal of NAND circuit CN7 is connected to the D terminal of D flip-flop circuit FF7. Furthermore, one input terminal of NAND circuit CN8 is connected to the output terminal of NAND circuit N15, and the output terminal of NAND circuit CN8 is connected to the D terminal of D flip-flop circuit FF8.

[0049] Activation signals AS[C1] to AS[C8] for activating the corresponding NAND circuits CN1 to CN8 are input to the other input terminal of each of the NAND circuits CN1 to CN8. Here, the logical values ​​of the activation signals AS[C1] to AS[C8] may be set by the control unit 33. For example, in the delay amount estimation process described with reference to FIGS. 4 and 5, the control unit 33 may set the logical value of each of the activation signals AS[C1] to AS[C8] to "1" (i.e., may activate each of the NAND circuits CN1 to CN8). Furthermore, in the output signal generation process described with reference to FIG. 6, the control unit 33 may set the logical value of each of the activation signals AS[C1] to AS[C8] to "0" (i.e., may deactivate each of the NAND circuits CN1 to CN8).

[0050] In the above-described embodiment and modified example, the delay line section 31 is formed in a U-shape in a plan view, but the present invention is not limited to this. The delay line section 31 may be formed in a linear shape, as shown in Fig. 8, or may have a shape other than a U-shape or a linear shape in a plan view.

[0051] Furthermore, in the above-described embodiment and modified example, a case where one delay unit is provided in each of the bypass routes BR1 to BR3 has been described as an example, but the present invention is not limited to this case. For example, two or more delay units (delay elements) may be provided in at least one of the multiple bypass routes BR1 to BR3.

[0052] Furthermore, in the above-described embodiment and modified example, the case where three bypass paths BR1 to BR3 are provided has been described as an example, but the present invention is not limited to this case. The number of bypass paths may be set arbitrarily depending on, for example, the number of delay units (delay elements) through which the input signal passes.

[0053] In addition, in the above-described embodiment and modified example, a case where a NAND circuit is used as a delay element has been described as an example, but the present invention is not limited to this case. For example, other circuits such as an inverter circuit or a buffer circuit may be used as a delay element.

[0054] Furthermore, in the above-described embodiment and modified examples, the semiconductor memory device is a DRAM, but the present invention is not limited to this. For example, the semiconductor memory device may be an SRAM (Static Random Access Memory), a pSRAM (Pseudo-Static Random Access Memory), a flash memory, or another semiconductor memory device. [Explanation of symbols]

[0055] 30...Control circuit 31...Delay line section 32...Detection unit 33...Control unit BR1, BR2, BR3...bypass route FF1, FF2, FF3, FF4, FF5, FF6, FF7, FF8...flip-flop circuits N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,BN1,BN2,BN3,CN1,CN2,CN3,CN4,CN5,CN6,CN7,CN8...NAND circuit U1, U2, U3, U4, U5, U6, U7, U8...Delay units clk_ref...Reference clock signal clk_fb...feedback signal end_tdc...End signal start_tdc…start signal

Claims

1. a delay line section to which a first signal is input, the delay line section including a plurality of delay units connected in series, each of the plurality of delay units delaying the input first signal; a detection unit to which a second signal, which is a delayed signal of the first signal, is input, the detection unit detecting, when the second signal is input after the first signal is input to the delay line unit, the number of delay units through which the first signal has passed before the second signal is input; a control unit that controls a transmission path of the first signal in the delay line unit so that the number of delay units through which the first signal passes before being output from the delay line unit is equal to the number of delay units detected by the detection unit. Control circuit.

2. the control unit controls the first signal to be transmitted through a bypass path formed in the delay line unit so that the number of delay units through which the first signal passes before being output from the delay line unit is equal to the number of delay units detected by the detection unit. The control circuit of claim 1 .

3. the delay line unit is provided with a plurality of bypass paths each having a different number of delay units through which the first signal passes before being output from the delay line unit; the control unit selects, from the plurality of bypass paths, a bypass path through which the first signal passes until the first signal is output from the delay line unit, the number of delay units being equal to the number of delay units detected by the detection unit, and controls the first signal to be transmitted via the selected bypass path.

3. The control circuit of claim 2.

4. the bypass path includes at least one delay unit; 3. The control circuit of claim 2.

5. The detection unit a latch section corresponding to each of the plurality of delay units, the latch section latching a signal output from the corresponding delay unit when the second signal is input; When the second signal is input, the number of delay units in which a signal having the same value as the first signal is latched by a corresponding latch unit is detected as the number of delay units through which the first signal has passed before the second signal is input. The control circuit of claim 1 .

6. At least one delay unit among the plurality of delay units includes a first delay element that delays the first signal, a second delay element connected to an output of the first delay element, and a third delay element connected between the first delay element and a corresponding latch unit.

6. The control circuit of claim 5.

7. the latch unit includes a flip-flop circuit, 6. The control circuit of claim 5.

8. the flip-flop circuit includes a D flip-flop circuit; 8. The control circuit of claim 7.

9. The delay line section is formed in a U-shape in a plan view. The control circuit of claim 1 .

10. each of the plurality of delay units includes one or more delay elements that delay the first signal; The control circuit of claim 1 .

11. each of the plurality of delay units includes an even number of NAND circuits as the one or more delay elements; 11. The control circuit of claim 10.

12. each of the plurality of delay units includes two NAND circuits as the one or more delay elements; 12. The control circuit of claim 11.

13. A control circuit according to any one of claims 1 to 12, Semiconductor memory device.

14. A control method executed by a control circuit provided in a semiconductor memory device, comprising: a delay line section to which a first signal is input, the delay line section including a plurality of delay units connected in series, each of the plurality of delay units delaying the input first signal; when a second signal, which is a delayed version of the first signal, is input to the control circuit after the first signal is input to the delay line section, detecting the number of delay units among the plurality of delay units through which the first signal has passed before the second signal is input; and controlling a transmission path of the first signal in the delay line unit so that the number of delay units through which the first signal passes before being output from the delay line unit is equal to the number of detected delay units. A method for controlling a semiconductor memory device.

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