Device structure and double-sided manufacturing technology for integrated circuits

Abstract

To provide integrated circuit (IC) structures.SOLUTION: In a double-sided device, a device layer 215 includes a plurality of semiconductor bodies 310 surrounded by an isolation dielectric 480. Each of the semiconductor bodies is a component comprising one or more finFETs. Front-side and back-side interconnect metalizations 333, 334 each include a plurality of interconnect metalization levels 320, 321 embedded in an inter-layer dielectric (ILD). The front-side and back-side interconnect metalizations have different material compositions and / or dimensions, and each have any number of levels with higher levels typically having dimensions relaxed from those of lower levels. An IC stratum 350 comprises only one, or both, of the front-side and back-side interconnect metalizations.SELECTED DRAWING: Figure 3I

Description

[Technical Field]

[0001] [Priority Claim] This application claims priority to U.S. Provisional Application No. 62 / 380,316, filed August 26, 2016, entitled "Integrated Circuit Device Structure and Fabrication Techniques Using Backside Exposure of Frontside Structures."

[0002] Related Applications This application is based on International Patent Application No. PCT / US2015 / 052033, filed October 1, 2015, entitled "Method for Fabricating Backside Self-Aligned Vias and Structures Formed Therein," and International Patent Application No. PCT / US2015 / 052440, filed September 25, 2015, entitled "Fabrication of Metal on Both Sides of Backside Contact Structures and Devices," and International Patent Application No. PCT / US2015 / 052440, filed September 25, 2015, entitled "Multi-H Si This application is related to International Patent Application No. PCT / US2015 / 052288, filed September 25, 2015, entitled "Backside Fin Recess Control Using Option," International Patent Application No. PCT / US2016 / 025576, filed April 1, 2016, entitled "Layer-Transferred Ferroelectric Memory Device," International Patent Application No. PCT / US2016 / 025579, filed April 1, 2016, entitled "Semiconductor Diode Utilizing a Backside Semiconductor or Metal," and International Patent Application No. PCT / US2016 / 025593, filed April 1, 2016, entitled "Transistor Structure Comprising a Deep Via Lined with Dielectric Material." [Background technology]

[0003] Device density within integrated circuits (ICs) has been increasing for decades, following Moore's Law. However, as the lateral dimensions of device features shrink with each technology generation, it becomes increasingly difficult to further reduce structural dimensions.

[0004] Currently, three-dimensional (3D) scaling is of great interest because reducing z-height (device thickness) provides another means to improve overall device density and IC performance. 3D scaling can take the form of chip stacking or packaged IC stacking, for example. Known 3D integration techniques are expensive and may only provide incremental improvements in z-height and device density. For example, a large portion of the chip thickness may be inactive substrate material. Such chip stacks may use through-substrate via (TSV) technology as a means of vertically interconnecting the chip stack. TSVs typically extend the substrate material by 20-50 μm or more and are therefore generally limited to via diameters at micron scales. As a result, TSV density is limited to well below the density of most device (e.g., transistor, memory) cells. Furthermore, the final z-height of a chip stack using TSV technology may be hundreds of microns thicker than the actual device layers used by the stacked devices.

[0005] 3D scaling may take the form of vertically oriented devices, e.g., where the length of the transistor channel is substantially perpendicular to the plane of the chip, rather than parallel to the plane for more common laterally oriented transistors. One problem faced by many vertical device architectures is how to fabricate terminals at either end of the device, which can be more easily achieved in laterally oriented devices. [Brief explanation of the drawings]

[0006] The materials described herein are shown by way of example, not limitation, in the accompanying drawings. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Also, while various physical features may be represented in these simplified, "idealized" forms and shapes for clarity of illustration, it should be understood that some embodiments may nonetheless approximate the ideal depicted. For example, smooth surfaces and orthogonal intersections may be depicted while ignoring the finite roughness, chamfers, and imperfectly angled intersections characteristic of structures formed by nanofabrication techniques. Thus, features depicted with a rectangular cross-section in the plane of a reference coordinate system may actually have a cross-sectional view that is rounded or sloped at one or more edges of the feature, resulting in a cross-sectional shape that is non-rectangular (e.g., hourglass-shaped, trapezoidal, etc.). Furthermore, where appropriate, reference numerals may be repeated among the figures to indicate corresponding or similar elements.

[0007] In the diagram: [Figure 1] FIG. 1 is a flow diagram illustrating a method for processing a double-sided device according to some embodiments. [Figure 2A] 1A-1C are plan views of a substrate processed using a double-sided device processing method according to some embodiments. [Figure 2B] 1A-1C are plan views of a substrate processed using a double-sided device processing method according to some embodiments. [Figure 2C] 1A-1C are plan views of a substrate processed using a double-sided device processing method according to some embodiments. [Figure 2D] 1A-1C are plan views of a substrate processed using a double-sided device processing method according to some embodiments. [Figure 2E] 1A-1C are plan views of a substrate processed using a double-sided device processing method according to some embodiments. [Figure 2F]1A-1C are plan views of a substrate processed using a double-sided device processing method according to some embodiments. [Figure 2G] 1A-1C are plan views of a substrate processed using a double-sided device processing method according to some embodiments. [Figure 2H] 1A-1C are plan views of a substrate processed using a double-sided device processing method according to some embodiments. [Figure 3A] 1A-1C are cross-sectional views of a substrate processed using a double-sided device processing method according to some embodiments. [Figure 3B] 1A-1C are cross-sectional views of a substrate processed using a double-sided device processing method according to some embodiments. [Figure 3C] 1A-1C are cross-sectional views of a substrate processed using a double-sided device processing method according to some embodiments. [Figure 3D] 1A-1C are cross-sectional views of a substrate processed using a double-sided device processing method according to some embodiments. [Figure 3E] 1A-1C are cross-sectional views of a substrate processed using a double-sided device processing method according to some embodiments. [Figure 3F] 1A-1C are cross-sectional views of a substrate processed using a double-sided device processing method according to some embodiments. [Figure 3G] 1A-1C are cross-sectional views of a substrate processed using a double-sided device processing method according to some embodiments. [Figure 3H] 1A-1C are cross-sectional views of a substrate processed using a double-sided device processing method according to some embodiments. [Figure 3I] 1A-1C are cross-sectional views of a substrate processed using a double-sided device processing method according to some embodiments. [Figure 3J] 1A-1C are cross-sectional views of a substrate processed using a double-sided device processing method according to some embodiments. [Figure 4A] FIG. 10 is an isometric view further illustrating an intervening layer comprising both III-N semiconductor and dielectric materials, according to some embodiments. [Figure 4B]FIG. 10 is an isometric view further illustrating an intervening layer comprising both III-N semiconductor and dielectric materials, according to some embodiments. [Figure 4C] FIG. 10 is an isometric view further illustrating an intervening layer comprising both III-N semiconductor and dielectric materials, according to some embodiments. [Figure 4D] FIG. 10 is a cross-sectional view further illustrating an intervening layer comprising both III-V semiconductor and dielectric materials, according to some embodiments. [Figure 5] FIG. 1 is a flow diagram illustrating a backside exposure method according to some embodiments. [Figure 6] 1 is a plan view of a substrate with an enlarged view of an IC die on the substrate and a transistor structure on the IC die, according to some embodiments. [Figure 7] FIG. 1 is a flow diagram illustrating a backside processing method including electrical isolation of a transistor semiconductor body, according to some embodiments. [Figure 8A] 8A-8C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 7 are performed, according to some embodiments. [Figure 8B] 8A-8C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 7 are performed, according to some embodiments. [Figure 8C] 8A-8C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 7 are performed, according to some embodiments. [Figure 9A] 8A-8C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 7 are performed, according to some embodiments. [Figure 9B] 8A-8C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 7 are performed, according to some embodiments. [Figure 9C] 8A-8C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 7 are performed, according to some embodiments. [Figure 10A]8A-8C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 7 are performed, according to some embodiments. [Figure 10B] 8A-8C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 7 are performed, according to some embodiments. [Figure 10C] 8A-8C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 7 are performed, according to some embodiments. [Figure 11A] 8A-8C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 7 are performed, according to some embodiments. [Figure 11B] 8A-8C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 7 are performed, according to some embodiments. [Figure 11C] 8A-8C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 7 are performed, according to some embodiments. [Figure 11D] 8A-8C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 7 are performed, according to some embodiments. [Figure 11E] 8A-8C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 7 are performed, according to some embodiments. [Figure 11F] 8A-8C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 7 are performed, according to some embodiments. [Figure 12] FIG. 1 is a flow diagram illustrating a backside processing method including backside transistor source / drain contact metallization, according to some embodiments. [Figure 13] 1 is a plan view of a transistor structure suitable for forming backside transistor source / drain contact metallization, according to some embodiments. [Figure 14A]13A-13C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 12 are performed, according to some embodiments. [Figure 14B] 13A-13C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 12 are performed, according to some embodiments. [Figure 14C] 13A-13C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 12 are performed, according to some embodiments. [Figure 14D] 13A-13C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 12 are performed, according to certain alternative embodiments. [Figure 14E] 13A-13C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 12 are performed, according to certain alternative embodiments. [Figure 14F] 13A-13C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 12 are performed, according to certain alternative embodiments. [Figure 15A] 13A-13C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 12 are performed, according to some embodiments. [Figure 15B] 13A-13C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 12 are performed, according to some embodiments. [Figure 15C] 13A-13C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 12 are performed, according to some embodiments. [Figure 15D] 13A-13C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 12 are performed, according to certain alternative embodiments. [Figure 15E] 13A-13C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 12 are performed, according to certain alternative embodiments. [Figure 15F]13A-13C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 12 are performed, according to certain alternative embodiments. [Figure 16A] 13A-13C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 12 are performed, according to some embodiments. [Figure 16B] 13A-13C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 12 are performed, according to some embodiments. [Figure 16C] 13A-13C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 12 are performed, according to some embodiments. [Figure 16D] 13A-13C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 12 are performed, according to certain alternative embodiments. [Figure 16E] 13A-13C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 12 are performed, according to certain alternative embodiments. [Figure 16F] 13A-13C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 12 are performed, according to certain alternative embodiments. [Figure 17] FIG. 1 is a flow diagram illustrating a backside processing method including backside transistor gate metallization, according to some embodiments. [Figure 18A] 1A-1C illustrate cross-sectional views of a transistor structure as some front-side fabrication steps are performed, according to some embodiments. [Figure 18B] 1A-1C illustrate cross-sectional views of a transistor structure as some front-side fabrication steps are performed, according to some embodiments. [Figure 19A] 1A-1C illustrate cross-sectional views of a transistor structure as some front-side fabrication steps are performed, according to some embodiments. [Figure 19B] 1A-1C illustrate cross-sectional views of a transistor structure as some front-side fabrication steps are performed, according to some embodiments. [Figure 20A]1A-1C illustrate cross-sectional views of a transistor structure as some front-side fabrication steps are performed, according to some embodiments. [Figure 20B] 1A-1C illustrate cross-sectional views of a transistor structure as some front-side fabrication steps are performed, according to some embodiments. [Figure 21A] 1A-1C illustrate cross-sectional views of a transistor structure as some front-side fabrication steps are performed, according to some embodiments. [Figure 21B] 1A-1C illustrate cross-sectional views of a transistor structure as some front-side fabrication steps are performed, according to some embodiments. [Figure 22A] 1A-1C illustrate cross-sectional views of a transistor structure as some front-side fabrication steps are performed, according to some embodiments. [Figure 22B] 1A-1C illustrate cross-sectional views of a transistor structure as some front-side fabrication steps are performed, according to some embodiments. [Figure 23A] 1A-1C illustrate cross-sectional views of a transistor structure as some front-side fabrication steps are performed, according to some embodiments. [Figure 23B] 1A-1C illustrate cross-sectional views of a transistor structure as some front-side fabrication steps are performed, according to some embodiments. [Figure 24A] 1A-1C illustrate cross-sectional views of a transistor structure as some front-side fabrication steps are performed, according to some embodiments. [Figure 24B] 1A-1C illustrate cross-sectional views of a transistor structure as some front-side fabrication steps are performed, according to some embodiments. [Figure 25A] 1A-1C illustrate cross-sectional views of a transistor structure as some front-side fabrication steps are performed, according to some embodiments. [Figure 25B] 1A-1C illustrate cross-sectional views of a transistor structure as some front-side fabrication steps are performed, according to some embodiments. [Figure 26A] 18A-18D illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 17 are performed, according to some embodiments. [Figure 26B]18A-18D illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 17 are performed, according to some embodiments. [Figure 26C] 18A-18D illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 17 are performed, according to some embodiments. [Figure 27A] 18A-18D illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 17 are performed, according to some embodiments. [Figure 27B] 18A-18D illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 17 are performed, according to some embodiments. [Figure 27C] 18A-18D illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 17 are performed, according to some embodiments. [Figure 28A] 18A-18D illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 17 are performed, according to some embodiments. [Figure 28B] 18A-18D illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 17 are performed, according to some embodiments. [Figure 28C] 18A-18D illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 17 are performed, according to some embodiments. [Figure 28D] 18A-18D show cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 17 are performed, according to certain alternative embodiments. [Figure 28E] 18A-18D show cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 17 are performed, according to certain alternative embodiments. [Figure 28F] 18A-18D show cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 17 are performed, according to certain alternative embodiments. [Figure 29A]18A-18D show cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 17 are performed, according to certain alternative embodiments. [Figure 29B] 18A-18D show cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 17 are performed, according to certain alternative embodiments. [Figure 29C] 18A-18D show cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 17 are performed, according to certain alternative embodiments. [Figure 30A] 18A-18D show cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 17 are performed, according to certain alternative embodiments. [Figure 30B] 18A-18D show cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 17 are performed, according to certain alternative embodiments. [Figure 30C] 18A-18D show cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 17 are performed, according to certain alternative embodiments. [Figure 31A] 18A-18D show cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 17 are performed, according to certain alternative embodiments. [Figure 31B] 18A-18D show cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 17 are performed, according to certain alternative embodiments. [Figure 31C] 18A-18D show cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 17 are performed, according to certain alternative embodiments. [Figure 32] FIG. 1 is a flow diagram illustrating a backside processing method including dielectric spacer replacement, according to some embodiments. [Figure 33A] 33A-33C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 32 are performed, according to some alternative embodiments. [Figure 33B]33A-33C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 32 are performed, according to some alternative embodiments. [Figure 33C] 33A-33C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 32 are performed, according to some alternative embodiments. [Figure 34A] 33A-33C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 32 are performed, according to some alternative embodiments. [Figure 34B] 33A-33C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 32 are performed, according to some alternative embodiments. [Figure 34C] 33A-33C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 32 are performed, according to some alternative embodiments. [Figure 35A] 33A-33C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 32 are performed, according to some alternative embodiments. [Figure 35B] 33A-33C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 32 are performed, according to some alternative embodiments. [Figure 35C] 33A-33C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 32 are performed, according to some alternative embodiments. [Figure 36A] 33A-33C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 32 are performed, according to some alternative embodiments. [Figure 36B] 33A-33C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 32 are performed, according to some alternative embodiments. [Figure 36C] 33A-33C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 32 are performed, according to some alternative embodiments. [Figure 37A]33A-33C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 32 are performed, according to some alternative embodiments. [Figure 37B] 33A-33C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 32 are performed, according to some alternative embodiments. [Figure 37C] 33A-33C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 32 are performed, according to some alternative embodiments. [Figure 38A] 1 illustrates a backside exposure method according to some embodiments. [Figure 38B] FIG. 1 is a flow diagram illustrating a method for forming backside source / drain semiconductor and contact metallization for non-planar transistors selective to planar transistors, according to some embodiments. [Figure 38C] FIG. 1 is a flow diagram illustrating a method for forming backside source / drain semiconductor and contact metallization of a non-planar transistor selective to other non-planar transistors, according to some embodiments. [Figure 39] 1A-1C are top views of a non-planar transistor structure lacking one source / drain contact metallization and a planar transistor structure having both source / drain metallization, according to some embodiments. [Figure 40A] 38C show cross-sectional views of a non-planar transistor structure as certain steps in the method shown in FIG. 38B are performed, according to some embodiments. [Figure 40B] 38C show cross-sectional views of a non-planar transistor structure as certain steps in the method shown in FIG. 38B are performed, according to some embodiments. [Figure 40C] 38C show cross-sectional views of a non-planar transistor structure as certain steps in the method shown in FIG. 38B are performed, according to some embodiments. [Figure 41A]38C show cross-sectional views of a planar transistor structure as certain steps in the method shown in FIG. 38B are performed, according to some embodiments. [Figure 41B] 38C show cross-sectional views of a planar transistor structure as certain steps in the method shown in FIG. 38B are performed, according to some embodiments. [Figure 41C] 38C show cross-sectional views of a planar transistor structure as certain steps in the method shown in FIG. 38B are performed, according to some embodiments. [Figure 42A] 38C show cross-sectional views of a non-planar transistor structure as certain steps in the method shown in FIG. 38B are performed, according to some embodiments. [Figure 42B] 38C show cross-sectional views of a non-planar transistor structure as certain steps in the method shown in FIG. 38B are performed, according to some embodiments. [Figure 42C] 38C show cross-sectional views of a non-planar transistor structure as certain steps in the method shown in FIG. 38B are performed, according to some embodiments. [Figure 43A] 38C show cross-sectional views of a planar transistor structure as certain steps in the method shown in FIG. 38B are performed, according to some embodiments. [Figure 43B] 38C show cross-sectional views of a planar transistor structure as certain steps in the method shown in FIG. 38B are performed, according to some embodiments. [Figure 43C] 38C show cross-sectional views of a planar transistor structure as certain steps in the method shown in FIG. 38B are performed, according to some embodiments. [Figure 44A] 38C show cross-sectional views of a non-planar transistor structure as certain steps in the method shown in FIG. 38B are performed, according to some embodiments. [Figure 44B] 38C show cross-sectional views of a non-planar transistor structure as certain steps in the method shown in FIG. 38B are performed, according to some embodiments. [Figure 44C] 38C show cross-sectional views of a non-planar transistor structure as certain steps in the method shown in FIG. 38B are performed, according to some embodiments. [Figure 45A] 38C show cross-sectional views of a planar transistor structure as certain steps in the method shown in FIG. 38B are performed, according to some embodiments. [Figure 45B] 38C show cross-sectional views of a planar transistor structure as certain steps in the method shown in FIG. 38B are performed, according to some embodiments. [Figure 45C] 38C show cross-sectional views of a planar transistor structure as certain steps in the method shown in FIG. 38B are performed, according to some embodiments. [Figure 46] 1A-1C are top views of a non-planar transistor structure lacking one source / drain contact metallization and a non-planar transistor structure having both source / drain metallization, according to some embodiments. [Figure 47A] 38D show cross-sectional views of a non-planar transistor structure as certain steps in the method shown in FIG. 38C are performed, according to some embodiments. [Figure 47B] 38D show cross-sectional views of a non-planar transistor structure as certain steps in the method shown in FIG. 38C are performed, according to some embodiments. [Figure 47C] 38D show cross-sectional views of a non-planar transistor structure as certain steps in the method shown in FIG. 38C are performed, according to some embodiments. [Figure 48A] 38D show cross-sectional views of a non-planar transistor structure as certain steps in the method shown in FIG. 38C are performed, according to some embodiments. [Figure 48B] 38D show cross-sectional views of a non-planar transistor structure as certain steps in the method shown in FIG. 38C are performed, according to some embodiments. [Figure 48C]38D show cross-sectional views of a non-planar transistor structure as certain steps in the method shown in FIG. 38C are performed, according to some embodiments. [Figure 49A] 38D show cross-sectional views of a non-planar transistor structure as certain steps in the method shown in FIG. 38C are performed, according to some embodiments. [Figure 49B] 38D show cross-sectional views of a non-planar transistor structure as certain steps in the method shown in FIG. 38C are performed, according to some embodiments. [Figure 49C] 38D show cross-sectional views of a non-planar transistor structure as certain steps in the method shown in FIG. 38C are performed, according to some embodiments. [Figure 50A] 38D show cross-sectional views of a non-planar transistor structure as certain steps in the method shown in FIG. 38C are performed, according to some embodiments. [Figure 50B] 38D show cross-sectional views of a non-planar transistor structure as certain steps in the method shown in FIG. 38C are performed, according to some embodiments. [Figure 50C] 38D show cross-sectional views of a non-planar transistor structure as certain steps in the method shown in FIG. 38C are performed, according to some embodiments. [Figure 51A] 38D show cross-sectional views of a non-planar transistor structure as certain steps in the method shown in FIG. 38C are performed, according to some embodiments. [Figure 51B] 38D show cross-sectional views of a non-planar transistor structure as certain steps in the method shown in FIG. 38C are performed, according to some embodiments. [Figure 51C] 38D show cross-sectional views of a non-planar transistor structure as certain steps in the method shown in FIG. 38C are performed, according to some embodiments. [Figure 52A] 38D show cross-sectional views of a non-planar transistor structure as certain steps in the method shown in FIG. 38C are performed, according to some embodiments. [Figure 52B] 38D show cross-sectional views of a non-planar transistor structure as certain steps in the method shown in FIG. 38C are performed, according to some embodiments. [Figure 52C] 38D show cross-sectional views of a non-planar transistor structure as certain steps in the method shown in FIG. 38C are performed, according to some embodiments. [Figure 53A] 38D show cross-sectional views of a non-planar transistor structure as certain steps in the method shown in FIG. 38C are performed, according to some embodiments. [Figure 53B] 38D show cross-sectional views of a non-planar transistor structure as certain steps in the method shown in FIG. 38C are performed, according to some embodiments. [Figure 53C] 38D show cross-sectional views of a non-planar transistor structure as certain steps in the method shown in FIG. 38C are performed, according to some embodiments. [Figure 54A] 38D show cross-sectional views of a non-planar transistor structure as certain steps in the method shown in FIG. 38C are performed, according to some embodiments. [Figure 54B] 38D show cross-sectional views of a non-planar transistor structure as certain steps in the method shown in FIG. 38C are performed, according to some embodiments. [Figure 54C] 38D show cross-sectional views of a non-planar transistor structure as certain steps in the method shown in FIG. 38C are performed, according to some embodiments. [Figure 55] FIG. 1 is a flow diagram illustrating a backside processing method including backside impurity implantation, according to some embodiments. [Figure 56A] 56A-56C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 55 are performed, according to some embodiments. [Figure 56B] 56A-56C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 55 are performed, according to some embodiments. [Figure 56C]56A-56C illustrate cross-sectional views of a transistor structure as certain steps in the method shown in FIG. 55 are performed, according to some embodiments. [Figure 57A] 1 illustrates a cross-sectional view of a transistor structure with backside implantation according to some embodiments. [Figure 57B] 1 illustrates a cross-sectional view of a transistor structure with backside implantation according to some embodiments. [Figure 57C] 1 illustrates a cross-sectional view of a transistor structure with backside implantation according to some embodiments. [Figure 58] FIG. 1 is a flow diagram illustrating a backside processing method including epitaxial growth of semiconductors, according to some embodiments. [Figure 59A] 59A-59C illustrate cross-sectional views of a III-N semiconductor device hierarchy as certain steps in the method illustrated in FIG. 58 are performed, according to some embodiments. [Figure 59B] 59A-59C illustrate cross-sectional views of a III-N semiconductor device hierarchy as certain steps in the method illustrated in FIG. 58 are performed, according to some embodiments. [Figure 59C] 59A-59C illustrate cross-sectional views of a III-N semiconductor device hierarchy as certain steps in the method illustrated in FIG. 58 are performed, according to some embodiments. [Figure 60A] 59A-59C illustrate cross-sectional views of semiconductor device layers as some steps in the method shown in FIG. 58 are performed, according to some embodiments. [Figure 60B] 59A-59C illustrate cross-sectional views of semiconductor device layers as some steps in the method shown in FIG. 58 are performed, according to some embodiments. [Figure 60C] 59A-59C illustrate cross-sectional views of semiconductor device layers as some steps in the method shown in FIG. 58 are performed, according to some embodiments. [Figure 61A] 1 illustrates a cross-sectional view of stacked semiconductor device layers according to some embodiments. [Figure 61B] 1 illustrates a cross-sectional view of stacked semiconductor device layers according to some embodiments. [Figure 62A]1 illustrates a cross-sectional view of stacked semiconductor device layers according to some embodiments. [Figure 62B] 1 illustrates a cross-sectional view of stacked semiconductor device layers according to some embodiments. [Figure 63A] 1 illustrates a cross-sectional view of stacked semiconductor device layers according to some embodiments. [Figure 63B] 1 illustrates a cross-sectional view of stacked semiconductor device layers according to some embodiments. [Figure 64A] 1 illustrates a cross-sectional view of stacked semiconductor device layers according to some embodiments. [Figure 64B] 1 illustrates a cross-sectional view of stacked semiconductor device layers according to some embodiments. [Figure 65] 1 shows a plan view of a vertically oriented device according to some embodiments. [Figure 66] FIG. 66 shows a cross-sectional view of the vertically oriented device shown in FIG. 65, according to some embodiments. [Figure 67A] 1 illustrates a cross-sectional view of a stacked 1T1R memory cell according to some embodiments. [Figure 67B] 1 illustrates a cross-sectional view of a stacked 1T1R memory cell according to some embodiments. [Figure 68A] 1 illustrates a cross-sectional view of a stacked 1T1R memory cell according to some embodiments. [Figure 68B] 1 illustrates a cross-sectional view of a stacked 1T1R memory cell according to some embodiments. [Figure 69] 1 shows a cross-sectional view of stacked device layers with intervening thermal conduits, according to some embodiments. [Figure 70] FIG. 1 is an isometric view of an electrical test apparatus for testing a test die through its backside, according to some embodiments. [Figure 71] 1 is an isometric view of an electrical test apparatus for simultaneously testing a die under test through its backside and frontside, according to some embodiments. FIG. [Figure 72] FIG. 1 is a flow diagram illustrating an electrical test processing method according to some embodiments. [Figure 73] FIG. 1 is a top view of a non-planar transistor structure undergoing electrical testing with simultaneous backside and frontside contact, according to some embodiments. [Figure 74A] 1 illustrates a cross-sectional view of a non-planar transistor structure contacted by a conductive pin for electrical testing, according to some embodiments. [Figure 74B] 1 illustrates a cross-sectional view of a non-planar transistor structure contacted by a conductive pin for electrical testing, according to some embodiments. [Figure 74C] 1 illustrates a cross-sectional view of a non-planar transistor structure contacted by a conductive pin for electrical testing, according to some embodiments. [Figure 75A] 1 illustrates a cross-sectional view of a non-planar transistor structure contacted by a conductive pin for electrical testing, according to some embodiments. [Figure 75B] 1 illustrates a cross-sectional view of a non-planar transistor structure contacted by a conductive pin for electrical testing, according to some embodiments. [Figure 75C] 1 illustrates a cross-sectional view of a non-planar transistor structure contacted by a conductive pin for electrical testing, according to some embodiments. [Figure 76A] 1 illustrates a cross-sectional view of a non-planar transistor structure contacted by a conductive pin for electrical testing, according to some embodiments. [Figure 76B] 1 illustrates a cross-sectional view of a non-planar transistor structure contacted by a conductive pin for electrical testing, according to some embodiments. [Figure 76C] 1 illustrates a cross-sectional view of a non-planar transistor structure contacted by a conductive pin for electrical testing, according to some embodiments. [Figure 77] FIG. 1 is a plan view of a logic transistor structure undergoing electrical testing with simultaneous backside and frontside contact, according to some embodiments. [Figure 78A] 1 illustrates a cross-sectional view of a logic transistor structure contacted by a conductive pin for electrical testing, according to some embodiments. [Figure 78B]1 illustrates a cross-sectional view of a logic transistor structure contacted by a conductive pin for electrical testing, according to some embodiments. [Figure 78C] 1 illustrates a cross-sectional view of a logic transistor structure contacted by a conductive pin for electrical testing, according to some embodiments. [Figure 79A] 1 illustrates a cross-sectional view of a logic transistor structure contacted by a conductive pin for electrical testing, according to some embodiments. [Figure 79B] 1 illustrates a cross-sectional view of a logic transistor structure contacted by a conductive pin for electrical testing, according to some embodiments. [Figure 79C] 1 illustrates a cross-sectional view of a logic transistor structure contacted by a conductive pin for electrical testing, according to some embodiments. [Figure 80A] 1 illustrates a cross-sectional view of a logic transistor structure contacted by a conductive pin for electrical testing, according to some embodiments. [Figure 80B] 1 illustrates a cross-sectional view of a logic transistor structure contacted by a conductive pin for electrical testing, according to some embodiments. [Figure 80C] 1 illustrates a cross-sectional view of a logic transistor structure contacted by a conductive pin for electrical testing, according to some embodiments. [Figure 81] 1 illustrates a mobile computing platform and data server machine using an SoC with multiple FETs including double-sided interconnects, according to an embodiment. [Figure 82] FIG. 1 is a functional block diagram of an electronic computer, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0008] One or more embodiments are described with reference to the accompanying figures. While specific configurations and arrangements are illustrated and described in detail, it should be understood that this is done for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements may be realized without departing from the spirit and scope of the description. It will be apparent to those skilled in the art that the techniques and / or arrangements described herein can be used in a variety of other systems and applications other than those specifically described herein.

[0009] Reference is made in the following detailed description to the accompanying drawings, which form a part hereof and illustrate exemplary embodiments. Additionally, it is to be understood that other embodiments may be utilized and structural and / or logical changes may be made without departing from the scope of the claimed subject matter. It should also be noted that directions and references such as up, down, top, and bottom may be used merely to facilitate description of features in the drawings. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of the claimed subject matter is defined solely by the appended claims and their equivalents.

[0010] In the following description, numerous details are set forth. However, it will be apparent to those skilled in the art that the embodiments may be practiced without these specific details. In some instances, well-known methods and devices are shown in block diagram form rather than in detail to avoid obscuring the embodiments. References throughout this specification to "an embodiment" or "one embodiment" or "some embodiments" mean that a particular feature, structure, function, or characteristic described in connection with an embodiment is included in at least one embodiment. Thus, the appearances of the phrases "in an embodiment" or "in one embodiment" or "some embodiments" in various places throughout this specification do not necessarily refer to the same embodiments. Furthermore, particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment unless particular features, structures, functions, or characteristics associated with the two embodiments are mutually exclusive.

[0011] As used in the description and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. The term "and / or," as used herein, is also understood to refer to and include any and all possible combinations of one or more of the associated listed items.

[0012] The terms "coupled" and "connected" may be used herein to describe a functional or structural relationship between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, "connected" may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. "Coupled" may be used to indicate that two or more elements are either in direct or indirect physical or electrical contact with each other (with other intervening elements) and / or that two or more elements cooperate or interact with each other (e.g., are in a causal relationship).

[0013] The terms "over," "under," "between," and "on," as used herein, refer to the relative location of one component or material with respect to another component or material to which such physical relationship is noteworthy. For example, in the context of materials, a material disposed above or below one material or another may be in direct contact or may have one or more intervening materials. Furthermore, a material or materials disposed between two materials may be in direct contact with the two layers or may have one or more intervening layers. On the other hand, a material or materials "on" a first material or second material is in direct contact with the second material / materials. In the context of component assemblies, a similar distinction is made.

[0014] As used throughout this description and claims, a list of items connected by the terms "at least one of" or "one or more of" may mean any combination of the listed items. For example, the phrase "at least one of A, B, or C" may mean A, B, C, A and B, A and C, B and C, or A, B, and C.

[0015] Described herein are IC device structures and fabrication techniques that use double-sided processing of device structures. In addition to the front-side processing typically used in IC device structure fabrication, double-sided processing further includes back-side processing of IC device structures. Double-sided processing may also involve non-standard front-side processing designed to facilitate back-side processing. In some exemplary embodiments, double-sided processing includes exposing the backside of the front-side device structure. In some exemplary embodiments, exposing the backside of the device structure (also referred to herein as "backside exposure" or "BSR") involves wafer-level backside processing that either comprehensively removes the bulk of the substrate material over an area of ​​the wafer or locally removes it within a portion of a region of the wafer, e.g., as confined by an etch mask. In contrast to conventional TSV-type technologies that merely provide electrical routing through the thickness of the substrate material, back-side exposure as described herein is intended to facilitate further fabrication of device structures within a device layer of an IC. Such back-side device layer fabrication can be performed at a density of individual devices (e.g., transistors) and even within subregions of a single device (e.g., terminals of a single transistor). Furthermore, such backside exposure can be performed to remove only a portion, or substantially all, of the donor substrate on which the device layers will be disposed during frontside device processing. As such, micron-deep TSVs may be unnecessary because the thickness of the semiconductor material of the device structures accessed from the backside may be only tens or hundreds of nanometers. In particular, micron-deep conductive TSVs may not require more initial backside processing to be performed in accordance with embodiments herein, while TSV-type techniques may still be utilized, for example, as a means to expose the backside of the device layers.

[0016] As further described below for several exemplary embodiments, processing of the exposed backside of the device structure may involve one or more of: removal of sacrificial device structures and / or artifacts of frontside processing; deposition of contact metallization, e.g., to increase device routing density and / or allow backside electrical probing and / or increase device terminal contact area; deposition of dielectrics, e.g., to increase device isolation, enhance gate electrode coupling and / or reduce parasitic capacitance; deposition of semiconductors, e.g., to reduce parasitic resistance and / or improve crystal quality, bandgap engineering, tensioning device semiconductor regions and / or forming vertically oriented devices; and / or fabricating stacked devices that are bonded or in close contact with each other.

[0017] The backside exposure techniques described herein can enable a paradigm shift from "bottom-up" style device fabrication to "center-out" fabrication, where the "center" is any layer used in front-side fabrication, exposed from the backside, and used again in back-side fabrication. As should become apparent from the following discussion, processing of both the front side and exposed backside of the device structure can address many of the challenges associated with fabricating 3D ICs with front-side processing alone.

[0018] The techniques described herein can be performed with sufficient precision to expose the backside of device layers at the transistor level (e.g., on the order of 5-10 nm). Virtually all material not used by the integrated device can then be discarded from the device. This precision is possible, in part, through advances in substrate (e.g., wafer) material uniformity control and material quality handling. Until now, TSV-based backside electrical connection techniques have not enabled interconnections at specific locations down to the device (e.g., transistor) level. This is because TSV technology typically only abrasively polishes the backside of the substrate to a level that retains at least 20-50 μm of residual substrate material, limiting the formable conductive vias to relatively large diameters (e.g., 2-5 μm).

[0019] Through the removal of large amounts of substrate material, electrical connections at the nanometer level become possible. As will be further described with respect to some exemplary embodiments below, techniques such as through-substrate vias use temporary bonds that are relatively well-suited and insufficiently hard to achieve sufficient thickness uniformity control, while permanent bonding of the carrier ("handle") may not be used. For example, permanent bonding, such as oxide fusion bonding, may achieve advantageous mechanical rigidity for fabricating the structures further described herein. Oxides are very hard and mechanically strong, but not at all compressible. Power Transistors

[0020] As further described in several exemplary embodiments below, CMP processes that are highly selective to oxide materials can be advantageously used to remove even micrometers of material and reduce material thickness in a planar fashion with sufficient thickness control to stop within 10 nm of the target thickness anywhere on the surface area of ​​the substrate. With such planarity, processes typically limited to only the front side of the substrate, e.g., high-resolution lithography, can be used on the back side of the substrate as well, so that electrical contacts have dimensions on the same order as those for typical front-side metallization (e.g., device contacts). For example, such planarization processes can be leveraged alone or in conjunction with other substrate removal techniques, including, but not limited to, nanometer-scale TSV-type substrate processing, to facilitate the formation of openings with lateral dimensions small enough to expose individual devices and / or individual terminals of individual devices.

[0021] FIG. 1 is a flow diagram illustrating a method 101 for processing a double-sided device according to some embodiments. Method 101 can be performed at the wafer level. In some exemplary embodiments, large substrate (e.g., 300 or 450 mm diameter) wafers can be processed through method 101. Method 101 begins at step 105 with a donor substrate containing a device layer. In certain embodiments, the device layer can include active or passive devices. In some embodiments, the device layer is a semiconductor material used by an IC device. In certain embodiments, the device layer is a single-crystal semiconductor material, as such materials often offer device performance advantages over thin-film semiconductor materials that are polycrystalline or amorphous. As an example, in a transistor device, such as a field-effect transistor (FET), the transistor channel is formed from the semiconductor device layer. As another example, for an optical device, such as a photodiode, drift and / or gain semiconductors are formed from the device layer. The device layer may also be used in passive structures with IC devices. For example, an optical waveguide may use semiconductors patterned from the device layer.

[0022] In some embodiments, the donor substrate has a stack of material layers. Such a material stack can facilitate the formation of subsequent IC device layers. As used herein, the term "device layer" refers to at least a device layer, lacking other layers of the donor substrate that are not required for the function of the IC device and therefore represent a significant amount of non-functional "overhead." For example, a "device layer" can include only one device layer, multiple device layers, or a device layer with one or more intervening layers. In certain embodiments, a "device layer" can further include one or more other non-native material layers, as further described below, deposited above or below the device layer. In the exemplary embodiment shown in FIG. 1 , method 101 provides a donor substrate including a carrier layer separated from the device layer by one or more intervening material layers. The carrier layer provides mechanical support during front-side processing of the device layer. The carrier may also provide a basis for crystallinity within the semiconductor device layer. Intervening layers need not be present, but the inclusion of one or more of such material layers may facilitate removal of the carrier layer from the device layer or otherwise expose the backside of the device layer.

[0023] Method 101 proceeds to step 110, where front-side fabrication steps are performed on the donor substrate to form a device structure including one or more regions within the device layer. Any suitable front-side processing technique may be used at step 110 to form any suitable IC device, and exemplary embodiments are further described elsewhere herein. Such IC devices may include devices (e.g., transistors) using device layer material and one or more levels of interconnect metallization formed above the front side of the device layer. At step 115, the front side of the donor substrate may be bonded to a host substrate to form a device-host assembly. The host substrate may be utilized to provide mechanical support for the front side during back-side processing of the device layer. The host substrate may include an integrated circuit to which IC devices fabricated on the donor substrate are interconnected. For such embodiments, bonding the host and donor substrates may further involve forming a 3D interconnect structure through a hybrid (dielectric / metal) bond. Any suitable host substrate and wafer-level bonding technique may be used in step 115, some exemplary embodiments of which are further described elsewhere herein.

[0024] The method 101 proceeds to step 120, where the backside of the device layer is exposed by removing at least a portion of the carrier layer. In some further embodiments, portions of any intervening layers below the device layer may be removed during exposing step 120. In some other embodiments, frontside material deposited above the frontside of the device layer may be removed during exposing step 120. As described elsewhere herein in the context of some exemplary embodiments, the intervening layers may facilitate highly uniform exposure of the backside of the device layer, for example, functioning as one or more of an etch marker or etch stop used in wafer-level backside exposure processing.

[0025] In step 125, the surface of the device layer exposed from the backside is processed to form a double-sided device layer. In certain embodiments, native materials, such as any of those of the donor substrate contacting any region of the device layer, may be replaced with one or more non-native materials in step 125. For example, portions of the semiconductor device layer or intervening layers may be replaced with one or more other semiconductor, metal, or dielectric materials. In some other embodiments, the non-native material may be deposited over or on at least a portion of the backside of the device layer. In some further embodiments, portions of the frontside material removed during exposing step 120 may be replaced in step 125. For example, portions of the semiconductor body, dielectric spacer, gate stack, or contact metallization formed during frontside device fabrication may be replaced with one or more other semiconductor, metal, or dielectric materials during backside deprocessing / rework of the frontside device. In still other embodiments, a second device layer or metal interposer is bonded to the exposed backside.

[0026] Method 101 completes with the output of a device layer-host substrate assembly at step 130. The device layer-host assembly may then be further processed. For example, any suitable technique may be used to singulate and package the device layer-host substrate assembly. If the host substrate is entirely sacrificed, packaging the device layer-host substrate may involve separating the host substrate from the device layer. If the host substrate is not entirely sacrificed (e.g., if the host substrate also includes a device layer), the output of the device layer-host assembly at step 130 may be fed back to step 115 during a subsequent iteration of method 101 (dashed line in FIG. 1 ) as the input for the host substrate. As the host substrate, the device layer-host assembly may be bonded with another donor substrate, and method 101 is repeated. Iterations of method 101 may thereby form wafer-level assemblies of any number of double-sided device layers, each, for example, only tens or hundreds of nanometers thick. In some embodiments, and as further described elsewhere herein, one or more devices (e.g., transistors) or device cells (e.g., 1T-1R memory cells) in the device hierarchy are electrically tested in step 130, for example, as a yield control point in the manufacture of wafer-level assembly of the double-sided device hierarchy. In some embodiments described further below, the electrical testing involves probing of the backside devices.

[0027] 2A, 2B, 2C, 2D, 2E, 2F, and 2G are plan views of a substrate processed using a double-sided device processing method, e.g., method 101, according to some embodiments. 3A, 3B, 3C, 3D, 3E, 3F, 3G, 3H, and 3I correspond to cross-sectional views of a substrate processed using a double-sided device processing method, according to some embodiments. As shown in FIGS. 2A and 3A, donor substrate 201 includes multiple IC dies 211 in any spatial layout across the entire front-side wafer surface. Front-side processing of IC dies 211 may be performed according to any technique to form any device structure. In an exemplary embodiment, die 211 includes one or more semiconductor regions within device layer 215. Die 211 further includes one or more front-side interconnect metallization levels (not shown) above the front side of device layer 215. Intermediate layer 210 separates the backside of device layer 215 from carrier layer 205. In an exemplary embodiment, intermediate layer 210 is in direct contact with both carrier layer 205 and device layer 215. Alternatively, one or more spacer layers may be disposed between intermediate layer 210 and device layer 215 and / or carrier layer 205. Donor substrate 201 may further include other layers, for example, above device layer 215 and / or below carrier layer 205.

[0028] The device layer 215 may include any device material composition known to be suitable for a particular IC device, such as, but not limited to, one or more layers of transistors, diodes, and resistors. In some exemplary embodiments, the device layer 215 includes one or more Group IV (i.e., IUPAC Group 14) semiconductor material layers (e.g., Si, Ge, SiGe), Group III-V semiconductor material layers (e.g., GaAs, InGaAs, InAs, InP), or Group III-N semiconductor material layers (e.g., GaN, AlGaN, InGaN). The device layer 215 may also include one or more Group II-VI semiconductor material layers or semiconducting transition metal dichalcogenide (TMD or TMDC) layers. In other embodiments, the device layer 215 includes one or more graphene layers or graphene material layers having semiconducting properties. In yet other embodiments, the device layer 215 includes one or more oxide semiconductor layers. Exemplary oxide semiconductors include oxides of transition metals (e.g., IUPAC Groups 4-10) or post-transition metals (e.g., IUPAC Groups 11-14). In advantageous embodiments, the oxide semiconductor includes at least one of Cu, Zn, Sn, Ti, Ni, Ga, In, Sr, Cr, Co, V, or Mo. The metal oxide may be a suboxide (AO), a monoxide (AO), a binary oxide (AO), a ternary oxide (ABO), or a mixture thereof. In other embodiments, the device layer 215 includes one or more magnetic, ferromagnetic, or ferroelectric material layers. For example, the device layer 215 may include one or more layers of any material known to be suitable for tunneling junction devices, such as, but not limited to, a magnetic tunnel junction (MTJ) device.

[0029] In some embodiments, device layer 215 is substantially monocrystalline. While monocrystalline, a significant number of intercrystalline defects may nevertheless be present. In other embodiments, device layer 215 is amorphous or polycrystalline (e.g., micro- or nanocrystalline). Device layer 215 may be of any thickness (e.g., the z-dimension in FIG. 3A ). In some exemplary embodiments, device layer 215 has a thickness that is greater than the z-dimension thickness of at least a portion of the semiconductor region of die 211 that is used as the functional semiconductor region. Functional regions built on and / or embedded within device layer 215 need not extend the entire thickness of device layer 215. In some embodiments, the semiconductor region of die 211 is disposed only within the top thickness of device layer 215, the boundary of which is defined in FIG. 3A by dashed line 212. For example, the semiconductor region of die 211 may have a z-direction thickness of 200-300 nm or less, while the device layer may have a z-direction thickness of 700-1000 nm or more. Thus, around 600 nm of device layer thickness may separate the semiconductor region of die 211 from intervening layer 210. Larger device layer thicknesses are also possible, for example, ranging from 1000 nm to 10 μm.

[0030] Carrier layer 205 may have the same material composition as device layer 215, or may have a different material composition than device layer 215. For embodiments in which carrier layer 205 and device layer 215 have the same composition, the two layers may be distinguished by their position relative to intervening layer 210. In some embodiments in which device layer 215 is a crystalline Group IV, III-V, or III-N semiconductor, carrier layer 205 is the same crystalline Group IV, III-V, or III-N semiconductor as device layer 215. In alternative embodiments in which device layer 215 is a crystalline Group IV, III-V, or III-N semiconductor, carrier layer 205 is a different crystalline Group IV, III-V, or III-N semiconductor than device layer 215. In still other embodiments, carrier layer 205 may include or be the material onto which device layer 215 is transferred or grown. For example, the carrier layer 205 may comprise one or more amorphous oxide layers (e.g., glass) or oxide crystalline layers (e.g., sapphire), a polymer sheet, or any material constructed or laminated to a structural support known to be suitable as a carrier during IC device processing. The carrier layer 205 may be of any thickness depending on the properties of the carrier material and the diameter of the substrate (e.g., the z-dimension in FIG. 3A ). For example, if the carrier layer 205 is a large (e.g., 300-450 mm) semiconductor substrate, the thickness of the carrier layer may be 700-1000 μm or greater.

[0031] In some embodiments, one or more intervening layers 210 are disposed between the carrier layer 205 and the device layer 215. In some exemplary embodiments, the intervening layer 210 is compositionally distinct from the carrier layer 205 so that it can serve as a detectable marker during subsequent removal of the carrier layer 205. In some such embodiments, the intervening layer 210 has a composition that, when exposed to an etchant for the carrier layer 205, etches at a significantly slower rate than the carrier layer 205 (i.e., the intervening layer 210 acts as an etch stop for the carrier layer etching process). In further embodiments, the intervening layer 210 has a composition that differs from the composition of the device layer 215, and the intervening layer 210 can be, for example, a metal, a semiconductor, or a dielectric material.

[0032] In some exemplary embodiments in which at least one of carrier layer 205 and device layer 215 is a crystalline semiconductor, intervening layer 210 is also a crystalline semiconductor layer. Intervening layer 210 may further have the same crystallinity and crystal orientation as carrier layer 205 and / or device layer 215. Such embodiments may have the advantage of reducing donor substrate costs relative to alternative embodiments in which intervening layer 210 is a material that requires the formation of an amorphous insulator or bonding (e.g., thermocompression bonding) of intervening layer 210 to device layer 215 and / or carrier layer 205.

[0033] For embodiments in which the intermediate layer 210 is a semiconductor, one or more of the primary semiconductor lattice elements, alloy composition, or impurity concentration may vary between at least the carrier layer 205 and the intermediate layer 210. In some embodiments in which at least the carrier layer 205 is a Group IV semiconductor, the intermediate layer 210 may be a Group IV semiconductor, but may be doped with a different Group IV element or alloy and / or impurity species to a different impurity level than the carrier layer 205. For example, the intermediate layer 210 may be a silicon-germanium alloy epitaxially grown on a silicon carrier. For such embodiments, the shadeomorphic intermediate layer may be heteroepitaxially grown to any thickness up to a critical thickness at which the intermediate layer becomes heteromorphic. Alternatively, the intermediate layer 210 may be a relaxed buffer layer having a thickness greater than the critical thickness.

[0034] In other embodiments, at least carrier layer 205 is a III-V semiconductor, and intermediate layer 210 may also be a III-V semiconductor, but may be doped with a different III-V alloy and / or impurity species to a different impurity level than carrier layer 205. For example, intermediate layer 210 may be an AlGaAs alloy epitaxially grown on a GaAs carrier. In some other embodiments in which both carrier layer 205 and device layer 215 are crystalline semiconductors, intermediate layer 210 may also be a crystalline semiconductor layer and further have the same crystallinity and crystal orientation as carrier layer 205 and / or device layer 215.

[0035] In embodiments in which both the carrier layer 205 and the intermediate layer 210 are the same or different from the primary semiconductor lattice elements, the impurity dopant may differentiate between the carrier and the intermediate layer. For example, the intermediate layer 210 and the carrier layer 205 may both be silicon crystals, with the intermediate layer 210 lacking impurities present in the carrier layer 205, or may be doped with impurities not present in the carrier layer 205, or may be doped to a different level than the impurities present in the carrier layer 205. The impurity differentiation may provide selective etching between the carrier and the intermediate layer, or may simply introduce a detectable species that can act as a marker upon which backside processing may be performed.

[0036] Intermediate layer 210 may be doped with electrically activated impurities (i.e., representing n-type or p-type semiconductors in intermediate layer 210), or otherwise provide an optional basis for detection 210 of the intermediate layer during subsequent carrier layer removal, e.g., as described in step 120. Exemplary electrically activated impurities for some semiconductor materials include group III elements (e.g., B), group IV elements (e.g., P). Any other elements may be used as non-electrically activated species. The concentration of impurity dopants in intermediate layer 210 need only vary from carrier layer 205 by a sufficient amount for detection, and may be predetermined depending on the detection technique and detector sensitivity.

[0037] Further, as described elsewhere herein, the intervening layer 210 may have a different composition than the device layer 215. In some such embodiments, the intervening layer 210 may have a bandgap that is different from the bandgap of the device layer 215. For example, the intervening layer 210 may have a wider bandgap than the device layer 215.

[0038] In embodiments in which the interposer layer 210 comprises a dielectric material, the dielectric material may be inorganic (e.g., SiO, SiN, SiON, SiOC, hydrogen silsesquioxane, methyl silsesquioxane) or organic (e.g., polyimide, polynorbornene, benzocyclobutene). For some dielectric embodiments, the interposer layer 210 may be formed as a buried layer (e.g., SiOx through implantation of oxygen into a silicon device and / or carrier layer). Other embodiments of the dielectric interposer layer may require bonding (e.g., thermocompression bonding) of the carrier layer 205 to the device layer 215. For example, if the donor substrate 201 is a semiconductor-on-oxide (SOI) substrate, either or both of the carrier layer 205 and the device layer 215 may be oxidized and bonded together to form the SiO interposer layer 210. Similar bonding techniques may be used for other inorganic or organic dielectric materials.

[0039] In some other embodiments, the intervening layer 210 includes two or more materials spaced laterally within the layer (i.e., the x-direction in FIG. 3A ). The two or more materials may include a dielectric and a semiconductor, a dielectric and a metal, a semiconductor and a metal, a dielectric and a semiconductor, two different dielectrics, two different semiconductors, or two different metals. Within such an intervening layer, a first material may surround islands of a second material that extend through the thickness of the intervening layer. For example, the intervening layer may include a field isolation dielectric that surrounds islands of semiconductor, which extend through the thickness of the intervening layer. The semiconductor may be epitaxially grown within openings in a patterned dielectric, or a dielectric material may be deposited within openings in a patterned semiconductor.

[0040] In some exemplary embodiments, semiconductor features, such as fins or mesas, are etched into the front surface of the semiconductor device layer. The trenches surrounding these features may later be backfilled with an isolation dielectric, for example, according to any known shallow trench isolation (STI) process. One or more of the semiconductor features or isolation dielectric may be used to terminate the backside carrier layer removal process, for example, as an etch stop for backside exposure. In some embodiments, exposure of the trench isolation dielectric may stop, significantly slow, or induce a detectable signal to terminate polishing of the backside carrier. For example, a CMP polish of a carrier semiconductor (e.g., Si) using a slurry with high selectivity favoring removal of the carrier semiconductor over removal of the isolation dielectric (e.g., SiO) may be significantly slowed once the (bottom) surface of the trench isolation dielectric surrounding the semiconductor features, including the device layer, is exposed. Because the device layer is disposed on the front side of the intervening layer, the device layer does not need to be directly exposed to the backside exposure process.

[0041] As another example, semiconductor islands may be grown from a crystalline carrier surface within pinholes that extend through the thickness of a dielectric layer disposed above the carrier layer. For such embodiments, the intervening layer is a composite of semiconductor islands embedded within the dielectric layer. Fabrication of the donor substrate may proceed using a crystalline carrier layer, e.g., silicon, another Group IV semiconductor, or an alternative. A dielectric layer (e.g., SiO) may be deposited above the carrier layer, masked, and etched to form a dense array of openings through the dielectric layer. Such openings may be trenches or pinholes. The critical dimension (CD) of such openings may be on the order of tens of nanometers to several microns. In some embodiments, the aspect ratio of the openings is sufficient (e.g., 4:1 or greater) to implement aspect ratio trapping (ART) for crystal pair defects in the semiconductor grown within the openings. A crystalline facet of the carrier layer is exposed within each of the openings. Heteroepitaxial or homoepitaxial growth from the exposed carrier surface backfills the array openings with crystalline semiconductor. In some exemplary embodiments, silicon is grown in an ART pattern on a non-silicon seed surface. In some other embodiments, III-V materials are grown in an ART pattern on a III-V or Group IV seed surface. In some other embodiments, III-N materials are grown in an ART pattern on a native or alloyed Group IV seed surface. In some further embodiments, lateral epitaxial overgrowth (LEO) of crystalline semiconductor is subsequently performed using any known technique to bridge the islands of crystalline semiconductor and form a continuous device layer 215 extending above the pinhole-like intermediate layer 210.

[0042] 4A, 4B, and 4C are isometric views further illustrating some exemplary embodiments in which a III-N semiconductor is grown as both part of the intervening layer 210 and as the device layer 215. In some such heteroepitaxial embodiments, the intervening layer semiconductor may be a III-N material (e.g., GaN) grown on a group IV (e.g., silicon) carrier layer. Each III-N epitaxial island may be relaxed with its hexagonal / wurtzite c-axis substantially perpendicular to the carrier growth plane. As shown in FIG. 4A, the donor substrate 201 includes a field isolation dielectric layer 480 (e.g., SiO) deposited above the carrier layer 205 (e.g., crystalline silicon). The semiconductor 410 is a III-N material (e.g., GaN) heteroepitaxial grown from the surface of the carrier layer 205, backfilling the opening in the field isolation dielectric layer 480. The LEO of the III-N semiconductor is further depicted in FIG. 4B. For additional information about epitaxial growth parameters that may be used in the growth process shown in Figures 4A-4C, the interested reader is referred to International Application No. PCT / USUS2014 / 56299 (U.S. Application No. 15504634), filed September 19, 2014, and commonly owned or assigned. As shown in Figure 4B, for a hexagonal crystal in the depicted orientation, crystal defects 440 slip laterally during lateral overgrowth, becoming more parallel to the III-N semiconductor c-plane as device layer 215 grows above field isolation dielectric layer 480. When III-N semiconductor islands are integrated, a contiguous III-N semiconductor device layer 215 is formed, as shown in Figure 4C. Additional material layers, such as polarization layers (not shown), can be grown as further components of device layer 215. The polarization layers can promote a 2D electron gas (2D EG) at material interfaces within device layer 215.

[0043] Advantageously, the donor substrate 201 shown in FIG. 4C can be fabricated without any bonding of a separate substrate and / or transfer of the device layer 215. The donor substrate 201 may be further processed according to any of the methods described elsewhere herein. In some III-N device layer embodiments, high electron mobility transistors (HEMTs) are fabricated in the III-N device layer 215. The carrier layer 205 and / or the intervening layer 210 may be removed from the device layer 215, for example, as described elsewhere herein. Advantageously, the pinned-down field isolation dielectric layer 480 may also provide an excellent etch stop during subsequent removal of the carrier layer 205. Following the etch stop, a backside exposure process may further remove the intervening layer 210 to expose the backside of the device layer 215.

[0044] The semiconductor material in the intervening layer, which includes both semiconductor and dielectric, may be heteroepitaxially grown III-V material. As used herein, heteroepitaxial growth refers to the growth of a crystal of one material composition from the surface of another crystal of another material composition. As an example, a III-V epitaxial device layer (e.g., InAlA, InGaA, etc.) may be grown through a pinhole-shaped dielectric disposed above a crystalline group IV (e.g., Si, Ge, SiGe) or group III-V (e.g., GaA) carrier layer. For some such embodiments, the donor substrate 201 may be substantially as shown in FIG. 4D , where the intervening layer 210 has a pinhole-shaped or trenched field isolation dielectric layer 480, and the semiconductor 410 is a III-V compound (e.g., InAlA) grown within the base of the pinholes and / or trenches. The device layer 215 is further grown above the semiconductor 410 within the top of the pinholes and / or trenches. In some exemplary embodiments, device layer 215 is a second III-V material (e.g., InGaAs) of a different alloy composition than the material grown as part of intervening layer 210. Subsequent processing may then form devices (e.g., transistors) in device layer 215. For example, as described elsewhere herein, device layer 215 may be fabricated into fins or other non-planar structures.

[0045] In particular, for embodiments in which the intervening layer includes both a semiconductor and a dielectric, the thickness of the intervening layer may be significantly greater than the critical thickness at which relaxation occurs as a result of lattice mismatch between the intervening layer and the carrier. On the other hand, an intervening layer below the critical thickness may be insufficiently thick to accommodate non-uniformities for wafer-level backside exposure processing, and embodiments with a larger thickness may be advantageous for increasing the backside exposure processing window. Embodiments with pinhole-like dielectrics may facilitate subsequent separation of the carrier layer from the device layer and improve crystalline quality within the device layer (e.g., within device layer 215).

[0046] The semiconductor material in the intervening layer, which includes both semiconductor and dielectric, may be homoepitaxial. As used herein, homoepitaxial growth refers to the growth of a crystal of one material composition from the surface of another crystal of the same material composition. In some exemplary embodiments, the silicon epitaxial device layer is grown through a pinhole dielectric disposed above a silicon carrier layer. For such embodiments, the donor substrate structure may be substantially as shown in FIG. 4D , where the pinhole dielectric may facilitate subsequent separation of the carrier layer and device layer.

[0047] The intervening layer, which includes both semiconductor and dielectric, may include semiconductor features, such as, but not limited to, silicon layers, etched into the front side of the carrier layer. These features, when surrounded by a dielectric material (e.g., STI), may have substantially the same architecture as homoepitaxial structures grown in pinhole dielectrics. For such embodiments, the donor substrate structure is similar to that shown in FIG. 4D , with the device layer 215 and the semiconductor in the intervening layer 210 being the same material as the carrier layer 205. In such embodiments, the dielectric material 480 may now facilitate subsequent separation of the carrier layer and device layer.

[0048] 2A and 3A, intervening layer 210 may be a metal. For such embodiments, the metal may be of any composition known to be suitable for bonding to carrier layer 205 or device layer 215. For example, either or both of carrier layer 205 and device layer 215 may be terminated with a metal, such as, but not limited to, Au or Pt, and subsequently bonded together to form, for example, Au or Pt intervening layer 210. Such a metal may be part of an intervening layer that further includes a patterned dielectric surrounding the metal structure.

[0049] The intermediate layer 210 may be of any thickness (e.g., height in the z-direction in FIG. 3A ). The intermediate layer 210 should be thick enough to ensure that the carrier removal process can be reliably completed before exposing the device region and / or device layer 215. Exemplary thicknesses of the intermediate layer 210 range from a few hundred nanometers to several micrometers. The thickness may vary depending on, for example, the amount of carrier material to be removed, the uniformity of the carrier removal process, and the choice of carrier removal process. For embodiments in which the intermediate layer 210 has the same crystallinity and crystal orientation as the carrier layer 205, the thickness of the carrier layer may be reduced by the thickness of the intermediate layer 210. In other words, the intermediate layer 210 may be on top of a 700-1000 μm thick group IV crystalline semiconductor substrate that is also used as the carrier layer 205. In shadeomorphic heteroepitaxial embodiments, the thickness of the intermediate layer may be limited to a critical thickness. For heteroepitaxial intervening layer embodiments using ART or another fully relaxed buffer architecture, intervening layer 210 may have any thickness.

[0050] As further shown in FIGS. 2B and 3B , for embodiments in which backside processing removes carrier substrate material over a significant portion of the wafer area (e.g., across the entire wafer), donor substrate 201 may first be bonded to host substrate 202 to form donor-host substrate assembly 203. In alternative embodiments in which backside processing down to submicron thicknesses is confined to a sufficiently small area (e.g., corresponding to a subset of transistors in an IC), such host substrate bonding may be avoided. However, in the illustrated embodiment, the front surface of donor substrate 201 is bonded to the surface of host substrate 202 such that device layer 215 is proximal to host substrate 202 and carrier layer 205 is distal from host substrate 202. Host substrate 202 may be any substrate known to be suitable for bonding to device layer 215 and / or the front side stack fabricated above device layer 215. In some embodiments, host substrate 202 includes one or more additional device layers. For example, host substrate 202 may further include one or more device layers (not shown). Host substrate 202 may include an integrated circuit to which IC devices fabricated in the device layers of host substrate 202 are interconnected, where bonding of device layer 215 to host substrate 202 may further involve forming a 3D interconnect structure through wafer-level bonding.

[0051] Although not illustrated in more detail in FIG. 3B , any number of front-side layers, such as interconnect metallization levels and interlayer dielectric (ILD) layers, may be present between the device layer 215 and the host substrate 202. The thicknesses of the host substrate 202 and the donor substrate 201 may vary from substantially the same thickness to being significantly thicker (e.g., 5-10x) than the others. For some embodiments, the host substrate 202 is many microns (e.g., 20-50 μm) thick and includes integrated circuits. In some embodiments, the donor substrate and the host substrate may be bonded back-to-face (e.g., the back surface of the host substrate 202 bonded to the front surface of the donor substrate 201). For such embodiments, the circuitry on the host substrate 201 may include TSVs that extend into the micron thickness of the host substrate. These TSVs may be bonded to features on the donor substrate 201 according to any known technique. In this manner, the host substrate 202, which is tens of microns thick, can function as a permanent feature of an IC having a greater thickness to bootstrap subsequent backside processing of the donor substrate 201, which is not constrained through the mechanical support provided by the host substrate 202. Alternatively, the donor substrate and host substrate may be bonded face-to-face. For such embodiments, the circuitry on the host substrate 201 need not include TSVs extending to the micron thickness of the host substrate. Rather, features on the front side of the donor substrate 201 may be bonded to features on the front side of the host substrate 202 according to any known technique. The host substrate 202, which is tens of microns thick, may now function to bootstrap subsequent backside processing of the donor substrate 201, which has a thickness free from minimum thickness limitations, due to the mechanical support provided by the host substrate 202. With the back side of the exposed host substrate 202, the host substrate 202 may be eventually thinned, for example, at the end of the manufacturing flow after the rigidity provided by the host substrate's thickness is no longer advantageous.

[0052] Any technique may be used to bond the host substrate 202 and the donor substrate 201. In some exemplary embodiments, further described elsewhere herein, the bonding of the donor substrate 201 to the host substrate 202 is through metal-metal, oxide-oxide, or hybrid (metal / oxide-metal / oxide) thermocompression bonding. Such permanent bonding techniques are advantageous in that they can provide high rigidity.

[0053] For host substrate 202 facing device layer 215 on the side opposite carrier layer 205, at least a portion of carrier layer 205 can be removed, as further shown in FIGS. 2C and 3C. If the entire carrier layer 205 is removed, donor-host substrate assembly 203 maintains a high, uniform thickness with planar backside and frontside surfaces. Alternatively, carrier layer 205 and intervening layer 210 can be selectively removed (e.g., masked carrier layer 205 and exposed or removed intervening layer 210 in only unmasked subregions) to form a non-planar backside surface. In the exemplary embodiment shown in FIGS. 2C and 3C, carrier layer 205 is removed from the entire backside surface of donor-host substrate assembly 203. The carrier layer 205 may be removed, for example, by cleaving, grinding and / or polishing (e.g., chemical mechanical polishing), and / or wet chemical etching and / or plasma etching through the thickness of the carrier layer to expose the intervening layer 210. One or more processes may be used to remove the carrier layer 205. Advantageously, the removal process may be terminated based on a duration or endpoint signal that is influenced by the exposure of the intervening layer 210.

[0054] In further embodiments, such as those illustrated by FIGS. 2D and 3D , intervening layer 210 may be at least partially etched to expose the backside of device layer 215. At least a portion of intervening layer 210 may be removed following its use as an etch stop for the carrier layer and / or an etch endpoint trigger for the carrier layer. If the entire intervening layer 210 is removed (e.g., using highly selective CMP), donor-host substrate assembly 203 maintains a high and uniform device layer thickness with planar backside and frontside surfaces provided by the intervening layer, which is significantly thinner than the carrier layer. Alternatively, intervening layer 210 may be masked, exposing only unmasked subregions of device layer 215, thereby forming a non-planar backside surface. In the exemplary embodiment illustrated by FIGS. 2D and 3D , intervening layer 210 is removed from the entire backside surface of donor-host substrate assembly 203. The intervening layer 210 may be removed, for example, by polishing (e.g., chemical mechanical polishing) through the thickness of the intervening layer and / or by blanket wet chemical etching and / or blanket plasma etching to expose the device layer 215. One or more processes may be used to remove the intervening layer 210. Advantageously, the removal process may be terminated based on a duration or endpoint signal affected to expose the device layer 215.

[0055] In some further embodiments, for example, as shown by FIGS. 2E and 3E , the device layer 215 is partially etched from the front-side processing to expose the backside of previously formed device structures. At least a portion of the device layer 215 can be removed after its fabrication in one or more of the device semiconductor regions and / or its use as an etch stop or endpoint trigger for intervening layers. If the device layer 215 is thinned across the entire substrate area, the donor-host substrate assembly 203 maintains a high and uniform reduced thickness on both the planar backside and frontside. Alternatively, the device layer 215 can be masked, with the device structures (e.g., device semiconductor regions) selectively exposed only in the unmasked subregions, thereby forming a non-planar backside surface. Some such embodiments are described further below. However, in the exemplary embodiment shown by FIGS. 2E and 3E , the device layer 215 is thinned across the entire backside surface of the donor-host substrate assembly 203. The device layer 215 may be thinned by, for example, polishing (e.g., chemical-mechanical polishing), and / or wet chemical etching, and / or plasma etching through the thickness of the device layer to expose one or more device semiconductor regions and / or one or more other device structures previously formed during front-side processing of the device layer 215 (e.g., contact metallization for front-side device terminals, spacer dielectric for gate electrodes, etc.). One or more processes may be used to thin the device layer 215. Advantageously, thinning the device layer may be terminated based on a duration or endpoint signal responsive to exposure of patterned features within the device layer 215. For example, if front-side processing forms device isolation features (e.g., shallow trench isolation), thinning the backside of the device layer 215 may be terminated upon exposure of the isolation dielectric material.

[0056] A non-native material layer may be deposited over the backside surfaces of intervening layers, device layers, and / or specific device regions within device layer 215, and / or over more other device structures (e.g., contact metallization for front-side device terminals, spacer dielectrics, etc.). One or more materials exposed from the backside may be covered or replaced with a non-native material layer. In some embodiments illustrated by FIGS. 2F and 3F, non-native material layer 220 is deposited over device layer 215. Non-native material layer 220 may be any material having a different composition and / or microstructure than the material removed to expose the backside of the device hierarchy. For example, if intervening layer 210 is removed to expose device layer 215, non-native material layer 220 may be another semiconductor of a different composition or microstructure than intervening layer 210. In some such embodiments in which device layer 215 is a III-N semiconductor, non-native material layer 220 may be a III-N semiconductor of the same or different composition regrown on the exposed backside surface of the III-N device region. This material may be epitaxially regrown from the exposed III-N device region, for example, to have better crystalline quality than that of the material being removed, and / or to induce strain in the device layer and / or device regions within the device layer, and / or to form a vertical (e.g., z-dimension) stack of device regions suitable for fabricating stacked (multilayer) devices.

[0057] In some other embodiments in which device layer 215 is a III-V semiconductor, non-native material layer 220 may be a III-V semiconductor of the same or different composition that is regrown on the exposed backside surface of the III-V device region. This material may be epitaxially regrown from the exposed III-V device region, for example, to have relatively better crystalline quality than that of the material being removed, and / or to induce strain in the device layer or specific device regions within the device layer, and / or to form a vertical stack of device semiconductor regions suitable for stacked (multilayer) devices.

[0058] In some other embodiments in which device layer 215 is a group IV semiconductor, non-native material layer 220 may be a group IV semiconductor of the same or different composition that is regrown on the exposed backside surface of the group IV device region. This material may be epitaxially regrown from the exposed group IV device region, for example, to have relatively better crystalline quality than that of the removed material, and / or to induce strain in the device region, and / or to form a stack of device semiconductor regions suitable for stacked (multilayer) devices.

[0059] In some other embodiments, non-native material layer 220 is a dielectric material such as, for example, but not limited to, SiO, SiON, SiOC, hydrogen silsesquioxane, methyl silsesquioxane, polyimide, polynorbornene, or benzocyclobutene. Such a dielectric deposition may serve to electrically isolate various device structures, e.g., semiconductor device regions, that may have been previously formed during front-side processing of donor substrate 201. Such a dielectric material layer may be the first layer of a back-side material stack that further includes an interconnect metallization layer or level.

[0060] In some other embodiments, non-native material layer 220 is a conductive material, such as any elemental metal or metal alloy known to be suitable for contacting one or more surfaces of device regions exposed from the backside. In some embodiments, non-native material layer 220 is a metallization suitable for contacting device regions exposed from the backside, such as the source / drain (i.e., source or drain) regions of a transistor.

[0061] In some embodiments, non-native material layer 220 is a stack of materials, such as a FET gate stack including both an F gate dielectric layer and a gate electrode layer. As an example, non-native material layer 220 may be a gate stack suitable for contacting a semiconductor device region exposed from the backside, such as a transistor channel region. Any of the other materials described as options for device layer 215 may be deposited over the backside of device layer 215. For example, non-native material layer 220 may be any of the oxide semiconductors, TMDCs, or tunneling materials described above, and may be deposited on the backside, e.g., to progressively fabricate vertically stacked device layers.

[0062] Backside wafer-level processing may continue in any manner known to be suitable for frontside processing. For example, non-native material layer 220 may be patterned into active device regions, device isolation regions, device contact metallization, or device interconnects using any known lithography and etching techniques. Backside wafer-level processing may further fabricate one or more interconnect metallization levels that couple the terminals of different devices to the IC. Additionally, in some embodiments described elsewhere herein, backside processing may be used to interconnect power buses to various device terminals within the IC.

[0063] In some embodiments, backside processing includes bonding to a secondary host substrate. Such bonding may use any layer transfer process to bond the backside (e.g., non-native) material layer to another substrate. Following such bonding, the original host substrate may be removed as a sacrificial donor to re-expose the front side of the front-side stack and / or device layers. Such embodiments may enable repeated side-by-side stacking of device hierarchies with the first device layer serving as the core of the assembly. In some embodiments shown in FIGS. 2G and 3G, the secondary host substrate 240 bonded to the non-native material layer 220 provides at least mechanical support while the host substrate 202 is removed.

[0064] Any bonding method, such as, but not limited to, thermocompression bonding or a similar sintering process, may be used to bond the secondary host substrate 240 to the non-native material layer 220. In some embodiments, both the surface layer of the secondary host substrate 240 and the non-native material layer 220 are continuous dielectric layers (e.g., SiO) that are thermocompression bonded. In some other embodiments, both the surface layer of the secondary host substrate 240 and the non-native material layer 220 have metal layers (e.g., Au, Pt, etc.) that are thermocompression bonded. In other embodiments, at least one of the surface layer of the secondary host substrate 240 and the non-native material layer 220 is patterned, the patterning including both patterned metal surfaces (i.e., traces) and surrounding dielectric (e.g., isolation), and thermocompression bonded to form a hybrid (e.g., metal / oxide) bond. For such embodiments, structural features in the secondary host substrate 240 and the patterned non-native material layer 220 may be aligned (e.g., optically) during the bonding process. In some embodiments, non-native material layer 220 includes one or more conductive backside traces that are coupled to terminals of transistors fabricated in device layer 215. The conductive backside traces may be bonded to metallization on secondary host substrate 240, for example.

[0065] In an alternative embodiment, a secondary donor substrate is bonded to the non-native material layer 220. The assembly shown in FIG. 3G is also applicable to such an embodiment. However, the host substrate 202 is not removed until at least backside processing of the secondary donor substrate is complete, e.g., in substantially the same manner as described above for the donor substrate 201. In this manner, any number of donor substrates can be stacked and thinned, depending on the support provided by the host substrate 202. After such support is no longer needed, the host substrate 202 may be thinned (e.g., if the host substrate 202 was bonded face-to-face with the donor substrate 201).

[0066] Bonding of the device layer to the host (or secondary donor) substrate may proceed from the front side and / or back side of the device layer before or after front-side processing of the device layer is complete. The bonding process may be performed after front-side fabrication of the devices (e.g., transistors) on the donor substrate is substantially complete. Alternatively, bonding of the host (or secondary donor) substrate may be performed before completing front-side fabrication of the devices (e.g., transistors) on the donor substrate, in which case the front side of the device layer on the donor substrate may undergo additional processing after back-side bonding to the host (or secondary donor) substrate. For example, as further shown in Figures 2H and 3H, front-side processing includes removal of the host substrate 202 to re-expose the front side of the device layer 215. At this point, the donor-host substrate assembly 203 includes the secondary host substrate 240 bonded to the device layer 215 through the non-native material layer 220.

[0067] FIG. 3I shows an expanded view of device layer 215 further illustrating front-side and back-side metallization, according to some embodiments. In FIG. 3I, the host substrate is not shown and may be removed, for example, during device packaging processing. Device layer 215 includes multiple semiconductor bodies 310 surrounded by isolation dielectric 480. Each of semiconductor bodies 310 may be, for example, a component of one or more FinFETs. Front-side interconnect metallization 333 includes multiple interconnect metallization levels 320 embedded within an interlayer dielectric (ILD). Back-side interconnect metallization 334 includes multiple interconnect metallization levels 321 embedded within an interlayer dielectric (ILD). Front-side interconnect metallization 333 and back-side interconnect metallization 334 may have different material compositions and / or dimensions, for example, as described further below. Each of the interconnect metallizations 333 and 334 may have any number of levels, with higher levels typically having relaxed dimensions from these lower levels. When fully interconnected with both the front-side interconnect metallization 333 and the back-side interconnect metallization 334, the device layer 215 is a single IC layer 350. An IC layer may include only one or both front-side and back-side interconnect metallizations. The single IC layer may be packaged according to any suitable technique. Alternatively, as described above, the IC layer may be bonded to a secondary host or donor substrate containing another device layer.

[0068] FIG. 3J further illustrates multiple IC layers 350 bonded to a 3D IC 360 according to some embodiments. Each IC layer 350 includes a device layer 215 and has, for example, any of the characteristics described elsewhere herein. As shown, the 3D IC 360 lacks any of the thickness overhead associated with bulk crystalline substrate materials. Absent such materials, the 3D IC 360 does not have micron-thick TSV structures. Rather, the IC layers 350 are bonded to one another through bonds 390, which may be any suitable bonding technique, such as, but not limited to, thermal compression bonding or solder bonding. The bonds 390 are between two interconnect metallization layers of sufficient shape to achieve proper alignment between the interconnect metallization features of the separate IC layers. Any number of IC layers 350 may be bonded, for example, according to one or more of the techniques described herein. In some embodiments, pairs of IC layers are bonded face-to-face (front-to-face). In some embodiments, pairs of IC layers are bonded back-to-back (back-to-back). In some embodiments, pairs of IC layers are bonded face-to-face (front-to-back), with the distinction between front and back being implementation dependent. In some embodiments having at least four IC layers, a first (inner) pair of IC layers are bonded face-to-face, while each member of the first pair is bonded back-to-back with a respective one of a second (outer) pair of IC layers.

[0069] FIG. 5 is a flow diagram 501 illustrating a backside exposure method according to some embodiments. Method 501 may be used, for example, to remove at least a portion of the carrier layer and intervening layers of a donor-host substrate assembly, such as part of step 120 (FIG. 1) and as shown in FIGS. 2C-2E and 3C-3E. Method 501 begins with input of a donor-host substrate assembly in step 505. In some embodiments, the donor-host substrate assembly received in step 505 is donor-host substrate assembly 203, as shown in FIG. 3B. In step 510, the thickness of the carrier layer within the donor host substrate is etched away through polishing (e.g., CMP) and / or wet or dry (e.g., plasma) etching processes. Any grinding, polishing, and / or masked or unmasked wet / dry etching processes known to be suitable for the carrier layer composition may be used in step 510. For example, if the carrier layer is a Group IV semiconductor (e.g., silicon), a CMP slurry known to be suitable for thinning semiconductors may be used in step 510. As another example, any wet etchant or plasma etching process known to be suitable for etching features into Group IV semiconductors may be used in step 510.

[0070] In some embodiments, step 510 proceeds by cleaving the carrier layer along a fracture plane substantially parallel to the intervening layer. The cleaving or fracture process may be utilized to remove a significant portion of the carrier layer as a bulk mass, reducing the polishing or etching time required to remove the carrier layer. For example, if the carrier layer is 400-900 μm thick, 100-700 μm may be removed. Any blanket implant known to promote wafer-level fracture may be used in step 510. In some exemplary embodiments, a light element (e.g., H, He, or Li) is implanted to a uniform target depth within the carrier layer where the fracture plane is desired. Following such a cleaving process, the thickness of the carrier layer remaining in the donor-host substrate assembly may then be polished or etched to complete the removal. Alternatively, if the carrier layer is not fractured, ground, polished, and / or etched, step 510 may be utilized to remove a greater thickness of the carrier layer.

[0071] In step 515, exposure of the intervening layer is detected. Detection step 515 identifies when the backside surface of the donor substrate progresses to the intervening layer prior to exposure of the device layer. Any endpoint detection technique known to be suitable for detecting the transition between the materials used in the carrier layer and the intervening layer may be performed in step 515. In some embodiments, one or more endpoint criteria are based on detecting a change in the light absorption or emission of the backside surface of the donor substrate during the polishing and / or etching of step 510. In some other embodiments, the endpoint criteria are related to a change in the light absorption or emission of by-products during the polishing or etching of the backside surface of the donor substrate. For example, the absorption or emission wavelengths associated with by-products during the etching of the carrier layer may change due to different compositions of the carrier layer and the intervening layer. In other embodiments, the endpoint criterion is related to a change in the mass of species in by-products during the polishing or etching of the backside surface of the donor substrate. For example, the by-products of step 510 may be sampled through a quadrupole mass analyzer, and changes in the mass of the species may be correlated to different compositions of the carrier layer and the intervening layer. In another exemplary embodiment, the endpoint criterion is associated with a change in the spallation between the backside surface of the donor substrate and the polishing surface in contact with the backside surface of the donor substrate.

[0072] Detection of the intervening layer is enhanced if the removal process is selective to the carrier layer relative to the intervening layer, since non-uniformities in the carrier removal process can be mitigated by the difference in etch rates between the carrier layer and the intervening layer. Furthermore, if the grinding, polishing, and / or etching step 510 removes the intervening layer at a rate significantly slower than the rate at which the carrier layer is removed, the detection step 515 is omitted. If no endpoint criteria are used in step 515, the grinding, polishing, and / or etching step 510 of a predetermined fixed duration may be stopped at the intervening layer material if the thickness of the intervening layer is sufficient for selective etching. In some examples where the carrier is a semiconductor and the intervening layer is a dielectric, the ratio of the carrier etch rate to the intervening layer etch rate may be 3:1 to 10:1 or greater. The CMP process used in step 510 may use a slurry that provides, for example, very high selectivity (e.g., 100:1 to 300:1 or greater) between the semiconductor (e.g., silicon) and the dielectric material (e.g., SiO) that surrounds the device layers and is embedded within intervening layers, such as, for example, electrical isolation between adjacent device regions.

[0073] Upon exposing the intervening layer, at least a portion of the intervening layer may be removed in step 520. For example, one or more component layers of the intervening layer may be removed. However, step 520 is optional. The thickness of the intervening layer may be uniformly removed, for example, by polishing. Alternatively, the thickness of the intervening layer may be removed using a masked or blanket etch process. Step 520 may use the same polishing or etch process used to thin the carrier in step 515, or may be a separate process with separate process parameters. For example, the intervening layer may provide an etch stop for the carrier removal process, and step 520 may use a different polishing or etch process that is convenient for removing the intervening layer over removing the device layers. When a thickness of the intervening layer less than a few hundred nanometers is removed, the removal process may be relatively slow, optimized, and more precisely controlled for uniformity across the wafer than if used for removing the carrier layer. The CMP process used in step 520 may use a slurry that provides, for example, very high selectivity (e.g., 100:1 to 300:1 or greater) between the semiconductor (e.g., silicon) and the dielectric material (e.g., SiO) that surrounds the device layers and is embedded within intervening layers, such as, for example, electrical isolation between adjacent device regions.

[0074] For embodiments in which the device layer is exposed through the completion of removal of the intervening layer, backside processing may begin on the exposed backside of the device layer or specific device regions within the device layer. In some embodiments, backside device layer processing includes further polishing or wet / dry etching through the thickness of the device layer, for example, the device layer disposed between the previously fabricated intervening layer and the device regions in the source / drain regions.

[0075] In some embodiments where the backside of the carrier layer, intervening layer, or device layer is recessed by wet and / or plasma etching, such etching may be a patterning etch or a materially selective etch that imparts significant non-planarity or topography to the backside surface of the device layer. As further described elsewhere herein, the patterning may be within a single device structure (i.e., "intra-cell" patterning) or may span multiple (e.g., all) device cells (i.e., "inter-cell" patterning). In some patterning etch embodiments, at least a partial thickness of the intervening layer is used as a hard mask for patterning the backside device layer. Thus, the mask etch in step 520 may precede the etch of the correspondingly masked device layer.

[0076] The output of method 501 is a donor-host substrate assembly including an IC device with front-side metallization exposed on the backside of an intervening layer, the backside of a device layer, and / or the backside of one or more semiconductor regions within the device layer, and / or where the front-side metallization was deposited over a topography formed in or through the device layer. Additional backside processing of any of these exposed regions can then be performed downstream of method 501. In some exemplary embodiments, backside processing performed downstream of method 501 includes, for example, deposition of a non-native material over the exposed regions, as further described elsewhere herein.

[0077] FIG. 6 is a plan view of donor substrate 201 with a close-up view of IC die 211 and a further close-up view of logic transistor structures 604 disposed within IC die 211, according to some embodiments. As described above, donor substrate 201 may be input to method 101 (FIG. 1), for example. With further reference to FIG. 6, a plurality of logic transistor structures 604 are arranged across an area of ​​a device layer within IC die 211. Additional device cells 602 may be, for example, memory cells, power transistor structures, RF transistor structures, or photonic device cells. Transistor structures 604 include field-effect FETs having source, drain, and gate terminals, according to some illustrative embodiments. In some embodiments, the source and drain terminals include semiconductors having the same conductivity type. In other embodiments, the source and drain terminals include semiconductors having complementary conductivity types (i.e., tunnel FETs or TFETs). FETs may include heterojunctions (i.e., HFETs), which may be considered high electron mobility transistors (HEMTs) if the channel includes III-V or III-N materials. In Figure 6, solid lines within transistor structure 604 indicate protruding material formed over other material or structural features shown as dashed lines within the transistor structure hierarchy. Thick dashed-dotted lines within Figure 6 indicate planes A-A', B-B', and C-C' along cross-sectional views, which are further provided as Figures 8A, 8B, 8C, 9A, 9B, 9C, and 11A, 11B, 11C, with letters in the figure numbers corresponding to the cross-sectional views designated by the same letters.

[0078] As further shown in FIG. 6 , the transistor structure 604 is supported by a backside substrate 605 having a semiconductor body 610 embedded in a frontside field isolation dielectric material 680. In some embodiments, the backside substrate 605 includes a carrier layer (e.g., carrier layer 205 of FIG. 3A ). In some embodiments, an intervening layer (not shown) separates the backside substrate 605 from the transistor structure 604. In some other embodiments, the backside substrate 605 includes both a carrier layer (e.g., carrier layer 205 of FIG. 3A ) and an intervening layer (e.g., intervening layer 210 of FIG. 3A ). In one example, the transistor structure 604 is fabricated on a donor substrate 201 ( FIG. 3A ). In particular embodiments, the transistor cell 604 includes a non-planar FET, such as a FinFET, Tri-gate, or omega-gate. Further referring to FIG. 6 , the transistor structure 604 includes a gate electrode 673 strapping across each channel region of the first and second semiconductor bodies 610. Although two semiconductor bodies 610 are shown in FIG. 6 , a non-planar FET may include one or more such semiconductor bodies. In some exemplary embodiments, semiconductor body 610 includes at least one semiconductor region originating from a device layer of donor substrate 201. For example, a transistor channel region in semiconductor body 610 may be derived from semiconductor device layer 215 of FIG. 3A . As such, semiconductor body 610 may include one or more semiconductor regions having any of the compositions described above for a device layer of a donor substrate suitable for a field-effect transistor (e.g., device layer 215 shown in FIG. 3A ). Example materials include, but are not limited to, Group IV semiconductors (e.g., Si, Ge, SiGe), Group III-V semiconductors (e.g., GaAs, InGaAs, InAs, InP), Group III-N semiconductors (e.g., GaN, AlGaN, InGaN), oxide semiconductors, TMDCs, graphene, etc. In some advantageous embodiments, semiconductor body 610 is single crystalline.

[0079] 6, source / drain metallization 650 is disposed adjacent to gate electrode 673 and extends across semiconductor body 610. In the illustrated embodiment, source / drain metallization 650 is disposed on regrown or raised source / drain semiconductor 640 and in contact with semiconductor body 610. Source / drain semiconductor 640 may be doped with electrically active impurities to impart n-type or p-type conductivity. For some exemplary embodiments, both source and drain semiconductors 640 are doped to the same conductivity type (e.g., n-type for NMOS and p-type for PMOS). In alternative embodiments (e.g., tunneling FETs), source and drain semiconductors 640 are doped to have complementary conductivity types (e.g., n-type source and p-type drain). The source / drain semiconductor 640 may be any semiconductor material compatible with the semiconductor body 610, such as, but not limited to, a Group IV semiconductor (e.g., Si, Ge, SiGe), and / or a Group III-V semiconductor (e.g., InGaAs, InA), and / or a Group III-N semiconductor (e.g., InGaN), and / or a (metal) oxide semiconductor.

[0080] An electrically insulating spacer dielectric 671 laterally separates the gate electrode 673 from the source / drain metallization 650 and / or the source / drain semiconductor 640. The source / drain metallization 650 may include one or more metals (e.g., Ti, W, Pt, alloys and nitrides thereof) that form ohmic or tunneling junctions with the doped source / drain semiconductor 640. The spacer dielectric 671 may be a dielectric or any dielectric material, such as, but not limited to, silicon dioxide, silicon nitride, or silicon oxynitride, or any known low-k material having a dielectric constant of 4.0 or less. Only one gate electrode 673 is shown in solid lines as part of a single logic transistor structure, while an exemplary second gate electrode 673 is depicted in dashed lines to indicate its association with an adjacent transistor structure. The second gate electrode is also laterally separated from the metallization 650 and / or the source / drain semiconductor 640 by the spacer dielectric 671.

[0081] FIG. 7 is a flow diagram 701 illustrating a method for backside isolation of a transistor according to some embodiments. Method 701 further illustrates the formation of layers of transistor structures that may be only a few hundred nanometers thick. Method 701 also shows how the techniques introduced above in the context of FIGS. 1-5 can be applied to provide backside isolation structures for device layers. As described elsewhere herein, such layers are suitable for vertical stacking into 3D ICs with potentially very high vertical cell densities (e.g., high number of layers / micrometer thickness). Method 701 can improve the electrical isolation of transistors, for example, by reducing through-substrate leakage between adjacent devices. Method 701 begins with a donor substrate containing a transistor structure using the device layer of the donor substrate at input 705. The transistor structure may be fully operational, as fabricated from the front side, including, for example, three terminals, as shown in FIG. 6. Alternatively, one or more terminals may be absent, such that the transistor structure is not operational until backside processing is complete. The donor substrate may include one or more of the features described above, such as, but not limited to, an intervening layer and a carrier layer. However, the carrier layer and / or the intervening layer are not required to perform method 701. In step 710, a donor-host substrate assembly is formed, for example, as described elsewhere herein (e.g., method 101 below). In step 715, the backside of the transistor structure is exposed by removing at least a portion of the donor substrate to form a transistor layer-host substrate assembly. An isolation dielectric may then be deposited over the exposed backside surface, which in an exemplary embodiment is a semiconductor or metal surface. In step 720, the backside isolated transistor layer-host substrate assembly is output from method 701 and is ready for further processing, for example, a subsequent iteration of method 101 (FIG. 1) below.

[0082] 8A, 9A, 10A, and 11A illustrate cross-sectional views of transistor structure 604 along the A-A' plane shown in FIG. 6 when steps in method 701 are performed, according to some embodiments. FIGS. 8B, 9B, 10B, and 11B illustrate cross-sectional views of transistor structure 604 along the B-B' plane shown in FIG. 6 when steps in method 701 are performed, according to some embodiments. FIGS. 8C, 9C, 10C, and 11C illustrate cross-sectional views of transistor structure 604 along the C-C' plane shown in FIG. 6 when steps in method 701 are performed, according to some embodiments. Notably, while transistor structure 604 illustrates a non-planar transistor structure with gate electrodes coupled to multiple sides of a semiconductor body, method 701 may be applied in a similar manner to planar transistor structures.

[0083] 8A-8C show the structure present in an exemplary transistor structure after front-side processing of the donor substrate. The semiconductor body 610 has a fin height H f The semiconductor body 610 has a fin structure that extends in the vertical direction (e.g., z dimension) by a channel height H c In some exemplary embodiments, the channel height H includes the device layer 215. In the embodiment shown in FIGS. 8A-8C, the semiconductor body 610 has a sub-fin height H that also includes the device layer 215. sfThe semiconductor fin body 610 further includes a sub-fin portion having a thickness of 100 Å. The transistor semiconductor body 610 may be formed, for example, using a patterned front-side recess etch of the device layer 215. As further described elsewhere herein, the semiconductor fin body may alternatively include a sub-fin semiconductor of a different composition than the channel portion, where the sub-fin semiconductor may be a component of the intervening layer 210 ( FIG. 3A ), while the device layer 215 may be only the channel portion. Alternatively, the sub-fin semiconductor may account for a spacer between the device layer 215 and the backside substrate 605 and may further include an intervening layer between the sub-fin semiconductor and a carrier layer. Surrounding one or more sidewalls of the semiconductor body 610 is a field isolation dielectric 680. The field isolation dielectric 680 may be one or more materials suitable for providing electrical isolation between laterally adjacent transistors (e.g., in the x or y dimensions). In some exemplary embodiments, the field isolation dielectric 680 comprises silicon dioxide. Other materials are possible, such as, but not limited to, SiN, SiON, SiOC, polyimide, HSQ, or MSQ. In some embodiments, field isolation dielectric 680 and the sub-fin portion of semiconductor body 610 create an intervening layer where the carrier removal process is stopped.

[0084] 8A and 8B, a gate stack including a gate electrode 673 disposed above a gate dielectric 845 that intersects with the channel portion of the transistor semiconductor body 610. The intersection of the source / drain metallization with the source / drain semiconductor 640 is further shown in FIG. 8C. The channel portion of the semiconductor body is coupled to the gate stack and has sidewalls with a height H c and the side wall height H c is the height H of the sub-fin in the z-direction sfWhile any gate stack material known to be suitable for semiconductor body 610 may be utilized, in some exemplary embodiments, the gate stack includes a high-k dielectric material (having a bulk dielectric constant greater than 9) and a metal gate electrode having a work function suitable for semiconductor body 610. Exemplary high-k materials include metal oxides, such as, but not limited to, Al2O3, HfO2, HfAlO x Silicates, such as, but not limited to, HfSiO x or TaSiO x may be suitable for some semiconductor body compositions (e.g., Si, Ge, SiGe, III-V). Gate electrode 673 may be advantageous in having a work function of 5 eV or less and may include an elemental metal layer, a metal alloy layer, or a stack of either or both. In some embodiments, the gate electrode is a metal nitride, such as TiN (e.g., 4.0-4.7 eV). The gate electrode may also be Al (e.g., TiAlN). Other alloying elements may be used in gate electrode 673, such as, but not limited to, C, Ta, W, Pt, and Sn.

[0085] 8A-8C further show a front side stack 690 disposed above the front side surface. The front side stack 690 is shown in dashed lines as part of a hierarchy of transistor structures that may vary without limitation and may include, for example, any number of back-end interconnect metallization levels. Such levels may be separated from the semiconductor body 610 and / or from each other by one or more interlevel dielectric (ILD) layers. A back side substrate 605, which may further include intervening layers and / or carrier layers, is disposed above the back side surface.

[0086] 9A-9C show transistor structure 604 after bonding of the donor substrate to host substrate 202. Host substrate 202 may have any of the properties described elsewhere herein. As shown, host substrate 202 is bonded to the front surface of front stack 690, for example, by thermocompression bonding. As further shown in FIGS. 9A-9C, back substrate 605 has been removed, exposing back surface 911 of interposer layer 210. Back substrate 605 may be removed by any technique, such as, but not limited to, method 501 (FIG. 5). A marker or etch stop may be present in interposer layer 210, for example, at the end of the carrier removal step, prior to exposing the backside of field isolation dielectric 680.

[0087] 10A-10C show transistor structure 604 after exposure of backside 1012 of semiconductor body 610. To expose the backside of transistor semiconductor body 610, the portion of the bulk semiconductor to which transistor semiconductor body 610 was anchored may be recess-etched using, for example, polishing and / or wet and / or dry etching processes, as described above for step 520 (FIG. 5). In some exemplary embodiments in which a highly selective (e.g., 200-300:1) CMP slurry is used that has a higher etch rate of device layer semiconductor (e.g., Si) over dielectric (e.g., SiO), the backside polish of intervening layer 210 may be stopped upon exposing field isolation dielectric 680. Any amount of overetch (overpolish) may further thin the sub-fin portion of semiconductor body 610 and the intervening layer with adjacent field isolation dielectric 680, thereby increasing the sub-fin height H. sf In some embodiments, the entire sub-fin for one or more semiconductor bodies in the transistor structure may be removed during the backside exposure step.

[0088] 11A-11C show the transistor structure 604 after depositing a backside isolation dielectric 1120 over the exposed backside of the transistor semiconductor body 610. The backside isolation dielectric 1120 is an example of a non-native material that replaces a portion of an intervening layer that was removed to expose the transistor semiconductor region. The backside isolation dielectric 1120 may be any dielectric material suitable for electrical isolation of the transistor. In some exemplary embodiments, the backside isolation dielectric 1120 is silicon dioxide. However, notably, because the backside isolation dielectric 1120 is deposited after backside exposure rather than pre-integrated into the donor substrate, a wider selection of materials is possible than, for example, SOI substrates where an insulator layer is provided upstream as a buried layer in the substrate. Accordingly, in some advantageous embodiments, the backside isolation dielectric 1120 has a low dielectric constant (e.g., as measured on the material in its bulk state). Such materials often cannot withstand the high temperature processes associated with many frontside fabrication processes (e.g., source / drain formation). The backside isolation dielectric 1120 may be a low-k dielectric material, such as any of those known to be suitable as a front-side ILD in a back-end interconnect stack. In some embodiments, the backside isolation dielectric 1120 has a dielectric constant no greater than, and more preferably less than, the field isolation dielectric 680. In some embodiments, the backside isolation dielectric 1120 has a dielectric constant less than 3.9, more preferably less than 3.5. In some embodiments, the backside isolation dielectric 1120 has the same composition as one or more ILD layers in the front-side stack 690. Exemplary backside isolation dielectric materials include SiOC, SiOCH, HSQ, or MSQ. Other low-k dielectrics are possible. Similarly, other dielectric materials with a dielectric constant greater than 3.9 (e.g., SiN, SiON) are also possible.

[0089] 11D-11F show the transistor structure 604 after replacing at least a portion of the semiconductor body 610 with a backside isolation dielectric 1120. FIG. 11D provides a view of the transistor structure 604 along the A-A' plane shown in FIG. 6, according to some embodiments. FIG. 11E shows a cross-sectional view of the transistor structure 604 along the B-B' plane shown in FIG. 6, and FIG. 11F shows a cross-sectional view of the transistor structure 604 along the B-B' plane shown in FIG. 6. In some exemplary embodiments, the sub-fin portion of the semiconductor body 610 is etched from the backside using, for example, any etch process selective to the sub-fin semiconductor above the field isolation 680. The recess in the backside sub-fin may or may not expose the backside of the device layer 215 (e.g., including the channel semiconductor). The backside isolation dielectric 1120 is then backfilled into the resulting recess. In an alternative embodiment, a portion of the intervening layer below the device layer is converted to an isolation dielectric. For example, a sub-fin portion of semiconductor body 610 may be converted to backside isolation dielectric 1120. In some advantageous embodiments, at least a partial thickness of semiconductor body 610 (e.g., silicon) below device layer 215 is converted to SiC using any known thermal and / or wet chemical and / or plasma etchant chemical oxidation process to form backside isolation dielectric 1120.

[0090] FIG. 12 is a flow diagram 1201 illustrating a method for forming backside transistor source / drain contact metallization according to some embodiments. Method 1201 further illustrates the formation of a layered transistor structure that may be only a few hundred nanometers thick. Method 1201 begins with a donor-host substrate assembly including a transistor structure as input 1205. The donor substrate may have one or more of the features described above, such as, but not limited to, an intervening layer and a carrier layer. However, the carrier layer and / or the intervening layer are not required to perform method 1201. At the input of method 1201, the transistor structure may be fully operational, including, for example, three terminals, as shown in FIG. 6. Alternatively, one or more terminals may be absent such that the transistor structure is not operational until backside processing is complete.

[0091] FIG. 13 is a plan view of a transistor structure 1304 lacking some source / drain metallization 650. The thick dashed dotted lines indicate the planes further provided as FIGS. 14A-14C, 15A-15C, and 16A-16C along the cross-sectional views. The absence of source or drain metallization 650 is advantageous in that pitch and / or critical dimension constraints for the source / drain metallization 650 and / or other front-side metallization levels (e.g., gate electrode 673 or higher metallization levels) may be relaxed. For example, the absence of source or drain metallization 650 may render the transistor structure 1304 inoperable until a third terminal connection is fabricated using backside transistor source / drain contact metallization method 1201 (FIG. 12). Such backside transistor source / drain contact metallization may provide the transistor structure with power rails (e.g., V cc) may be coupled to interconnect traces located on both sides of the transistor structure, advantageously placing power and signal (gate electrode voltage) routing on both sides of the transistor structure hierarchy. Similar advantages are possible for memory cells, e.g., SRAM or other memory cells. For example, bit line, source line, and / or word line metallization may be on both sides of a single memory cell hierarchy. In particular, backside transistor source / drain contact metallization method 1201 may be implemented for transistor structures that are fully functional when fabricated from the front side (e.g., including all device terminals). For such embodiments, backside transistor source / drain contact metallization method 1201 may be implemented to wrap source / drain transistor terminals to interconnect traces located on both sides of the transistor hierarchy, advantageously reducing source / drain contact resistance and / or allowing the source / drain semiconductor regions of the transistor to be circuit nodes that are directly fanned out to at least two other circuit nodes.

[0092] In step 1210, the backside of the source / drain regions of at least one transistor is exposed. In some embodiments, a patterned backside recess etch is performed in step 1210 to selectively expose the source / drain regions relative to other regions of the transistor structure. Alternatively, the source / drain semiconductor (or any sacrificial material) at the source / drain locations is extended from the front side to a greater depth than other transistor regions, and step 1210 may involve an unpatterned backside recess etch or polish that stops upon exposing the source / drain semiconductor (or other sacrificial material) before exposing other device regions, such as the channel semiconductor. Once exposed, method 1201 completes in step 1215, where source / drain semiconductor and / or contact metallization are deposited over the backside of the source / drain semiconductor. The source / drain semiconductor and / or contact metallization are further examples of non-native materials that may be deposited, for example, as described above in the context of step 125 of FIG. 1.

[0093] Figures 14A, 15A, and 16A show cross-sectional views of transistor structure 1304 along the A-A' plane shown in Figure 13 when steps in method 1201 are performed according to some embodiments. Figures 14B, 15B, and 16B show cross-sectional views of transistor structure 1304 along the B-B' plane shown in Figure 13 when steps in method 1201 are performed according to some embodiments. Figures 14C, 15C, and 16C show cross-sectional views of transistor structure 1304 along the C-C' plane shown in Figure 13 when steps in method 1201 are performed according to some embodiments.

[0094] 14A-14C illustrate the structures present in an exemplary transistor structure following front-side processing of the donor substrate and bonding to the host substrate 202. As further illustrated in FIGS. 14A-14C, the backside substrate is removed by any technique, such as, but not limited to, method 501 (FIG. 5). The structural features illustrated in FIGS. 14A-14C may have any of the characteristics described above (e.g., FIGS. 8A-8C and 9A-9C) with similar reference numerals. An etch mask 1410 is aligned to the front-side transistor features visible upon removal of the backside substrate. Alignment 640 to the source / drain semiconductors need not be precise, and overlap with the gate electrode 673 is minimized or avoided. The etch mask 1410 is intended to protect only a portion of the intervening layer 210. The etch mask 1410 may be, for example, another intervening layer of the backside substrate. Alternatively, the etch mask 1410 may be a dielectric (e.g., SiO, SiN, etc.) deposited after exposing the intervening layer 210 during removal of the carrier layer. In yet another embodiment, the etch mask 1410 is a soft mask (e.g., photosensitive resist) applied over the backside surface of the device layer 215. The unprotected device semiconductor regions 1411 are then recess-etched using any wet and / or plasma etching process known to be suitable for the material composition. For example, a dry etch and / or a wet etch selective to silicon above the etch mask may be used to selectively remove portions of the silicon semiconductor sub-fin and expose the source / drain of the transistor.

[0095] 14D-14F illustrate the structures present in an exemplary transistor structure following front-side processing of the donor substrate and bonding to the host substrate 202. As further illustrated in FIGS. 14D-14F, the backside substrate is removed by any technique, such as, but not limited to, method 501 (FIG. 5). The structural features illustrated in FIGS. 14D-14F may have any of the characteristics described above (e.g., FIGS. 8A-8C and 9A-9C) with similar reference numerals. For this embodiment, no etch mask is used to selectively expose certain source or drain semiconductors 640. Rather, the front-side processing differentiates the depth in the z-direction between the two regions of the source and drain semiconductors 640 on either side of the channel. In the exemplary embodiment, the source semiconductor 640 has a depth substantially equal to the height of the semiconductor body 610, although it may have a depth less than or greater than that shown.

[0096] 15A-15C are a continuation of the structure shown in Figures 14A-14C. As shown in Figures 15A-15C, a substantial portion of the transistor semiconductor body 610 is removed in the selective exposure recess 1540, while the sub-fin height H sfThe selective exposure recess 1540 is maintained in the transistor structure region protected by the etch mask 1410. The selective exposure recess 1540 may be of any depth and lateral dimension. For example, the selective exposure recess 1540 may completely remove the sub-fin portion of the semiconductor body 610 (i.e., the semiconductor portion of the intervening layer 210) to expose the source / drain semiconductor 640. In other embodiments, the selective exposure recess 1504 may be used as a backside fin cut to bifurcate the fin into two separate fins, for example, to allow one fin to implement a PMOS FET and the other fin to implement an NMOS FET. On the other hand, when limited to frontside processing, with backside fin bifurcation, the fin bifurcation is typically early in the processing during fin patterning, and there is no fin end that needs to be defined throughout all of the frontside processing. Therefore, frontside fin processing may also better align ID gate patterning with NMOS and PMOS FETs fabricated together in a single fin. Upon backside exposure, the individual transistors may be imaged through cuts in the backside fins.

[0097] 15D-15F are a continuation of the structure shown in FIGS. 14D-14F. The intervening layer 210 is removed, for example, using a blanket polishing or etching process, to selectively expose the source / drains of the deep transistor relative to the shallow source / drains. As shown in FIGS. 15D-15F, the deep source / drain semiconductor 640 is exposed while maintaining the sub-fin height H sf is maintained in the transistor structure 1304 in the other region.

[0098] 16A-16C are continuations of the structure shown in FIGS. 15A-15C. FIGS. 16A-16C show the transistor structure 1304 after epitaxial growth or deposition of a p-type or n-type impurity doped backside source / drain semiconductor 1640 and subsequent deposition of a backside source / drain metallization 1650. Any epitaxial growth or deposition process may be used to form the backside source / drain semiconductor 1640. For example, the same epitaxial or deposition process used to form the source / drain semiconductor 640 may be used to form the backside source / drain semiconductor 1640. Similarly, any metal deposition process may be used to form the backside source / drain metallization 1650. For example, the same deposition process used to form the source / drain metallization 650 may be used to form the backside source / drain metallization 1650. The backside source / drain semiconductor 1640 has a longitudinal length L fThe semiconductor body 610 has a smaller longitudinal length L1 and a lateral length L2 that is substantially equal to the lateral length of the semiconductor body 610. Thus, in an exemplary embodiment, the source / drain semiconductor 640 has a lateral length L3 that is greater than the backside source / drain semiconductor 1640. Similarly, the longitudinal lengths of the frontside and backside source / drain semiconductors may be different. For example, in some embodiments in which the backside source / drain semiconductor 1640 is operable as a transistor source, a tip region (e.g., a lightly doped source semiconductor) may be included that is absent in the source / drain semiconductor 640 that is operable as a transistor drain. Such a selective source tip region may be formed, for example, during epitaxial growth of the impurity-doped backside source / drain semiconductor 1640. A transistor drain without a tip may exhibit, for example, less drain-induced barrier lowering (DIBL), while the lowest source resistance may depend on the tip-doped source semiconductor. However, it is often difficult to introduce asymmetry in the source / drain architecture of a FET through frontside processing alone. Thus, decoupling fabrication of the drain semiconductor from the source semiconductor to separate frontside / backside processing can facilitate the formation of asymmetric source / drain architectures.

[0099] 16A-16C, the excess overburden of the backside metallization is removed by polishing (e.g., CMP) using the source / drain contact metallization to re-expose the etch mask 1410 and / or the intervening layer 210, thereby confining by backfilling the selectively exposed recesses 1540. Subsequent backside processing may further include fabrication of one or more backside interconnect metallization levels (not shown) that electrically couple at least the source / drain metallization 1650. In some such embodiments, such backside interconnect metallization is of a different composition than the frontside interconnect metallization level. For example, if the frontside interconnect metallization is primarily copper (e.g., a Cu-rich alloy), the backside metallization may have a lower copper content (e.g., an Al-rich alloy). In another example, where the front-side interconnect metallization has a low copper content (e.g., is an Al-rich alloy), the back-side metallization is primary copper (e.g., is a Cu-rich alloy). The back-side interconnect metallization may be different in size (e.g., larger) than the corresponding level of front-side interconnect metallization. For example, in some embodiments where the back-side interconnect metallization supplies power to a transistor structure, the back-side metallization has lines with a larger lateral width and / or vertical height (e.g., z-dimension). Back-side metallization with larger dimensions may be advantageous for architectures in which power rails are confined to the back-side metallization and signal lines are confined to the front-side metallization. Back-side metallization with larger dimensions may also be advantageous for architectures in which long bus lines or clock distribution lines are provided on the back side of the device hierarchy.

[0100] 16D-16F are continuations of the structure shown in FIGS. 15D-15F. In FIGS. 16D-16F, transistor structure 1304 is shown after deposition of backside source / drain metallization 1650 in contact with deep source / drain semiconductor 1650. Any metal deposition process may be used to form backside source / drain metallization 1650. For example, the same deposition process used to form source / drain metallization 650 may be used to form backside source / drain metallization 1650. Formation of backside source / drain metallization 1650 may further involve formation of backside dielectric 1410, for example, according to any known damascene interconnect metallization technique.

[0101] While the above description has provided some illustrative examples of backside metallization structures, other structures may be fabricated using substantially the same techniques. In general, any terminal of a device fabricated in a device hierarchy may have a backside metallization structure. For example, rather than (or in addition to) the backside source and / or drain contact metallization shown above, other terminals of transistors may be interconnected by backside metallization. For example, in a three-terminal device, the third terminal (e.g., the gate electrode in a FET or the base in a bipolar junction transistor) may have a backside metallization structure. Similarly, in a four-terminal device, the fourth terminal (e.g., a floating body tap or field plate) may have a backside metallization structure.

[0102] Thus, exposing the backside of the transistor structure may further include exposing the gate electrode and / or channel semiconductor of the transistor. In some embodiments, backside gate electrode processing is used to completely surround the transistor channel with a gate electrode, thereby forming a nanowire transistor with a wraparound gate electrode. Additionally or alternatively, the exposed gate electrode may be coupled to a backside interconnect that is further fabricated on the backside of the layer containing the transistor structure. In some other embodiments, the backside gate electrode processing replaces a sacrificial gate mandrel or placeholder fabricated during frontside processing. Figure 17 is a flow diagram 1701 illustrating a method for forming a gate electrode of a backside transistor, according to some embodiments. Method 1701 further illustrates backside processing of a layer of a transistor structure that may be only a few hundred nanometers thick. Method 1701 begins with a donor-host substrate assembly containing the transistor structure as input 1705. The donor substrate may have one or more of the features described above, such as, but not limited to, an intervening layer and a carrier layer. However, notably, the carrier layer and / or intervening layer are not required to perform method 1701 .

[0103] The transistor structure may be fully operational to accept input 1705 and include, for example, three terminals as shown in FIG. 6 . Alternatively, one or more terminals (e.g., the gate electrode) may be absent so that the transistor structure is not operational until backside processing is complete. In step 1710, the backside of the transistor's gate electrode, the sacrificial gate mandrel, and / or the transistor channel semiconductor are exposed during a backside exposure process. In some embodiments, the backside exposure process performed in step 1710 includes one or more of the steps of method 501 ( FIG. 5 ). The backside exposure process may expose the semiconductor channel region, for example, by removing at least a portion of the donor substrate (e.g., carrier layer). In step 1715, a gate stack is formed from the backside of the device layer. The gate stack may be formed on the backside of the semiconductor channel, or it may be formed on the front side of the semiconductor channel, depending on how much of the channel semiconductor is exposed in step 1710. The method 1701 concludes with the output of a hierarchy of transistor structures that includes gate electrode material disposed above the backside of the transistor channel semiconductor.

[0104] In some embodiments, method 1701 is facilitated by one or more front-side processing steps. For example, during front-side processing, the depth (e.g., z-dimension position) of a transistor's gate electrode or gate mandrels may be larger than one or more transistor's source / drain regions to facilitate exposing the gate electrode or gate mandrels from the backside without exposing one or more source / drain regions. To illustrate such synergy between front-side and back-side processing, FIGS. 18A-26A provide cross-sectional views along the A-A' plane indicated by the thick dashed-dotted line in the plan view of exemplary transistor structure 604 ( FIG. 6 ), according to some exemplary embodiments. FIGS. 18B-26B show cross-sectional views along the B-B' plane indicated by the thick dashed-dotted line in the plan view of exemplary transistor structure 604 as front-side transistor processing is performed, according to some exemplary embodiments. The illustrated front-side transistor processing may be performed upstream of back-side processing embodiments described elsewhere herein, for example. Illustratively, the semiconductor device layer is a fin of a transistor formed using an additive process. Alternatively, the semiconductor layer may be a fin of a transistor formed by any subtractive process (e.g., patterning of a successive semiconductor device layer).

[0105] In the embodiment shown in FIGS. 18A and 18B, trench 1809 is anisotropically etched into field isolation dielectric 680, exposing a portion of backside substrate 605 at the bottom of trench 1809. In some embodiments, the exposed portion of backside substrate 605 is recess-etched, as shown. In some embodiments, trench 1809 has a CD between 10 and 200 nm. However, the z-direction thickness and CD of the trench material may be scaled as needed to maintain an aspect ratio that works for a predetermined fin height selected for the desired transistor current-carrying width. As further shown in FIGS. 19A and 19B, a sub-fin semiconductor 1810 is epitaxially grown selective to the substrate seed surface to partially backfill trench 1809. In some exemplary embodiments, sub-fin semiconductor 1810 further serves as an intervening layer (e.g., 210 in FIG. 3A) used in subsequent removal of backside substrate 605. A semiconductor device layer 215 is further epitaxially grown from the seed surface of the sub-fin as a semiconductor body 610 extending from the surface of the sub-fin still contained within the trench. The device layer 215 and the sub-fin semiconductor 1810 may be of the same or different compositions. For example, both the device layer 215 and the sub-fin semiconductor 1810 may be silicon. Alternatively, the device layer 215 may be a first semiconductor alloy and the sub-fin semiconductor 1810 is a second semiconductor alloy.

[0106] After epitaxial fin growth, the surrounding field isolation dielectric 680 may be selectively recessed to a desired level below the device layers 215, as further depicted in FIG. 20A. In an exemplary embodiment, the field isolation dielectric 680 is recessed sufficiently to fully expose the device layers 215 in preparation for raised source / drain regrowth. At this point in the front-side processing, the sub-fin height H sfThe sub-fin semiconductor 1810 is embedded within the field isolation dielectric 680. In particular, a subtractive patterning process in which the fin patterning is etched into the backside substrate 605 can arrive at a fin structure substantially similar to that shown in FIG. 20A. For such embodiments, the device layer 215 and the sub-fin semiconductor 1810 can be the same semiconductor material (e.g., both silicon) or different semiconductor materials.

[0107] As shown in FIGS. 21A and 21B , gate stack mandrels including sacrificial gate material 2173 (e.g., polysilicon) are formed above device layer 215 using any conventional technique. The sacrificial gate material 2173 may be formed on at least two sidewalls of device layer 215, landing on field isolation dielectric 680. Spacer dielectric 671 may be formed using any conventional technique. For the embodiment depicted in FIG. 21A , sacrificial gate material 2173 does not cover a portion of the sidewalls of any sub-fin material 110, which may correspond to a recess in the isolation dielectric. After gate mandrel formation, a doped semiconductor (or any sacrificial material) is formed on the source / drain ends of semiconductor device layer 215. In some embodiments, the raised source / drain regions are formed by depositing a heavily doped semiconductor of any composition suitable for semiconductor device layer 215. In the exemplary embodiment shown in FIGS. 22A-22B, epitaxial processing is used to form single-crystal raised source / drain semiconductors 640. As further depicted in FIGS. 23A-23B, an additional field isolation dielectric 680 is then deposited above the raised source / drain semiconductors 640 and planarized using gate mandrels.

[0108] 24A-24B, the sacrificial gate material 2173 is removed selectively to the surrounding field isolation dielectric 680, exposing the semiconductor device layer 215. Any conventional technique may be used to remove the sacrificial gate mandrel. After gate mandrel removal, the exposed field isolation dielectric 680 may be further recessed selectively to other areas, thereby further exposing at least a portion of the sub-fin semiconductor 1810 within the recess 2470. As shown, after the field isolation dielectric 680 is recessed, the portion of the sub-fin semiconductor 1810 embedded within the field isolation dielectric 680 is exposed to H sf,2 25A-25B, a gate stack including gate dielectric 845 and gate electrode 673 is deposited in recess 2470. Any gate stack backfill process known to be suitable for replacement gate applications may be performed.

[0109] For transistors in which the depth of the gate electrode extends shallower than the depth of the device layer, the gate electrode may be exposed from the backside (e.g., during method 1101), as further shown in Figures 26A-26C, 27A-27C, and 28A-28C, which show cross-sectional views along the A-A', B-B', and C-C' planes indicated by thick dashed-dotted lines in a plan view of exemplary transistor structure 604 (Figure 6). Such techniques may be further combined with exposing one or more source / drain regions, for example, as described elsewhere herein.

[0110] 26A-26C further illustrate a front-side stack 690 disposed above the front-side cell surface. The front-side stack 690 is shown in dashed lines as part of a hierarchy of a transistor structure that may vary without limitation and may include, for example, any number of back-end interconnect metallization levels. The host substrate 202 may have, for example, any of the characteristics described elsewhere herein. As shown, the host substrate 202 is bonded to the front-side surface of the front-side stack 690, for example, by thermo-compression bonding. As further shown in FIGS. 26A-26C, at least a portion of the donor substrate has been removed, exposing the backside surface 2611 of the sub-fin semiconductor 1810. The donor substrate may be thinned and / or removed by any technique, for example, but not limited to, method 501 (FIG. 5). In method 501, for example, the intervening layer may be one or more of the sub-fin semiconductor 1810 and the field isolation dielectric 680. Alternatively, the intervening layer used in method 501 may be the topmost layer of the backside substrate 605 .

[0111] 27A-27C show the transistor structure 604 after exposure of the backside 2712 of the gate electrode 673. To expose the backside of the gate electrode 673, portions of the sub-fin semiconductor 1810 may be recess-etched using polishing (e.g., CMP) and / or wet and / or dry etching processes, for example, as described above for step 525 (FIG. 5). Such etching processes may be masked or unmasked. In some exemplary embodiments, a highly selective (e.g., 200-300:1) CMP slurry having a higher etch rate of semiconductor (e.g., Si) than dielectric is used, and the backside polish of the device layer 215 may be stopped upon exposing the gate dielectric 845. An optional amount of overetch (over-polish) may be performed. In some embodiments, the entire sub-fin may be removed during the backside exposure step relative to one or more semiconductor bodies in the transistor structure. In the exemplary embodiment shown in Figures 27A-27C, the gate electrode 673 is exposed before the source / drain semiconductor 640 is exposed and the exposure process is stopped before exposing the source / drain semiconductor 640.

[0112] For some embodiments, backside metallization is deposited over the backside surface of gate electrode 673. For example, low-power logic state signals may be passed to transistor structure 604 from other transistor structures in the IC through backside metallization in contact with gate electrode 673. Thus, the backside metallization may provide source / drain and / or gate electrode interconnections between transistor structures. In some other embodiments, gate electrode 673 is grown from the backside to form a nanowire or gate-all-around (GaAs) transistor in which the gate electrode surrounds all sides of the semiconductor body. For such embodiments, the backside of semiconductor device layer 215 is exposed, and a backside gate stack is deposited over the backside of semiconductor device layer 215 and interconnected with gate electrode 673.

[0113] 28A-28C further show the transistor structure 604 after deposition of a backside gate stack including a backside gate dielectric 2845 and a backside gate electrode 2873. As shown in this exemplary embodiment, the backside gate stack is deposited directly on the exposed surface of the semiconductor device layer 215. To expose the device layer 215, any remaining portions of the sub-fin semiconductor 1810 may be selectively etched (e.g., using a wet or dry chemical etch) to create a recess in the back surface of the semiconductor fin relative to the back surfaces of the gate electrode 673 and / or field isolation dielectric 680, as shown in FIGS. 28A-28C. For embodiments in which the sub-fin semiconductor 1810 has a different composition than the device layer 215, the recess etch may be even more selective to the device layer 215, effectively stopping when exposing the device layer 215. The sub-fin semiconductor 1810 may have the same composition as the device layer 215 (e.g., both are fin silicon patterned from the device layer), and the recess etch may be of a predetermined fixed duration or may be stopped at an impurity-dopant interface.

[0114] A backside gate dielectric 2845 is deposited over or on the exposed device layers 215. The backside gate dielectric 2845 is another example of a non-native material deposited over the backside of the transistor semiconductor region. The backside gate dielectric 2845 may be any dielectric material known to be suitable for field effect transistors. In some exemplary embodiments, the backside gate dielectric is any of the materials described elsewhere herein for the gate dielectric 845, and may be the same material.

[0115] The backside gate electrode 2873, which may be deposited over the backside gate dielectric 2845 and / or directly on the exposed surface of the gate electrode 673, is another example of a non-native material deposited over the backside of a transistor semiconductor region. The backside gate electrode 2873 may be any doped semiconductor or metal known to be suitable for gated field effect transistors. In some exemplary embodiments, the backside gate electrode 2873 is any of the materials described elsewhere herein for the gate electrode 673, and may be the same material. For some nanowire transistor embodiments, the backside gate electrode 2873 may be deposited over the backside gate dielectric 2845 and planarized (e.g., by CMP) with the surrounding backside surface of the gate electrode 673. In some embodiments, a subsequent backside metallization layer (not shown) is deposited in direct contact with the gate electrode 673 and the backside gate electrode 2873 as an interconnect between the gate electrode 673 and the backside gate electrode 2873 and / or other IC nodes located within other transistor structures. With gate electrodes 2873 and 673 both tied to the same potential, the channel region of the FET may be fully depleted.

[0116] In an alternative embodiment, the front gate electrode is electrically independent from the back gate electrode. Such an independent back gate electrode may be connected to a predetermined transistor threshold voltage (V t ) can be controlled to one of a number of predetermined voltage levels, each associated with a different threshold voltage. With the ability to set different threshold voltages, the transistor becomes a multi-state device (i.e., having more states than just on / off). In some such embodiments, the potential of the back-side gate electrode is controlled through back-side interconnect metallization that is not even in contact with the (front-side) gate electrode. Similarly, the front-side gate electrode may be controlled by front-side interconnect metallization disposed within, for example, the front-side stack, thereby implementing a four-terminal device.

[0117] Such double-gate transistor structure architectures can be readily fabricated according to method 1701. For example, with further reference to the front-side processing shown in FIGS. 18A-24A, the recessing of the field isolation dielectric 680 exposed following the gate mandrel removal shown in FIG. 24A may be omitted, thereby avoiding any exposure of the sub-fin semiconductor 1810 within the recess 2470. For such embodiments, the gate electrode 673 then does not extend along the sidewalls of the sub-fin semiconductor 1810 in the manner shown in FIG. 25A. Rather, the depth of the gate electrode 673 is substantially flat with the interface of the device layer 215 and the sub-fin semiconductor 1810, and the sub-fin semiconductor 1810 may then be selectively recessed or polished by a predetermined amount without exposing the backside of the gate electrode 673. As further shown in FIGS. 28D, 28E, and 28F, for example, the sub-fin semiconductor 1810 is selectively recessed from the backside of the field isolation dielectric 680. The resulting backside recess is backfilled with the gate stack (backside gate dielectric 2845 and gate electrode 2873). A subsequent backside metallization layer (not shown), which is then deposited in direct contact with the backside gate electrode 2873, is electrically isolated from the gate electrode 673.

[0118] In some embodiments, the backside of the transistor gate mandrels is exposed. For such embodiments, the gate mandrels may be fabricated using, for example, frontside transistor processing using any known technique. The mandrels may then be later exposed and replaced with a permanent gate electrode during backside processing. Thus, backside processing performance may be performed relative to the frontside processing steps to delay the formation of one or more transistor device regions until after, for example, the frontside interconnect metallization level and interlayer dielectric (ILD) have been formed. Thus, higher temperature processing may be performed prior to temperature-sensitive processing, potentially increasing the thermal budget of the transistor structure.

[0119] For transistors in which the gate mandrel depth extends shallower than the device layer depth, the gate mandrels may be exposed from the backside (e.g., during method 1101), as further shown in FIGS. 29A-29C, 30A-31C, and 33A-33C, which illustrate cross-sectional views along the A-A', B-B', and C-C' planes indicated by thick dashed-dotted lines in the plan view of example transistor structure 604 (FIG. 6). The transistor structures shown in FIGS. 29A-29C are substantially the same as those shown in FIGS. 27A-27C. Thus, the transistor structures shown in FIGS. 29A-29C may be fabricated using front-side processing substantially as described with respect to FIGS. 18A-25A, with the exception that gate electrode 673 and / or gate dielectric 845 are later replaced as secondary mandrels. As such, gate electrode 673 and / or gate dielectric 845 may have a composition selected to be preferentially etched relative to semiconductor device layer 215. For example, gate electrode 673 may have the same composition as sacrificial gate material 2173 (e.g., polysilicon), where semiconductor device layer 215 is other than silicon (e.g., SiGe, III-V, or III-N). Alternatively, if semiconductor device layer 215 is silicon, gate electrode 673 may be another polycrystalline semiconductor, such as, but not limited to, SiGe or Ge. For example, gate dielectric 845, if it is also sacrificial, may be silicon dioxide. For example, gate dielectric 845, if it is not sacrificial, may be a high-k material, such as any of those described above.

[0120] 29A-29C show the transistor structure 604 after exposure of the backside 2912 of the (sacrificial) gate electrode 673. Portions of the sub-fin semiconductor 1810 may be recess-etched using polishing (e.g., CMP) and / or wet and / or dry etching processes, for example, as described above with respect to step 525 (FIG. 5). In some exemplary embodiments in which a highly selective (e.g., 200-300:1) CMP slurry having a higher etch rate of semiconductor (e.g., Si) over dielectric is used, the backside polish may be stopped upon exposing the (sacrificial) gate dielectric 845. In some alternative embodiments in which a dry or wet semiconductor etch is performed, the etch may be stopped upon exposing the gate dielectric 845. Any amount of overetch (overpolish) may be performed. In some embodiments, the entire sub-fin is removed during the backside exposure step relative to one or more semiconductor bodies in the transistor structure. In the exemplary embodiment shown, the gate electrode 673 may be exposed before the source / drain semiconductors 640 are exposed and the exposure process may be stopped before exposing the source / drain semiconductors 640 .

[0121] The gate electrode 673 is then removed using a selective etching process, forming the void 3040 shown in Figures 30A-30C. Any etching process known to etch the (sacrificial) gate electrode 673 may be used. For example, a polysilicon etchant, a SiGe etchant, or a Ge etchant may be used to isotropically remove the gate electrode 673. After removal, the exposed surface of the semiconductor device layer 215 may then be covered with a permanent gate electrode stack. As further shown in Figures 31A-31C, a backside gate stack is deposited directly on the exposed surface of the semiconductor device layer 215. To fully expose the device layer 215, any remaining portions of the sub-fin semiconductor 1810 may be selectively etched (e.g., using a wet or dry chemical etch) to recess the back surface of the semiconductor fin relative to the back surface of the field isolation dielectric 680. For embodiments in which the sub-fin semiconductor 1810 has a different composition than the device layer 215, the recess etch may be more selective to the device layer 215, effectively stopping when the device layer 215 is exposed. For embodiments in which the sub-fin semiconductor 1810 has the same composition as the device layer 215 (e.g., both are silicon comprising fins patterned from the device layer), the recess etch may be of a predetermined fixed duration. The backside gate dielectric 2845 and backside gate electrode 2873 are then deposited above or on the exposed device layer 215, substantially as described above.

[0122] In particular, even when the same gate stack materials are used for both the front-side and back-side gate stacks, various structural features may differentiate nanowire transistor structures fabricated exclusively from the front side from nanowire transistor structures fabricated using back-side processing according to some embodiments of the present disclosure. For example, the presence of back-side gate dielectric 2845 over the portion of device layer 215 that extends beyond the channel region contacted by front-side gate dielectric 845 indicates a patterning process that is self-aligned with respect to the other structures used to deposit the back-side gate stack and pattern the front side of the gate stack. Similarly, differences in the scale or location of back-side gate electrode 2873 relative to front-side gate electrode 673 are indicative of a back-side fabrication process. For example, as shown in both Figures 28A and 31A, the backside gate electrode 2873 extends a longitudinal length of the backside surface semiconductor device layer 215 that is greater than but approximately equal to or just slightly less than the longitudinal length of the gate electrode 673, and the recessed length Lf of the fin along the longitudinal length of the semiconductor device layer 215 is self-aligned with respect to the semiconductor body.

[0123] Backside processing of exposed portions of the device hierarchy may include deprocessing and / or replacement of other transistor structures formed during frontside fabrication processes. During such deprocessing, one or more materials deposited or structures formed during frontside processing may be removed during backside processing after such materials and / or temporary structures or mandrels are no longer needed for device fabrication and / or their retention as components of the device is no longer optimal for device operation. For example, sidewall spacer dielectrics are often used during frontside transistor processing to facilitate self-alignment of transistor features and / or to prevent electrical shorts between adjacent features. However, such sidewall spacer dielectrics may not be optimal for device operation, for example, contributing to parasitic capacitance. Therefore, backside deprocessing may later remove such spacer dielectrics from the device structures to improve device operation. Once removed, the spacer dielectrics may be replaced with another material more favorable for device operation, or voids where the spacer dielectrics were removed may be retained as artifacts in the transistor hierarchy. In some advantageous embodiments, the spacer dielectric used in front-side processing is replaced with another dielectric having a lower dielectric constant than the spacer dielectric during back-side processing. Often, low-k materials are susceptible to damage upon exposure to subsequent processes, such as plasma etching. Therefore, a high high-k material can be advantageous as the spacer dielectric during front-side fabrication. However, if this high high-k material is retained within the transistor hierarchy, it increases the parasitic capacitance of the device during processing. After back-side exposure according to some embodiments, the high high-k material is replaced with a low-k material. The back-filled low-k material then tolerates any damage associated with exposure to front-end processing.

[0124] FIG. 32 is a flow diagram 3201 illustrating a backside processing method including sidewall spacer dielectric removal, according to some embodiments. Method 3201 further illustrates backside processing of a device (e.g., transistor structure) layer that may be only a few hundred nanometers thick. Method 3201 begins with a donor-host substrate assembly including a device layer as input 3205. The donor substrate may have one or more of the features described above, such as, but not limited to, an intervening layer and a carrier layer. However, the carrier layer and / or intervening layer are not specifically required to perform method 3201. In step 3210, the backside of the device layer or intervening layer is exposed during a backside exposure process. In some embodiments, the backside exposure process performed in step 3210 includes one or more of the steps of method 501 (FIG. 5). The backside exposure process may expose the device layer or intervening layer, for example, by removing at least a portion of the donor substrate (e.g., carrier layer).

[0125] 33A-33C, 34A-34C, 35A-35C, and 36A-36C illustrate cross-sectional views along the A-A', B-B', and C-C' planes indicated by the thick dashed-dotted lines in the plan view of an exemplary transistor structure 604 (FIG. 6). The transistor structure illustrated in FIGS. 33A-33C is substantially similar to the transistor structure illustrated in FIGS. 10A-10C after a backside exposure process that exposes the backside 1012 of the semiconductor body 610. In some embodiments, the transistor structure illustrated in FIGS. 33A-33C may be fabricated using any front-side process known to be suitable for fabricating FinFETs. In some embodiments, once the semiconductor body 610 is formed by any known technique, front-side processing begins, as described above in the context of FIGS. 20A-25A.

[0126] 33A-33C further illustrate where dielectric sidewall spacers may be found for some exemplary embodiments. In FIG. 33A, spacer dielectric 671 is disposed at the transverse edges of gate electrode 673. Such sidewall spacers may be formed in embodiments in which the spacer dielectric is deposited after the (sacrificial) gate electrode is fully patterned. For example, the spacer dielectric is deposited after the edges of sacrificial gate material 2173 are patterned (FIGS. 21A, B). Alternatively, the sidewall spacer dielectric may be deposited before such patterning, with spacer dielectric 671 only present on the longitudinal sidewalls of gate electrode 673 shown in FIG. 33B. The spacer dielectric may be deposited with the purpose of forming self-aligned spacers along the sidewalls of the gate electrode that demark the boundary between the transistor channel and source / drain regions. However, due to non-planarity in the semiconductor body, self-aligned spacers may form along one or more sidewalls of the semiconductor body as an artifact of front-side processing. As an example, FIG. 33C shows spacer dielectric 671 further disposed along the sidewalls of semiconductor body 610.

[0127] 34A-34C further illustrate how the backside exposure process can continue to sufficiently remove intervening layers and expose the backside of semiconductor body 610. In particular, such removal may use masking and / or other selective techniques so that only portions of the backside are exposed. To arrive at the structure shown in FIGS. 34A-34C, for example, a backside etch or CMP polish through a portion (sub-fin) of semiconductor body 610 may be performed for a predetermined time or terminated upon detecting one or more of source / drain semiconductor 640, spacer dielectric 671, gate dielectric 845, and gate electrode 673. As shown in FIGS. 34A-34C, the exposure of the device layers also exposes spacer dielectric 671 disposed between gate electrode 673 and source / drain semiconductor 640 and / or source / drain metallization 650t.

[0128] Returning to FIG. 32 , method 3201 begins, at step 3220, etching at least a portion of the exposed spacer dielectric. Ideally, the etch of the spacer dielectric is highly selective to the target dielectric material and does not significantly affect the exposed surrounding semiconductor, dielectric, and / or metallization on the backside. In some embodiments, the dielectric spacer is removed using an isotropic etch (e.g., a wet chemical etch or a plasma etch). For example, a wet chemical etch may isotropically remove the spacer dielectric, including one or more of silicon nitride (SiN), carbon-doped silicon (SiC), or carbon-doped silicon nitride (SiCN) in the spacer dielectric. In the example shown in FIGS. 35A-35C , removal of spacer dielectric 671 is selective to the gate stack, including gate electrode 673 and gate dielectric 845, forming spacer recess 3512.

[0129] Continuing with FIG. 32 , in step 3220, the recesses formed from deprocessing the dielectric spacers may be backfilled with another material (e.g., a low-k dielectric), or alternatively, may be filled with any suitable dielectric material to integrate one or more air gaps or voids into the transistor hierarchy. In some advantageous embodiments, the dielectric material deposited in step 3230 has a lower dielectric constant than the dielectric material removed in step 3220. In some such embodiments, the dielectric material deposited in step 3230 has a dielectric constant less than 4.5, advantageously less than 3.9, and even more advantageously less than 3.5. For some embodiments in which voids are filled, the dielectric material may be deposited using any non-conformal deposition technique, such as, but not limited to, physical vapor deposition (sputter deposition) or some chemical vapor deposition techniques. Voids having a sufficiently high aspect ratio are then sealed with a non-conformal dielectric material.

[0130] In the example shown in FIGS. 36A-36C, backside dielectric 3671 backfills spacer recess 3512 (FIGS. 35A-35C). Backside dielectric 3671 may be any material known to have a low dielectric constant (e.g., less than about 4.5). Example materials include SiOC, SiOCH, HSQ, or MSQ. Deposition techniques may be known that are suitable for backfilling recesses using the selected material, such as, but not limited to, chemical vapor deposition (CVD) and spin-on processes. In the example shown in FIGS. 35A-35C, backside dielectric 3671 also covers the backside surfaces of semiconductor body 610 and source / drain semiconductors 640. If desired, backside dielectric 3671 may be later planarized with the backside surface of semiconductor body 610.

[0131] 37A-37C, the backside dielectric 3671 has insufficient conformality to backfill the high aspect ratio spacer recess 3512 (FIGS. 35A-35C), but blocks the opening of the recess to form a void 3771. The void 3771 may then be permanently retained as a structural feature of the transistor structure 604. The method 3201 (FIG. 32) is then substantially completed with an output 3240 including a device structure having low-k spacers and / or air gaps surrounding one or more transistor structures, such as, for example, a gate electrode and / or a semiconductor body.

[0132] Any front-side device structure may be substantially removed and / or replaced, as described above in the context of dielectric spacer replacement. Depending on the backside processing being performed in the device fabrication flow, sacrificial placeholders for any portion of the device layer (e.g., transistor channel region) or terminal (e.g., transistor gate electrode or transistor source / drain semiconductor and / or metallization) may be exposed during backside processing, at least partially selectively removed from the surrounding structure, and backfilled with a suitable replacement material. In some exemplary embodiments, a sacrificial device terminal material (e.g., any suitable dielectric) may be formed during front-side processing to facilitate its subsequent selective removal during backside processing. Once removed, terminal semiconductor (e.g., transistor source / drain semiconductor and / or metallization (e.g., transistor source / drain contact metallization)) may be deposited within the resulting recess. Front-side device processing then follows a paradigm in which various structures are fabricated to facilitate their subsequent exposure during backside processing. For example, during front-side processing, the depth (z-height) of sacrificial structures removed from the backside may be deeper than non-sacrificial structures that are not removed through the backside, so that the sacrificial structures are pre-exposed during backside exposure processing and can then be selectively replaced.

[0133] Thus, any of the front-side structures described elsewhere herein (e.g., a transistor's gate electrode, source / drain contact metallization, etc.) may be sacrificial and ultimately replaced during backside processing. However, to facilitate subsequent exposure of various structures during backside processing, those fabricated during front-side processing need not be sacrificial. During front-side processing, the depth (height in the z-direction) of a non-sacrificial structure (e.g., a source or drain semiconductor, a gate electrode, or a source / drain contact metallization) that is electrically contacted through the backside may be deeper than another non-sacrificial structure (e.g., a source or drain semiconductor, a gate electrode, or a source / drain contact metallization) that is contacted through the backside. During backside exposure processing, deep structures are exposed before shallow structures. Thus, any of the front-side structures described elsewhere herein (e.g., a transistor's gate electrode, a source / drain semiconductor, or a contact metallization, etc.) may be sacrificial and ultimately replaced during backside processing, or non-sacrificial and ultimately contacted during backside processing.

[0134] In particular, any of the above backside exposure techniques and device architectures may be implemented globally across the entire wafer area, or selectively on a subset of regions on the wafer. In some embodiments, a masked exposure technique may be used to selectively expose regions of non-planar power transistor structures relative to regions of non-planar logic transistor structures, or vice versa. Furthermore, the selective exposure process may be within a single device structure (e.g., on an inter-cell basis), across multiple device structures (e.g., on an intra-cell basis), or may be region-based. The device-level selectivity of the backside exposure process is facilitated, for example, by the rigidity of the permanent bond and host-donor substrate architecture, as described above. The device-level selectivity of the backside exposure process is also facilitated, for example, by the use of highly selective exposure techniques, as described above. Such selective exposure processes may provide differentiation between logic transistors and power transistors or any other classification of transistors (e.g., RF and logic, memory access transistors and logic, planar and non-planar transistors, etc.). Exemplary embodiments further illustrating selective exposure techniques are described below in the context of some of the double-sided transistor architectures introduced above. These same techniques can similarly be applied to fabricate stacked frontside / backside devices in some areas selectively relative to other areas of a fabrication substrate (e.g., wafer).

[0135] 38A is a flow diagram 3801 illustrating a backside exposure method according to some embodiments. Method 3801 may be used, for example, to remove at least a portion of a carrier layer, an intervening layer (if present), and / or a portion of a device layer of a donor-host substrate assembly to selectively expose a device layer or device region for backside processing. The device region may be any suitable material, for example, a semiconductor, a metal, or a dielectric. As described elsewhere herein, exposing the device region may provide backside contact to the device region, backside access for removing the device region or portions thereof, etc.

[0136] As shown in Figure 38A, method 3801 begins with the input of a donor-host substrate assembly in step 3805. In some embodiments, the donor-host substrate assembly received in step 3805 is donor-host substrate assembly 203 (see Figure 3B). However, the donor-host substrate assembly received in step 3805 may be any suitable donor-host substrate assembly described herein.

[0137] The donor-host substrate assembly may include any suitable structure. In an embodiment, method 3801 provides a technique for fabricating integrated circuits, where the donor-host substrate assembly includes a substrate having a front-side device layer (e.g., a semiconductor device layer) above a back-side layer. The device layer includes a first device region of a first device and a second device region of a second device. The first and / or second device regions may be any semiconductor, metal, or dielectric material or structure, such as a channel semiconductor, a source / drain semiconductor, a source / drain metal, a gate metal, or a dielectric layer or material. The first and second devices may be the same type of device, or they may be different. Such differences between the first and second devices may be functional, structural, or both. For example, the first and / or second devices may be any combination of logic transistors, memory transistors, power transistors, n-type transistors, p-type transistors, planar transistors, or non-planar transistors. Furthermore, the first device and the second device may be in cells of the same architecture of an integrated circuit (e.g., such that the backside exposure differentiation within a cell is the same as for each of many identical cells), or they may be in different cells of the integrated circuit (e.g., such that the backside exposure differentiation between cells occurs between different cells). Also, the first device region of the first device and the second device region of the second device may be the same, or they may be different. For example, the first and / or second device regions may be any combination of channel semiconductor, source / drain semiconductor, source / drain metal, gate metal, dielectric layer or material, etc.

[0138] In method 3801, the backside of the first device region is selectively exposed relative to the second device region by removing at least a partial thickness of the backside layer described above. Such selective exposure is advantageous in that it may not expose (i.e., protect) the second device region to further processing, but may provide access to the first device region through the backside. Thereby, for example, further processing may be selectively applied to the first device region but not the second device region. The selective backside exposure of the backside of the first device region may be provided using any suitable technique or techniques, such as a masked exposure technique, a blanket exposure technique, or both.

[0139] In embodiments, a patterned mask is formed over the back layer such that the patterned mask protects the backside of the second device region. A recess is etched in the unmasked portion of the back layer to expose the first device region, while the second device region is protected by the patterned mask. The removed portion of the back layer may be part of an intervening layer and / or device layer. Such techniques are further described herein with respect to Figures 38B and 39-45C.

[0140] In embodiments, full backside removal of the backside layer is performed to expose the backside of the frontside semiconductor device layer. A patterned dielectric hardmask layer is formed over the backside of the frontside semiconductor device layer, such that the patterned dielectric hardmask layer protects the backside of the second device region. Recesses are etched through at least a partial thickness of the frontside semiconductor device layer in the unmasked portions of the frontside semiconductor device layer to expose the first device region, while the second device region is protected by the patterned dielectric hardmask layer. In such techniques, the patterned dielectric hardmask layer may remain after processing to provide isolation dielectric between devices. For example, the patterned dielectric hardmask layer may be an oxide or nitride, etc. Such techniques are described herein with respect to Figures 38C and 46-54C.

[0141] In embodiments, a partial thickness of the backside layer is removed over both the first device region of the first device and the second device region of the second device to expose the backside of the first device region. For example, the first device region of the first device and the second device region of the second device of the front-side semiconductor device layer may have structural differences such that when a blanket exposure is provided to the integrated circuit, the first device region is selectively exposed relative to the second device region. Such techniques may include any process or structure described herein. Differentiating structural features of the gate electrodes may be used to selectively expose a subset of the gate electrodes from the backside of the device hierarchy, for example, as described above with respect to Figures 17 and 24A-34C. For example, a first gate electrode (e.g., a first device region) of a first non-planar device may extend deeper within or through a device level than a gate electrode (e.g., a second device region) of a second non-planar device such that upon blanket exposure (e.g., planar processing), the first gate electrode is exposed while the second gate electrode is not exposed.

[0142] As shown in FIG. 38A , method 3801 provides various processing branches to provide backside exposure and related techniques for a received donor-host substrate assembly. For example, steps 3820, 3850, 3825, and 3855 are shown connected through dashed lines within any level (e.g., L2) and solid lines between two levels (e.g., L2 and L3) to illustrate various possible arrangements. The selection of such processing branches may be based, at least in part, on the received donor-host substrate assembly, the desired structures to be exposed, and / or the desired processes to be performed on the backside-exposed structures. As shown, the first level (e.g., L1) of method 3801 (e.g., steps 3810 and / or 3815) may include wafer-level full backside exposure, partial backside exposure, or both. The first level may provide a backside exposure technique. A second level (e.g., L2) of method 3801 (e.g., steps 3820 and / or 3850) may include cell-level differentiation provided by the exposure technique implemented. The second level may provide exposure (represented by dashed lines) on a cell-to-cell basis, an intra-cell basis, or both. A third level (e.g., L3) of method 3801 (e.g., steps 3825 and / or 3858) may include exposure types used for partial backside exposure. The third level may provide exposure types that are masked exposure, blanket exposure, or both. All of these exposure types may be used to achieve either cell-to-cell differentiation or intra-cell differentiation, as represented by the intersecting solid line connector between L2 and L3. Additionally, the third level may provide a basis for exposure differentiation. For example, exposure may be based on the function of the device being selectively exposed, the structure of the device being selectively exposed, or both. A fourth level (e.g., L4) of method 3801 (e.g., steps 3830, 3835, and / or 3840), when exposed by steps 3825 and / or 3858, may provide options for functional and / or structural differentiation of the device.For example, device exposure may be selectively performed based on whether the device is logic, memory, or power, based on whether the device is n-type or p-type, based on whether the device is non-planar or planar, or any combination thereof.

[0143] As shown, method 3801 includes branching from step 3805 through step 3810 to step 130, which provides the output of a device layer-host substrate assembly. Step 3810 provides a wafer-level full backside exposure of the received donor-host substrate assembly to provide the device layer-host substrate assembly in step 130. Such wafer-level full backside exposure techniques are described with respect to FIG. 5 and elsewhere herein. For example, wafer-level full backside exposure may include polishing and / or etching through the thickness of the carrier layer, detecting any intervening layers, and polishing and / or etching through the thickness of the intervening layers. As the name suggests, such processing is performed across the entire received donor-host substrate assembly without masking or the like. In embodiments, wafer-level full backside exposure is performed to expose the intervening layers. In embodiments, wafer-level full backside exposure is performed to expose the backside of the device layer. In embodiments, the received donor-host substrate assembly does not include a carrier layer, and wafer-level full backside exposure removes the thickness or entirety of the intervening layers. In embodiments, the wafer-level full backside exposure exposes intervening layers and / or device layers such that further processing (e.g., a mask or blanket exposure process) is performed to expose a first device region of a first device selectively to a second device region of a second device. As described above, in embodiments, the wafer-level full backside exposure exposes a first device region of a first device selectively to a second device region of a second device. For example, such wafer-level full backside exposure for selective device region exposure may be based on structural differences between the first and second devices, such that the first device region is exposed during the wafer-level full backside exposure process, while the second device region of the second device remains unexposed after such processing.

[0144] Also, as indicated by the diagonal line connecting steps 3810 and 3815, in some embodiments, a wafer-level full backside exposure as provided by step 3810 may be followed by a partial backside exposure in step 3815. For example, a wafer-level full backside exposure of a received donor-host substrate assembly in step 3810 may expose intervening layers and / or device layers (but, e.g., not device regions), while a partial backside exposure via any branches shown therewith may provide exposure of device layers or portions thereof (e.g., device regions selectively exposed relative to other device regions) in step 3815. An example of such a wafer-level full backside exposure followed by a partial backside exposure is shown with reference to FIG. 38C and elsewhere herein.

[0145] Method 3801 also begins with step 3815, which may include various branches from step 3805 (or step 3810, as described). In step 3815, a partial backside exposure is provided or initiated. Such partial backside exposure may provide options for a range of backside exposures. In embodiments, the backside exposure is based on the layout of the area of ​​the donor-host substrate assembly. For example, the backside exposure may provide selective exposure based on cell-to-cell exposure in step 3820, intra-cell exposure in step 3850, or area-based exposure (not shown). In this context, a cell is the smallest functional unit within the device hierarchy. A transistor cell, for example, includes one transistor; a 1T-1R memory cell includes one transistor and one resistor; and a 1T-1C memory cell includes one transistor and one capacitor. For cells that include passive devices, e.g., resistors or capacitors, the cell-to-cell exposure in step 3820 may expose only active devices (e.g., transistors), only passive devices, or both active and passive devices, depending, for example, on their associated location within the cell.

[0146] Differentiating backside exposure between cells, as provided in step 3820, provides backside exposure of device regions within certain cells while leaving device regions covered (or unexposed) in other cells. The exposed device regions within a cell may be any suitable region or regions, such as a channel semiconductor, a source / drain semiconductor, a source / drain metal, a gate metal, a dielectric layer or material, etc. In some embodiments, as shown in step 3825, such differentiating backside exposure between cells is provided using a masked exposure technique. In other embodiments, as shown in step 3858, such differentiating backside exposure between cells is provided using a blanket exposure technique.

[0147] Continuing with step 3825, such masked exposure techniques between cells may provide functional and / or structural differentiation, such that devices corresponding to exposed device regions have different functions and / or structures relative to devices having unexposed device regions. As illustrated with respect to steps 3830, 3835, and 3840, such functional and / or structural differentiation may correspond to exposing only device regions of transistors, other devices in various contexts. As illustrated with respect to step 3830, functional and / or structural differentiation between cells may correspond to exposing only device regions of logic transistors selective to device regions of memory and / or power transistors, exposing only device regions of memory transistors selective to device regions of logic and / or power transistors, exposing only device regions of power transistors selective to device regions of logic and / or memory transistors, etc. In some embodiments, such differentiation may be based on device design rules, device critical dimensions, etc. As shown with respect to step 3835, the functional and / or structural-based differentiation between the cells may correspond to exposing only device regions of selective n-type transistors relative to device regions of p-type transistors, or vice versa. As shown with respect to step 3840, the functional and / or structural-based differentiation between the cells may correspond to exposing only device regions of selective non-planar transistors (e.g., fin transistors) relative to device regions of planar transistors, or vice versa.

[0148] Furthermore, differentiation between combinations of such logic / memory / power exposure, n-type / p-type exposure, and non-planar / planar exposure is available, as shown with respect to the diagonal lines connecting steps 3830, 3835, and 3840. For example, device regions of logic n-type planar devices may be selectively exposed to memory / power n-type planar devices, logic p-type planar devices, logic n-type non-planar devices, memory / power p-type planar devices, and memory / power p-type non-planar devices, etc. To give one other example, device regions of power p-type planar devices may be selectively exposed to logic / memory p-type planar devices, power n-type planar devices, power p-type non-planar devices, logic / memory n-type planar devices, or logic / memory n-type non-planar devices. For example, such selectivity may be provided between device function types (e.g., selected from logic / memory / power), polarities (e.g., selected from n-type / p-type), and / or device structures (e.g., selected from planar / non-planar) in any arrangement. Further, additional options are available, such as differentiation between device types (e.g., transistors, resistors, diodes, etc.) and / or other structures. For example, device regions may be selectively exposed based on any suitable combination of function, type, structure, or other suitable characteristics.

[0149] Returning to the third level of method 3801, as shown in step 3855, differentiation of backside exposure between cells may be provided using blanket exposure techniques, in which the selective exposure is a function of structural differences in the device features created by frontside processing. Such blanket exposure techniques may include polishing and / or etching through the thickness of an intervening layer or layers and / or device layers to expose the first device region but not the second device region. Such blanket exposure processes are performed across the intervening layers and / or device layers without masking. In embodiments, the blanket exposure process exposes a first device region of a first device selective to the second device region based on the first device region positioned to be exposed and the second device region positioned not to be exposed by such blanket exposure process. For example, the first device region, or a portion thereof, may extend beneath (e.g., toward the backside) the second device region such that the first device region is exposed in a planarization or etching step prior to exposing the second device region. The blanket exposure process may be stopped (eg, based on timing or a marker) when the first device region is exposed and the second device region is not exposed.

[0150] As shown in step 3855, the selective blanket exposure process may rely on structural differentiation between the first and second devices with respect to the first and second device regions. The structural differentiation may be, as discussed above, a first device region extending below the second device region, a material difference between the first and second device regions, etc. In addition to the structural differentiation with respect to backside exposure (e.g., a structural differentiation in backside exposure), the first and second devices may have any suitable functional and / or other structural differences to differentiate between the cells. For example, such a structural differentiation in backside exposure may be provided between transistors of different functions, such as a first device (e.g., having a first device region whose backside is exposed) being a logic transistor and a second device (e.g., having a second device region that is not exposed) being a memory or power transistor. In embodiments, structural differences in backside exposure may be provided between transistors of different polarities, such that a first device (e.g., having a first device region whose backside is exposed) is an n-type transistor and a second device (e.g., having a second device region whose backside is not exposed) is a p-type transistor, or vice versa. In embodiments, structural differences in backside exposure may be provided between transistors of different device structures, such that a first device (e.g., having a first device region whose backside is exposed) is a non-planar transistor and a second device (e.g., having a second device region whose backside is not exposed) is a planar transistor, or vice versa. In embodiments, structural differences in backside exposure may be provided in devices that are otherwise of the same function, polarity, and / or structure.

[0151] For example, as shown with respect to steps 3830, 3835, and 3840, structural differences in backside exposure may be provided across device function type (e.g., selected from logic / memory / power), polarity (e.g., selected from n-type / p-type), and / or device structure (e.g., selected from planar / non-planar) in any arrangement. Furthermore, additional options, such as differentiation between device types (e.g., transistors, resistors, diodes, etc.) and / or other structures, are available. For example, device regions may be selectively exposed based on any suitable combination of function, type, structure, or other suitable characteristics.

[0152] Consider now the intra-cell backside exposure differentiation provided in step 3850. Such intra-cell exposure provides backside exposure of a specific device region or regions, while other device regions of other devices within the same cell remain unexposed (e.g., remain covered from the backside). The exposed device regions may be any suitable regions, such as a channel semiconductor, a source / drain semiconductor, a source / drain metal, a gate metal, a dielectric layer or material, etc. Also, as shown with respect to the diagonal line connecting steps 3820 and 3850, such inter-cell and intra-cell exposure differentiation may be used in various combinations. For example, differentiation may be such that no device region of a first cell is exposed, while a specific device region of a second cell is exposed. Such differentiation provides inter-cell differentiation between the first cell and the second cell. Furthermore, within the second cell, a specific device region of the first device is exposed, while a device region of the second device is not exposed. Such differentiation between the first and second devices in the second cell provides intra-cell differentiation between the first and second devices of the second cell. While described with respect to differentiation between two cells using one cell having two device types, such differentiation may be provided at an inter-cell level between any number of cell types, and at an intra-cell level with differently exposed cells being differentially exposed on an intra-cell basis. For example, of three cell types, one may be completely unexposed, and the second and third may be exposed such that all devices of the second cell type have exposed device areas, while intra-cell differentiation is provided within the third cell (e.g., some devices in the third cell are unexposed, while other devices have exposed device areas).

[0153] In some embodiments, as shown in step 3825, masked exposure techniques facilitate backside exposure differentiation. Furthermore, such masked exposure techniques may provide functional and / or structural differentiation, such that devices corresponding to exposed regions have different functions relative to devices having unexposed regions. For example, as shown with respect to step 3830, intra-cell functional and / or structural differentiation may correspond to exposing only device regions of logic transistors selective to device regions of memory and / or power transistors, exposing only device regions of memory transistors selective to device regions of logic and / or power transistors, or exposing only device regions of power transistors selective to device regions of logic and / or memory transistors, etc. In some embodiments, such differentiation may be based on device design rules, device critical dimensions, etc. As shown with respect to step 3835, intra-cell functional and / or structural differentiation may correspond to exposing only device regions of n-type transistors selective to device regions of p-type transistors, or vice versa. As shown with respect to step 3840, intra-cell functional-based and / or structural-based differentiation may correspond to exposing only device regions of selective non-planar transistors (e.g., fin transistors) relative to device regions of planar transistors, or vice versa.

[0154] Furthermore, as described with respect to differentiation between cells, and as indicated with respect to the diagonal lines connecting steps 3830, 3835, and 3840, differentiation between combinations of logic / memory / power exposure, n-type / p-type exposure, and non-planar / planar exposure is available on an intra-cell basis. For example, such selectivity may be provided between device functional types (e.g., selected from logic / memory / power), polarities (e.g., selected from n-type / p-type), and / or device structures (e.g., selected from planar / non-planar) in any arrangement. Furthermore, additional options are available, such as differentiation between device types (e.g., transistors, resistors, diodes, etc.) and / or other structures. For example, device regions may be selectively exposed based on any suitable combination of function, type, structure, or other suitable characteristics.

[0155] Referring again to the third level of method 3801, as shown in step 3855, differential backside exposure within a cell can be provided using a blanket exposure technique. As discussed above, such blanket exposure techniques may include polishing and / or etching through the thickness of an intervening layer or layers and / or device layers to expose a first device region without exposing a second device region. The blanket exposure process may expose a first device region of a first device selectively to a second device region of a second device based on the location of the first device region that was left exposed and the second device region that was left unexposed by such blanket exposure process. For example, in a planarization or etching step, the first device region, or a portion thereof, may extend below (e.g., toward the backside) the second device region such that the first device region is exposed before the second device region is exposed. The blanket exposure process may be stopped (eg, based on timing or a marker) when the first device region is exposed and the second device region is not exposed.

[0156] With respect to intra-cell differentiation, the blanket exposure process may rely on structural differentiation between the first and second devices with respect to the first and second device regions. The structural difference may be, for example, a first device region extending below the second device region, or a material difference between the first and second device regions, as discussed above. In addition to structural differences with respect to backside exposure (e.g., structural differences in backside exposure), the first and second devices may have any suitable functional and / or other structural differences to provide intra-cell differentiation. For example, such structural differences in backside exposure may be provided between transistors of different functions, such as a first device (e.g., having a first device region whose backside is exposed) being a logic transistor and a second device (e.g., having a second device region that is not exposed) being a memory or power transistor. In embodiments, structural differences in backside exposure may be provided between transistors of different polarities, such that a first device (e.g., having a first device region whose backside is exposed) is an n-type transistor and a second device (e.g., having a second device region whose backside is not exposed) is a p-type transistor, or vice versa. In embodiments, structural differences in backside exposure may be provided between transistors of different device structures, such that a first device (e.g., having a first device region whose backside is exposed) is a non-planar transistor and a second device (e.g., having a second device region whose backside is not exposed) is a planar transistor, or vice versa. In embodiments, structural differences in backside exposure may be provided in devices that are otherwise of the same function, polarity, and / or structure.

[0157] For example, as shown with respect to steps 3830, 3835, and 3840, structural differentiation may be provided across device function type (e.g., selected from logic / memory / power), polarity (e.g., selected from n-type / p-type), and / or device structure (e.g., selected from planar / non-planar) in any arrangement. Further, additional options are available, such as differentiation between device types (e.g., transistors, resistors, diodes, etc.) and / or other structures. For example, device regions may be selectively exposed based on any suitable combination of function, type, structure, or other suitable characteristics.

[0158] As discussed above, in some embodiments, backside exposure is based on the function and / or structure of devices within such regions, defining such regions, or interspersed throughout the donor-host substrate assembly. For example, backside exposure may provide selective exposure between logic devices and memory devices, between logic devices and power devices, between memory devices and power devices, or may otherwise be provided based on device function or device critical dimensions (e.g., in step 3830). In other examples, backside exposure provides selective exposure between n-type and p-type devices (e.g., step 3835), between fin or non-planar-based devices and planar devices (e.g., step 3840), etc. Additionally, other device-type-based backside exposure options are available.

[0159] As described with respect to step 3815, in some embodiments, partial backside exposure is provided based on a masked exposure. For example, such techniques may include selectively removing material (e.g., via etching, etc.) from unexposed masked areas, regions, IC cells or subcells, etc., and from unmasked areas, regions, cells, subcells, etc. Such techniques may provide selective backside exposure between cells (e.g., between cells), between cells (e.g., within a cell), between devices of different functions, between devices having different structures, etc.

[0160] Further, as shown with respect to step 3855, in some embodiments, partial backside exposure is provided by a blanket exposure process. In such embodiments, no masking needs to be provided, and backside exposure may be provided based on structural differences (e.g., structural differences in backside exposure) between devices that have exposed regions and those that do not have unexposed regions. For example, blanket exposure may provide selective backside exposure based on structural differences between exposed and unexposed devices. Such structural differences may be between devices in different cells or subcells, etc., and they may be provided between the same or different devices. Such different devices may differ in function, structure other than the structural differences in backside exposure, etc.

[0161] Various branches of method 3801 provided by steps 3815, 3820, 3850, 3825, 3855, 3830, 3858, 3836, 3835, and 3840 may be implemented to generate a range of device layer-host substrate assemblies output at step 130. For example, steps 3805, 3815, 3820, 3825, 3830, and 130 may provide partial backside exposure (e.g., at step 3815) of the received donor-host substrate assembly (e.g., received at step 3805) to provide backside exposure differentiation (e.g., at step 3820) between cells: logic and memory and / or power transistors, memory and logic and / or power transistors, and power and logic and / or memory transistors (e.g., at step 3830). Steps 3805, 3815, 3850, 3825, 3835, and 130 provide partial backside exposure (e.g., in step 3815) of the received donor-host substrate assembly (e.g., received in step 3805) to provide backside exposure differentiation (e.g., in step 3825) within the cells between n-type and p-type transistors (e.g., in step 3830). As shown, a wide variety of other processes are available.

[0162] For example, FIG. 38A illustrating method 3801 may be read to provide the following options for providing selective backside exposure (e.g., of one device region selective to another device region) for a received donor-host substrate assembly (e.g., received in step 3805): Either or both of wafer-level full backside exposure and partial backside exposure may be performed (e.g., in L1 steps 3810 and 3815). Differentiation of backside exposure between and / or within cells may be provided (e.g., in L2 steps 3820 and 3850). Such inter- or intra-cell level differentiation may be provided by mask and / or blanket exposure (e.g., in L3 steps 3825 and 3855). Masked exposure may provide functional- and / or structural-based differentiation in backside exposure. The differentiation (e.g., between cells or within cells) provided by the selective backside exposure (e.g., using a masked or blanket exposure) may provide differentiation between logic / memory / power transistors, between n-type and p-type transistors, between planar and non-planar transistors, or any combination thereof. As shown, the output of the device layer-host substrate assembly with selective backside exposure and / or additional processing is provided in step 130.

[0163] The discussion now turns to specific example techniques further illustrating method 3801. A first embodiment is provided with respect to Figures 38B and 39-45C, and a second embodiment is provided with respect to Figures 38C and 46-54C. The example techniques described with respect to such embodiments may be extended to any specific method or branch of method 3801.

[0164] FIG. 38B is a flow diagram 3802 illustrating a method for forming backside transistor source / drain semiconductor and contact metallization for non-planar transistors selective to planar transistors, according to some embodiments. Method 3802 begins with a donor-host substrate assembly including planar and non-planar transistor structures as input 3806. The donor substrate may have one or more of the features described herein, such as, but not limited to, an intervening layer and a carrier layer. However, a carrier layer is not required to perform method 3802. The non-planar and / or planar transistor structures at the input of method 3802 may be fully operational, for example. Alternatively, one or more terminals may be absent such that the non-planar transistor structure is not operational until backside processing is complete.

[0165] 39 is a plan view of a non-planar transistor structure 1304 lacking one source / drain metallization 650 and a planar transistor structure 3904 having both source / drain metallization 650, according to some embodiments. The thick dashed-dotted lines shown with respect to the non-planar transistor structure 1304 indicate aspects further provided as cross-sectional views in FIGS. 40A-40C, 42A-42C, and 44A-44C. Similarly, the thick dashed-dotted lines shown with respect to the planar transistor structure 3904 indicate aspects further provided as cross-sectional views in FIGS. 41A-41C, 43A-43C, and 45A-45C. Using the techniques described herein and shown with respect to method 3802, selective backside processing can provide the non-planar transistor structure 1304 without providing backside processing for the planar transistor structure 3904.

[0166] 38B , the selective backside processing provided by method 3802 provides backside exposure of the source / drain semiconductor 640 (e.g., a first device region) of the non-planar transistor structure 1304 (e.g., a first device). Furthermore, the selective backside processing provided by method 3802 is selective to the planar transistor structure 3904 (e.g., a second device), thereby exposing the backside of the source / drain semiconductor 640 of the non-planar transistor structure 1304 selective to each device region of the planar transistor structure 3904. For example, the selective backside exposure of the source / drain semiconductor 640 of the non-planar transistor structure 1304 is selective to the source / drain semiconductor 640, the source / drain metallization 650, the spacer dielectric 671 separating the gate electrode 673 from the source / drain metallization 650 and / or the source / drain semiconductor 640, the field isolation dielectric 680, and the device layer 215 of the planar transistor structure 3904. Although described with respect to selective backside exposure of the source / drain semiconductor 640 of the non-planar transistor structure 1304 selective to the planar transistor structure 3904, the method 3802 may provide selective backside exposure of any one or more device regions of the planar transistor structure 3904 selective to any one or more device regions of the non-planar transistor structure 1304. Furthermore, the method 3802 may provide selective backside exposure of any one or more device regions of the non-planar transistor structure 1304 selective to any one or more device regions of the planar transistor structure 3904.

[0167] Additionally, method 3802 may provide for disposing (e.g., by deposition, etc.) one or more non-native materials over the exposed source / drain semiconductor 640 (e.g., exposed first device regions). In an example of method 3802, a backside source / drain semiconductor 1640 and a backside source / drain metallization 1650 are disposed over the exposed (e.g., backside exposed) source / drain semiconductor 640. Although described with respect to disposing the backside source / drain semiconductor 1640 and the backside source / drain metallization 1650 over the source / drain semiconductor 640, any suitable non-native material may be disposed over any exposed device region. For example, the non-native material or materials may include a semiconductor material, a metallic material, or a dielectric material.

[0168] 39, in some embodiments, non-planar transistors and planar transistors may be integrated on the same integrated circuit. For example, non-planar transistor structure 1304 and planar transistor structure 3904 may be integrated on IC die 601. Planar transistor structure 3904 exhibits similar structures, such as numbers, relative to non-planar transistor structure 1304. For example, planar transistor structure 3904 includes gate electrode 673, source / drain semiconductor 640, source / drain metallization 650, spacer dielectric 671 separating gate electrode 673 and / or source / drain semiconductor 640 from source / drain metallization 650, field isolation dielectric 680, and device layer 215. As can be seen, in contrast to non-planar transistor structure 1304, gate electrode 673 (and gate dielectric 845 in FIG. 41A ) is not disposed around the channel region of the transistor channel.

[0169] Advantageously, the absence of source or drain metallization 650 for the non-planar transistor structure 1304 relaxes pitch and / or critical dimension restrictions on the source / drain metallization 650 and / or other front-side metallization levels (e.g., gate electrode 673 or higher metallization levels). The absence of source or drain metallization 650 may render the non-planar transistor structure 1304 inoperable until a third terminal connection is fabricated, for example, using backside transistor source / drain contact metallization method 3802 (FIG. 38B). Such backside transistor source / drain contact metallization may provide a power rail (e.g., V cc ) may be coupled to the backside of the transistor structure, advantageously placing power (source) and signal (gate electrode voltage) routing on both sides of the transistor structure hierarchy. In particular, the selective backside transistor source / drain contact metallization method 3802 may be implemented for transistor structures that are fully functional when fabricated from the front side (e.g., including all device terminals). For such embodiments, the backside transistor source / drain contact metallization method 3802 may be implemented to wrap the source / drain transistor terminals to interconnect traces located on both sides of the transistor hierarchy, advantageously reducing source / drain contact resistance and / or allowing the source / drain device regions of the transistor to be circuit nodes that fan out directly to at least two other circuit nodes.

[0170] As described further herein and illustrated with respect to Figures 40A-45C, during such backside transistor source / drain contact metallization of the non-planar transistor structure 1304, the planar transistor structure 3904 is masked and selectively unexposed (e.g., the device region of the planar transistor structure 3904 is not exposed during backside exposure of the source / drain semiconductor 640 of the non-planar transistor structure 1304). For example, the selective backside transistor source / drain contact metallization method 3802 may be performed on the planar transistor structure 3904 such that the planar transistor structure is fully functional when fabricated from the front side (e.g., including all device terminals) and backside processing of the non-planar transistor structure 1304 does not affect the functionality of the planar transistor structure 3904.

[0171] Returning to FIG. 38B , in step 3808, the backside of the device layer (e.g., the intervening layer or layers) is exposed by removing the carrier layer. In some further embodiments, portions of any intervening layers and / or frontside materials deposited above the device layer may be removed during exposing step 3808. As described elsewhere herein in the context of some illustrative embodiments, the intervening layer may facilitate highly uniform exposure of the backside of the device layer, for example, functioning as one or more of an etch marker or etch stop used in wafer-level backside exposure processes. For example, the intervening layer may separate the device layer from the removed carrier layer such that the intervening layer was in direct contact with both the carrier layer and the device layer prior to removal. As discussed previously, in some embodiments, the donor-host substrate assembly including the planar and non-planar transistor structures received in step 3806 does not include a carrier layer; in such embodiments, step 3808 may be omitted.

[0172] Method 3802 proceeds to step 3812, where the backside of the planar transistor structure is masked. Such selective masking of the backside of the planar transistor structure provides selective exposure or access to the backside of the non-planar transistor structure (e.g., access to the backside of selective device regions of the non-planar transistor structure). Further, in step 3812, portions of the backside of the non-planar transistor may be masked to provide selective access to particular structures of the non-planar transistor (e.g., source / drain semiconductor regions). The mask provided in step 3812 may include any suitable mask applied using any suitable technique or techniques.

[0173] Method 3802 proceeds to step 3818, where a backside of a source / drain region of at least one non-planar transistor in the non-planar transistor structure is exposed. In some embodiments, a backside recess etch is performed in step 3818 such that the backside recess etch has a patterning provided by the mask applied in step 3812. The backside recess etch may expose the source / drain semiconductor region (e.g., a first device region) of the non-planar transistor structure (e.g., a first device) selectively to other regions of the non-planar transistor structure (e.g., those device regions not exposed) and selectively to a device region (e.g., a second region or regions) of the planar transistor structure (e.g., a second device). As discussed above, selectivity to a device region of a planar transistor structure may be provided selectively to the entire planar transistor structure (e.g., all device regions).

[0174] Once the selective source / drain semiconductor regions of the non-planar transistor structure are exposed, method 3802 completes with step 3826, in which source / drain semiconductor of a non-native material is deposited from the backside on or above the exposed source / drain regions of the non-planar transistor, and / or contact metallization is deposited above the source / drain semiconductor added from the backside. Source / drain semiconductor and / or contact metallization are examples of non-native materials that may be disposed above the exposed semiconductor regions on the backside. As shown, step 3826 outputs a non-planar transistor structure having contact metallization above the backside source / drain semiconductor integrated with the planar transistor structure that was not selectively exposed by such backside processing.

[0175] 40A, 42A, and 44A show cross-sectional views of the non-planar transistor structure 1304 along the A-A' plane shown in FIG. 39 when steps in method 3802 are performed according to some embodiments. 41A, 43A, and 45A show cross-sectional views of the planar transistor structure 3904 along the A-A' plane shown in FIG. 39 when steps in method 3802 are performed according to some embodiments. 40B, 42B, and 44B show cross-sectional views of the non-planar transistor structure 1304 along the B-B' plane shown in FIG. 39 when steps in method 3802 are performed according to some embodiments. 41B, 43B, and 45B show cross-sectional views of the planar transistor structure 3904 along the B-B' plane shown in FIG. 39 when steps in method 3802 are performed according to some embodiments. Figures 40C, 42C, and 44C show cross-sectional views of the non-planar transistor structure 1304 along the CC' plane shown in Figure 39 when steps in method 3802 are performed according to some embodiments. Figures 41C, 43C, and 45C show cross-sectional views of the planar transistor structure 3904 along the CC' plane shown in Figure 39 when steps in method 3802 are performed according to some embodiments.

[0176] 40A-40C illustrate cross-sectional views of structures present in exemplary non-planar transistor structure 1304 after front-side processing and / or optional carrier removal, according to some embodiments. The structural features illustrated in FIGS. 40A-40C may have any of the characteristics described herein with reference to like reference numerals. Additionally, FIGS. 41A-41C illustrate structures present in exemplary planar transistor structure 3904 after front-side processing and / or optional carrier removal. The structural features illustrated in FIGS. 41A-41C may have any of the characteristics described herein with reference to like reference numerals. For example, FIGS. 40A-40C and 41A-41C illustrate cross-sectional views of non-planar transistor structure 1304 and planar transistor structure 3904 after step 3806 of method 3802 has been performed (see FIG. 38B).

[0177] 42A-42C and 43A-43C, etch mask 1410 (e.g., a patterned mask) is aligned with the backside structure of non-planar transistor structure 1304 and planar transistor structure 3904. Additionally, a substantial portion of intervening layer 210 and transistor semiconductor body 610 (e.g., part of device layer 215) is removed to provide selectively exposed recess 1540 within the unmasked portions defined by etch mask 1410. In alternative embodiments where there are structural differences (e.g., depth differences) between source / drain regions, etch mask 1410 may be limited to protect only structure 3904 with processing of structure 1304, as described elsewhere in the context of FIGS. 14D, 15D, and 16D.

[0178] As shown, the etch mask 1410 masks the entire backside of the planar transistor structure 3904 (see FIGS. 43A-43C). Additionally, the etch mask 1410 exposes portions of the backside of the non-planar transistor structure 1304 that allow access to or exposure of the source / drain semiconductor 640 through selective exposure recesses 1540 (see FIGS. 42A-42C). Alignment 640 to the source / drain semiconductor need not be precise, so that overlap with the gate electrode 673 can be minimized or avoided. As previously discussed, the etch mask 1410 may be another intervening layer of the backside substrate and may be deposited after exposing the intervening layer 210, a soft mask (e.g., a photosensitive resist) applied over the backside surface of the intervening layer 210, or the like. As discussed above, the device areas that are not to be patterned (e.g., unmasked or exposed areas) are then recess etched using any wet and / or plasma etching process known to be suitable for the applicable material composition.

[0179] Furthermore, after removal of the intervening layer 210 and a substantial portion of the transistor semiconductor body 610, the sub-fin height H sf The selective exposure recess 1540 may be of any depth and lateral dimension. For example, the selective exposure recess 1540 may completely remove a sub-fin portion of the semiconductor body 610 (e.g., the semiconductor portion of the intervening layer 210) to expose the source / drain semiconductor 640. As shown, the etching mask 1410 masks the entire backside of the planar transistor structure 3904 (see Figures 43A-43C). For example, Figures 42A-42C and 43A-43C show cross-sectional views of the non-planar transistor structure 1304 and the planar transistor structure 3904, respectively, after steps 3812 and 3818 (Figure 38B) have been performed.

[0180] 44A-44C and 45A-45C show the non-planar transistor structure 1304 and the planar transistor structure 3904 after epitaxial growth or deposition of a p-type or n-type impurity doped backside source / drain semiconductor 1640 and subsequent deposition of a backside source / drain metallization 1650. As shown, the backside source / drain semiconductor 1640 is disposed adjacent to or above the source / drain semiconductor 640. The backside source / drain semiconductor 1640 may be disposed above the source / drain semiconductor 640 using any suitable technique or techniques, such as an epitaxial growth process, a deposition process, etc. For example, the same epitaxial or deposition process used to form the source / drain semiconductor 640 may be used to form the backside source / drain semiconductor 1640. The backside source / drain semiconductor 1640 may be any suitable material, such as, but not limited to, a Group IV semiconductor (e.g., Si, Ge, SiGe) and / or a Group III-V semiconductor (e.g., InGaAs, InA) and / or a Group III-N semiconductor (e.g., InGaN).

[0181] Also as shown, backside source / drain metallization 1650 is disposed adjacent to or above backside source / drain semiconductor 1640. Backside source / drain metallization 1650 may be disposed above source / drain semiconductor 1640 using any suitable technique or techniques, such as a metal deposition process. For example, the same deposition process used to form backside source / drain metallization 650 may be used to form backside source / drain metallization 1650. Backside source / drain metallization 650 may comprise any suitable material, such as Ti, W, Pt, or alloys thereof. Also as shown in FIGS. 45A-45C , planar transistor structure 3904 may remain masked by etch mask 1410 such that neither backside source / drain semiconductor nor backside source / drain contact metallization is provided on planar transistor structure 3904. For example, backside source / drain semiconductor 1640 and backside source / drain metallization 1650 of non-native material may be selectively provided to non-planar transistor structure 1304, while not being added to planar transistor structure 3904. For example, Figures 42A-42C and 43A-43C show cross-sectional views of non-planar transistor structure 1304 and planar transistor structure 3904, respectively, after step 3826 (Figure 38B) has been performed.

[0182] 44A-44C and 45A-45C, the excess overburden of the backside metallization is removed by polishing (e.g., CMP) using the source / drain contact metallization to re-expose the etch mask 1410 and / or the intervening layer 210, thereby confining by backfilling the selectively exposed recesses 1540. Subsequent backside processing may further include fabrication of one or more backside interconnect metallization levels (not shown) that electrically couple at least the source / drain metallization 1650. In some such embodiments, such backside interconnect metallization is of a different composition than the frontside interconnect metallization level and / or has a greater lateral dimension or thickness than the corresponding level of frontside interconnect metallization. For example, relative to the backside interconnect metallization, the frontside interconnect metallization may be predominantly copper (e.g., mostly Cu or a Cu-rich alloy) with a high percentage of Cu. The backside interconnect metallization may instead be predominantly non-copper (e.g., a Cu-lean alloy or a Cu-free alloy that is not predominantly Cu). The frontside interconnect metallization may similarly be predominantly non-copper, while the backside interconnect metallization may be predominantly copper. If the interconnect metallization is not copper-based, the backside interconnect metallization may be any other suitable metal / metal alloy, including one or more of Ru, Rh, Pd, Ir, Pt, Au, W, Cr, or Co. Separation of metallization composition between the frontside and backside of a device hierarchy is advantageous in that it may compartmentalize the use of different material systems and interconnect technologies between the frontside (e.g., Ru) and backside processes (e.g., Cu).

[0183] The dimensions and / or thickness of the lateral interconnects for any level (e.g., metal 1, metal 2, etc.) may differ between the front and back sides of the device hierarchy. For example, a power line coupled to a source terminal of a transistor via a backside interconnect metallization may have a larger lateral dimension (e.g., linewidth) and / or thickness than a front-side interconnect metallization coupled to a gate and / or drain terminal of the transistor via the front-side interconnect metallization. The distinction in size and thickness between the front-side interconnect metallization and the backside interconnect metallization may advantageously provide flexibility in the interconnect fabrication process. In some embodiments where the backside interconnect metallization has a larger lateral dimension and / or thickness, the backside interconnect metallization is copper-based, while the front-side interconnect metallization of a smaller lateral dimension and / or thickness is other than copper (e.g., Ru-based).

[0184] Using the described techniques, backside exposure of the source / drain semiconductor 640 of the non-planar transistor structure 1304 is selective to the device region of the planar transistor structure 3904. Such masked exposure techniques may be extended to expose any device region (e.g., channel, gate dielectric, gate electrode, etc.) of the non-planar transistor structure 1304 selective to any device region of the planar transistor structure 3904, or vice versa. Furthermore, such selective exposure processes may be inter-cell base, intra-cell base, or area base (as shown). Such selective exposure processes provide differentiation between non-planar and planar transistors. Such non-planar and planar transistors may be distinguished based on function and / or polarity, as described herein. In embodiments, the non-planar transistors are logic transistors, and the planar transistors are memory and / or power transistors.

[0185] FIG. 38C is a flow diagram 3803 illustrating a method for forming backside transistor source / drain semiconductor and contact metallization of a non-planar transistor selective to other non-planar transistors, according to some embodiments. Method 3803 begins with a donor-host substrate assembly including first and second (e.g., power and logic) non-transistor structures as input 3807. The donor substrate may have one or more of the features described herein, such as, but not limited to, an intervening layer and a carrier layer. However, the carrier layer and / or the intervening layer are not required to perform method 3803. The non-planar power and / or non-planar logic transistor structures at the input of method 3803 may be fully operational, or one or more terminals may be absent such that the non-planar transistor structures are not operational until backside processing is complete.

[0186] 46 is a plan view of a non-planar (e.g., power) transistor structure 1304 lacking one source / drain metallization 650 and a non-planar (e.g., logic) transistor structure 604 having both source / drain metallization 650, according to some embodiments. The thick dashed-dotted lines shown with respect to the non-planar (e.g., power) transistor structure 1304 indicate aspects further provided as Figures 48A-48C, 50A-50C, 52A-52C, and 54A-54C along cross-sectional views. Similarly, the thick dashed-dotted lines shown with respect to the non-planar (e.g., logic) transistor structure 604 indicate aspects further provided as Figures 47A-47C, 49A-49C, 51A-51C, and 53A-53C along cross-sectional views. Referring to method 3802, using the techniques described herein, selective backside processing can provide the non-planar transistor structure 1304 without providing backside processing to the non-planar transistor structure 1304.

[0187] 38C , the backside processing provided by method 3803 provides backside exposure of the source / drain semiconductor 640 (e.g., first device region) of non-planar transistor structure 1304 (e.g., first device) such that the backside processing is selective to non-planar transistor structure 604 (e.g., second device), thereby exposing the backside of the source / drain semiconductor 640 of non-planar transistor structure 1304 selective to each device region of non-planar transistor structure 604. The backside exposure of the source / drain semiconductor 640 of non-planar transistor structure 1304 is selective to the source / drain semiconductor 640, the source / drain metallization 650, the spacer dielectric 671 separating the gate electrode 673 from the source / drain metallization 650 and / or source / drain semiconductor 640, the field isolation dielectric 680, and the device layer 215 of non-planar transistor structure 604. Method 3803 may alternatively provide selective backside exposure of any one or more device regions of non-planar transistor structure 604 selective to any one or more device regions of non-planar transistor structure 1304. Additionally, method 3803 may provide selective backside exposure of any one or more device regions of non-planar (e.g., power) transistor structure 1304 selective to any one or more device regions of non-planar (e.g., logic) transistor structure 604.

[0188] Additionally, as shown with respect to step 3834, method 3803 may form (e.g., by deposition, etc.) one or more non-native materials onto the exposed source / drain semiconductor 640 (e.g., exposed first device regions). In an example of method 3803, backside source / drain semiconductor 1640 and backside source / drain metallization 1650 are disposed over the exposed (e.g., exposed backside) source / drain semiconductor 640. Any suitable non-native material may be disposed over any exposed device regions using method 3803. For example, the non-native material or materials may include a semiconductor material, a metallic material, or a dielectric material.

[0189] As shown in Figure 46, in some embodiments, non-planar power transistors and non-planar logic transistors may be integrated on the same integrated circuit. For example, non-planar transistor structure 1304 and non-planar transistor structure 604 may be integrated on IC die 601 as power and logic transistors, respectively. In Figure 46, non-planar transistor structure 604, as well as numbers related to non-planar transistor structure 1304, indicate similar structures with respect to other descriptions herein.

[0190] As described with respect to FIG. 39 , if there is no source or drain metallization 650 in a non-planar transistor structure 1304, pitch and / or critical dimension restrictions for the source / drain metallization 650 and / or other front-side metallization levels may be relaxed, and the absence of source or drain metallization 650 may render the non-planar (e.g., power) transistor structure 1304 inoperable until a third terminal connection is fabricated. Such backside transistor source / drain contact metallization may couple power rails to the power transistor structure and establish power and signal (gate electrode voltage) routing on both sides of the transistor structure hierarchy. Alternatively, an optional backside transistor source / drain contact metallization method 3803 may be performed on a transistor structure that is fully functional when fabricated from the front side, such that the backside transistor source / drain contact metallization method 3802 may be performed to wrap source or drain transistor terminals to interconnect traces located on both sides of the transistor hierarchy.

[0191] 47A-54C, the non-planar (e.g., logic) transistor structure 604 is masked and left unexposed during such backside transistor source / drain contact metallization of the non-planar (e.g., power) transistor structure 1304. For example, a selective backside transistor source / drain contact metallization method 3803 may be performed on the non-planar transistor structure 604 so that the non-planar power transistor structure is fully functional when fabricated from the front side and backside processing of the non-planar transistor structure 1304 does not affect the functionality of the non-planar transistor structure 604.

[0192] Returning to FIG. 38C , in step 3809, the device layer (e.g., the intervening layer or layers) is exposed by removing the carrier layer. In some embodiments, portions of any intervening layer and / or front-side material deposited above the device layer may be removed during step 3809. As described herein, the intervening layer may facilitate more uniform exposure of the backside of the device layer. For example, the intervening layer may separate the device layer from the removed carrier layer such that the intervening layer was in direct contact with both the carrier layer and the device layer prior to removal. As discussed above, in some embodiments, the donor-host substrate assembly including the non-planar logic transistor structure and the non-planar power transistor structure received in step 3807 does not include a carrier layer, and step 3808 may be omitted.

[0193] Method 3802 proceeds to step 3813, where at least a thickness of the exposed intervening layer is removed. In an example of method 3802, the exposed thickness of the intervening layer is removed by a polishing process. However, the exposed thickness of the intervening layer may be removed using any suitable technique or techniques. For example, the intervening layer or one or more component layers of the intervening layers may be removed. In an embodiment, the thickness of the intervening layer is uniformly removed by the polishing process. In an embodiment, the thickness of the intervening layer is removed using a mask or blanket etch process. Step 3813 may use the same polishing and / or etch process used to remove the carrier layer in step 3809, or step 3813 may be a separate process using separate process parameters. For example, the intervening layer provides an etch stop for the carrier removal process, and step 3813 may use a different polishing or etch process.

[0194] The method 3802 proceeds to step 3819, where a backside isolation dielectric is disposed over the backside of the non-planar logic transistor structure and the non-planar power transistor structure. The backside isolation dielectric may be disposed over the backside of the non-planar logic transistor structure and the non-planar power transistor structure using any suitable technique or techniques, for example, a dielectric deposition technique. Furthermore, the backside isolation dielectric may be any suitable material, for example, silicon dioxide, silicon nitride, SiOC, SiOCH, HSQ, MSQ, SiON, etc.

[0195] Method 3802 proceeds to step 3825, where a backside of at least one source / drain region in the non-planar power transistor structure is exposed selectively to the non-planar logic transistor structure. In some embodiments, the backside isolation dielectric is patterned to form an etch mask, and a backside recess etch is performed in step 3825, such that the backside recess etch has a pattern defined by the etch mask. Patterning the backside isolation dielectric to create the etch mask may be performed using any suitable patterning technique, e.g., lithography techniques. Furthermore, the backside recess etch may be performed using any suitable technique, e.g., wet or dry etching techniques. The backside recess etch may expose the source / drain semiconductor regions (e.g., first device regions) of the non-planar power transistor structure (e.g., first device) selectively to other regions of the non-planar power transistor structure (e.g., those device regions not exposed) and selectively to the device regions (e.g., second region or regions) of the non-planar logic transistor structure (e.g., second device). As discussed above, selectivity to the device regions of the non-planar logic transistor structure may be provided selectively to the entire non-planar logic transistor structure (e.g., all device regions).

[0196] Once the selective source / drain semiconductor regions of the non-planar power transistor structure are exposed, method 3803 completes with step 3834, in which source / drain semiconductor of a non-native material is deposited from the backside on or above the exposed source / drain regions of the non-planar power transistor, and / or contact metallization is deposited above the added source / drain semiconductor from the backside. Source / drain semiconductor and / or contact metallization are examples of non-native materials that may be disposed above the exposed backside semiconductor regions. As shown, step 3834 outputs a non-planar power transistor structure having terminal backside metallization above the backside source / drain semiconductor integrated with the non-planar logic transistor structure not selectively exposed by such backside processing.

[0197] 47A, 49A, 51A, and 53A show cross-sectional views of the non-planar transistor structure 1304 along the A-A' plane shown in FIG. 46 when steps in method 3803 are performed, according to some embodiments. 48A, 50A, 52A, and 54A show cross-sectional views of the non-planar transistor structure 604 along the A-A' plane shown in FIG. 46 when steps in method 3803 are performed, according to some embodiments. 47B, 49B, 51B, and 53B show cross-sectional views of the non-planar transistor structure 1304 along the B-B' plane shown in FIG. 46 when steps in method 3803 are performed, according to some embodiments. 48B, 50B, 52B, and 54B show cross-sectional views of the non-planar transistor structure 604 along the B-B' plane shown in FIG. 46 when steps in method 3803 are performed, according to some embodiments. Figures 47C, 49C, 51C, and 53C show cross-sectional views of non-planar transistor structure 1304 along the CC' plane shown in Figure 46 when steps in method 3803 are performed according to some embodiments. Figures 48C, 50C, 52C, and 54C show cross-sectional views of non-planar transistor structure 604 along the CC' plane shown in Figure 46 when steps in method 3803 are performed according to some embodiments.

[0198] 47A-47C show cross-sectional views of structures present in an exemplary non-planar transistor structure 1304 after front-side processing and / or optional carrier removal, according to some embodiments. In some embodiments, the non-planar transistor structure 1304 is a power transistor. The structural features shown in FIGS. 47A-47C may have any of the characteristics described herein with reference to like reference numbers. FIGS. 48A-48C show structures present in an exemplary non-planar transistor structure 604 after front-side processing and / or optional carrier removal. In some embodiments in which the non-planar transistor structure 1304 is a power transistor, the non-planar transistor structure 604 is a logic transistor. The structural features shown in FIGS. 41A-41C may have any of the characteristics described herein with reference to like reference numbers. For example, Figures 47A-47C and 48A-48C show cross-sectional views of non-planar transistor structures 1304 and 604 after step 3809 (Figure 38C) has been performed.

[0199] 49A-49C and 50A-50C, the backside 1012 of semiconductor body 610 and / or other structures, e.g., non-planar transistor structure 1304 and field isolation dielectric 680 of non-planar transistor structure 604, is exposed by removal of intervening layer 210. Such exposure may be performed using any suitable technique or techniques. For example, to expose the backside of transistor semiconductor body 610, the portion of the bulk semiconductor to which transistor semiconductor body 610 is anchored may be polished and / or recess-etched using wet and / or dry etching processes, e.g., as described herein with respect to step 510 (see FIG. 5). In some embodiments, the backside polishing of intervening layer 210 may be stopped when polished field isolation dielectric 680 is exposed. Any amount of overetching (or overpolishing) may further thin the sub-fin portion of semiconductor body 610 and the adjacent device layers, including field isolation dielectric 680, thereby increasing sub-fin height H. sf49A-49C and 50A-50C show cross-sectional views of non-planar transistor structure 1304 and non-planar transistor structure 604 after step 3813 of method 3803 has been performed (see FIG. 38C).

[0200] 51A-51C and 52A-52C, an etch mask 1410 (e.g., a patterned mask) is aligned to the backside structure of non-planar transistor structure 1304 and non-planar transistor structure 604. Additionally, removal of a substantial portion of transistor semiconductor body 610 (e.g., a portion of device layer 215) is performed to provide a selectively exposed recess 1540 within the unmasked portion provided by etch mask 1410.

[0201] In the context of Figures 51A-51C and 52A-52C, the etch mask 1410 is a hard mask layer and a dielectric layer that remains to be isolated. The etch mask 1410 may be provided using any suitable technique or techniques. In an embodiment, a backside isolation dielectric (e.g., backside isolation dielectric 1120) is deposited over the exposed backside. The backside isolation dielectric is an example of a non-native material that replaces a portion of the intervening layer that was removed to expose the transistor semiconductor region. The backside isolation dielectric may be any dielectric material suitable for transistor electrical isolation, such as silicon dioxide, a low-k material, a material with a dielectric constant less than that of the field isolation dielectric 680, a material with a dielectric constant less than 3.9 or less than 3.5, SiOC, SiOCH, HSQ, MSQ, SiN, or SiON. The backside isolation dielectric is then patterned to provide the etch mask 1410.

[0202] As shown, the etch mask 1410 masks the entire non-planar transistor structure 604 (see FIGS. 51A-51C). Additionally, the etch mask 1410 exposes a backside portion of the non-planar transistor structure 1304, allowing access to or exposure of the source / drain semiconductor 640 through a selectively exposed recess 1540 (see FIGS. 52A-52C). Alignment 640 to the source / drain semiconductor need not be precise, so that overlap with the gate electrode 673 can be minimized or avoided. As discussed above, the etch mask 1410 may be an isolation dielectric deposited after exposure of the backside 1012. Also, as discussed above, the device regions that are not to be patterned (e.g., the unmasked or exposed regions) are then recess-etched using any wet and / or plasma etching process known to be suitable for the applicable material composition.

[0203] After removal of a substantial portion of the transistor semiconductor body 610, the sub-fin height H sf The selective exposure recess 1540 may be of any depth and lateral dimension. For example, the selective exposure recess 1540 may completely remove a sub-fin portion of the semiconductor body 610 (e.g., the semiconductor portion of the intervening layer 210) to expose the source / drain semiconductor 640. As shown, the etching mask 1410 masks the entire backside of the non-planar transistor structure 604 (see Figures 52A-52C). For example, Figures 51A-51C and 52A-52C show cross-sectional views of the non-planar transistor structure 1304 and the non-planar transistor structure 604 after step 3819 (Figure 38C) has been performed.

[0204] 53A-53C and 54A-54C show non-planar transistor structure 1304 and non-planar transistor structure 604 after epitaxial growth or deposition of p-type or n-type impurity doped backside source / drain semiconductor 1640 and subsequent deposition of backside source / drain metallization 1650. As shown, backside source / drain semiconductor 1640 is disposed adjacent to or above source / drain semiconductor 640. Backside source / drain semiconductor 1640 may be disposed above source / drain semiconductor 640 using any suitable technique or techniques, such as, for example, an epitaxial growth process or a deposition process. For example, the same epitaxial or deposition process used to form source / drain semiconductor 640 may be used to form backside source / drain semiconductor 1640. The backside source / drain semiconductor 1640 may be any suitable material, such as, but not limited to, a Group IV semiconductor (e.g., Si, Ge, SiGe) and / or a Group III-V semiconductor (e.g., InGaAs, InA) and / or a Group III-N semiconductor (e.g., InGaN).

[0205] Also shown, backside source / drain metallization 1650 is disposed adjacent to or above backside source / drain semiconductor 1640. Backside source / drain metallization 1650 may be disposed above source / drain semiconductor 1640 using any suitable technique or techniques, such as a metal deposition process. For example, the same deposition process used to form backside source / drain metallization 650 may be used to form backside source / drain metallization 1650. Backside source / drain metallization 650 may comprise any suitable material, such as Ti, W, Pt, or alloys thereof. Also shown in FIGS. 53A-53C, non-planar transistor structure 604 may remain masked by etch mask 1410 such that neither backside source / drain semiconductor nor source / drain contact metallization is provided on non-planar transistor structure 604. For example, backside source / drain semiconductor 1640 and backside source / drain metallization 1650 of non-native material may be selectively provided to non-planar transistor structure 1304, while not being added to non-planar transistor structure 604. For example, Figures 52A-52C, 53A-53C, and 54A-54C show cross-sectional views of non-planar transistor structure 1304 and planar transistor structure 3904 after step 3834 (Figure 38B) has been performed.

[0206] 53A-53C and 54A-54C, the excess overburden of the backside metallization is removed by polishing (e.g., CMP) to re-expose the etch mask 1410 with the source / drain contact metallization, thereby confining by backfilling the selectively exposed recesses 1540. Subsequent backside processing may further include fabrication of one or more backside interconnect metallization levels (not shown) electrically coupled to at least the source / drain metallization 1650. In some such embodiments, such backside interconnect metallization is of a different composition than the frontside interconnect metallization level and / or has larger lateral dimensions and / or a larger thickness than the corresponding level of frontside interconnect metallization.

[0207] The above description describes various backside processing steps that can be used to complete and / or modify the frontside transistor structure. Such processing may be used, for example, to prepare a device layer for singulation and packaging, or for bonding with another device layer in the context of stacked 3D device layer embodiments. It is also noted that backside processing may be extended to fabricate a second device (e.g., FET, TFET, TFT, STTM) on the exposed backside of the device layer. Fabrication of such a double-sided layer may be considered a supplement or alternative to wafer-level layer bonding, in which the exposed backside is bonded to another, previously fabricated device layer. When such a double-sided layer is later bonded to another layer, the bonding interface separates the stacked device pair from another device or another pair of stacked devices.

[0208] A given device stack may be better suited to double-sided incremental device fabrication or one or other of prefabricated device layers when bonding depending on the processing conditions and / or the level of compatibility between materials required by the stacked devices. For example, backside devices that require high-temperature activation anneals (e.g., anneals after impurity dopant implantation) or high-temperature semiconductor growth (e.g., epitaxial growth) may be less suitable for incremental fabrication with backside processing because backside processing conditions may be detrimental to frontside devices when wafer-level backside bonding is preferred. On the other hand, low-temperature compatible devices, such as many TFTs, oxide semiconductor TFETs, or STTM devices, may be well suited to being incrementally fabricated using backside processing.

[0209] In particular, backside processing may be performed sequentially, either before performing any frontside processing or inserted between frontside processing stages when all frontside processing is complete. While parallel double-sided processing is conceivable, the practical advantages of a supporting (e.g., donor or host) substrate favor performing substantially all processing on a first side before mimicking processing on a second side. Thus, in some embodiments, substantially all frontside processing may be performed (e.g., all the way through multiple levels of backend metallization) before the backside is exposed. Substantially all backside processing may be performed (e.g., all the way through one or more levels of backend metallization) when the backside is exposed. Different frontside and backside metallizations may be performed in such fully serialized frontside and backside processing stages, respectively, once they begin. Different frontside and backside devices may be implemented in this manner. In alternative embodiments where front-side and back-side processing steps are alternated, additional transfers may be required between the donor substrate and the host substrate, adding complexity and expense to the manufacturing process. For example, all back-side processing may be inserted between front-side device cell fabrication and front-side back-end interconnect metallization, with one additional transfer performed from the front-side host substrate to the back-side host substrate.

[0210] As noted above, backside processing may be intentionally differentiated from frontside processing. Different material sets and / or processing conditions may be used for the backside processing than for the frontside processing. For example, the frontside metallization may use a first metal, e.g., a Cu-based metal (i.e., a metal alloy that is primarily or more than 50% Cu), and the backside metallization may use a second metal other than the Cu-based metal (i.e., a metal alloy that is primarily or more than 50% Cu). The frontside device may use a first material system (e.g., a semiconductor composition), while the backside device may use a second, different material system. In this same vein, backside exposure and subsequent backside processing may be positioned within the manufacturing process with respect to various frontside processing steps to compartmentalize the double-sided manufacturing process in a manner that allows for additional degrees of freedom in device integration. For example, backside processing may be used as a means of integrating planar FETs with non-planar FETs or as a means of integrating devices with different thermal budgets. For example, high temperature processes (eg, >350° C.) are classified as front side processes, while back side processes are restricted to lower temperatures (eg, <350° C.).

[0211] Backside processing of exposed portions of a device hierarchy may include implanting species into structures formed during frontside fabrication processes. Implantation is an example of a process that may involve high-temperature processing (e.g., for an activation anneal) that may be integrated with frontside processing at a point before frontside back-end interconnects are formed. In some embodiments, dopant species may be implanted into device layers or intervening layers from the exposed backside of the device and / or intervening layers. Backside implantation techniques may utilize backside exposure processing as a means to modify the composition of one or more non-semiconductor regions of a device structure or surrounding structure. For example, portions of dielectrics (e.g., gate spacers, gate dielectrics, etc.) or metals (e.g., gate metals, source / drain contact metals, etc.) may be altered after they are fabricated by frontside processing. Material modification via backside implantation may take the form of microstructural modification (e.g., amorphization) and / or compositional modification. Such material modification may be used, for example, as a basis for subsequent selective material removal or growth.

[0212] Implantation techniques may utilize backside exposure processes as a means to modify the electrical properties of semiconductor structures formed during frontside processing. Implantation after backside exposure may effectively delay the introduction of dopants into one or more semiconductor structures, improving the thermal budget for a given device and / or sharpening the dopant diffusion profile. After the backside exposure implantation step, it may be possible to dope semiconductor regions that are inaccessible from the front side of the device and inaccessible from the back side of the device until the backside of the doped semiconductor region is exposed (e.g., through substrate thinning or removal). After the backside exposure implantation step, it may modify active device regions (e.g., FET channels, sources, drains), enable backside bonding to active device regions, or promote backside isolation of active device regions. After the backside exposure implantation step, which requires an activation anneal, it may be performed between front-end device processing compatible with the activation anneal temperature and processing limited to low-temperature processing, such as front-side interconnect metallization. Post-backside exposure implantation steps requiring an activation anneal may be performed after all front-end device processing is complete, including front-side interconnect metallization. The activation anneal involves a thermal process that maintains a large temperature gradient across the thickness of the donor-host assembly. For example, the host substrate may be maintained at a first temperature well below 400 °C, while heat is rapidly applied to the exposed backside surface of the device layers.

[0213] FIG. 55 is a flow diagram 5501 illustrating a backside processing method including backside implantation of dopants into a semiconductor device structure, according to some embodiments. Method 5501 further illustrates backside processing of a device (e.g., transistor) cell layer, which may be only a few hundred nanometers thick. Method 5501 begins with a donor-host substrate assembly including a device layer as input 5505. The donor substrate may have one or more of the features described above, such as, but not limited to, an intervening layer and a carrier layer. However, the carrier layer and / or the intervening layer are not specifically required to perform method 5501. In step 5510, the backside of the device layer or intervening layer is exposed during a backside exposure process. In some embodiments, the backside exposure process performed in step 5510 includes one or more of the steps of method 501 (FIG. 5). The backside exposure process may expose the device layer or intervening layer, for example, by removing at least a portion of the donor substrate (e.g., carrier layer). One or more dopants are then implanted into the exposed device layers and / or intervening layers. Output 5515 includes a device cell having a backside doped layer and may be expected to have a dopant profile indicative of introduction of dopant species from the backside of the device structure and / or indicative of introduction of dopant species after fabrication of the frontside structure. The dopant profile may, for example, indicate a higher species concentration proximate the backside of the device structure than proximate the frontside of the device structure. Dopant species introduced from the backside may be present in materials surrounding the semiconductor structure formed during frontside processing prior to the backside implantation process. A combination of materials including dopant species and / or profiles of dopant species within these materials in a view of the surrounding frontside structure may indicate an implantation process after backside exposure according to an embodiment of method 5501.

[0214] 56A and 57A show cross-sectional views of transistor structure 604 along the A-A' plane shown in FIG. 6 when steps in method 5501 are performed according to some embodiments. FIGS. 56B and 57B show cross-sectional views of transistor structure 604 along the B-B' plane shown in FIG. 6 when steps in method 5501 are performed according to some embodiments. FIGS. 56C and 57C show cross-sectional views of transistor structure 604 along the C-C' plane shown in FIG. 6 when steps in method 5501 are performed according to some embodiments.

[0215] 56A-56C illustrate structures present in an exemplary transistor structure following front-side processing of a donor substrate. The semiconductor body 610 is a fin structure extending in a vertical direction (e.g., the z-dimension). The semiconductor body 610 includes a channel portion having a device layer 215. In the embodiment shown in FIGS. 56A-56C, the semiconductor body 610 further includes a sub-fin portion having the same semiconductor composition as the device layer 215 (e.g., Si). The semiconductor body 610 may be formed, for example, using a patterned front-side recess etch of the device layer 215. As further described elsewhere herein, the semiconductor fin body may alternatively include a sub-fin semiconductor of a different composition than the channel portion, where the sub-fin semiconductor may be a component of the intervening layer 210 (FIG. 3A), while the device layer 215 may only be present in the device channel. Alternatively, the sub-fin semiconductor may allow for a spacer between the device layer 215 and the backside substrate and may further include an intervening layer between the sub-fin semiconductor and the carrier layer. A field isolation dielectric 680 surrounds one or more sidewalls of the semiconductor body 610. Further shown in Figures 56A and 56B is a gate stack including a gate electrode 673 disposed above a gate dielectric 845 that intersects the channel portion of the transistor semiconductor body 610, while the intersection of the source / drain metallization with the source / drain semiconductor 640 is shown in Figure 56C.

[0216] 56A-56C, backside surface 3911 of intervening layer 210 is exposed by any technique, for example, but not limited to, method 501 (FIG. 5). A marker or etch stop is present in first intervening layer 210 to terminate a carrier removal step before exposing the backside of field isolation dielectric 680, for example. Although not shown, the backside of transistor semiconductor body 610 may be exposed by further removing portions of the bulk semiconductor to which transistor semiconductor body 610 is anchored, for example, as substantially described above with respect to step 520 (FIG. 5). With the backside surface of intervening layer 210 (or body 610) exposed, a backside implant 5610 is performed. Backside implant 5610 may be a blanket implant having a dopant species implanted into semiconductor body 610 and surrounding material, for example, field isolation dielectric 680. A blanket implant utilizes patterning of the front side of body 610 with all exposed portions to receive the dopant. If less than all of body 610 receives the implant, backside implant 5610 may be a selective (masked) implant. The backside implant may utilize any dopant species, dopant level, and implant energy level known to be suitable for the composition of semiconductor body 610. In some embodiments, the backside implant involves implantation of an impurity species that can be electrically activated by a subsequent thermal anneal at any temperature above ambient (e.g., 400-800°C) to impart n-type or p-type conductivity to the doped semiconductor.

[0217] 57A-57C illustrate transistor structures including semiconductor regions doped by one or more backside implants. As shown, the intervening layer 210 and the sub-fin portion of the semiconductor body 610 are doped with a dopant species, thereby differentiating the intervening layer 210 from the device layer 215 of each semiconductor body 610. Such backside impurity doping may be used to form well structures, such as, but not limited to, n-wells suitable for fabricating PMOS FETs having p-type source / drain semiconductors 640. Such backside impurity doping may also be used as a punch-through stopper. In some alternative embodiments, only the intervening layer 210 is doped by backside implantation, and the sub-fin portion of the semiconductor body 610 is not doped. In other alternative embodiments, only a portion of the sub-fin region is doped by backside implantation. In still other embodiments, multiple backside implants are performed to achieve dopant gradients and / or complementary doped semiconductor junctions within or between the semiconductor body 610 and the intervening layer 210. For example, p-type and n-type junctions may be formed through backside implantation, where the backside portion of semiconductor body 610 is lightly to moderately "p" doped, while source / drain semiconductor 640 is heavily doped n-type. For example, p-type and n-type junctions may be formed through backside implantation, where the backside portion of semiconductor body 610 is lightly to moderately "n" doped, while source / drain semiconductor 640 is heavily doped p-type. Such complementary backside doping of semiconductor body 610 may function to reduce on-state leakage between fins through intervening layer 210. For embodiments in which intervening layer 210 is eliminated and fin-to-fin leakage is less of a concern, the backside doping of semiconductor body 610 may provide a means to fabricate diodes in a manufacturing flow that does not distinguish between frontside processing of transistors and p / n diodes.

[0218] In some embodiments, the backside implant process involves multiple selective implant steps. For example, a first backside implant may dope a first semiconductor region (e.g., first body 610 and intervening layer 210 of FIGS. 57A-57C) to a first conductivity type (e.g., p-type). A second backside implant may dope a second adjacent semiconductor region (e.g., second body 610 and intervening layer 210 of FIGS. 57A-57C) to a second, complementary conductivity type (e.g., n-type). The two complementary doped semiconductor regions may form a P / N junction, for example, within intervening layer 210. Contacts to the complementary ends of the junction may be through frontside and / or backside metallization. In one front-side metallization embodiment, a first transistor structure having p-type doped source / drain semiconductors 640 (e.g., a PMOS FET) is implanted on the backside to have a p-type sub-fin and a p-type intermediate layer surrounding the p-type sub-fin (e.g., first body 610 and part of intermediate layer 210 in Figures 57A-57C). The p-type doping on the backside may be electrically coupled to the front-side metallization through the p-type doped source / drain semiconductors 640. The gate electrode 673, in the context of a diode, may be a residual structure in this case. A second transistor structure having n-type doped source / drain semiconductors 640 (e.g., an NMOS FET) is implanted on the backside to have an n-type sub-fin and an n-type intermediate layer surrounding the n-type sub-fin (e.g., second body 610 and part of intermediate layer 210 in Figures 57A-57C). The backside n-type doping may be electrically coupled to the frontside metallization through n-type doped source / drain semiconductors 640. The interface between the p-type and n-type interlayer regions defines the P / N junction of the diode. Alternatively, the p-type interlayer region may be separated from the n-type interlayer region by an intrinsic (undoped) portion of the interlayer to define a p-i-n diode.

[0219] In some embodiments, backside processing of the exposed portion of the device layer includes epitaxially growing a semiconductor material over the backside of the semiconductor device layer. Epitaxial growth is another example of backside processing that may involve high processing temperatures and therefore may be performed relative to frontside processing for compatibility with all materials in the device layer. In some such embodiments, doped source / drain semiconductors may be epitaxially grown on the backside of the device layer along with fabrication of backside contact and / or interconnect metallization. In other embodiments, backside processing includes epitaxial growth of semiconductor material to replace other semiconductor material removed during the backside exposure process. The epitaxially grown semiconductor may be of a different composition and / or better crystalline quality than that removed during the backside exposure process. To perform high-temperature processing, backside exposure and backside epitaxial growth may be performed to occur before frontside metallization, for example. In particular, epitaxial growth of semiconductors on the backside of the frontside device layers may be further utilized in subsequent incremental backside fabrication of various backside device structures, for example, as described further elsewhere herein.

[0220] Alternatively, low temperature deposition may be used to form a polycrystalline (e.g., micro- or nanocrystalline) or amorphous semiconductor layer, such as, but not limited to, an oxide semiconductor layer (e.g., IGZO) on the backside of the exposed device layer. Any thin film transistor (TFT) fabrication process may then utilize this backside thin film semiconductor to form the backside TFT circuitry.

[0221] FIG. 58 is a flow diagram 5801 illustrating a backside processing method including epitaxial growth or bonding of a substantially single-crystalline backside semiconductor layer, according to some embodiments. Polycrystalline or amorphous semiconductors may be formed, for example, at lower temperatures (e.g., 100-400°C). Method 5801 further illustrates backside processing of device (e.g., transistor) cell layers, which may be only a few hundred nanometers thick. Method 5801 begins with a donor-host substrate assembly including a device layer as input 5805. The donor substrate has one or more of the features described above, such as, but not limited to, an intervening layer and a carrier layer. However, the carrier layer and / or the intervening layer are not specifically required to perform method 5801. In step 5810, the backside of the device layer or intervening layer is exposed during a backside exposure process. In some embodiments, the backside exposure process performed in step 5810 includes one or more of the steps of method 501 (FIG. 5). The backside exposure process may expose the device layer or an intervening layer, for example, by removing at least a portion of the donor substrate (e.g., carrier layer). One or more semiconductor layers are then grown or deposited on the exposed device layer. Alternatively, one or more semiconductor layers are bonded to the exposed device layer, for example, at a semiconductor-oxide bonding interface. Output 5815 includes a device cell having a single-crystalline semiconductor material disposed over the backside of device layer 215. Alternatively, if low-temperature deposition is used, the product of method 5801 is a device having a polycrystalline or amorphous semiconductor material disposed over the backside of device layer 215.

[0222] 59A, 59B, and 59C illustrate cross-sectional views of a III-N semiconductor device hierarchy as certain steps of method 5801 are performed on a donor-host assembly 203, according to some embodiments. As shown in FIG. 59A, the donor-host assembly 203 includes a donor substrate 201 bonded to a host substrate 202, with an optional front-side laminate 690 disposed therebetween, for example, substantially as described above with respect to FIGS. 4A-4C. The front-side laminate 690 is shown in dashed lines as part of a device cell hierarchy that may vary without limitation and may include, for example, any number of back-end interconnect metallization levels. The host substrate 202 may have, for example, any of the characteristics described elsewhere herein. As shown, the host substrate 202 is bonded to the front surface of the front-side laminate 690, for example, by thermocompression bonding. In an embodiment further illustrating how backside device layer processing can precede much frontside device layer processing, device terminals have not yet been formed in or bonded to device layer 215.

[0223] As further shown in FIG. 59B, donor substrate 201 has been removed, exposing the backside surface of intervening layer 210, which includes semiconductor islands surrounded by isolation dielectric 480. Donor substrate 201 may be thinned and / or removed by any technique, including, but not limited to, method 501 (FIG. 5). The exposed surface of the semiconductor may have numerous defects 440, propagated, for example, during heteroepitaxial growth. Intervening layer 210 may then be removed from device layer 215, exposing the backside of device layer 215. Intervening layer 210 may be removed by CMP, if both the semiconductor and isolation dielectric 480 can be removed. Alternatively, intervening layer 210 may be removed using an etch process selective to the semiconductor, if isolation dielectric 480 can be retained. For some embodiments, the backside surface of device layer 215 (e.g., when device layer 215 is GaN) has a significantly lower defect density (i.e., better crystalline quality) than the semiconductor that was removed as part of intervening layer 210.

[0224] Next, semiconductor layer 5915 is deposited or grown on the backside surface of device layer 215, for example, using any epitaxial growth or deposition technique known to be suitable for the selected semiconductor material. Semiconductor layer 5915 may be grown or deposited into the opening in isolation dielectric 480, if retained. Because device layer 215 provides a high-quality seed surface, the quality of the regrown semiconductor layer 5915 is also high, with fewer crystal defects 440. After backside epitaxial growth, which may be a high-temperature process (e.g., greater than 900° C. for III-V embodiments), backside and / or frontside processing may continue using low-temperature processes to fabricate devices (e.g., HFETs) in device layer 215 and / or in the epitaxially grown semiconductor layer 5915. Notably, semiconductor layer 5915 need not have the same composition as device layer 215. The compositional difference between device layer 215 and semiconductor layer 5915 may be exploited to impart strain to layer 215 or 5915, for example, through lattice mismatch engineering. In some embodiments in which device layer 215 is GaN, semiconductor layer 5915 is a III-N alloy having a different lattice constant than device layer 215. In some embodiments in which device layer 215 is Si, semiconductor layer 5915 is a III-V or IV alloy having a different lattice constant than device layer 215. For such embodiments, semiconductor layer 5915 is advantageous in that it can impart uniaxial and / or biaxial strain to device layer 215, or vice versa.

[0225] In yet another embodiment, the device layer 215 is a III-N alloy and the epitaxially grown semiconductor layer 5915 is a transition metal dichalcogenide (TMD or TMDC). Similar to graphene, TMDC exhibits semiconducting properties as a monolayer sheet of M, where M is a transition metal atom (e.g., Mo, W) and X is a chalcogen atom (S, Se, or Te). In the monolayer crystalline sheet, one layer of M atoms is disposed between two layers of X atoms. After growth of the TMDC sheet, backside processing may further include fabricating a TMDC channel transistor with any known architecture.

[0226] In some embodiments, the backside semiconductor is epitaxially grown or deposited in polycrystalline or amorphous form during fabrication of vertically stacked or vertically oriented devices. For some exemplary architectures, the frontside device layers are epitaxially grown on a donor substrate; then, upon removal of the donor substrate, backside exposure may expose a layer of semiconductor with favorable crystallinity for regrowth of a second backside device layer. The frontside and backside device layers within the device hierarchy may then be used to separate functional regions of a vertically oriented transistor or may be used for two vertically stacked, horizontally oriented transistors. One challenge faced by many vertical device architectures is the fabrication of device terminals at both ends of the device, which can be difficult when relying solely on frontside processing. However, the backside exposure techniques described herein, once exposed, enable a paradigm shift from "bottom-up" device fabrication to "center-out" device fabrication, with a first portion of the device epitaxially grown from the front side and a second portion of the device epitaxially grown from the back side. Thus, an exemplary vertical FET may be fabricated by first forming a source (drain) semiconductor on the front side of the device layer, which provides the transistor channel. After a backside exposure process, the drain (or source) semiconductor may be formed on the backside of the device layer, which is then bonded to backside metallization. Similarly, a bipolar transistor may be fabricated, for example, by first forming an emitter (collector) semiconductor on the front side of the device layer, which provides the transistor base. After a backside exposure process, a collector (or emitter) semiconductor is then formed on the backside of the device layer.

[0227] 60A, 60B, and 60C illustrate cross-sectional views of semiconductor device layers as several steps in method 5801 are performed, according to several stacked device layer embodiments. Method 5801 begins with receiving a donor-host assembly 203 including a host substrate 202 and a donor substrate 201, for example, substantially as described above with respect to FIG. 59A. However, in the embodiment illustrated by FIG. 60A, the donor-host assembly 203 includes a front-side device layer 215B above a core semiconductor device layer 215A. The semiconductor material of the core device layer 215A is patterned into features (e.g., fins, pillars, dots, etc.) surrounded by a field isolation dielectric 6080. The semiconductor features of the front-side device layer 215B are above the core device layer features. A front-side stack 690 is above the front-side device layer 215B. In some embodiments, if the front-side device layer feature is a doped source / drain semiconductor, the front-side stack 690 may include front-side source / drain contact metal. The front-side stack 690 may further include a gate electrode coupled to the core semiconductor layer feature. During back-side processing, the backside of the core device layer 215A is exposed. For example, as further shown in FIG. 60B, the donor substrate 205 and intervening layer 210 are removed during a back-side exposure step, exposing the core device layer 215A and field isolation dielectric 6080. As shown in FIG. 60C, a back-side semiconductor layer 5915 is then epitaxially grown or deposited (e.g., selectively) on the backside surface of the core device layer 215A. The semiconductor layer 5915 may be grown or deposited to form laterally or vertically oriented devices independent of or dependent on the front-side device layer 215B. Next, a backside stack 6090 is fabricated and / or bonded to the double-sided stack to interconnect features in the backside semiconductor layer 5915. For example, the backside stack 6090 may include backside source / drain contact metal.

[0228] In some embodiments, the core device layer 215A provides electrical isolation between the front-side device layer 215B and the back-side semiconductor layer 5915. For example, the core device layer 215A may have a wide bandgap and / or bandgap offset in one or both of the conduction and valence bands such that charge carriers are confined within the front-side and back-side device layers 215B, 5915, respectively. Homogeneous semiconductor embodiments may rely on the core device layer 215A to provide dopant junction isolation between the front-side device layer 215B and the back-side semiconductor layer 5915. For such architectures, the front-side stack 690 may provide all terminals (e.g., gate, source, and drain) of a front-side laterally oriented device (e.g., FET) using the front-side device layer 215B. A comparable back-side stack may further provide all terminals (e.g., gate, source, and drain) for a back-side laterally oriented device (e.g., FET) using the back-side semiconductor layer 5915.

[0229] As an alternative to backside epitaxial growth or amorphous / polycrystalline film deposition, the backside semiconductor structure may be fabricated as a fin, for example, by exposing a sub-fin portion of the frontside fin structure by selectively recessing the backside of a field isolation dielectric surrounding the frontside fin. Alternatively, the backside semiconductor body may be patterned from an intervening semiconductor layer exposed during backside exposure. For such embodiments, backside epitaxy and / or backside implantation may be used to form the backside semiconductor layer 5915, including the backside source / drain semiconductor regions.

[0230] FIG. 61A shows a cross-sectional view of a transistor structure 604 along the A-A′ plane shown in FIG. 6 stacked with a planar backside transistor structure 6104, according to some stacked FET embodiments. FIG. 61B shows a cross-sectional view of a transistor structure 604 along the B-B′ plane shown in FIG. 6 stacked with a planar backside transistor structure 6104, according to some stacked FET embodiments. In some embodiments, the backside transistor structure 6104 is fabricated incrementally from the exposed backside of the transistor structure 604. For such embodiments, the backside exposure not only partitions the fabrication of the frontside from the backside fabrication, but also partitions the fabrication process of the non-planar FET from the fabrication process of the planar FET. In an alternative embodiment, the backside transistor structure 6104 has been fabricated and transferred as a second device layer bonded to the exposed backside of the transistor structure 604, for example, at a bond interface 6199.

[0231] In particular, while planar FETs are advantageous for many applications (e.g., high current power FETs), planar FET fabrication is often incompatible with FinFET fabrication, making it difficult to incorporate both transistor architectures in different regions of the substrate. Using double-sided processing enabled by backside exposure techniques, planar FET fabrication can be sequentially integrated with FinFET fabrication, for example, as described elsewhere herein.

[0232] As shown in FIG. 61A , front-side device layer 215A is disposed on semiconductor body 610 having a lateral length extending in the A-A′ plane. A sub-fin portion of semiconductor body 610 and any intervening layer 210 function as core device layer 215B (e.g., silicon or a suitably matched compound semiconductor). Back-side semiconductor layer 5915 may be epitaxially grown on the exposed backside surface of core device layer 215B. Semiconductor layer 5915 may be of any composition, such as any of those provided for device layer 215A. In some embodiments, semiconductor layer 5915 has a different composition than device layer 215A. In some embodiments, semiconductor layer 3915 has the same composition as device layer 215A. In some embodiments, semiconductor layer 5915 has a conductivity type complementary to that of device layer 215A (e.g., semiconductor layer 5915 is p-type while device layer 215A is n-type, or vice versa). In some embodiments, semiconductor layer 5915 is a single-crystal III-V material while device layer 215A is single-crystal silicon. In other embodiments, device layer 215A is a single-crystal III-V material while semiconductor layer 5915 is single-crystal silicon. In some embodiments, device layer 215A is silicon and semiconductor layer 5915 is single-crystal III-N (e.g., GaN). Instead of bonding or backside epitaxial growth of semiconductor layer 5915 (e.g., using an oxide-bonded interface), intervening layer 210 may serve as a foundation for a backside device layer with, for example, FET channel region 6110 disposed within intervening layer 210.

[0233] A backside gate stack including a backside gate dielectric 6145 and a backside gate electrode 6173 is disposed over the channel region 6110. Backside source / drain semiconductors 6140 are epitaxially grown, deposited, or otherwise formed on either side of the channel region 6110 and are electrically isolated from the backside gate electrode 6173 by intervening backside dielectric spacers 6171. The backside source / drain semiconductors 6140 may be of any composition, such as any of those provided for the source / drain semiconductors 640. In some embodiments, the source / drain semiconductors 6140 have the same composition as the source / drain semiconductors 640. In some embodiments, the source / drain semiconductors 6140 are of a complementary conductivity type to the source / drain semiconductors 640 (e.g., 6140 is p-type where 640 is n-type, or vice versa). In some embodiments, the source / drain semiconductors 6140 are of the same conductivity type as the source / drain semiconductors 640. A backside field isolation dielectric 6180 surrounds the active device structures, similar to field isolation dielectric 680 .

[0234] In particular, the gate length of the front-side transistor structure 604 spans the A-A' plane, as shown in FIG. 61B, while the back-side planar transistor structure 6104 has a channel length that spans the B-B' plane, as shown in FIG. 61A. As such, current flow through the stacked channel regions is advantageously orthogonal, rather than parallel. The illustrated relative orientation of the stacked FET cells may offer advantages such as reduced parasitics (inductive, capacitive crosstalk), and FET orientations that result in parallel channel currents are also possible. Similarly, while the example shown in FIGS. 61A and 61B shows a planar transistor structure 6104 having a footprint substantially equal to the transistor structure 604 using two semiconductor bodies 610, the relative dimensions of the front-side FinFET and back-side planar FET may vary. Additionally, although the example shown in Figures 61A-61B shows a planar transistor structure 6104 that is vertically aligned with respect to transistor structure 604, stacked transistor embodiments may incorporate any amount of lateral offset between the front and back side transistor structures.

[0235] Figure 62A shows a cross-sectional view of transistor structure 604 along the A-A' plane shown in Figure 6 stacked on a backside transistor structure 6204, according to some stacked FET embodiments. Figure 62B shows a cross-sectional view of transistor structure 604 along the B-B' plane shown in Figure 6 stacked on a backside transistor structure 6204, according to some stacked FET embodiments. In some embodiments, backside transistor structure 6204 is fabricated incrementally from the exposed backside of transistor structure 604. In alternative embodiments, backside transistor structure 6104 is pre-fabricated or transferred as a second device layer that is bonded to the exposed backside of transistor structure 604, for example, at bond interface 6199.

[0236] Backside exposure, semiconductor layer patterning, bonding, and / or subsequent epitaxial device layer growth or deposition may be used to increase the density of transistor gates for a given footprint (e.g., double the number of FinFET cells for a given area). As shown in FIG. 62A, a frontside device layer 215A is disposed on a semiconductor body 610 having a lateral length extending in the A-A' plane. A sub-fin portion of the semiconductor body 610 and any intervening layers 210 function as a core device layer 215B (e.g., silicon or a suitably matched compound semiconductor). A backside semiconductor layer 5915 may be epitaxially grown on the exposed backside surface of the core device layer 215B, or may be deposited as a polycrystalline or amorphous thin film. Film growth or deposition may be confined (or selectively performed) to form the non-planar backside semiconductor body 6210, or a backside patterning process may be used to define the non-planar backside semiconductor body 6210 from epitaxially grown or non-epitaxially deposited semiconductor layers. In some alternative embodiments, the intervening layer 210 may instead act as a backside device layer and is patterned into the backside fin body.

[0237] A backside gate stack including a backside gate dielectric 6145 and a backside gate electrode 6173 is disposed over the channel region of the backside semiconductor body 6210. Backside source / drain semiconductors 6140 may be epitaxially grown, not epitaxially deposited, and / or doped with impurities at either end of the channel region 6110 and are electrically isolated from the backside gate electrode 6173 by intervening backside dielectric spacers 6171. A backside field isolation dielectric 6180, like the field isolation dielectric 680, surrounds the active device structures.

[0238] In particular, the gate length of the front-side transistor structure 604 spans the A-A' plane, as shown in FIG. 62B, while the back-side transistor structure 6204 has a channel length that spans the B-B' plane, as shown in FIG. 62A. Therefore, current flow through the stacked channel regions is advantageously orthogonal, rather than parallel. The illustrated relative orientation of the stacked FET cells may be advantageous, for example, to provide reduced parasitics (inductive, capacitive crosstalk), although stacked FET orientations that result in parallel channel currents are also possible. Similarly, while the example shown in FIGS. 62A-B shows transistor structure 6204 having a footprint substantially equal to transistor structure 604, the relative dimensions of the front-side and back-side FinFETs may vary. Furthermore, while the example shown in FIGS. 62A-B shows transistor structure 6204 vertically aligned with transistor structure 604, stacked transistor embodiments may again incorporate any lateral offset between the front-side and back-side transistor structures.

[0239] FIG. 63A shows a cross-sectional view of transistor structure 604 and backside transistor structure 6304 along the A-A' plane shown in FIG. 6, according to some stacked FET embodiments. FIG. 63B shows a cross-sectional view of transistor structure 604 and backside transistor structure 6304 along the B-B' plane shown in FIG. 6, according to some stacked FET embodiments. For these embodiments, backside transistor structure 6304 is fabricated incrementally from the exposed backside of transistor structure 604. Such backside processing may utilize self-alignment techniques to fabricate additional FET structures in the frontside fabricated semiconductor body. Thus, the frontside FET and backside FET have channel regions disposed on the frontside and backside of the semiconductor body, respectively. In contrast to the example shown in FIGS. 62A and 62B, the channel current in backside FET cell 6304 is substantially parallel to the channel current in frontside transistor structure 604. For such embodiments, the backside semiconductor body 6210 may be fabricated as a fin, for example, by selectively recessing the backside of the field isolation dielectric 680 surrounding the body to expose a sub-fin portion of the body 610.

[0240] Alternatively, and further referring to Figures 62A and 62B, the semiconductor body 6210 may be patterned from an intervening semiconductor layer exposed during backside exposure. In other embodiments, the semiconductor body 6210 may be epitaxially grown from a backside see...

Claims

1. A front-side device, a body of single crystal semiconductor material adjacent to an isolation dielectric; a gate stack adjacent a sidewall of the body, the gate stack including a gate electrode separated from the sidewall by a gate dielectric; a source and a drain coupled to the body on either side of the gate stack; a front device having a front-side interconnect metallization layer on the front-side surface of the body and coupled to at least one of the source, the drain, or the gate electrode; A backside device, a backside device layer on a backside surface of the body opposite the front-side interconnect metallization layer, the backside device layer comprising an oxide semiconductor material or a metal chalcogenide material; a backside device layer of the oxide semiconductor material or the metal chalcogenide material in contact with the backside surface of the body; a backside device terminal electrically coupled to the backside device layer; a backside device having 1. An integrated circuit (IC) structure comprising:

2. A front-side device, a body of single crystal semiconductor material adjacent to an isolation dielectric; a gate stack adjacent a sidewall of the body, the gate stack including a gate electrode separated from the sidewall by a gate dielectric; a source and a drain coupled to the body on either side of the gate stack; a front device having a front-side interconnect metallization layer on the front-side surface of the body and coupled to at least one of the source, the drain, or the gate electrode; A backside device, a backside device layer opposite the frontside interconnect metallization layer, the backside device layer including a backside semiconductor body of the monocrystalline semiconductor material integral with the body of the frontside device; a backside device terminal electrically coupled to the backside device layer; a backside device having 1. An integrated circuit (IC) structure comprising:

3. 3. The IC structure of claim 1, wherein the backside device is a transistor, and the backside device terminal is one of a source, drain, or gate terminal of the transistor.

4. 4. The IC structure of claim 3, wherein the transistor is one of a thin film transistor (TFT) or a tunneling field effect transistor (TFET).

5. 5. The IC structure of claim 4, wherein the backside device is a TFT and the backside device layer comprises a metal and a chalcogen.

6. 5. The IC structure of claim 4, wherein the backside device is a TFT and the backside device layer comprises metal and oxygen.

7. 7. The IC structure of claim 6, wherein the backside device layer comprises oxygen, indium, gallium, and zinc.

8. A front-side device, a body of single crystal semiconductor material adjacent to an isolation dielectric; a gate stack adjacent a sidewall of the body, the gate stack including a gate electrode separated from the sidewall by a gate dielectric; a source and a drain coupled to the body on either side of the gate stack; a front device having a front-side interconnect metallization layer on the front-side surface of the body and coupled to at least one of the source, the drain, or the gate electrode; A backside device, a backside device layer disposed on an opposite side of the backside surface of the body from the front-side interconnect metallization layer, the backside device layer including a ferroelectric material; a backside device terminal electrically coupled to the backside device layer; a backside device having Equipped with the backside device is a non-volatile memory (NVM) device, and the backside device terminal is an electrode of the NVM device; The NVM device is an integrated circuit (IC) structure having a magnetic tunnel junction (MTJ).

9. The IC structure of claim 8, wherein the front-side device and the back-side device are interconnected by vias to a vertical 1T1R cell.

10. The IC structure of claim 9, wherein the via is adjacent to and in contact with a sidewall of the source or the drain.

11. 9. The IC structure of claim 8, wherein the source or the drain of the front side device is in direct contact with an electrode of an NVM device.

12. The backside device is a transistor having a backside gate electrode; The gate electrode is perpendicular to the back gate electrode. The IC structure of claim 1 .

13. A field effect transistor (FET), a body of single crystal silicon adjacent to an isolation dielectric; a gate stack adjacent a sidewall of the body, the gate stack including a gate electrode separated from the sidewall by a gate dielectric; a source and a drain coupled to the body on either side of the gate stack; a field effect transistor having a front-side interconnect metallization layer on the front-side surface of the body and coupled to at least one of the source, the drain, or the gate electrode; A thin film transistor (TFT), a channel material layer on a backside surface of the body opposite the front-side interconnect metallization layer, the channel material layer comprising a metal and a chalcogen or a metal and oxygen, the channel material layer contacting the backside surface of the body; a backside device terminal electrically coupled to the channel material layer; a thin film transistor (TFT) having A vertically stacked integrated circuit (IC) device structure comprising:

14. 14. The IC device structure of claim 13, wherein the source or the drain is in direct contact with the backside device terminal.

15. 15. The IC device structure of claim 14, wherein the channel material layer comprises oxygen and at least one of indium, gallium, or zinc.

16. 15. The IC device structure of claim 14, wherein the channel material layer comprises oxygen, indium, gallium, and zinc.

17. forming a field effect transistor (FET), the field effect transistor (FET) comprising: a body of single crystal silicon adjacent to an isolation dielectric; a gate stack adjacent a sidewall of the body, the gate stack including a gate electrode separated from the sidewall by a gate dielectric; a source and a drain coupled to the body on either side of the gate stack; forming a field effect transistor (FET) having: forming a front-side interconnect metallization layer on a front-side surface of the body, the front-side interconnect metallization layer being coupled to at least one of the source, drain or gate electrodes; removing a thickness of single crystal silicon material from a backside of the FET to expose a backside of the FET; forming a backside device on the exposed backside of the FET; Equipped with forming a backside device on the exposed backside of the FET; forming a backside device layer comprising an oxide semiconductor material, a metal chalcogenide material, or a ferroelectric material; forming a backside device terminal electrically coupled to the backside device layer, before or after forming the backside device layer; A method comprising:

18. The method of claim 17, wherein the backside device comprises a thin film transistor (TFT), a tunneling field effect transistor (TFET) or a non-volatile memory (NVM) device.

19. 20. The method of claim 17, wherein forming the backside device layer comprises depositing a polycrystalline or amorphous semiconductor material containing metal and oxygen, or metal and chalcogen.

20. 20. The method of claim 17, wherein forming the backside device layer comprises epitaxially growing the backside device layer from single crystal silicon on the backside of the FET.

21. A step of forming a field effect transistor (FET), the field effect transistor (FET) comprising: a body of single crystal silicon adjacent to an isolation dielectric; a gate stack adjacent a sidewall of the body, the gate stack including a gate electrode separated from the sidewall by a gate dielectric; a source and a drain coupled to the body on either side of the gate stack; forming a field effect transistor (FET) having: forming a front-side interconnect metallization layer on a front-side surface of the body, the front-side interconnect metallization layer being coupled to at least one of the source, drain or gate electrodes; removing a thickness of single crystal silicon material from a backside of the FET to expose a backside of the FET; forming a non-volatile memory (NVM) device having a magnetic tunnel junction (MTJ) on the exposed backside of the FET; A method comprising:

22. The method of claim 20, wherein forming the NVM device comprises bonding a donor substrate above the backside of the FET, the donor substrate including the NVM device.

22. The method of claim 21.

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