Image sensing device and electronic device including the same

Abstract

To provide an image sensing device that is capable of high-speed operation.SOLUTION: In an imaging device, a pixel PX of an image sensor includes a photoelectric element PD, a charge transfer transistor CT, a reset transistor RT, a floating diffusion FD, a drive transistor DT, a selection transistor ST, and a DCG (dual conversion gain) transistor GT. The selection transistor ST outputs a first pixel signal to a column line based on electric charges stored in the floating diffusion FD in a state in which the DCG transistor GT is turned off. The DCG transistor GT is provided with a gain control signal CGCS determined based on the output first pixel signal. An operation in which the first pixel signal is output to the column line and an operation in which the DCG transistor GT is provided with the gain control signal CGCS are performed while a selection signal maintains a first level.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to image sensing devices and electronic devices including same. [Background technology]

[0002] An image sensing device is a semiconductor device that converts optical information into an electrical signal. Such image sensing devices can include charge-coupled devices (CCDs) and complementary metal-oxide semiconductor (CMOS) image sensing devices.

[0003] A CMOS image sensor is abbreviated as CIS (CMOS image sensor). A CIS may have a plurality of pixels arranged two-dimensionally. Each pixel may include, for example, a photodiode (PD). The photodiode may convert incident light into an electrical signal.

[0004] Recently, with the development of the computer and communications industries, there has been an increasing demand for image sensors with improved performance in a variety of fields, including digital cameras, video cameras, smartphones, game consoles, security cameras, medical micro cameras, robots, etc. Furthermore, as semiconductor devices become more highly integrated, image sensors are also becoming more highly integrated. Summary of the Invention [Problem to be solved by the invention]

[0005] A technical problem to be solved by the present invention is to provide an image sensing device capable of high-speed operation.

[0006] Another technical problem to be solved by the present invention is to provide an electronic device capable of high-speed image sensing operation.

[0007] The technical problems of the present invention are not limited to those mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0008] According to some embodiments, an image sensing device for achieving the above technical objectives includes a floating diffusion that stores charges generated by a photoelectric element, a drive transistor that generates a pixel signal based on the charges stored in the floating diffusion, a selection transistor that outputs the pixel signal generated by the drive transistor to a column line based on a selection signal, and a DCG (Dual Conversion Gain) transistor that changes the capacitance of the floating diffusion based on a gain control signal, wherein the selection transistor outputs a first pixel signal to the column line based on the charges stored in the floating diffusion when the DCG transistor is turned off, and the DCG transistor receives a gain control signal determined based on the output first pixel signal, and the operation of outputting the first pixel signal to the column line and the operation of the DCG transistor receiving the gain control signal are performed while the selection signal maintains a first level.

[0009] According to some embodiments, an image sensing device for achieving the above technical objectives includes a pixel circuit that outputs a pixel signal in response to a selection signal, and a readout circuit that outputs a digital signal corresponding to the pixel signal provided from the pixel circuit, wherein the readout circuit receives a first pixel signal from the pixel circuit, generates a gain control signal based on the first pixel signal, and provides the gain control signal to the pixel circuit; receives a second pixel signal output by the pixel circuit using the gain control signal, and outputs a digital signal corresponding to the second pixel signal; the operation of the readout circuit providing the gain control signal to the pixel circuit and the operation of the pixel circuit outputting the second pixel signal to the readout circuit are performed while the selection signal provided to the pixel circuit is maintained at a first level.

[0010] According to some embodiments, an image sensing device for achieving the above technical objectives includes a pixel circuit that outputs a pixel signal in response to a selection signal; a ramp signal generator that generates a ramp signal; and a readout circuit that receives the pixel signal from the pixel circuit, compares the pixel signal with the ramp signal provided by the ramp signal generator, and outputs a digital signal corresponding to the pixel signal, wherein the ramp signal generator provides a ramp signal to the readout circuit, the ramp signal including a first pulse that drops from a reference voltage by a first level, a second pulse that drops from the reference voltage by a second level different from the first level, and a third pulse that drops from the reference voltage by a third level different from the second level, and the ramp signal generator provides the first to third pulses to the readout circuit while the selection signal provided to the pixel circuit is maintained at a first level.

[0011] According to some embodiments, an electronic device for achieving the technical objective includes an image sensor including a plurality of sensing units, which senses light provided to each of the sensing units and outputs an image signal, and a processor which receives the image signal from the image sensor and performs image processing on the image signal, wherein the image sensor provides an image signal including conversion gain information for each of the sensing units to the processor, and the processor performs image processing using the conversion gain information for each of the sensing units included in the image signal.

[0012] Specific details of other embodiments are included in the detailed description and drawings. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a block diagram of an image sensing device according to some embodiments. [Figure 2] FIG. 2 shows a conceptual layout of the image sensor of FIG. 1. [Figure 3] FIG. 2 is an exemplary diagram for explaining the pixel array of FIG. 1. [Figure 4] FIG. 4 is a cross-sectional view taken along line AA' in FIG. [Figure 5] FIG. 2 is a circuit diagram of a unit pixel included in the pixel array of FIG. 1. [Figure 6] FIG. 2 is a block diagram illustrating the pixel array and readout circuitry of FIG. 1. [Figure 7] 1 is a timing diagram illustrating the operation of an image sensing device according to some embodiments. [Figure 8] 7 is a diagram for explaining the structure of a digital signal output from the readout circuit of FIG. 6. FIG. [Figure 9] 1A and 1B are diagrams for explaining the effects of an image sensing device according to some embodiments. [Figure 10]FIG. 10 is a block diagram of an image sensing device according to some other embodiments. [Figure 11] FIG. 11 is an exemplary circuit diagram of the timing controller of FIG. 10. [Figure 12] 10A and 10B are timing diagrams illustrating the operation of an image sensing device according to some other embodiments. [Figure 13] 10A and 10B are exemplary diagrams illustrating pixel arrays of image sensing devices according to still other embodiments. [Figure 14] 10A and 10B are circuit diagrams illustrating pixel circuits of image sensing devices according to still other embodiments. [Figure 15] 10A and 10B are exemplary diagrams illustrating pixel arrays of image sensing devices according to still other embodiments. [Figure 16] FIG. 1 is a block diagram of an electronic device including a multi-camera module. [Figure 17] FIG. 17 is a detailed block diagram of the camera module of FIG. 16. DETAILED DESCRIPTION OF THE INVENTION

[0014] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments according to the technical concept of the present invention will be described with reference to the accompanying drawings.

[0015] FIG. 1 is a block diagram of an image sensing device according to some embodiments.

[0016] Referring to FIG. 1, the image sensing device 1 may include an image sensor 100 and an image processor 900 .

[0017] The image sensor 100 may sense an image of a target object using light and generate an image signal IMS. In some embodiments, the generated image signal IMS may be, for example, a digital signal, although embodiments are not limited in this respect.

[0018] The image signal IMS may be provided to and processed by the image processor 900. The image processor 900 may receive the image signal IMS output from the buffer 170 of the image sensor 100 and process or otherwise adapt the received image signal IMS for display.

[0019] In some embodiments, the image processor 900 may perform digital binning on the image signal IMS output from the image sensor 100. In this case, the image signal IMS output from the image sensor 100 may be a raw image signal from the pixel array 140 without analog binning, or may be an image signal IMS on which analog binning has already been performed.

[0020] In some embodiments, the image sensor 100 and the image processor 900 may be disposed separately from each other as shown in the drawings. For example, the image sensor 100 may be mounted on a first chip, and the image processor 900 may be mounted on a second chip, and they may communicate with each other via a predetermined interface. However, the embodiments are not limited thereto, and the image sensor 100 and the image processor 900 may be embodied in a single package, for example, a multi-chip package (MCP).

[0021] The image sensor 100 may include a control register block 110, a timing generator 120, a row driver 130, a pixel array 140, a readout circuit 150, a ramp signal generator 160, and a buffer unit 170.

[0022] The control register block 110 may control the overall operation of the image sensor 100. In particular, the control register block 110 may directly transmit operation signals to the timing generator 120, the ramp signal generator 160, and the buffer unit 170.

[0023] The timing generator 120 may generate a signal that serves as a reference for the operation timing of various components of the image sensor 100. The operation timing reference signal generated by the timing generator 120 may be transmitted to the row driver 130, the readout circuit 150, the ramp signal generator 160, etc.

[0024] The ramp signal generator 160 may generate and transmit a ramp signal used in the readout circuit 150. For example, the readout circuit 150 may include a correlated double sampler (CDS), a comparator, etc., and the ramp signal generator 160 may generate and transmit a ramp signal used in the correlated double sampler (CDS), a comparator, etc.

[0025] The buffer unit 170 may include, for example, a latch unit, and may temporarily store the image signal IMS to be provided to the outside and transmit the image signal IMS to an external memory or an external device.

[0026] The pixel array 140 may sense an external image. The pixel array 140 may include a plurality of pixels (or unit pixels). The row driver 130 may selectively activate rows of the pixel array 140.

[0027] The readout circuit 150 may sample the pixel signal provided by the pixel array 140, compare it with the ramp signal, and then convert the analog image signal (data) into a digital image signal (data) based on the comparison result.

[0028] FIG. 2 is a diagram showing a conceptual layout of the image sensor of FIG.

[0029] 2, the image sensor 100 may include first and second regions S1 and S2 stacked in a first direction (Z, e.g., vertical direction). The first and second regions S1 and S2 may extend in a second direction X and a third direction Y as shown in the drawing, and the blocks shown in FIG. 1 are disposed in the first and second regions S1 and S2.

[0030] Although not shown in the drawings, a third region including a memory may be disposed below the second region S2. The memory disposed in the third region may receive image data from the first and second regions S1 and S2, store or process the image data, and retransmit the image data to the first and second regions S1 and S2. The memory may include memory devices such as dynamic random access memory (DRAM), static random access memory (SRAM), spin transfer torque magnetic random access memory (STT-MRAM), and flash memory. For example, if the memory includes a DRAM, the image data may be transferred and processed at a relatively high speed. In some embodiments, the memory may be disposed in the second region S2.

[0031] The first region S1 may include a pixel array region PA and a first peripheral region PH1, and the second region S2 may include a logic circuit region LC and a second peripheral region PH2. The first and second regions S1 and S2 are stacked one on top of the other.

[0032] In the first region S1, the pixel array region PA may be a region where the pixel array (140 in FIG. 1) described with reference to FIG. 1 is arranged. The pixel array region PA may include a plurality of unit pixels (PX(i,j) in FIG. 3) arranged in a matrix shape. Each pixel may include a photodiode and a transistor. This will be described in more detail later.

[0033] The first peripheral area PH1 may include a plurality of pads arranged around the pixel array area PA, and the pads may transmit and receive electrical signals to and from an external device.

[0034] In the second region S2, the logic circuit region LC may include electronic elements including a plurality of transistors. The electronic elements included in the logic circuit region LC are electrically connected to the pixel array region PA and may provide a constant signal or control an output signal to each unit pixel PX in the pixel array region PA.

[0035] In the logic circuit region LC, for example, the control register block 110, the timing generator 120, the row driver 130, the readout circuit 150, the ramp signal generator 160, the buffer unit 170, etc., which are described with reference to Fig. 1, are arranged. In the logic circuit region LC, for example, the blocks in Fig. 1 other than the pixel array 140 are arranged.

[0036] In the second region S2, a second peripheral region PH2 may be arranged in a region corresponding to the first peripheral region PH1 of the first region S1, but the embodiment is not limited thereto.

[0037] FIG. 3 is an exemplary diagram for explaining the pixel array of FIG.

[0038] 3, the pixels PX(i,j) of the pixel array 140 are arranged in, for example, a Bayer pattern. However, the embodiment is not limited thereto, and the pixels PX(i,j) may be arranged in, for example, a tetrahedral pattern or a nona pattern.

[0039] 3 shows only 16 filters arranged in 4 rows and 4 columns to explain the Bayer pattern, but this shows only a portion of the filter area for the purpose of explanation, and the embodiment is not limited thereto. That is, the number of filters in the Bayer pattern can be modified and implemented in any number of different ways.

[0040] The Bayer pattern may include filters consisting of three hues: red, green, and blue. The R filter R is an optical filter that transmits only red light, the G filters Gr and Gb are optical filters that transmit only green light, and the B filter B is an optical filter that transmits only blue light. In the Bayer pattern, the R, G, and B filters R, Gb, Gr, and B are arranged in a certain pattern, as shown in Figure 3. Due to human visual characteristics, the G filters may include a G filter Gr located next to the R filter R and a G filter Gb located next to the B filter B, as shown in Figure 3.

[0041] As shown in the drawing, each color filter (for example, R, Gr, Gb, or B) may form a region configured in a 1x1 matrix to form a Bayer pattern.

[0042] FIG. 4 is a cross-sectional view taken along line AA' in FIG.

[0043] Referring to FIG. 4, the image sensor includes substrates 146R and 146Gr, phototransistors 148R and 148Gr, an anti-reflection film 147, a side anti-reflection film 144, color filters R and Gr, an upper planarization film 142, a lower planarization film 145, and microlenses 141-1 and 141-2.

[0044] The substrates 146R and 146Gr may be, for example, a P-type or N-type bulk substrate, a P-type or N-type epitaxial layer grown on a P-type bulk substrate, or an N-type bulk substrate with a P-type or N-type epitaxial layer grown on a P-type bulk substrate. Furthermore, the substrates 146R and 146Gr may be, in addition to semiconductor substrates, organic plastic substrates or other substrates.

[0045] The photoelectric transistors 148R and 148Gr may be a photodiode, a phototransistor, a photogate, a pinned photodiode, or a combination thereof. Although the following description will be given using a photodiode as an example of a photoelectric element, the embodiment is not limited thereto.

[0046] The anti-reflection coating 147 and the side anti-reflection coating 144 can prevent light incident on the microlenses 141-1 and 141-2 from penetrating into the R region and the Gr region. The anti-reflection coating 147 and the side anti-reflection coating 144 are made of an insulating film such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a resin, a combination thereof, or a laminate thereof, but the embodiment is not limited thereto.

[0047] The upper planarization layer 142 and the lower planarization layer 145 are formed flat with the color filters R and Gr interposed therebetween. The upper planarization layer 142 and the lower planarization layer 145 may include at least one of a silicon oxide-based material, a silicon nitride-based material, a resin, or a combination thereof, but the embodiment is not limited thereto.

[0048] FIG. 5 is a circuit diagram of a unit pixel included in the pixel array of FIG.

[0049] Referring to FIG. 5, the pixel PX may include a photosensitive element PD, a charge transfer transistor CT, a reset transistor RT, a floating diffusion FD, a drive transistor DT, a selection transistor ST, and a DCG (Dual Conversion Gain) transistor GT.

[0050] The photoelectric element PD may sense an external image (or light) and generate charges. The cathode of the photoelectric element PD may be connected to the floating diffusion FD via the charge transfer transistor CT, and the anode of the photoelectric element PD may be grounded.

[0051] The photoelectric element PD may be, for example, a photodiode, a phototransistor, a photogate, a pinned photodiode, or a combination thereof, but the embodiment is not limited thereto.

[0052] In some embodiments, the photoelectric element PD may include an organic photodiode.

[0053] When the photoelectric element PD is an organic photodiode, the photoelectric element PD may include first and second electrodes arranged parallel to each other and an organic light conversion layer disposed therebetween, and the organic light conversion layer may generate electric charges upon receiving light in a predetermined wavelength range.

[0054] The charge transfer transistor CT may be turned on by a transmission signal TG provided by, for example, a row driver (130 in FIG. 1) to transfer the charge generated by the photoelectric element PD to the floating diffusion FD.

[0055] The floating diffusion FD may act as a kind of capacitor C1 having a predetermined capacitance and may store the charge generated by the photoelectric element PD.

[0056] The gate terminal of the drive transistor DT may be connected to the floating diffusion FD. The drive transistor DT may operate as a source follower buffer amplifier using the charge stored in the floating diffusion FD. That is, the drive transistor DT may amplify the charge generated in the photoelectric element PD and transferred to the floating diffusion FD using the power supply voltage VDD, and transfer the amplified charge to the selection transistor ST.

[0057] The selection transistor ST may be turned on by a selection signal SEL provided by, for example, a row driver (130 in FIG. 1) to perform switching and addressing operations. When the selection signal SEL is applied from the row driver (130 in FIG. 1), a pixel signal VO may be output to a column line connected to the selection transistor ST. This pixel signal VO may be detected by a readout circuit (150 in FIG. 1).

[0058] The reset transistor RT can be turned on by, for example, a reset signal RG input by a row driver (130 in FIG. 1). When the reset transistor RT is turned on by the reset signal RG, the floating diffusion FD and the capacitor C2 are reset to the power supply voltage VDD.

[0059] The DCG transistor GT may be turned on by, for example, a gain control signal CGCS provided from a readout circuit (150 in FIG. 1). Specifically, the DCG transistor GT may be turned on by, for example, at least one of a reset signal RG provided from a row driver (130 in FIG. 1) and a gain control signal CGCS provided from the readout circuit (150 in FIG. 1). To this end, for example, the gate of the DCG transistor GT may be connected to the output of an OR gate ORG, which may OR the reset signal RG and the gain control signal CGCS and provide the result to the gate of the DCG transistor GT.

[0060] When the DCG transistor GT is turned on, the floating diffusion FD may be reset to the power supply voltage VDD, and the capacitance of the floating diffusion FD may increase to the sum of the capacitance of the capacitor C1 and the capacitance of the capacitor C2. That is, when the DCG transistor GT is turned off, the floating diffusion FD has the capacitance of the capacitor C1, so the image sensor 100 generates an image signal in a high conversion gain mode, and when the DCG transistor GT is turned on, the capacitance of the floating diffusion FD increases by the capacitance of the capacitor C2, so the image sensor 100 may generate an image signal in a low conversion gain mode.

[0061] In some embodiments, the ratio of the capacitance of capacitor C1 to the capacitance of capacitor C2 may be approximately 1:3, although embodiments are not limited thereto.

[0062] In this embodiment, the reset transistor RT and the drive transistor DT are each shown to be supplied with a power supply voltage VDD, but the embodiment is not limited thereto. If necessary, the voltages supplied to the reset transistor RT and the drive transistor DT may be modified in a manner different from that shown. For example, in some embodiments of the present invention, the reset transistor RT may be supplied with a first voltage, and the drive transistor DT may be supplied with a second voltage different from the first voltage.

[0063] FIG. 6 is a block diagram illustrating the pixel array and readout circuitry of FIG.

[0064] 6, pixel array 140 may include a plurality of pixels PX(i,j). The plurality of pixels PX(i,j) may be arranged into a plurality of rows (i) and a plurality of columns (j). A row line is arranged for each of the plurality of rows (i), and a column line is arranged for each of the plurality of columns (j). Each pixel PX(i,j) may be selected by transmission signals TG(i), TG(i+1), TG(i+2) and selection signals SEL(i), SEL(i+1), SEL(i+2) to output pixel signals VO(j), VO(j+1), VO(j+2).

[0065] The readout circuit 150 may include a plurality of comparators 152(j), 152(j+1), 152(j+2) and a plurality of counters 154(j), 154(j+1), 154(j+2) coupled to a plurality of columns (j) of the pixel array 140. The readout circuit 150 may perform, for example, correlated double sampling and analog-to-digital conversion operations via the plurality of comparators 152(j), 152(j+1), 152(j+2) and the plurality of counters 154(j), 154(j+1), 154(j+2).

[0066] The ramp signal generator 160 may generate a ramp signal VR. The ramp signal VR may have the form of, for example, a triangular wave, as a signal for converting the pixel signals VO(j), VO(j+1), and VO(j+2), which are analog signals, into digital signals OD(j), OD(j+1), and OD(j+2).

[0067] The ramp signal generator 160 may generate the ramp signal VR in response to, for example, the ramp enable signal R_EN generated by the control register block 110. In some embodiments, the ramp signal generator 160 may control the ramp signal VR by causing a pulse due to a voltage drop to be generated in the ramp signal VR during an interval in which the ramp enable signal R_EN is enabled, but the embodiments are not limited thereto.

[0068] The ramp signal VR generated by the ramp signal generator 160 may be provided to each of the comparators 152(j), 152(j+1), and 152(j+2). Each of the comparators 152(j), 152(j+1), and 152(j+2) may correspond one-to-one to a column line (j) of one pixel PX(i,j).

[0069] Comparators 152(j), 152(j+1), and 152(j+2) may compare the ramp signal VR with the pixel signals VO(j), VO(j+1), and VO(j+2). Specifically, comparators 152(j), 152(j+1), and 152(j+2) may compare the ramp signal VR with the reset voltages of pixel signals VO(j), VO(j+1), and VO(j+2), perform a first comparison between the ramp signal VR and the signal voltages of pixel signals VO(j), VO(j+1), and VO(j+2), and perform a second comparison between the ramp signal VR and the signal voltages of pixel signals VO(j), VO(j+1), and VO(j+2). This will be described in detail later.

[0070] In some embodiments, comparators 152(j), 152(j+1), and 152(j+2) may compare the ramp signal VR with the pixel signals VO(j), VO(j+1), and VO(j+2) and output a comparison signal based on the comparison result. Such a comparison signal may be a binary signal indicating whether the ramp signal VR or the pixel signals VO(j), VO(j+1), and VO(j+2) is greater. For example, if the ramp signal VR is greater, a "1" is output, and if the pixel signals VO(j), VO(j+1), and VO(j+2) are greater, a "0" is output. Alternatively, the comparators may be configured to output the opposite.

[0071] Each counter 154(j), 154(j+1), 154(j+2) may correspond one-to-one to each comparator 152(j), 152(j+1), 152(j+2). That is, one comparison signal may be counted by one counter 154(j), 154(j+1), 154(j+2). However, the embodiment is not limited to this.

[0072] Counters 154(j), 154(j+1), and 154(j+2) count how long the comparison signals output from comparators 152(j), 152(j+1), and 152(j+2) maintain the same value, for example, based on the point in time when ramp enable signal R_EN is enabled (or based on the point in time when a separate counter signal is enabled). Based on the counting results, counters 154(j), 154(j+1), and 154(j+2) can output digital signals OD(j), OD(j+1), and OD(j+2) corresponding to analog pixel signals VO(j), VO(j+1), and VO(j+2).

[0073] Control signal generators 156(j), 156(j+1), and 156(j+2) may generate gain control signals CGCS(j), CGCS(j+1), and CGCS(j+2), respectively. Specifically, control signal generators 156(j), 156(j+1), and 156(j+2) may generate gain control signals CGCS(j), CGCS(j+1), and CGCS(j+2) based on the outputs of comparators 152(j), 152(j+1), and 152(j+2). This will be described in more detail below.

[0074] The gain control signals CGCS(j), CGCS(j+1), and CGCS(j+2) generated from the control signal generators 156(j), 156(j+1), and 156(j+2) can be provided to a plurality of pixels PX(i,j) via column lines.

[0075] 6 shows a configuration in which control signal generators 156(j), 156(j+1), and 156(j+2) generate gain control signals CGCS(j), CGCS(j+1), and CGCS(j+2) based on the outputs of comparators 152(j), 152(j+1), and 152(j+2), but the embodiment is not limited to this. In some other embodiments, control signal generators 156(j), 156(j+1), and 156(j+2) can also generate gain control signals CGCS(j), CGCS(j+1), and CGCS(j+2) based on the outputs of counters 154(j), 154(j+1), and 154(j+2).

[0076] The operation of the image sensing device according to some embodiments will now be described with reference to FIGS.

[0077] 7 is a timing diagram illustrating the operation of an image sensing device according to some embodiments, and FIG. 8 is a diagram illustrating the structure of a digital signal output from the readout circuit of FIG.

[0078] The ramp signal VR shown in FIG. 7 is a signal provided to the comparator 152 during one sensing period 1H in which the selection signal SEL maintains a logic high level (hereinafter, H level).

[0079] That is, the ramp signal generator 160 may provide the comparator 152 with a ramp signal VR in which a first pulse P1 that drops from the reference voltage to the ramp reset voltage V1 by a first level dV1, a second pulse P2 that drops from the reference voltage to the ramp reference voltage REF by a second level dV2, and a third pulse P3 that drops from the reference voltage to the ramp signal voltage V3 by a third level dV3 are sequentially applied during one sensing period 1H in which the selection signal SEL maintains an H level.

[0080] Specifically, the ramp signal generator 160 may respond to the ramp enable signal R_EN during one sensing period 1H by sequentially generating a first pulse P1 having a first magnitude, a second pulse P2 having a second magnitude greater than the first magnitude, and a third pulse P3 having a third magnitude greater than the second magnitude as the ramp signal VR and providing the ramp signal VR to the comparator 152.

[0081] Here, the ramp reference voltage REF may be determined between the ramp reset voltage V1 and the ramp signal voltage V3. That is, the second pulse P2 of the ramp signal VR may fall further below the first level dV1 from the reference voltage, but less below the third level dV3.

[0082] In some embodiments, the lamp reference voltage REF is determined by the saturation voltage of an analog-to-digital converter included in the readout circuit 150, although embodiments are not limited thereto.

[0083] The selection signal SEL, reset signal RG, transmission signal TG, etc. shown in FIG. 7 are provided, for example, from a timing generator (120 in FIG. 1) under the control of a control register block (110 in FIG. 1), but the embodiment is not limited to this.

[0084] 5 to 7, in the first section T1, the reset signal RG goes high, turning on the reset transistor RT. The high-level reset signal RG is also provided to the OR gate ORG connected to the gate of the DCG transistor GT, so the output of the OR gate ORG also goes high, turning on the DCG transistor GT.

[0085] Therefore, a reset voltage is provided to the floating diffusion FD and the capacitor C2, resetting the floating diffusion FD and the capacitor C2. In this embodiment, the reset voltage may be, for example, the power supply voltage VDD. In the following description, the reset voltage is the power supply voltage VDD as an example.

[0086] Next, when the reset signal RG transitions from H level to logic low level (hereinafter referred to as L level), the reset transistor RT and the DCG transistor GT are turned off. Meanwhile, the drive transistor DT generates a pixel signal VO based on the charge stored in the floating diffusion FD (the charge reset by the power supply voltage VDD), and since the selection transistor ST is turned on, the generated pixel signal VO is output to the readout circuit 150 along the column line.

[0087] The readout circuit 150 receives the pixel signal VO and compares it with the first pulse P1 to convert the reset signal of the pixel PX into a digital signal OD.

[0088] Next, in the second section T2, when the transmission signal TG transitions from L level to H level, the charge transfer transistor CT is turned on. When the charge transfer transistor CT is turned on, the charge generated by the photoelectric element PD is provided to the floating diffusion FD (or the amount of charge stored in the floating diffusion FD is changed by the light incident on the photoelectric element PD).

[0089] The driving transistor DT generates a pixel signal VO based on the charge stored in the floating diffusion FD (the charge generated by the photoelectric element PD), and since the selection transistor ST is turned on, the generated pixel signal VO is output to the readout circuit 150 along the column line.

[0090] If the optical power of the sensed image is low (e.g., in a dark environment), the voltage level of the pixel signal VO will change only slightly compared to the reset signal, like the low pixel signal VOL, or if the optical power of the sensed image is high (e.g., in a bright environment), the voltage level of the pixel signal VO will change more compared to the reset signal, like the high pixel signal VOH.

[0091] It is preferable that the low pixel signal VOL generates an image signal at a high conversion gain (HCG) without increasing the capacitance of the floating diffusion FD in order to maximize sensing efficiency, and it is preferable that the high pixel signal VOH generates an image signal at a low conversion gain (LCG) by increasing the capacitance of the floating diffusion FD in order to maximize sensing saturation level.

[0092] To determine this, the readout circuit 150 receives the pixel signal VO and compares it with the second pulse P2 to determine the signal level of the gain control signal CGCS.

[0093] In the second section T2, the second pulse P2 drops to the lamp reference voltage REF, and then in the third section T3, the second pulse P2 maintains the lamp reference voltage REF.

[0094] At this time, the control signal generator 156 monitors the signal of the comparator 152 and determines whether the pixel signal VO provided from the pixel PX in the second period T2 is the low pixel signal VOL or the high pixel signal VOH.

[0095] For example, if the pixel signal VO provided from the pixel PX is the low pixel signal VOL, the comparator 152 outputs 0 indicating that the pixel signal VO is greater than the ramp signal VR, and the control signal generator 156 receives this signal and understands that it must generate an image signal with a high conversion gain in the current sensing period 1H. Also, if the pixel signal VO provided from the pixel PX is the high pixel signal VOH, the comparator 152 outputs 1 indicating that the pixel signal VO is less than the ramp signal VR, and the control signal generator 156 receives this signal and understands that it must generate an image signal with a low conversion gain in the current sensing period 1H.

[0096] Next, in the fourth section T4, the control signal generator 156 generates and outputs the gain control signal CGCS at an H level or an L level.

[0097] If the pixel signal VO provided from the pixel PX is the low pixel signal VOL, the control signal generator 156 outputs a low-level gain control signal CGCS to keep the DCG transistor GT turned off. In the fourth interval T4, the reset signal RG is kept low, so that the DCG transistor GT is turned on or off depending on the signal level of the gain control signal CGCS.

[0098] The driving transistor DT generates a pixel signal VO based on the charge stored in the floating diffusion FD (the charge generated by the photoelectric element PD), and since the selection transistor ST is turned on, the generated pixel signal VO is output to the readout circuit 150 along the column line.

[0099] The readout circuit 150 receives the pixel signal VO and compares it with the third pulse P3 to convert the image signal of the pixel PX into a digital signal OD.

[0100] Specifically, the comparator 152 compares the ramp signal VR with the pixel signal VO from a specific point in time (e.g., the point in time when the comparator 152 is enabled) and outputs the comparison result as a comparison signal to the counter 154. The counter 154 can count the comparison signal and convert the pixel signal VO into a digital signal OD.

[0101] Conversely, if the pixel signal VO provided from the pixel PX is the high pixel signal VOH, the control signal generator 156 outputs a high-level gain control signal CGCS to turn on the DCG transistor GT. As a result, the capacitance of the floating diffusion FD increases in response to the effect of the capacitor C2, and the signal level of the pixel signal VO may change in response to a change in the capacitance of the floating diffusion FD.

[0102] The driving transistor DT generates a pixel signal VO based on the charge stored in the floating diffusion FD (the charge generated by the photoelectric element PD), and since the selection transistor ST is turned on, the generated pixel signal VO is output to the readout circuit 150 along the column line.

[0103] The readout circuit 150 receives the pixel signal VO and compares it with the third pulse P3 to convert the image signal of the pixel PX into a digital signal OD.

[0104] Specifically, the comparator 152 may compare the ramp signal VR with the pixel signal VO from a specific point in time (e.g., the point in time when the comparator 152 is enabled) and output the comparison result as a comparison signal to the counter 154. The counter 154 may count the comparison signal and convert the pixel signal VO into a digital signal OD.

[0105] Referring to FIG. 8, the digital signal OD output from the readout circuit 150 for each sensing period 1H may include digital image data DID and conversion gain information GI.

[0106] The digital image data DID may be, for example, data generated based on the difference between the image signal of pixel PX and the reset signal of pixel PX, and the conversion gain information GI may be information indicating whether the digital image data DID is data generated with a low conversion gain or data generated with a high conversion gain.

[0107] The digital signal OD thus generated can be provided in the form of an image signal (IMS in FIG. 1) to an image processor 900 outside the image sensor 100. The image processor 900 can determine and perform necessary processing on the digital image data DID based on the conversion gain information GI.

[0108] FIG. 9 is a diagram illustrating the effects of the image sensing device according to some embodiments.

[0109] 8 and 9, the image sensing device according to this embodiment can generate a digital signal OD in different gain modes by comparing the optical power of the sensed image with the lamp reference voltage REF within one sensing period 1H in which the selection signal SEL maintains an H level.

[0110] If the optical power of the sensed image is lower than the lamp reference voltage REF, the digital signal OD is generated with a high conversion gain to maximize the sensing efficiency since optical efficiency is more important than dynamic range. Conversely, if the optical power of the sensed image is higher than the lamp reference voltage REF, the digital signal OD is generated with a low conversion gain to maximize the dynamic range.

[0111] In this embodiment, the conversion gain or low conversion gain is not determined based on an image of a previous frame or an image signal of another sensing period, but the operation of determining the high conversion gain or low conversion gain and the operation of generating the digital signal OD are all performed within one sensing period 1H, thereby enabling high-speed operation of the image sensor.

[0112] Hereinafter, image sensing devices according to some embodiments will be described with reference to Figures 10 and 11. In the following, a description of the same configuration as in the previously described embodiments will be omitted and differences will be mainly described.

[0113] 10 is a block diagram of an image sensing device according to some other embodiments. FIG. 11 is an exemplary circuit diagram of the timing controller of FIG.

[0114] Referring to FIG. 10, the readout circuit 150 of the image sensor 200 may further include timing controllers 158(j), 158(j+1), and 158(j+2).

[0115] Timing controllers 158(j), 158(j+1), and 158(j+2) receive first gain control signals CGCS1(j), CGCS1(j+1), and CGCS1(j+2) from control signal generators 156(j), 156(j+1), and 156(j+2), and provide second gain control signals CGCS2(j), CGCS2(j+1), and CGCS2(j+2) to DCG transistors (GT in FIG. 5 ). The DCG transistors (GT in FIG. 5 ) may be turned on or off depending on the signal levels of the second gain control signals CGCS2(j), CGCS2(j+1), and CGCS2(j+2).

[0116] Timing controllers 158(j), 158(j+1), and 158(j+2) adjust the timing of first gain control signals CGCS1(j), CGCS1(j+1), and CGCS1(j+2) generated by control signal generators 156(j), 156(j+1), and 156(j+2), and provide the signals to the DCG transistors (GT in FIG. 5) in the form of second gain control signals CGCS2(j), CGCS2(j+1), and CGCS2(j+2). That is, the first gain control signals CGCS1(j), CGCS1(j+1), and CGCS1(j+2) and the second gain control signals CGCS2(j), CGCS2(j+1), and CGCS2(j+2) may have the same signal levels but different signal transition timings.

[0117] Such timing controllers 158(j), 158(j+1), and 158(j+2) can be implemented in various forms. An example of timing controllers 158(j), 158(j+1), and 158(j+2) will be described below with reference to FIG. 11.

[0118] Referring to FIG. 11, the timing controller 158 may include a first switch 158a, a storage unit 158b, and a second switch 158c.

[0119] The first switch 158a is controlled by a first switch signal SW1, and when the first switch 158a is turned on, for example, the gain control signal CGCS provided from the control signal generator 156 may be stored in the storage unit 158b.

[0120] The second switch 158c is controlled by a second switch signal SW2, and when the second switch 158c is turned on, the second switch 158c may provide the gain control signal CGCS stored in the storage unit 158b to, for example, the DCG transistor (GT in FIG. 5).

[0121] Therefore, the gain control signal CGCS provided to the timing controller 158 may be provided to the outside after its timing has been adjusted (for example, delayed).

[0122] 12 is a timing diagram illustrating the operation of an image sensing device according to some other embodiments. Hereinafter, the same operations as those in the previously described embodiments will be omitted and differences will be mainly described.

[0123] 10 to 12, during the third period T3, while the control signal generator 156 generates the first gain control signal CGCS1, the first switch signal SW1 transitions to an H level and the second switch signal SW2 maintains an L level. Therefore, the first gain control signal CGCS1 is stored in the storage unit 158b of the timing controller 158. At this time, because the second switch 158c is turned off, the first gain control signal CGCS1 is not provided to the DCG transistor (GT in FIG. 5).

[0124] Subsequently, the first switch signal SW1 transitions to an L level and the second switch signal SW2 transitions to an H level, so that the first gain control signal CGCS1 stored in the storage unit 158b of the timing controller 158 is provided to the DCG transistor (GT in FIG. 5) as the second gain control signal CGCS2.

[0125] In this way, by separating the timing at which the gain control signal CGCS is generated from the timing at which the gain control signal CGCS is provided to the DCG transistor (GT in FIG. 5), it is possible to prevent negative feedback from the readout circuit 150 from occurring in the pixel PX.

[0126] Although the above description has been given of an example in which a unit sensing unit that generates and outputs a pixel signal in an image sensor corresponds to one pixel PX, the embodiment is not limited thereto. The invention may also be embodied in a form in which a unit sensing unit of an image sensor corresponds to multiple pixels PX. Some embodiments will be described below, but the embodiment is not limited to the following examples.

[0127] FIG. 13 is an exemplary diagram illustrating a pixel array of an image sensing device according to still other embodiments.

[0128] 13, the pixel array of the image sensor 300 may be configured in a tetra pattern. The tetra pattern in FIG. 13 shows a case where only 16 filters are arranged in four rows and four columns, but this is merely an example of a partial filter area for convenience, and the embodiment is not limited thereto. That is, any number of filters may be applied to the tetra pattern.

[0129] The tetrahedron pattern may include filters of three hues: red, green, and blue. That is, the R filter R may transmit only red light, the G filters Gr and Gb may transmit only green light, and the B filter B may transmit only blue light.

[0130] The tetrahedral pattern has R, G, and B filters R, Gb, Gr, and B arranged in a regular pattern as shown in Fig. 13. Taking into account the characteristics of human vision, the G filters may include a G filter Gr located next to the R filter R and a G filter Gb located next to the B filter B as shown in Fig. 13.

[0131] Each color filter (e.g., R, Gr, Gb, or B) may form a 2x2 matrix of sensing units to form a tetrahedral pattern. In the tetrahedral pattern, the same color filters (e.g., R, Gr, Gb, or B) are adjacent to each other, resulting in high spatial similarity. This can effectively reduce noise caused by, for example, binning.

[0132] FIG. 14 is a circuit diagram showing a pixel circuit of an image sensing device according to still other embodiments.

[0133] 14, in the tetra pattern described with reference to FIG. 13, for example, four photoelectric elements PD1, PD2, PD3, and PD4 may share one floating diffusion FD. As shown in the drawing, the four photoelectric elements PD1, PD2, PD3, and PD4 may also share the reset transistor RT, the drive transistor DT, and the select transistor ST.

[0134] When the transmission signal TG(i) of the photoelectric element PD1 goes high, the charge transfer transistor TG is turned on and connected to the floating diffusion FD. When the transmission signal TG(i+1) of the photoelectric element PD2 goes high, the charge transfer transistor TG is turned on and connected to the floating diffusion FD. When the transmission signal TG(i+2) of the photoelectric element PD3 goes high, the charge transfer transistor TG is turned on and connected to the floating diffusion FD. When the transmission signal TG(i+3) of the photoelectric element PD4 goes high, the charge transfer transistor TG is turned on and connected to the floating diffusion FD.

[0135] The timing of the transmission signals TG(i), TG(i+1), TG(i+2), and TG(i+4) is adjusted to determine the conversion gain mode for each sensing unit including four photoelectric elements PD1, PD2, PD3, and PD4, and image data can be generated according to the determined conversion gain mode.

[0136] Meanwhile, the sensor array of the image sensor may be modified to form unit sensing units in which N*N (N is a natural number greater than or equal to 3) pixels have the same color filter, and generate independent image signals for each unit sensing unit, unlike the previously described embodiment.

[0137] 15 is an exemplary diagram illustrating a pixel array of an image sensing device according to still other embodiments, and the following description will focus on differences from the previously described embodiments.

[0138] Referring to FIG. 15, each pixel of the image sensor 400 is provided with a pixel circuit PC and a readout circuit ROC.

[0139] Here, the pixel circuit PC arranged in each pixel may include, for example, the pixel circuit PX shown in Fig. 5, and the readout circuit ROC may include the comparator 152, counter 154, and control signal generator 156 shown in Fig. 6. Also, in some embodiments, the readout circuit ROC may include the comparator 152, counter 154, control signal generator 156, and timing controller 158 shown in Fig. 10.

[0140] In this embodiment, since a readout circuit ROC is disposed in each pixel, each pixel may output a digital signal OD rather than an analog signal. At this time, the digital signal OD output from each pixel may include conversion gain information (GI in FIG. 8) corresponding to the digital image data (DID in FIG. 8) sensed by each pixel. Therefore, the digital signals OD output from each pixel may include different conversion gain information (GI in FIG. 8).

[0141] For example, when sensing one frame of image, pixel PX(a, b) may output a digital signal OD including conversion gain information (GI in FIG. 8) corresponding to a low conversion gain and digital image data (DID in FIG. 8) sensed at the low conversion gain, and pixel PX(c, d) may output a digital signal OD including conversion gain information (GI in FIG. 8) corresponding to a high conversion gain and digital image data (DID in FIG. 8) sensed at the high conversion gain.

[0142] In some embodiments, when the image sensor 400 includes an upper substrate and a lower substrate stacked on top of each other, the readout circuit ROC included in each pixel is disposed on the lower substrate, although embodiments are not limited thereto.

[0143] Fig. 16 is a block diagram of an electronic device including a multi-camera module, and Fig. 17 is a detailed block diagram of the camera module of Fig. 16.

[0144] Referring to FIG. 16, an electronic device 1000 may include a camera module group 1100, an application processor 1200, a PMIC 1300, and an external memory 1400.

[0145] The camera module group 1100 may include multiple camera modules 1100a, 1100b, and 1100c. Although the drawings show an embodiment with three camera modules 1100a, 1100b, and 1100c, the embodiment is not limited thereto. In some embodiments, the camera module group 1100 may be modified to include only two camera modules. In some embodiments, the camera module group 1100 may be modified to include n camera modules (n is a natural number greater than or equal to 4).

[0146] The detailed configuration of the camera module 1100b will be described in more detail below with reference to FIG. 17, but the following description can also be similarly applied to the other camera modules 1100a and 1100c according to the embodiment.

[0147] Referring to FIG. 17, the camera module 1100b may include a prism 1105, an optical path folding element (hereinafter, "OPFE") 1110, an actuator 1130, an image sensing device 1140, and a storage unit 1150.

[0148] The prism 1105 includes a reflective surface 1107 made of a light-reflecting material and can change the path of light L incident from the outside.

[0149] In some embodiments, the prism 1105 may change the path of light L incident in a first direction X to a second direction Y perpendicular to the first direction X. The prism 1105 may also change the path of light L incident in the first direction X to the perpendicular second direction Y by rotating the reflective surface 1107 of the light-reflecting material about a central axis 1106 in a direction A or by rotating the central axis 1106 in a direction B. At this time, the OPFE 1110 may also move in a third direction Z perpendicular to the first direction X and the second direction Y.

[0150] In some embodiments, as shown in the drawings, the maximum rotation angle of prism 1105 in the A direction may be less than 15 degrees in the plus (+) A direction and greater than 15 degrees in the minus (-) A direction, although embodiments are not limited thereto.

[0151] In some embodiments, prism 1105 can move 20 degrees in or out in the plus (+) or minus (-) B direction, or between 10 and 20 degrees, or between 15 and 20 degrees, where the angle of movement can be the same angle in the plus (+) or minus (-) B direction, or can move to a similar angle within a range of 1 degree in or out.

[0152] In some embodiments, the prism 1105 may move the reflective surface 1107 of the light-reflecting material in a third direction (eg, Z direction) parallel to the extension direction of the central axis 1106 .

[0153] The OPFE 1110 may include, for example, m (where m is a natural number) groups of optical lenses. The m lenses can move in the second direction Y to change the optical zoom ratio of the camera module 1100b. For example, if the basic optical zoom ratio of the camera module 1100b is Z, moving the m optical lenses included in the OPFE 1110 can change the optical zoom ratio of the camera module 1100b to 3Z, 5Z, or more than 5Z.

[0154] The actuator 1130 can move the OPFE 1110 or the optical lens (hereinafter referred to as the optical lens) to a specific position. For example, the actuator 1130 can adjust the position of the optical lens so that the image sensor 1142 is located at the focal length of the optical lens for accurate sensing.

[0155] Image sensing device 1140 may include an image sensor 1142, control logic 1144, and memory 1146. Image sensor 1142 may sense an image of a sensing target using light L provided through an optical lens. In some embodiments, image sensor 1142 may include at least one of image sensors 100, 200, 300, and 400 described above.

[0156] The control logic 1144 may control the overall operation of the camera module 1100b. For example, the control logic 1144 may control the operation of the camera module 1100b by a control signal provided via the control signal line CSLb.

[0157] The memory 1146 may store information necessary for the operation of the camera module 1100b, such as calibration data 1147. The calibration data 1147 may include information necessary for the camera module 1100b to generate image data using externally provided light L. The calibration data 1147 may include, for example, information regarding the degree of rotation, the focal length, and the optical axis, as previously described. If the camera module 1100b is embodied in the form of a multi-state camera in which the focal length changes depending on the position of the optical lens, the calibration data 1147 may include a focal length value for each position (or state) of the optical lens and information related to autofocusing.

[0158] The storage unit 1150 may store image data sensed via the image sensor 1142. The storage unit 1150 may be disposed outside the image sensing device 1140 and may be embodied in a stacked form with the sensor chips constituting the image sensing device 1140. In some embodiments, the storage unit 1150 may be embodied as an EEPROM (Electrically Erasable Programmable Read-Only Memory), but the embodiment is not limited thereto.

[0159] 16 and 17 , in some embodiments, each of the camera modules 1100a, 1100b, and 1100c may include an actuator 1130. As such, each of the camera modules 1100a, 1100b, and 1100c may include calibration data 1147 that is the same as or different from one another due to the operation of the actuator 1130 included therein.

[0160] In some embodiments, one of the multiple camera modules 1100a, 1100b, and 1100c (e.g., 1100b) may be a folded lens type camera module including the previously described prism 1105 and OPFE 1110, and the remaining camera modules (e.g., 1100a and 1100c) may be vertical type camera modules that do not include the prism 1105 and OPFE 1110, but the embodiments are not limited to this.

[0161] In some embodiments, one of the camera modules 1100a, 1100b, and 1100c (e.g., 1100c) may be a vertical depth camera that extracts depth information using infrared rays (IR). In this case, the application processor 1200 may merge image data provided by the vertical depth camera with image data provided by a different camera module (e.g., 1100a or 1100b) to generate a 3D depth image.

[0162] In some embodiments, at least two camera modules (e.g., 1100a, 1100b) of the plurality of camera modules 1100a, 1100b, 1100c may have different fields of view (fields of view) from each other, for example, but not limited to, the optical lenses of at least two camera modules (e.g., 1100a, 1100b) of the plurality of camera modules 1100a, 1100b, 1100c may be different from each other.

[0163] In some embodiments, the camera modules 1100a, 1100b, and 1100c may have different viewing angles, and in this case, the optical lenses included in the camera modules 1100a, 1100b, and 1100c may also be different, but this is not limiting.

[0164] In some embodiments, each of the camera modules 1100a, 1100b, and 1100c is physically separated from the others, i.e., instead of the multiple camera modules 1100a, 1100b, and 1100c sharing the sensing area of ​​a single image sensor 1142, an independent image sensor 1142 is disposed within each of the multiple camera modules 1100a, 1100b, and 1100c.

[0165] 16, the application processor 1200 may include an image processing unit 1210, a memory controller 1220, and an internal memory 1230. The application processor 1200 may be implemented separately from the camera modules 1100a, 1100b, and 1100c. For example, the application processor 1200 and the camera modules 1100a, 1100b, and 1100c may be implemented separately from each other on separate semiconductor chips.

[0166] The image processing device 1210 may include multiple sub-image processors 1212 a , 1212 b , 1212 c , an image generator 1214 , and a camera module controller 1216 .

[0167] The image processing device 1210 may include a plurality of sub-image processors 1212a, 1212b, and 1212c, the number of which corresponds to the number of the camera modules 1100a, 1100b, and 1100c.

[0168] Image data generated from each of camera modules 1100a, 1100b, and 1100c is provided to corresponding sub-image processors 1212a, 1212b, and 1212c via separate image signal lines ISLa, ISLb, and ISLc. For example, image data generated from camera module 1100a is provided to sub-image processor 1212a via image signal line ISLa, image data generated from camera module 1100b is provided to sub-image processor 1212b via image signal line ISLb, and image data generated from camera module 1100c is provided to sub-image processor 1212c via image signal line ISLc. Such image data transmission may be performed using a camera serial interface (CSI) based on MIPI (Mobile Industry Processor Interface), for example, but is not limited to this embodiment.

[0169] In some embodiments, the image data generated from each of the camera modules 1100a, 1100b, and 1100c may include the conversion gain information (GI in FIG. 8) for each sensing unit described above. This conversion gain information (GI in FIG. 8) is provided to the sub-image processors 1212a, 1212b, and 1212c or the image generator 1214 for use in image processing.

[0170] In some embodiments, each camera module 1100a, 1100b, 1100c generates first and second image signals that constitute one frame image, and may provide a first image signal including first conversion gain information to sub-image processors 1212a, 1212b, 1212c or image generator 1214, and a second image signal including second conversion gain information different from the first conversion gain information to sub-image processors 1212a, 1212b, 1212c or image generator 1214. That is, the first and second image signals that constitute one frame image may include different conversion gain information.

[0171] The sub-image processors 1212a, 1212b, 1212c or the image generator 1214 may perform first image processing using first conversion gain information contained in the first image signal, and may perform second image processing using second conversion gain information contained in the second image signal.

[0172] On the other hand, in some embodiments, one sub-image processor may be arranged to correspond to multiple camera modules. For example, instead of being implemented separately from each other as shown in FIG. 1, sub-image processor 1212a and sub-image processor 1212c may be integrated into one sub-image processor, and image data provided from camera module 1100a and camera module 1100c may be selected by a selection element (e.g., a multiplexer) and then provided to the integrated sub-image processor.

[0173] The image data provided to each of the sub-image processors 1212a, 1212b, and 1212c is provided to an image generator 1214. The image generator 1214 can generate an output image using the image data provided from each of the sub-image processors 1212a, 1212b, and 1212c in response to image generation information or a mode signal.

[0174] Specifically, the image generator 1214 may generate an output image by merging at least a portion of the image data generated from the camera modules 1100a, 1100b, and 1100c having different viewing angles in response to the image generation information or the mode signal. Alternatively, the image generator 1214 may generate an output image by selecting one of the image data generated from the camera modules 1100a, 1100b, and 1100c having different viewing angles in response to the image generation information or the mode signal.

[0175] In some embodiments, the image generation information may include a zoom signal or zoom factor, and in some embodiments, the mode signal may be based on a mode selected by a user, for example.

[0176] If the image generation information is a zoom signal (zoom factor) and each of the camera modules 1100a, 1100b, and 1100c has a different field of view (viewing angle), the image generator 1214 may perform different operations depending on the type of zoom signal. For example, if the zoom signal is a first signal, the image generator 1214 may merge the image data output from camera module 1100a and the image data output from camera module 1100c, and then generate an output image using the merged image signal and the image data output from camera module 1100b that was not used in the merging. If the zoom signal is a second signal different from the first signal, the image generator 1214 may not merge the image data, but may instead select one of the image data output from each of the camera modules 1100a, 1100b, and 1100c to generate an output image. However, the embodiments are not limited thereto, and the method of processing image data may be modified as needed.

[0177] In some embodiments, the image generator 1214 receives multiple image data with different exposure times from at least one of the multiple sub-image processors 1212a, 1212b, and 1212c, and can generate merged image data with an increased dynamic range by performing HDR (high dynamic range) processing on the multiple image data.

[0178] The camera module controller 1216 can provide control signals to each of the camera modules 1100a, 1100b, and 1100c. The control signals generated by the camera module controller 1216 are provided to the corresponding camera modules 1100a, 1100b, and 1100c via separate control signal lines CSLa, CSLb, and CSLc.

[0179] One of the camera modules 1100a, 1100b, and 1100c is designated as a master camera (e.g., 1100b) according to image generation information including a zoom signal or a mode signal, and the remaining camera modules (e.g., 1100a and 1100c) are designated as slave cameras. This information is included in a control signal and provided to the corresponding camera modules 1100a, 1100b, and 1100c via separate control signal lines CSLa, CSLb, and CSLc.

[0180] The camera modules operating as the master and slave may be changed depending on the zoom factor or the operation mode signal. For example, if the viewing angle of camera module 1100a is wider than that of camera module 1100b and the zoom factor indicates a low zoom ratio, camera module 1100b may operate as the master and camera module 1100a may operate as the slave. Conversely, if the zoom factor indicates a high zoom ratio, camera module 1100a may operate as the master and camera module 1100b may operate as the slave.

[0181] In some embodiments, the control signals provided from the camera module controller 1216 to each of the camera modules 1100a, 1100b, and 1100c may include a sync enable signal. For example, if camera module 1100b is a master camera and camera modules 1100a and 1100c are slave cameras, the camera module controller 1216 may transmit a sync enable signal to camera module 1100b. Upon receiving the sync enable signal, camera module 1100b may generate a sync signal based on the provided sync enable signal and provide the generated sync signal to camera modules 1100a and 1100c via sync signal line SSL. Camera modules 1100b and 1100a and 1100c may transmit image data to application processor 1200 synchronized by the sync signal.

[0182] In some embodiments, the control signals provided from the camera module controller 1216 to the camera modules 1100a, 1100b, and 1100c may include mode information corresponding to the mode signal, and based on the mode information, the camera modules 1100a, 1100b, and 1100c may operate in a first operating mode or a second operating mode associated with a sensing speed.

[0183] In a first operating mode, the camera modules 1100a, 1100b, and 1100c may generate image signals at a first rate (e.g., generate image signals at a first frame rate), encode the image signals at a second rate higher than the first rate (e.g., encode image signals at a second frame rate higher than the first frame rate), and transmit the encoded image signals to the application processor 1200. In this case, the second rate may be 30 times or less than the first rate.

[0184] The application processor 1200 stores the received image signal, i.e., the encoded image signal, in the internal memory 1230 or the external storage 1400 of the application processor 1200, and thereafter reads and decodes the encoded image signal from the memory 1230 or the storage 1400, and may display image data generated based on the decoded image signal. For example, a corresponding one of the sub-processors 1212a, 1212b, and 1212c of the image processing device 1210 may perform decoding and image processing on the decoded image signal.

[0185] In the second operating mode, the camera modules 1100a, 1100b, and 1100c may generate image signals at a third rate lower than the first rate (e.g., generate image signals at a third frame rate lower than the first frame rate) and transmit the image signals to the application processor 1200. The image signals provided to the application processor 1200 may be unencoded signals. The application processor 1200 may perform image processing on the received image signals or store the image signals in the memory 1230 or the storage 1400.

[0186] The PMIC 1300 may supply power, e.g., a power supply voltage, to each of the multiple camera modules 1100a, 1100b, and 1100c. For example, under the control of the application processor 1200, the PMIC 1300 may supply a first power to the camera module 1100a via a power signal line PSLa, a second power to the camera module 1100b via a power signal line PSLb, and a third power to the camera module 1100c via a power signal line PSLc.

[0187] The PMIC 1300 generates power and adjusts the power levels for each of the camera modules 1100a, 1100b, and 1100c in response to a power control signal PCON from the application processor 1200. The power control signal PCON may include a power adjustment signal for each operation mode of the camera modules 1100a, 1100b, and 1100c. For example, the operation mode may include a low power mode, and the power control signal PCON may include information about the camera module operating in the low power mode and the power level to be set. The power levels provided to each of the camera modules 1100a, 1100b, and 1100c may be the same or different from one another. Furthermore, the power levels may be dynamically changed.

[0188] Although the present invention has been described above with reference to the accompanying drawings, it should be understood that the present invention is not limited to the above-described embodiments and may be implemented in various different forms, and that those skilled in the art will understand that the present invention may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, the above-described embodiment is illustrative in all respects and is not limiting. [Explanation of symbols]

[0189] PD: Photoelectric element FD: Floating diffusion RT: Reset transistor GT: DCG (Dual Conversion Gain) transistor DT: drive transistor ST: Select transistor C2: Capacitor CGCS: Gain Control Signal 152: Comparator 154: Counter 156: Control signal generator 158: Timing controller

Claims

1. a floating diffusion for storing the charge generated by the photoelectric element; a driving transistor that generates a pixel signal based on the charge stored in the floating diffusion; a selection transistor that outputs a pixel signal generated by the driving transistor to a column line based on a selection signal; a DCG (Dual Conversion Gain) transistor that changes the capacitance of the floating diffusion based on a gain control signal; The selection transistor outputs a first pixel signal to the column line based on the charge stored in the floating diffusion when the DCG transistor is turned off, the DCG transistor receives a gain control signal determined based on the output first pixel signal; an operation of outputting the first pixel signal to the column line and an operation of receiving the gain control signal from the DCG transistor are performed while the select signal maintains a first level; An image sensing device, wherein a signal level of the gain control signal is determined using a comparison result between the first pixel signal and a ramp signal while the select signal maintains the first level.

2. a reset transistor that provides a reset voltage to the floating diffusion based on a reset signal; further comprising a capacitor connected between the reset transistor and the DCG transistor; The image sensing device of claim 1 , wherein the DCG transistor uses the capacitor to change the capacitance of the floating diffusion.

3. The image sensing device according to claim 2 , wherein the capacitance of the capacitor is greater than the capacitance of the floating diffusion.

4. The image sensing device of claim 2 , wherein the reset transistor and the DCG transistor are simultaneously turned on based on the reset signal.

5. The image sensing device of claim 2 , further comprising an OR gate that receives the gain control signal and the reset signal, performs an OR operation on the received signal, and provides the result to the DCG transistor.

6. a charge transfer transistor that provides charge generated by the photoelectric element to the floating diffusion based on a transmission signal; The photoelectric elements include first to fourth photoelectric elements separated from each other, The charge transfer transistor is a first charge transfer transistor coupled to the first photoelectric element and the floating diffusion; a second charge transfer transistor coupled to the second photoelectric element and the floating diffusion; a third charge transfer transistor connected to the third photoelectric element and the floating diffusion; The image sensing device of claim 1 , further comprising a fourth charge transfer transistor coupled to the fourth photosensitive element and the floating diffusion.

7. a row driver that outputs a selection signal; a pixel circuit that outputs a pixel signal in response to the selection signal; a readout circuit for outputting a digital signal corresponding to the pixel signal provided by the pixel circuit; The readout circuit receiving a first pixel signal from the pixel circuit, generating a gain control signal based on a comparison result between the first pixel signal and a ramp signal, and providing the gain control signal to the pixel circuit; receiving a second pixel signal output by the pixel circuit using the gain control signal, and outputting a digital signal corresponding to the second pixel signal; the operations of the readout circuit receiving the first pixel signal from the pixel circuit, the readout circuit providing the gain control signal to the pixel circuit, and the pixel circuit outputting the second pixel signal to the readout circuit are performed while the select signal provided from the row driver to the pixel circuit maintains a first level.

8. The readout circuit a comparator that compares a ramp signal with the first pixel signal and outputs a comparison signal; The image sensing device of claim 7 , further comprising a control signal generator that generates the gain control signal based on the comparison signal.

9. The readout circuit 9. The image sensing device of claim 8, further comprising a timing controller configured to receive the first gain control signal generated by the control signal generator and to provide the pixel circuit with a second gain control signal obtained by adjusting a timing of the first gain control signal.

10. 10. The image sensing device of claim 9, wherein the timing controller includes a storage unit that stores the first gain control signal when a first switch is turned on and outputs the stored first gain control signal as the second gain control signal when a second switch is turned on.

11. 11. The image sensing device of claim 7, wherein the digital signal corresponding to the second pixel signal output from the readout circuit includes conversion gain information corresponding to a gain control signal generated based on the first pixel signal.

12. further comprising a pixel array including a plurality of pixels; a first pixel of the plurality of pixels outputs a third pixel signal; a second pixel of the plurality of pixels outputs a fourth pixel signal; the third pixel signal and the fourth pixel signal constitute an image of the same frame; The readout circuit outputting a first digital signal corresponding to the third pixel signal and a second digital signal corresponding to the fourth pixel signal; The image sensing device of claim 11 , wherein the first digital signal and the second digital signal include different conversion gain information.

13. further comprising a pixel array including a plurality of pixels; 13. The image sensing device of claim 7, wherein each pixel of the pixel array comprises the pixel circuit and the readout circuit.

14. a row driver that outputs a selection signal; a pixel circuit that outputs a pixel signal in response to the selection signal; a ramp signal generator that generates a ramp signal; a readout circuit that receives the pixel signal from the pixel circuit, compares the pixel signal with the ramp signal provided by the ramp signal generator, and outputs a digital signal corresponding to the pixel signal; the ramp signal generator provides the readout circuit with a ramp signal including a first pulse that drops from a reference voltage by a first level, a second pulse that drops from the reference voltage by a second level different from the first level, and a third pulse that drops from the reference voltage by a third level different from the second level; the ramp signal generator provides the first to third pulses to the readout circuit while the select signal provided from the row driver to the pixel circuit maintains a first level; the readout circuit receives a first pixel signal from the pixel circuit, compares the first pixel signal with a ramp signal to generate a gain control signal, and provides the gain control signal to the pixel circuit while the select signal provided from the row driver to the pixel circuit maintains the first level.

15. The image sensing device of claim 14 , wherein the first level is less than the second level, and the second level is less than the third level.

16. The readout circuit a comparator that compares the ramp signal with the pixel signal and outputs a comparison signal; a control signal generator that generates a gain control signal based on the comparison signal and provides the gain control signal to the pixel circuit; 16. The image sensing device according to claim 14, wherein the gain control signal is determined by a comparison result between the pixel signal and the second pulse.

17. The pixel circuit a photoelectric element; a floating diffusion for storing charges generated by the photoelectric element; a reset transistor that provides a reset voltage to the floating diffusion based on a reset signal; a capacitor coupled to the reset transistor; a DCG transistor connected to the capacitor and configured to change the capacitance of the floating diffusion using the capacitance of the capacitor based on the gain control signal; a driving transistor that generates the pixel signal based on the charge stored in the floating diffusion; 17. The image sensing device according to claim 16, further comprising a selection transistor that outputs a pixel signal generated by the drive transistor based on the selection signal to the readout circuit.

18. the first pulse ramps down from the reference voltage to a ramp reset voltage; the second pulse ramps down from the reference voltage to a ramp reference voltage; the third pulse ramps down from the reference voltage to a ramp signal voltage; The image sensing device of claim 14 , wherein the second pulse has a sustain section in which the lamp reference voltage is sustained for a predetermined period of time.

19. The readout circuit a comparator that compares the ramp signal with the pixel signal and outputs a comparison signal; a control signal generator that generates a first gain control signal based on the comparison signal; 20. The image sensing device of claim 18, further comprising: a timing controller configured to receive the first gain control signal generated by the control signal generator, to generate a second gain control signal by adjusting a timing of the first gain control signal during the sustain period, and to provide the second gain control signal to the pixel circuit.

20. the timing controller includes a first switch, a storage unit, and a second switch, which are serially connected to each other; At a first time point of the sustain period, the first switch is turned on and the second switch is turned off, and the first gain control signal is stored in the storage unit; 20. The image sensing device of claim 19, wherein at a second time point subsequent to the first time point of the sustain period, the first switch is turned off and the second switch is turned on, and the first gain control signal stored in the storage unit is provided to the pixel circuit as the second gain control signal.

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