Image forming device

Abstract

To reduce component cost and reduce the substrate occupied area of an entire power supply circuit.SOLUTION: A power supply device comprises booster circuits each including an MOSFET Q101, a transformer T101, a diode D101 and a comparator CP101, and a CPU 200 which outputs a PWM signal corresponding to a target voltage to the comparator CP101. The power supply device includes at least two booster circuits, and a plurality of booster circuits (100DEV, 100TRP and 100PR) are capable of outputting different high voltages (development output, transfer output and charge output). The CPU 200 outputs a common driving signal (CommCLK) to the plurality of booster circuits (100DEV, 100TRP and 100PR).SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention , painting This paper relates to image forming devices, such as electrophotographic image forming devices, including copying machines, laser printers, LED (Light Emitting Diode) printers, and electrophotographic facsimiles. [Background technology]

[0002] Electrophotographic image forming devices, which use electrophotographic technology to copy images onto recording paper, have been widely used. These image forming devices project light, such as a laser, onto a photosensitive drum uniformly charged to a positive or negative high potential, depending on the image to be copied, creating a latent image on the photosensitive drum using electrostatic charge. Developer, such as toner, is then electrostatically dispersed to the area where the latent image is formed, developing the image on the photosensitive drum to form a developer image. Next, recording paper is placed over the formed developer image, and a charge of opposite polarity to the charge held by the developer is applied from the back of the recording paper, electrostatically attracting the developer to the surface of the recording paper and transferring it. The transferred developer is then fixed to the recording paper by applying heat and pressure to the recording paper. Because electrostatic force is used to move the developer in each process in the electrophotographic system, various polarities and high voltages are required. While various high-voltage power supplies are available to accommodate these voltages, Patent Document 1 describes a circuit that requires a small number of components and can be constructed at low cost. Furthermore, Patent Document 2 discloses a technique for reducing the ripple of the output voltage by using the circuit of Patent Document 1 and improving the control method. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 09-191644 [Patent Document 2] Japanese Patent Application Publication No. 2019-213409 Summary of the Invention [Problem to be solved by the invention]

[0004] However, as shown in Figure 5, the conventional method requires the use of two CPU output ports (input 1 and input 2). Figure 5 shows a single high-voltage power supply circuit. Electrophotographic image forming devices generally require at least three high-voltage power supplies. These three refer to the transfer, charging, and development circuits. Since the entire high-voltage circuit requires inputs 1 and 2, a total of six CPU ports are required. Figure 6 shows a block diagram of this configuration. Furthermore, when driving Q101 directly from a CPU port as shown in Figure 5, Q101 must be capable of being driven at 3.3V, since the CPU's power supply voltage is generally 3.3V. However, as supply decreases year by year, using "low-voltage drive, high-voltage FETs" poses challenges to supply stability and future viability, and they are rarely adopted. Instead, 4V drive, high-voltage FETs are being adopted. This means that the drain-source ON resistance (ON resistance) is guaranteed at a gate-source voltage of 4V or higher. Therefore, to drive this FET from a CPU that operates at 3.3V, a circuit that converts the voltage level from 3.3V to 4V or higher must be added between input 1 and Q101. An example of a voltage level conversion circuit is shown in Figure 7. Figure 7 shows the same circuit as Figure 5, with a voltage level conversion circuit added between input 1 and Q101. The newly added components are R201 to R203, Q201, and ZD201. These five components are added for each high-voltage power supply, so if there are three high-voltage power supplies for charging, transfer, and development, a total of 15 components will be added. This is undesirable, as it increases costs and takes up a lot of space on the board.

[0005] The present invention has been made under these circumstances, and has as its object to reduce component costs and the area occupied by the entire power supply circuit on the board. [Means for solving the problem]

[0006] In order to solve the above-mentioned problems, the present invention has the following configuration.

[0007] (1) An image forming apparatus comprising: a charging unit that charges a photosensitive member; a developing unit that develops a latent image on the photosensitive member with a developer; a transfer unit that transfers the developer image onto a recording material; and a power supply device, wherein the power supply device has three boost circuits, each of which: The power supply includes a generating means having a switching element and a transformer that are turned on or off by a drive signal and that generates a high voltage, a rectifying means that rectifies the high voltage generated by the generating means, a detecting means that detects the output of the high voltage rectified by the rectifying means, a comparing means that compares the detection result by the detecting means with a target voltage, and a control means that controls the driving signal to be turned on or off so that the high voltage becomes a constant output voltage based on the comparison result by the comparing means. death , The power supply device an output means for outputting the drive signal and outputting a PWM signal corresponding to the target voltage to the comparison means; have , Three The boost circuit When they are respectively referred to as a first booster circuit, a second booster circuit, and a third booster circuit, the first booster circuit generates a charging voltage to be supplied to the charging means, the second booster circuit generates a developing voltage to be supplied to the developing means, and the third booster circuit generates a transfer voltage to be supplied to the transfer means, and the first booster circuit, the second booster circuit, and the third booster circuit are mutually The output means is capable of outputting different high voltages, and outputs the drive signal common to the plurality of boost circuits. The output means sequentially changes the frequency and ON time of the drive signal in accordance with a printing sequence in an electrophotographic process. Characterized by Image formation Device. [Effects of the Invention]

[0009] According to the present invention, it is possible to reduce component costs and the area occupied by the entire power supply circuit on the board. [Brief explanation of the drawings]

[0010] [Figure 1] Illustrative diagram of an image forming apparatus according to first to third embodiments. [Figure 2] Block diagram showing voltage control in the first embodiment [Figure 3] Block diagram showing voltage control in the second embodiment [Figure 4] FIG. 10 is a sequence diagram showing an image forming operation according to a third embodiment of the present invention; [Figure 5] FIG. 1 shows a conventional power supply device. [Figure 6] Block diagram showing voltage control in a conventional example [Figure 7] FIG. 1 shows a conventional power supply device. DETAILED DESCRIPTION OF THE INVENTION

[0011] [General power supply circuit (example 1)] Figure 5 is a circuit diagram of a high-voltage power supply serving as a power supply device that uses two output ports of a CPU (Central Processing Unit). Boost circuit 100 includes resistors R101-R107, capacitors C101-C103, and diodes D101 and D102. Boost circuit 100 also includes a metal-oxide semiconductor field-effect transistor (hereinafter referred to as MOSFET) Q101, a high-voltage transformer (hereinafter referred to as transformer) T101, and a comparator CP101. Boost circuit 100 outputs a negative high voltage from output 1. Generating means includes a switching element, MOSFET Q101, and transformer T101. Diode D101 functions as rectifying means.

[0012] Power supply V1 generates the primary current of transformer T101 and is a DC power supply with a relatively large voltage such as 24V. Power supply V2 is the power supply for the control circuit and is a relatively small, high-precision DC power supply with a voltage such as 3.3V or 5V. A pulse signal, which is the drive signal for driving MOSFET Q101 (turning it on or off), is input to input 1 from a control device such as a CPU. A PWM signal that determines the target voltage for output 1 is input to input 2, also from the control device.

[0013] [Power supply operation] The operation of the boost circuit 100 will be explained below. First, a pulse signal of, for example, 16 kHz with a duty cycle of approximately 10% is input from a control device to input 1. The MOSFET Q101 then turns ON / OFF in accordance with the input pulse signal, causing an excitation current to flow through the transformer T101. The transformer T101 has a primary and secondary winding with a turns ratio of 84:2700 for boosting purposes. Furthermore, the primary winding of the transformer T101 has a center tap. When the MOSFET Q101 is ON, the current flowing through the primary winding is in the following order: V1 → R107 → T101 → Q101. On the other hand, when the MOSFET Q101 is OFF, the regenerative current flows in the following order: T101 → C103 → D102. The secondary side of transformer T101 operates as follows: when MOSFET Q101 is on, diode D101 is on, and current flows in the order T101 → GND → C102 → D101, and a negative high voltage is output to Output 1. Note that if the direction of diode D101 is reversed, a positive high voltage is output to Output 1.

[0014] Next, we will explain feedback control. Output 1 is input to the non-inverting input terminal of comparator CP101 via resistor R105. As MOSFET Q101 is repeatedly turned on and off and the negative voltage appearing at Output 1 increases (as an absolute value), the voltage applied to the non-inverting input terminal of comparator CP101 gradually decreases. The PWM signal input from Input 2 is integrated by resistor R103 and capacitor C101, becoming a DC voltage according to the duty cycle of the PWM signal and being applied to the inverting input terminal of comparator CP101. The PWM signal from Input 2 is the target voltage (target value) for the output voltage from Output 1, and the low duty cycle ratio is proportional to the output voltage of Output 1.

[0015] Specifically, when the negative voltage of Output 1 increases (in absolute value) and the voltage applied to the non-inverting input terminal of comparator CP101 falls below the voltage applied to the inverting terminal, the output of comparator CP101 goes low. This forces the gate voltage of MOSFET Q101 to zero. At this time, even if a pulse signal is input from Input 1, current is drawn by comparator CP101, so MOSFET Q101 remains OFF as long as the output voltage of Output 1 exceeds the target value. After a while, the voltage of Output 1 decreases (in absolute value), and the potential relationship between the non-inverting and inverting input terminals of comparator CP101 reverses. This causes MOSFET Q101 to resume oscillation, and the output voltage from Output 1 (in absolute value) begins to increase again. By repeating this operation, the voltage of Output 1 is maintained at the target voltage. Comparator CP101 functions as a detection means for detecting high voltage output 1, a comparison means for comparing output 1 (detection result) with a target voltage, and a control means for controlling the pulse signal to be on or off based on the comparison result so that output 1 becomes a constant output voltage.

[0016] (General power supply issues) Next, we will explain the issues that arise when there are at least two of the above-mentioned boost circuits 100. The boost circuit 100 in Figure 5 is one high-voltage power supply circuit. An electrophotographic image forming apparatus generally requires at least three high-voltage power supplies. These three refer to the three types: transfer, charging, and development. In other words, the high-voltage power supply circuit as a whole requires input 1 and input 2 for each, resulting in a total of at least six CPU ports (inputs). A block diagram of this is shown in Figure 6.

[0017] In FIG. 6, the CPU 200 corresponds to the control device described above. The CPU 200 functions as an output unit that outputs a drive signal to input 1 of the boost circuit 100 described above and outputs a PWM signal corresponding to a target voltage to input 2. The development power supply 100DEV, transfer power supply 100TRP, and charging power supply 100PR all have the same configuration as the boost circuit 100 described in FIG. 5. The development power supply 100DEV outputs a development output (development voltage). The transfer power supply 100TRP outputs a transfer output (transfer voltage). The charging power supply 100PR outputs a charging output (charging voltage). Each of the multiple boost circuits 100 (100DEV, 100TRP, 100PR) can output a different high voltage. In addition, a pulse signal and a PWM signal are input to each of the boost circuits 100 from the CPU 200 via input 1 and input 2. Specifically, the CPU 200 outputs a pulse signal from DEVCLK to input 1 of the development power supply 100DEV and outputs a PWM signal from DEVPWM to input 2. The CPU 200 outputs a pulse signal from TRPCLK to input 1 of the transfer power supply 100TRP, and outputs a PWM signal from TRPPWM to input 2. The CPU 200 outputs a pulse signal from PRCLK to input 1 of the charging power supply 100PR, and outputs a PWM signal from PRPWM to input 2.

[0018] Furthermore, when MOSFET Q101 is driven directly from the CPU200 port (as shown in Figure 5), the CPU200 typically uses a 3.3V power supply, so MOSFET Q101 must be capable of 3.3V operation. Previously, there were many low-voltage, high-voltage FETs on the market that could be driven at 3.3V and had a drain-source voltage of around 150V. However, production and distribution of such FETs began to decline around 2010, leaving few options available. As a result, in the 2020s, the use of low-voltage, high-voltage FETs poses challenges in terms of supply stability and future viability, and they are increasingly being adopted. Instead, 4V-driven, high-voltage FETs are being adopted for FETs with drain-source voltages exceeding 100V. However, these FETs are driven at 4V; more specifically, they are FETs whose drain-source ON resistance is guaranteed at a gate-source voltage of 4V or higher. Therefore, to drive this FET from CPU 200 operating at 3.3V (first voltage), as shown in Figure 5, it is necessary to do the following: A conversion circuit that converts the voltage level from 3.3V to 4V or higher (a second voltage higher than the first voltage) must be added between input 1 and MOSFET Q101.

[0019] [Conversion circuit] FIG. 7 shows a boost circuit 120 including a conversion circuit 130 that converts the voltage level of input 1. The boost circuit 120 of FIG. 7 is the same as the boost circuit 100 of FIG. 5, except that a conversion circuit 130 that converts the voltage level is added between input 1 and MOSFET Q101. Note that the same components as in FIG. 5 are designated by the same reference numerals, and their explanations are omitted. The conversion circuit 130 includes resistors R201-R203, transistor Q201, and Zener diode ZD201. These five components are added for each high-voltage power supply. Therefore, if there are three high-voltage power supplies for charging, transfer, and development, as shown in FIG. 6, a total of 15 components will be added. This is undesirable because it increases costs and occupies a large area on the circuit board.

[0020] [Output voltage ripple] A method for reducing output voltage ripple using the boost circuit 100 shown in Figure 5 is described. The reason for the large output voltage ripple is that the pulse signal applied to input 1 is significantly decimated by comparator CP101, resulting in intermittent oscillation. Therefore, in the conventional boost circuit 100, the frequency of the clock signal applied to input 1 is varied depending on the target voltage applied to input 2. This reduces the amount of pulse signal decimated by comparator CP101, thereby lowering the output voltage ripple. For example, when the output voltage target voltage is low, the frequency of the pulse signal applied to input 1 is lowered, preventing intermittent oscillation and suppressing output voltage ripple. Conversely, when the output voltage target voltage is high, the frequency of the clock signal applied to input 1 is increased enough to prevent decimation by comparator CP101, thereby reducing output voltage ripple even in the high-voltage range. [Example]

[0021] The present invention is applied to an image forming apparatus, and therefore, first, a laser printer (hereinafter referred to as an image forming apparatus), which is one type of image forming apparatus, will be described.

[0022] <Configuration of image forming device> Figure 1 shows a cross-sectional view of a monochrome laser printer (hereinafter referred to as printer) 300 as an image forming apparatus. Printer 300 includes a paper feed unit 101, a laser scanner 102, a toner tank 103, a developing roller 104 as a developing means, a photosensitive drum 105 as a photosensitive body, a transfer roller 106 as a transferring means, a charging roller 107 as a charging means, and a waste toner tank 108. Printer 300 also includes a fixing roller 109, a pressure roller 110, a discharge unit 111, and a conveying path 112. Note that a laser optical path 113 is also shown in Figure 1 by a dashed line.

[0023] The paper feeder 101 stores paper, which is the recording material to be printed, and the paper is stacked inside. The toner tank 103 contains magnetic toner. The blade 114 regulates the amount of toner on the developing roller 104.

[0024] <Explanation of the operation of the image forming device> Next, the operation of the printer 300 will be described. When the printer 300 receives a print job, it starts operating each roller and the laser scanner 102. The charging roller 107 receives power from the circuit board, carries a negative high voltage, and charges the surface of the photosensitive drum 105. When an image signal is sent from a personal computer or the like, the laser scanner 102 scans the surface of the photosensitive drum 105 in the longitudinal direction (main scanning direction) while flashing the laser according to the pixels. The charge on the photosensitive drum 105 disappears where the laser hits, and a latent image is formed. The developing roller 104 contains a magnet. When a negative high voltage is supplied to the developing roller 104, it attracts magnetic toner in the toner tank 103 by magnetic force, and then moves the toner (developer) to the photosensitive drum 105 according to the latent image by electrostatic force, forming a toner image (developer image). The developing blade 114 is given a potential difference of several hundred volts relative to the developing roller 104, and the toner on the developing roller 104 is uniformly coated by electrostatic force as well as physical regulation by the blade 114 itself.

[0025] Meanwhile, paper fed from paper feed unit 101 passes through transport path 112 and is sandwiched between transfer roller 106 and photosensitive drum 105. At this time, a positive high voltage is applied to transfer roller 106, and the toner on photosensitive drum 105 (on the photosensitive body) is attracted to transfer roller 106 and transferred to the paper. The paper with the toner then moves toward discharge unit 111 and is sandwiched between fixing roller 109 and pressure roller 110. Here, the paper is heated to several hundred degrees by fixing roller 109 and pressed by pressure roller 110, and the toner on the paper is fixed only by electrostatic force. After the fixing process is complete, the paper is discharged to discharge unit 111 and stacked.

[0026] Meanwhile, some toner remains on the surface of the photosensitive drum 105 even after transfer to paper. Ideally, all of the toner should be transferred to paper, but in reality, the amount of charge held by the toner is not uniform, so some toner remains on the photosensitive drum 105 even after transfer. The waste toner tank 108 is where the remaining toner is scraped off and collected by a blade that is in contact with the photosensitive drum 105. This removes the toner from the photosensitive drum 105, which is then charged again by the charging roller 107, and the next latent image is drawn by the scanner 102. The printer 300 forms images by repeating the above operations.

[0027] <Description of the circuit of the present invention> As described above, the printer 300 requires various high voltages and has a built-in high-voltage generation circuit for them. This circuit is similar to the system shown in FIG. 5, so FIG. 5 is incorporated herein. FIG. 2 also shows a block diagram of the entire high-voltage circuit (charging, transfer, and development). Note that the same components in the block diagram of FIG. 2 are designated by the same reference numerals as those in FIG. 6. DEVPWM, TRPPWM, and PRPWM correspond to PWM signals for development, transfer, and charging, respectively, and correspond to input 2 in FIG. 5 for each voltage. Target values ​​for the output voltages of each voltage are input to these as PWM signals. While the multiple boost circuits 100 in the first embodiment can each output different high voltages, the CPU 200 outputs a common drive signal (CommCLK, described later) to the multiple boost circuits 100.

[0028] In Figure 2, the DEVCLK, TRPCLK, and PRCLK in Figure 6 are standardized and unified as CommCLK. The same components as in Figure 6 are given the same reference numerals and their explanations are omitted. Note that DEVCLK is a pulse signal that drives the MOSFET Q101 of the development power supply 100DEV, and TRPCLK is a pulse signal that drives the MOSFET Q101 of the transfer power supply 100TRP. Also, PRCLK is a pulse signal that drives the MOSFET Q101 of the charging power supply 100PR.

[0029] Furthermore, instead of assembling the part that converts the voltage level from 3.3V to 5.4V with discrete components as shown in Figure 7, logic ICs (buffers or inverters) 151, 152, and 153 are used as the conversion means. Since logic ICs usually have multiple logic elements within a single IC, replacing each voltage level conversion with a single logic IC takes up less space on the board than performing voltage level conversion for each voltage individually with discrete components. In other words, the three elements can be combined into a single logic IC.

[0030] Furthermore, in the past, when driving or stopping charging, transfer, or development, DEVCLK, TRPCLK, and PRCLK in Figure 6 were oscillated or stopped individually, but in the configuration shown in Figure 2, they are unified into CommCLK, so they cannot be controlled individually. Therefore, for example, if you want to stop the output of the development voltage, you can set DEVPWM, which is the target value for the development voltage (development output), to zero, and the output voltage will be set to zero through feedback control. The same applies to charging and transfer.

[0031] This configuration reduces the number of ports used by the CPU 200, and also reduces the board area occupied by the circuit that performs voltage level conversion. In Figure 2, the six ports required in Figure 6 have been reduced to four. There are two types of logic ICs: TTL and CMOS. Generally, TTL logic ICs can drive larger currents and have faster operating speeds. However, recent CMOS logic ICs have adopted finer processes and some of them have faster operating speeds than TTL logic ICs, so CMOS logic ICs can also be used if attention is paid to their characteristics.

[0032] As described above, according to the first embodiment, it is possible to reduce the cost of components and the area occupied by the entire power supply circuit on the board. [Example]

[0033] Example 2 is shown in Figure 3. Figure 3 is a block diagram of the entire high-voltage circuit (charging, transfer, and development). Note that in the block diagram of Figure 3, the same components as in Figure 6 are assigned the same reference numerals. In Figure 3, logic ICs 151, 152, and 153 (buffers or inverters) were placed for each voltage in Figure 2 to perform voltage level conversion. In Example 2, the CLKs for each voltage are first commonized to CommCLK, and voltage level conversion is performed by a single logic IC 154 as a conversion means. After voltage level conversion is performed by the single logic IC 154, the signal is branched to input 1 of the development power supply 100DEV, input 1 of the transfer power supply 100TRP, and input 1 of the charging power supply 100PR. This configuration reduces the number of logic ICs to one, allowing the use of an IC with only one element, further reducing the area occupied on the board.

[0034] On the other hand, if one element is to supply pulse signals to three inputs, a slightly larger current is required. For example, if the resistor R101 used in the conversion circuit 130 in FIG. 7 is 1 kΩ, then: (3.3V-0.6V)÷1kΩ=2.7mA This requires a current of 2.7 mA. The printer 300 requires three boost circuits 100 (100DEV, 100TRP, and 100PR), so it must supply a current of 8.1 mA (= 2.7 mA x 3). Some CMOS logic ICs have a low sink current capacity per element and cannot tolerate 8.1 mA. However, single-element CMOS buffers capable of driving large currents include the Texas Instruments SN74LVC1G07. This IC is available in several packages, the smallest being 0.85 mm x 0.85 mm, with a maximum sink current of 32 mA, making it capable of driving the circuit shown in Figure 3. Thus, a logic IC can be selected based on the required current. Note that some ICs, such as the SN74LVC1G07, have an open-drain output stage, so in Figure 3, the output is pulled up to 5.4 V by resistor R301. This approach solves both the current supply shortage and the voltage level conversion issue.

[0035] As described above, according to the second embodiment, it is possible to reduce the cost of components and the area occupied by the entire power supply circuit on the board. [Example]

[0036] In the first and second embodiments, the three clocks conventionally divided into DEVCLK, TRPCLK, and PRCLK are unified into CommCLK. Each high-voltage power supply is feedback-controlled, so it can output a different output voltage. In the third embodiment, the output voltage ripple will be further explained. In the third embodiment, the CPU 200 reduces the output voltage ripple by sequentially changing the frequency and ON time (ON time) of a common drive signal (CommCLK) in accordance with each timing of the print sequence in the electrophotographic process.

[0037] In Figure 6, the CPU 200 outputs pulse signals as DEVCLK, TRPCLK, and PRCLK so that each high-voltage circuit outputs the optimal output voltage. This is because each high-voltage circuit uses different transformers and FETs. For example, PRCLK has a frequency of 16.7 kHz and a duty of 10%, DEVCLK has a frequency of 25 kHz and a duty of 12%, and TRPCLK has a frequency of 5 kHz and a duty of 3.6%.

[0038] In Figures 2 and 3, to ensure that all voltages produce maximum output, it is necessary to select the pulse signal with the highest frequency and longest ON time as CommCLK from among these numerical combinations. If the high-voltage circuit is configured as boost circuit 100 in Figure 5, if the CommCLK ON time is too long, it will be clamped by comparator CP101, suppressing output. On the other hand, a problem arises if the CommCLK ON time is too short. Specifically, if the CommCLK ON time is too short, the high-voltage circuit, which requires the highest output among charging, developing, and transfer, may not be able to output the target high voltage. Therefore, in the example above, it is necessary to determine which CommCLK frequency and ON time are the highest and which are the longest.

[0039] The definition (ON time) of each pulse signal in FIG. 6 is as follows: DEVCLK 25kHz, duty 12% → ON time 4.8usec TRPCLK 5kHz, duty 3.6% → ON time 7.2usec PRCLK 16.7kHz, duty 10% → ON time 6usec

[0040] Of these, TRPCLK has the longest ON time, so an ON time of 7.2 usec is selected, and DEVCLK has the highest frequency, so 25 kHz is selected. In other words, CommCLK is a pulse signal with a frequency of 25 kHz and an ON time of 7.2 usec. By using this as a common clock, each circuit will then appropriately thin out CommCLK and switch each MOSFET Q101 so that the output voltage reaches the target value, making it possible to output different output voltages.

[0041] (CommCLK according to the operation of the printer 300) It is possible to change CommCLK to achieve the optimal output conditions for each high voltage in the print sequence. For example, suppose you want to minimize ripple in the output voltage of the charging power supply 100PR during the preparatory operation (pre-rotation) for printing. Conventionally, PRCLK was set to 16.7 kHz with a duty of 10%. Therefore, CommCLK is set to 16.7 kHz with a duty of 10% only during the pre-rotation. Furthermore, during the post-printing operation (post-rotation), for example, to prioritize the transfer power supply 100TRP for cleaning the transfer roller 106, CommCLK is set to 5 kHz with a duty of 3.6%, which is the original TRPCLK for transfer. Because charging and development are important during printing, the value with the highest frequency and longest ON time is selected from the two: PRCLK 16.7 kHz with a duty of 10% and DEVCLK 25 kHz with a duty of 12%. In other words, CommCLK is set to 25 kHz and the duty to 12%. In this way, by changing the specifications of the CommCLK pulse signal over time, it is possible to achieve a configuration in which the ripple in the output voltage of each high voltage power supply is small during the print sequence and the supply capacity is not excessive.

[0042] FIG. 4 shows the print sequence and the CommCLK specifications (frequency, duty) selected for each sequence. In FIG. 4, the horizontal axis represents time, and the vertical axis represents the state of the printer 300 and the CommCLK frequency and duty for that state. When the printer 300 is in standby mode, the CPU 200 does not output CommCLK (stopped). As described above, during pre-rotation, the CPU 200 outputs CommCLK with a frequency of 16.7 kHz and a duty of 10%. During pre-rotation, to suppress ripple in the charging voltage, the CPU 200 outputs CommCLK with a frequency of 16.7 kHz and a duty of 10%. During printing, to suppress ripple in the development voltage, the CPU 200 outputs CommCLK with a frequency of 25.7 kHz and a duty of 12%. During post-rotation, to suppress ripple in the transfer voltage, the CPU 200 outputs CommCLK with a frequency of 5 kHz and a duty of 3.6%. In this way, the frequency and duty of the unified CommCLK may be changed depending on the operating status of the printer 300.

[0043] (environmental temperature) Furthermore, if the printer 300 is equipped with an environmental detection means such as a temperature sensor and detects that the environment is low and a fairly high voltage must be output as the transfer voltage, the clock signal in the print sequence may be selected to prioritize transfer over charging. In other words, CommCLK may be set to 5 kHz of TRPCLK with a duty of 3.6%.

[0044] If one voltage is prioritized and output voltage ripple is kept small, the same control method as in Prior Art Document 2 can be used. Specifically, if you want to suppress the ripple in the output voltage of charging power supply 100PR in Figure 3, you can do it as follows. That is, after inputting the target output voltage value to PRPWM, you output CommCLK at a frequency corresponding to that duty. This prevents CommCLK from being thinned out by comparator CP101 within the charging voltage range, and MOSFET Q101 oscillates almost continuously rather than intermittently, minimizing output voltage ripple. The same applies to development and transfer. Note that the frequency corresponding to the target output voltage duty is the threshold frequency (the lowest value) at which MOSFET Q101 can oscillate continuously and output the target voltage in a pulse signal.

[0045] As described above, according to the third embodiment, it is possible to reduce the cost of components and the area occupied by the entire power supply circuit on the board.

[0046] The disclosure of this embodiment includes the following configuration. (Configuration 1) a boost circuit including: a generating means having a transformer and a switching element that is turned on or off by a drive signal, and that generates a high voltage; a rectifying means that rectifies the high voltage generated by the generating means; a detecting means that detects the output of the high voltage rectified by the rectifying means; a comparing means that compares the detection result by the detecting means with a target voltage; and a controlling means that controls the driving signal to be turned on or off based on the comparison result by the comparing means so that the high voltage becomes a constant output voltage; an output means for outputting the drive signal and outputting a PWM signal corresponding to the target voltage to the comparison means; A power supply device comprising: At least two of the boost circuits are provided, the plurality of boost circuits are each capable of outputting a different high voltage; The power supply device according to claim 1, wherein the output means outputs the drive signal common to a plurality of the boost circuits. (Configuration 2) the switching element is a field effect transistor with a drain-source breakdown voltage exceeding 100 V, 2. The power supply device according to configuration 1, wherein the field effect transistor has an on-resistance guaranteed at a gate-source voltage of 4 V or more. (Configuration 3) the output means operates at a first voltage and has one port for outputting the drive signal; a conversion means for converting the level of the drive signal output from the one port; 3. The power supply device according to claim 2, wherein the conversion means converts the first voltage into a voltage at a level equal to or higher than a second voltage that is higher than the first voltage. (Configuration 4) the output means operates at a first voltage; the output means has one port for outputting the drive signal; a conversion means is provided between the one port and a switching element of each of the boost circuits; 3. The power supply device according to claim 2, wherein each of said conversion means converts said first voltage to a voltage at a level equal to or higher than a second voltage that is higher than said first voltage. (Configuration 5) 5. The power supply device according to configuration 3 or 4, wherein the conversion means is a logic IC. (Configuration 6) a charging means for charging the photosensitive member; a developing means for developing the latent image on the photosensitive member with a developer; a transfer means for transferring the developer image onto a recording material; The power supply device according to any one of configurations 1 to 5; Equipped with The image forming apparatus is characterized in that the power supply device generates a charging voltage to be supplied to the charging means, a developing voltage to be supplied to the developing means, and a transfer voltage to be supplied to the transfer means. (Configuration 7) 7. The image forming apparatus according to configuration 6, wherein the output means successively changes the frequency and ON time of the drive signal in accordance with a print sequence in an electrophotographic process. [Explanation of symbols]

[0047] 100DEV, 100TRP, 100PR boost circuit 200 CPU CP101 Comparator D101 Diode Q101 MOSFET T101 transformer

Claims

1. A charging means for charging a photosensitive member; a developing means for developing the latent image on the photosensitive member with a developer; a transfer means for transferring the developer image onto a recording material; a power supply; An image forming apparatus comprising: the power supply device has three boost circuits, Each of the three boost circuits has a switching element and a transformer that are turned on or off by a drive signal, and includes a generating means for generating a high voltage, a rectifying means for rectifying the high voltage generated by the generating means, a detecting means for detecting the output of the high voltage rectified by the rectifying means, a comparing means for comparing the detection result by the detecting means with a target voltage, and a controlling means for controlling the driving signal to be turned on or off based on the comparison result by the comparing means so that the high voltage becomes a constant output voltage; the power supply device has an output means for outputting the drive signal and outputting a PWM signal corresponding to the target voltage to the comparison means, When the three booster circuits are respectively designated as a first booster circuit, a second booster circuit, and a third booster circuit, the first booster circuit generates a charging voltage to be supplied to the charging means, the second booster circuit generates a developing voltage to be supplied to the developing means, the third booster circuit generates a transfer voltage to be supplied to the transfer means, the first booster circuit, the second booster circuit, and the third booster circuit are capable of outputting high voltages different from one another; the output means outputs the drive signal common to the plurality of boost circuits; The image forming apparatus is characterized in that the output means successively changes the frequency and ON time of the drive signal in accordance with a printing sequence in an electrophotographic process.

2. the switching element is a field effect transistor having a drain-source breakdown voltage exceeding 100 V; 2. The image forming apparatus according to claim 1, wherein the on-resistance of the field effect transistor is guaranteed at a gate-source voltage of 4 V or more.

3. the output means operates at a first voltage and has one port for outputting the drive signal; a conversion means for converting the level of the drive signal output from the one port; 3. The image forming apparatus according to claim 2, wherein said conversion means converts said first voltage into a voltage having a level equal to or higher than a second voltage that is higher than said first voltage.

4. the output means operates at a first voltage and has one port for outputting the drive signal; a conversion means is provided between the one port and a switching element of each of the boost circuits, 3. The image forming apparatus according to claim 2, wherein each of said conversion means converts said first voltage into a voltage having a level equal to or higher than a second voltage that is higher than said first voltage.

5. 5. The image forming apparatus according to claim 3, wherein the conversion means is a logic IC.

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