Isolated Power Supply

Abstract

To easily determine whether or not ZVS control is performed, in an insulation type power supply device comprising an active clamp circuit and adopting the zero-voltage switching control system.SOLUTION: A semiconductor device for controlling a primary side power supply is provided with: a first external terminal that receives a drain side voltage of a switching element, an auxiliary coil voltage of a transformer, or a voltage obtained by dividing these voltages; a second external terminal that receives a voltage converted by a current-voltage conversion element; an on / off-controlling circuit that turns on and off the switching element on the basis of the input voltage of the first external terminal; and a ZVS determination circuit that determines that the drain side voltage of the switching element becomes a zero voltage on the basis of the input voltage of the second external terminal and determines whether or not a zero-voltage switching control is performed.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to an isolated power supply device including a power supply control semiconductor device that controls a switching element connected in series with a primary winding of a voltage conversion transformer. [Background technology]

[0002] Conventionally, one type of switching power supply device has been a switching power supply device (isolated DC-DC converter) that includes a transistor (including transistors on a silicon substrate, as well as GaN or SiC substrates) as a switching element for intermittently passing current through the primary coil of a transformer, and a control circuit (IC) that controls the on / off of the switching element, and that passes current through the primary coil, rectifying the current induced in the secondary coil with a diode and smoothing it with a capacitor before outputting it. DC power supply devices also include a diode bridge circuit that rectifies AC power, and an isolated AC-DC converter that steps down the DC voltage rectified by the circuit using the switching power supply device (isolated DC-DC converter) to convert it into a DC voltage of the desired potential.

[0003] Isolated AC-DC converters use a switching method called soft switching, which utilizes high-frequency resonance to turn on / off a switching element when the applied voltage to the switching element reaches 0 V or the conduction current reaches 0 A. A method that switches when the voltage is zero is called zero-voltage switching. This soft switching is attracting attention because it is expected to reduce switching loss and electromagnetic interference (EMI) noise compared to a switching method called hard switching, which directly interrupts and conducts the DC power supply voltage. Patent Document 1, for example, describes an invention related to zero-voltage switching.

[0004] In addition, some isolated AC-DC converters and isolated DC-DC converters with transformers are configured to have an active clamp circuit with an energy regeneration function on the primary winding side of the transformer in order to improve efficiency. Inventions relating to switching power supplies equipped with active clamp circuits are described in, for example, Patent Documents 2 and 3. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2017-112797 [Patent Document 2] Japanese Patent Application Laid-Open No. 2006-325325 [Patent Document 3] Japanese Patent Application Laid-Open No. 2013-201829 Summary of the Invention [Problem to be solved by the invention]

[0006] In an isolated AC-DC converter equipped with an active clamp circuit and employing a zero voltage switching control method (hereinafter referred to as ZVS), when the switching element (main FET) is turned on, the charge accumulated in the capacitance component of the drain terminal of the main FET is discharged. The inventors' investigations have revealed that the amount of this discharged charge is proportional to the drain voltage and increases as the on / off timing under ZVS control deviates from the optimal timing, resulting in noise generation during the discharge of the accumulated charge and a decrease in the conversion efficiency of the power supply device due to unnecessary energy loss. Furthermore, directly monitoring the drain voltage of the switching element and determining whether or not ZVS control is being performed has the following problems. (1) Because the drain voltage rises to several hundred volts, a large, high-voltage element is required for the detection section. (2) If voltage is divided using resistors, etc., low-voltage elements can be used, but the current to the voltage divider circuit will lead to increased losses. (3) If the impedance of the voltage divider circuit is high, the current can be reduced, but the time constant of the filter formed by the voltage divider circuit and the input capacitance of the terminal becomes high, causing the waveform to become distorted and deviating from the optimal ZVS timing.

[0007] The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide an isolated power supply device that employs zero voltage switching control and is equipped with an active clamp circuit, whereby it is possible to easily determine whether or not ZVS control is being performed, without directly monitoring the drain voltage. [Means for solving the problem]

[0008] In order to achieve the above object, the present invention provides: An isolated power supply device comprising: a voltage conversion transformer; a switching element connected in series with a primary winding of the transformer; an active clamp circuit connected between terminals of the primary winding of the transformer; and a power supply controlling semiconductor device that controls the switching element and the active clamp circuit, The switching element is composed of a field effect transistor, and a current-voltage conversion element is connected between the source terminal of the switching element and a ground point; The power supply control semiconductor device includes: The drain side of the switching element of Voltage or The drain side a first external terminal to which a voltage obtained by dividing the voltage of a second external terminal to which the voltage converted by the current-voltage conversion element is input; an on / off control circuit that turns on and off the switching element based on an input voltage of the first external terminal; a ZVS determination circuit that determines whether a drain voltage of the switching element has become zero voltage based on an input voltage of the second external terminal, and determines whether zero voltage switching control is being performed; Prepared And, The on / off control circuit has a turn-on timing detection circuit that detects the turn-on timing of the switching element based on the input voltage of the first external terminal, and a turn-off timing detection circuit that compares the input voltage of the second external terminal with a predetermined reference voltage to detect the turn-off timing of the switching element. This is what we have done.

[0009] With the above configuration, it is possible to easily determine whether ZVS control is being performed in an isolated power supply device that employs a zero voltage switching control method and is equipped with an active clamp circuit. Furthermore, by extending the on-time of the active clamp transistor when ZVS control is not being performed, it is possible to reduce noise generated when the switching element is turned on and improve the conversion efficiency of the power supply device. [Effects of the Invention]

[0010] According to the present invention, in an isolated power supply device that is equipped with an active clamp circuit and employs a zero voltage switching control method, it is possible to easily determine whether or not ZVS control is being performed without directly monitoring the drain voltage. As a result, if ZVS control is not being performed, the on time of the active clamp transistor is extended, thereby reducing noise generated when the switching element is turned on, and reducing unnecessary energy loss, thereby improving the conversion efficiency of the power supply device. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a circuit configuration diagram showing an embodiment of an AC-DC converter as an isolated power supply device according to the present invention. [Figure 2] 2 is a circuit configuration diagram showing a first embodiment of a power supply controlling semiconductor device that is provided on the primary side of a transformer in the AC-DC converter of FIG. 1 and controls a switching element. FIG. [Figure 3] 2 is a circuit diagram showing an equivalent circuit of a DC-DC converter portion of the AC-DC converter of FIG. 1. FIG. [Figure 4] 4 is a waveform diagram showing signal waveforms at various parts of the power supply controlling semiconductor device shown in FIG. 3. [Figure 5] 4 is a timing chart showing changes in voltage and current at each part of the DC-DC converter of FIG. 3 when ZVS control is being performed. [Figure 6] 4 is a timing chart showing changes in voltage and current at each part of the DC-DC converter of FIG. 3 when ZVS control is not being performed. [Figure 7] 4 is a timing chart showing changes in the drain voltage, clamp current, and current of an exciting inductor in the DC-DC converter of FIG. 3. [Figure 8] FIG. 10 is a circuit diagram showing a second embodiment of a power supply controlling semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of an AC-DC converter as an isolated power supply device using a power supply control semiconductor device according to the present invention. The AC-DC converter of this embodiment is a flyback converter and includes a diode bridge circuit 12 and a smoothing capacitor C1 that rectify the AC voltage from an AC power source 11, a voltage conversion transformer 13 that has a primary winding Np, a secondary winding Ns, and an auxiliary winding Nb and is connected to a voltage input terminal IN, a switching transistor SW1 connected in series with the primary winding Np of the transformer 13, and a power supply control semiconductor device (hereinafter referred to as a power supply control IC) 14 that drives the switching transistor SW1 to turn on and off.

[0013] The secondary side of the transformer 13 is provided with a rectifying diode D2 connected in series with the secondary winding Ns, and a smoothing capacitor C2 connected between the cathode terminal of this diode D2 and the other terminal of the secondary winding Ns. By intermittently passing a current through the primary winding Np, the AC voltage induced in the secondary winding Ns is rectified and smoothed to generate a DC output voltage Vout, which is output from output terminals OUT1 and OUT2. The secondary side of the transformer 13 is provided with an output voltage detection circuit 15 that is configured with a shunt regulator equipped with an error amplifier and the like to detect the output voltage Vout, and a photodiode PD that constitutes a photocoupler for transmitting an output voltage detection signal corresponding to the detected voltage to the primary side.

[0014] Meanwhile, a phototransistor PT, which constitutes a photocoupler together with the photodiode PD, is provided on the primary side of the transformer 13, and an external terminal FB to which the phototransistor PT is connected is provided on the power supply control IC 14. That is, a current corresponding to the voltage detected by the output voltage detection circuit 15 flows through the photodiode PD, and is transmitted to the primary side as an optical signal having an intensity corresponding to the detected voltage, causing a current corresponding to the optical intensity to flow through the phototransistor PT, and this current is converted to a voltage VFB by a pull-up resistor (Rp in FIG. 2) or the like inside the power supply control IC 14 and transmitted.

[0015] In the AC-DC converter of this embodiment, the higher the secondary side output voltage Vout, the greater the current flowing through the photodiode PD and the phototransistor PT, and the lower the voltage VFB at the external terminal FB of the power supply control IC 14. The power supply control IC 14 also has an external terminal CS as a current detection terminal to which a voltage Vcs converted from current to voltage by a current detection resistor Rs connected between the source terminal of the switching transistor SW1 and the ground point is input.

[0016] Furthermore, in this embodiment, an active clamp circuit 16 consisting of a transistor MAC and a capacitor CAC connected in series is provided between the low-side terminal of the primary winding Np of the transformer 13 and the voltage input terminal IN, and the power supply control IC 14 has a built-in active clamp control circuit that controls the transistor MAC of the active clamp circuit 16. Although not particularly limited, a discharge resistor Rdc is connected in parallel to the capacitor CAC to discharge the charge of the capacitor CAC. The DC-DC converter of this embodiment is also provided with a rectifying and smoothing circuit consisting of a rectifying diode D0 connected in series with the auxiliary winding Nb of the transformer 13 and a smoothing capacitor C0 connected between the cathode terminal of this diode D0 and ground, and the voltage rectified and smoothed by the rectifying and smoothing circuit is applied to the power supply voltage terminal VDD of the power supply control IC 14.

[0017] In this embodiment, the switching transistor SW1 and the active clamp transistor MAC are configured as discrete components using N-channel MOSFETs (insulated gate field effect transistors). The power supply control IC 14 is also provided with an external terminal GATE1 that outputs a signal to drive the gate terminal of the transistor SW1, an external terminal GATE2 that outputs a signal to drive the gate terminal of the transistor MAC, and an external terminal VD to which the drain voltage of the transistor SW1 is input. The drain voltage of the transistor SW1 may be divided by an external resistor and input to the external terminal VD.

[0018] (First Example) FIG. 2 shows the circuit configuration of a first embodiment of the power supply control IC 14. As shown in FIG. 2, the power supply control IC 14 of this embodiment includes a turn-on trigger generation circuit 41 that monitors the voltage VD at an external terminal VD to which the drain voltage of the switching transistor SW1 is input and generates a turn-on signal for the transistor SW1, and a turn-off trigger generation circuit 42 that includes a comparator and the like that compares the voltage Vcs at the current detection terminal CS with a predetermined reference voltage (for example, the voltage VFB at the feedback terminal FB) and generates a turn-off signal for the transistor SW1.

[0019] The power supply control IC 14 also includes a latch circuit 43, such as an RS flip-flop, that receives the outputs of the turn-on trigger generation circuit 41 and the turn-off trigger generation circuit 42 as inputs; a driver circuit 44 that generates a gate drive signal VG_MAIN for driving the switching transistor SW1 in response to the output of the latch circuit 43 and outputs the signal from an external terminal GATE1; and an active clamp control circuit 46 that generates a signal VG_AC for driving the gate terminal of a timer circuit 45 and an active clamp transistor MAC and outputs the signal from an external terminal GATE2. The latch circuit 43 and driver circuit 44 function as a drive signal generation circuit that generates a drive signal for the switching transistor SW1. Although not shown, the active clamp control circuit 46 also includes a driver circuit similar to the driver circuit 44.

[0020] The turn-on trigger generation circuit 41 includes a turn-on timing detection circuit 41A consisting of a comparator and the like that detects "when the drain voltage VD of SW1 input to the external terminal VD falls below a predetermined threshold" or "when a predetermined period of time has passed without turning on (when it does not reach zero voltage during a burst, etc.)", a resonance bottom detection circuit 41B that detects the resonance bottom of the drain voltage VD, and a logic circuit 41C consisting of an OR gate and the like that takes the logical sum of the detection signals of these detection circuits 41A and 41B. In this specification, the above control of turning on SW1 upon detecting that VD has fallen to a predetermined threshold value or less is referred to as ZVS (zero voltage switching) control. Furthermore, instead of the circuit 41B that detects the bottom of the resonance of the drain voltage VD, a circuit that detects the bottom of the induced voltage of the auxiliary winding Nb of the transformer 13 may be provided. The induced voltage bottom detection circuit for the auxiliary winding is described in, for example, JP 2020-58166 A.

[0021] On the other hand, the turn-off trigger generation circuit 42 is composed of a comparator that compares the voltage Vcs of the current detection terminal CS with the feedback voltage VFB, and a mask circuit 47 made up of logic gates such as an AND gate is provided in the subsequent stage to block the transmission of the turn-off signal to the latch circuit 43 for a predetermined time (minimum on time) after the turning-on of the switching transistor SW1, based on a signal MSK from a timer circuit 45.

[0022] Furthermore, in this embodiment, the output of the comparator in the turn-off trigger generation circuit 42 is supplied to the active clamp control circuit 46. If the active clamp control circuit 46 receives a pulsed signal SPD from the turn-off trigger generation circuit 42 within a predetermined time after the transistor SW1 is turned on, the active clamp control circuit 46 determines that the drain voltage has not dropped to zero voltage and that zero voltage switching control is not being performed, and if the pulsed signal SPD is not received within the predetermined time, the active clamp control circuit 46 determines that zero voltage switching control is being performed. Therefore, the active clamp control circuit 46 can easily determine whether or not ZVS control is being performed.

[0023] Furthermore, the active clamp control circuit 46 is configured to extend the on-time of the gate drive signal VG_AC of the transistor MAC by a predetermined time Δt when it is determined that zero voltage switching control is not being performed based on the output from the turn-off trigger generation circuit 42. This function and the resulting effects will be described in detail later. To achieve the above functions, timer circuit 45 is provided with a first timer (timer 1) 45A that measures the minimum on-time MOT, a second timer (timer 2) 45B that measures the MAC on extension time, and a counter 45C that counts the pulse-like spike detection signal SPD output from the comparator in turn-off trigger generation circuit 42. Timers 1 and 2 can be configured as analog timers using a capacitance element, a constant current source (resistor) for charging the capacitance element, a discharge switch (transistor), an inverter, a comparator, or the like.

[0024] Counter 45C counts up when spike detection signal SPD is continuously input, and second timer (timer 2) 45B measures the extension time according to the value of counter 45C. In other words, the extension time is increased in stages as spike detection signal SPD is continuously input. Furthermore, counter 45C is configured to hold its value when spike detection signal SPD is not continuously input.

[0025] However, the counter 45C may be omitted and the on-time of the MAC may be extended by the same extension time each time the spike detection signal SPD is input consecutively, or the counter 45C may be configured to count down when the spike detection signal SPD is not input consecutively. 2 is shown for the sake of convenience in explaining this embodiment, and does not mean that there are no timers other than timers 45A and 45B in the power supply control IC 14, and timers may be provided in other circuit blocks. For example, timer 45A may be provided in the turn-on trigger generation circuit 41, and timer 45B, counter 45C, and other timers may be provided in the active clamp control circuit 46.

[0026] The following describes the specific functions and operations of each of the functional blocks of the power supply control IC 14. First, the basic functions and operations of the active clamp control circuit 46 are explained using Figure 3, and then the cooperative operations of the turn-on trigger generation circuit 41, the turn-off trigger generation circuit 42, and the active clamp control circuit 46 are explained. Fig. 3 shows an equivalent circuit of the DC-DC converter portion of the isolated power supply of this embodiment shown in Fig. 1. In Fig. 3, Cp represents the parasitic capacitance present at the drain terminal of the switching transistor SW1, Lm represents the excitation inductance of the transformer 13, and Lk represents the parasitic inductance on the primary side of the transformer 13.

[0027] In the DC-DC converter of Figure 3, when the switching transistor SW1 is turned on, the input voltage Vin is applied to the primary winding Np of the transformer 13, and an excitation current flows. Note that this turning on of the switching transistor SW1 can be done under ZVS control, or it can be triggered by a general flyback power supply on condition, such as forced turn-on immediately after startup, bottom detection of the auxiliary winding, or timeout during burst operation. Transistor SW1, which has been turned on, is turned off when the voltage Vcs at the current detection terminal CS reaches the voltage VFB. When SW1 is turned off, the drain current ISW1 begins to decrease and the drain voltage VD begins to increase simultaneously, and there is a period when both begin to cross, so ZVS does not occur.

[0028] When the transistor SW1 turns off, the energy stored on the primary winding Np side of the transformer 13 is released to the secondary side. Also, due to the sudden change in dISW1 / dt, the voltage of the transformer 13 is reversed, the drain parasitic capacitance Cp of the transistor SW1 is charged, and the drain voltage VD of the transistor SW1 rises. When the drain voltage VD of SW1 rises and becomes higher than the drain voltage of transistor MAC in the active clamp circuit 16, the body diode of MAC becomes conductive. After the body diode becomes conductive, MAC is turned on. The drain-source voltage VDS of MAC is the diode's forward voltage Vf (≒ 1V), and can be considered to be nearly ZVS. Then, a resonant circuit is formed by the parasitic inductance Lk on the primary side of transformer 13 and capacitor CAC in the active clamp circuit 16, and the energy of Lk is regenerated on the CAC side. Meanwhile, due to the voltage reversal of the transformer 13, the current Im of the excitation inductance Lm changes to a negative slope as shown in FIG. 7. The slope at this time is -(Np / Ns)*Vout / Lm. The active clamp circuit 46 turns off MAC when Im becomes negative. The longer the MAC is on, the larger the negative amplitude of Im becomes. Furthermore, by turning off MAC when Lm is negative, the current flows in a direction that discharges the parasitic capacitance Cp of the drain of SW1. Then, by turning on SW1 when Cp is discharged to zero volts, switching loss can be reduced by ZVS. Note that, as described above, the transistor SW1 that is turned on is turned off when the voltage Vcs at the current detection terminal CS reaches the voltage VFB, and the above operation is repeated.

[0029] However, if the negative amplitude of Im is insufficient, Cp cannot be discharged to zero volts, and the charge accumulated in the drain parasitic capacitance Cp of transistor SW1 is discharged to the ground side through SW1 when transistor SW1 is on. The amount of this discharged charge is proportional to the drain voltage VD of transistor SW1, and becomes larger as the ZVS control timing deviates from the optimal timing. If the surge current associated with this discharge is large, a spike SP will occur in the voltage Vcs of the current detection terminal CS of the power supply control IC 14, as shown in Figure 4(B).

[0030] 2, if the turn-off trigger generation circuit 42 of the power supply control IC 14 is configured to generate a turn-off signal for the transistor SW1 based on the voltage Vcs at the current detection terminal CS, the spike SP may cause noise to appear in the output of the comparator in the turn-off trigger generation circuit 42. Therefore, as described above, a mask circuit 47 is provided in the subsequent stage of the turn-off trigger generation circuit 42 to remove noise caused by detecting the spike SP, thereby preventing the transistor SW1 from being turned off by mistake.

[0031] That is, in a situation where a spike SP occurs in the voltage Vcs of the current detection terminal CS as shown in Figure 4(B), ZVS control is not performed because the drain voltage VD is not zero when transistor SW1 is turned on, as shown in Figure 4(C). This situation occurs when the response timing of the turn-on timing detection circuit 41A is shifted from the drain voltage VD being zero, or when transistor SW1 is turned on by the resonant bottom detection circuit 41B in the turn-on trigger generation circuit 41, which detects the resonant bottom of the drain voltage VD of transistor SW1 and generates a turn-off signal. When SW1 is on, the drain voltage VD does not become zero, resulting in switching loss. As described above, in the power supply control IC 14 of this embodiment, the active clamp control circuit 46 is configured to extend the on-time of the gate drive signal VG_AC of the transistor MAC by a predetermined time in response to the signal (SPD) from the turn-off trigger generation circuit 42. In other words, the active clamp control circuit 46 is configured to have a ZVS determination function that determines whether or not ZVS control is being performed, and a function that generates the gate drive signal VG_AC so as to extend the on-time of the MAC by a predetermined time when ZVS control is not being performed.

[0032] The reasons for extending the on-time of the gate drive signal VG_AC and its advantages will be explained below using the timing charts in Figures 5 and 6. Of Figures 5 and 6, Figure 5 shows the case where the power supply control IC 14 is performing ZVS (zero voltage switching) control, and Figure 6 shows the case where the power supply control IC 14 is not performing ZVS control.

[0033] When the power supply control IC 14 is performing ZVS control, as shown in FIG. 5, at timing t1 when the turn-on timing detection circuit 41A detects that the drain voltage VD of the switching transistor SW1 (hereinafter referred to as the main switch) has become zero, the gate drive signal VG_MAIN of the main switch SW1 changes from low level to high level, SW1 is turned on, and current Isw1 flows. Then, during the period T1 when SW1 is on, the drain current Isw1 and the voltage Vcs at the current detection terminal CS increase linearly, as shown in (C) and (E). Then, at time t2 when the turn-off trigger generation circuit 42 detects that the voltage Vcs at the terminal CS has reached the reference voltage VFB, the gate drive signal VG_MAIN for the main switch SW1 changes from high to low, turning SW1 off. Then, the current Isw1 rapidly decreases, while the drain parasitic capacitance Cp of SW1 is charged by the current Im through the magnetizing inductor of the transformer, causing the drain voltage VD to rise rapidly.

[0034] When the drain voltage VD becomes higher than the sum (Vin + VCLAMP) of the input voltage Vin and the voltage VCLAMP of the capacitance CAC of the active clamp circuit 16, the body diode of the active clamp transistor MAC becomes conductive, and the source-drain voltage of MAC becomes nearly zero. At time t3, the gate drive signal VG_AC of transistor MAC changes from low to high, turning MAC on. As a result, current ICRAMP begins to flow from the MAC source to the drain, then gradually decreases, reversing its direction midway, and increasing in the opposite direction (from the drain to the source) (period T2). Controlling transistor MAC at the above timing reduces the switching loss of MAC.

[0035] After that, at time t4, a predetermined time T2 has elapsed since time t3, a signal from a timer (not shown) causes the MAC gate drive signal VG_AC to change from high to low, turning the MAC off. Then, the drain voltage VD of the main switch SW1 rapidly drops to zero (time t5). By repeating the above operation, normal ZVS control is performed. As shown in Figure 5(D), the current Im of the transistor's excitation inductor changes from increasing to decreasing near timing t2, and from decreasing to increasing near timing t4, similar to the drain current Isw1 of SW1. Here, the current Im of the excitation inductor can be calculated by (transformer primary input current + secondary current / transformer winding ratio). Furthermore, once the current Im of the excitation inductor is determined, the off period T2 of the transistor MAC can be calculated and the timing t4 can be determined.

[0036] On the other hand, when the power supply control IC 14 is not performing ZVS control, as shown in Figure 6, the drain voltage VD of the main switch SW1 does not drop to zero, so the turn-on timing detection circuit 41A cannot detect the zero voltage of VD. Instead, at timing t1 when the resonance bottom detection circuit 41B detects the resonance bottom of VD, the gate drive signal VG_MAIN of the main switch SW1 changes from low level to high level, SW1 turns on, and current flows.

[0037] At this time, because VD is not zero, charge remains in the drain parasitic capacitance Cp of the main switch SW1, and when this charge is discharged through SW1, a surge current flows, causing a spike SP in the voltage Vcs of the current detection terminal CS. As a result, the comparator in the turn-off trigger generation circuit 42 detects the spike SP and generates noise in its output. However, as described above, the output of the comparator is masked only for the minimum on-time MOT (see FIG. 4) by the subsequent mask circuit 47, so that it is possible to prevent a turn-off signal from being erroneously supplied to the latch circuit 43.

[0038] 6 and 5, the operation is the same whether ZVS control is being performed or not, except for the operation of turning on SW1 upon detecting the bottom of the VD resonance. However, when ZVS control is not being performed, as described above, in response to the comparator in the turn-off trigger generation circuit 42 detecting the spike SP, the high-level period T2 of the gate drive signal VG_AC of the transistor MAC output from the active clamp control circuit 46 is extended by Δt at timing t4 as indicated by the dashed line B in FIG. 6(A), and the on-time of the transistor MAC is extended by Δt. As a result, the drain voltage VD of the main switch SW1 approaches zero. When a spike SP occurs again in the voltage Vcs in the next cycle, the on-time of the transistor MAC is further extended, and by repeating this process, the drain voltage VD of SW1 reaches zero, thereby achieving ZVS control.

[0039] Next, the effect of extending the ON time of the active clamp transistor MAC will be described with reference to the waveform diagram of FIG. Figure 7 shows the changes in the gate drive signal VG_AC of the transistor MAC, the drain voltage VD of the main switch SW1, the clamp current ICLAMP (see Figure 3) flowing by the active clamp circuit 16, and the current Im flowing through the excitation inductor Lm of the transformer 13 when the active clamp circuit 16 is operating and ZVS control is being performed.

[0040] 7, while the active clamp transistor MAC is on (period T2), the current Im through the inductor Lm decreases linearly, and when the gate drive signal VG_AC for the transistor MAC changes from high to low at time t4 and MAC turns off, the current path switches to the main switch SW1 side, and the drain voltage VD of the main switch SW1 drops rapidly. Also, the current Im through the inductor Lm changes to a negative direction just before time t4, and then changes to a positive slope as MAC turns off.

[0041] Here, in order to perform zero voltage switching (ZVS) on the main switch SW1, a current is required to discharge the capacitance between the terminals of the active clamp transistor MAC when the transistor MAC is turned off, and this condition is met when the current Im of the magnetizing inductor is negative. Therefore, Im needs to drop to minus (negative), which increases the amplitude on the negative side of the current Im and extends the bottom of the current Im to the negative side, making the bottom value of the current Im even smaller than 0.

[0042] Therefore, when ZVS control is not possible as in the power supply control IC of the above embodiment, ZVS control can be more easily achieved by extending the on time of the active clamp transistor MAC. Specifically, the falling slope of the current Im through the magnetizing inductor Lm can be calculated using the formula -N × Vout / Lm, which is the turns ratio N of the transformer 13, the output voltage Vout, and the magnetizing inductance Lm. Therefore, the time until the current Im becomes negative can be calculated using the calculated slope and the peak value of the current Im. This time is set as the initial value of the on-period of the MAC, and ZVS control can be achieved by extending the on-period of the MAC when a drain current surge, i.e., a spike in the voltage Vcs at the current detection terminal CS, is detected. Note that extending the bottom of the current Im too far to the negative side reduces efficiency, so it is desirable to extend the bottom of the current Im as far as possible while still achieving ZVS control. Therefore, as described above, it is advisable to gradually extend the on-period of the MAC when the spike is detected.

[0043] (Second Example) Next, a second embodiment of the power supply control IC 14 will be described with reference to FIG. 8 does not include the counter 45C of the timer circuit 45 in the first embodiment, and is provided with a register 48 that sets the time counting time of a second timer 45B, and a terminal 49 for inputting the value (binary code) to be set in the register 48 via serial transmission. When an analog timer is used, the resistor that determines the current value is switched depending on the value set in the register 48. Terminal 49 may be provided as an external terminal of the IC, or as an on-chip pad. Register 48 may also be configured as a nonvolatile memory element such as an EEPROM element. Register 48 may also be configured so that setting values ​​can be input via parallel transmission.

[0044] As described above, providing the register 48 has the advantage that the time counted by the timer can be changed and an external resistor for changing the counted time is not required. Also in this embodiment, when the active clamp control circuit 46 determines that zero voltage switching control is not being performed, it may extend the on-time of the transistor MAC constituting the active clamp circuit by a predetermined amount set in the register 48, or when it determines that zero voltage switching control is not being performed for multiple consecutive cycles, it may extend the on-time of the transistor MAC in stages by the predetermined amount set in the register 48.

[0045] The present invention has been specifically described above based on the embodiments, but the present invention is not limited to these embodiments. For example, in the above embodiments, the switching transistor SW1 is an element separate from the power supply control IC 14, but the switching transistor SW1 may be incorporated into the power supply control IC 14 to form a single semiconductor integrated circuit. Furthermore, in the above embodiments, a diode rectification circuit is used as the secondary side circuit, but a synchronous rectification circuit may also be used.

[0046] In addition, in the above embodiment, the active clamp circuit 16 is shown to be configured with a transistor MAC, a capacitor CAC, and a resistor Rdc, but it may also be configured to include a passive clamp circuit configured with diodes, resistors, capacitors, etc. in addition to these elements. Furthermore, in the above embodiment, the present invention has been described as being applied to an AC-DC converter, but the present invention can also be applied to a DC-DC converter in which the diode bridge circuit 12 is omitted. [Explanation of symbols]

[0047] 11...AC power supply, 12...diode bridge circuit, 13 transformer, 14...semiconductor device for switching power supply (power supply control IC), 15...output voltage detection circuit, 16...active clamp circuit, 41...turn-on trigger generation circuit (turn-on timing detection circuit), 42...turn-off trigger generation circuit (turn-off timing detection circuit), 43...latch circuit, 44...driver circuit, 45...timer circuit, 46...active clamp control circuit (ZVS determination circuit, signal generation circuit), 47...mask circuit, 48...register, VD...external terminal (first external terminal), CS...current detection terminal (second external terminal)

Claims

1. An isolated power supply device comprising: a voltage conversion transformer; a switching element connected in series with a primary winding of the transformer; an active clamp circuit connected between terminals of the primary winding of the transformer; and a power supply controlling semiconductor device that controls the switching element and the active clamp circuit, The switching element is composed of a field effect transistor, and a current-voltage conversion element is connected between the source terminal of the switching element and a ground point; The power supply control semiconductor device includes: a first external terminal to which a voltage on the drain side of the switching element or a voltage obtained by dividing the voltage on the drain side is input; a second external terminal to which the voltage converted by the current-voltage conversion element is input; an on / off control circuit that turns on and off the switching element based on an input voltage of the first external terminal; a ZVS determination circuit that determines whether a drain voltage of the switching element has become zero voltage based on an input voltage of the second external terminal, and determines whether zero voltage switching control is being performed; It is equipped with the on / off control circuit includes a turn-on timing detection circuit that detects a turn-on timing of the switching element based on an input voltage of the first external terminal, and a turn-off timing detection circuit that compares the input voltage of the second external terminal with a predetermined reference voltage to detect a turn-off timing of the switching element.

2. The isolated power supply device described in Claim 1, characterized in that the ZVS judgment circuit determines that zero voltage switching control is not being performed if there is an output from the turn-off timing detection circuit within a predetermined time immediately after the turn-on timing is detected by the turn-on timing detection circuit, and determines that zero voltage switching control is being performed if there is no output from the turn-off timing detection circuit within the predetermined time.

3. a signal generating circuit that generates a control signal for controlling the active clamp circuit; 3. The isolated power supply device according to claim 1, wherein the signal generating circuit extends an on-time of a transistor constituting the active clamp circuit by a predetermined amount when the ZVS determination circuit determines that zero voltage switching control is not being performed.

4. a signal generating circuit that generates a control signal for controlling the active clamp circuit; 3. The isolated power supply device according to claim 1, wherein the signal generation circuit gradually extends an on-time of a transistor constituting the active clamp circuit when the ZVS determination circuit determines that zero voltage switching control is not being performed for a plurality of consecutive cycles.

5. 5. The isolated power supply device according to claim 3, wherein, when the ZVS determination circuit determines that zero voltage switching control is being performed, the signal generation circuit maintains the on-time of a transistor constituting the active clamp circuit to be the same as the on-time in the immediately preceding cycle.

6. The on / off control circuit is a drive signal generation circuit that generates a gate drive signal for the switching element based on an output of the turn-on timing detection circuit and an output of the turn-off timing detection circuit; a mask circuit that blocks transmission of the output of the turn-off timing detection circuit to the drive signal generation circuit for a predetermined time immediately after the turn-on timing detection circuit detects the turn-on timing; a timer circuit that measures the predetermined time, the timer circuit starts a timing operation in response to the turn-on timing detection circuit detecting the turn-on timing, stops the timing operation when a predetermined time has been measured, and outputs a signal indicating that timing is in progress while timing is in progress; 3. The isolated power supply device according to claim 1, wherein the mask circuit cuts off the output of the turn-off timing detection circuit while the timer circuit is outputting a signal indicating that the timer circuit is timing.

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