Chiplets, chips and chip trial test methods

Abstract

Chiplets, chips and chip trial testing methods are provided. The present invention provides a chiplet including at least one inter-chiplet interconnection interface for connecting to and communicating with at least one other chiplet, a selection module connected to the at least one inter-chiplet interconnection interface, and a processing module connected to the selection module. A chip and a method for trial testing the chip are also provided.

Description

[Technical Field]

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly to chiplets, chips, and chip trial testing methods. [Background technology]

[0002] With the development of electronic technology, chip designs have become increasingly complex, and it is no longer possible for a single chip to meet all functional needs. Therefore, more complex functions must be achieved through the cooperation of multiple chips. Chip trial testing is an important part of the program development and chip design process, and its purpose is to identify, isolate, and repair errors in the program or chip.

[0003] Some related technologies use a "Joint Test Action Group (JTAG) daisy chain" method for multi-chip test. Each chip and its neighboring chips are serially connected through the JTAG interface to form a chain. This method tests all chips through a single JTAG interface. A single point of failure (a failure of any chip or its JTAG interface on the chain) affects the test of all chips on the chain. Furthermore, the length of a "JTAG daisy chain" is limited by its physical and electrical characteristics. A chain that is too long can affect signal integrity, resulting in signal attenuation and noise interference, limiting the scalability of the number of chips. Furthermore, JTAG interface wiring is required for each chip on the chain to ensure the signal path is correct. This increases the complexity and cost of printed circuit board (PCB) wiring in complex multi-chip designs and limits package formats. Summary of the Invention [Means for solving the problem]

[0004] The present disclosure provides chiplets, chips, and methods for chip trial testing. In a first aspect, an embodiment of the present disclosure provides a chiplet including at least one inter-chiplet interconnection interface for connecting to at least one other chiplet and communicating with the at least one other chiplet; a selection module connected to the at least one inter-chiplet interconnection interface; and a processing module connected to the selection module, wherein the at least one inter-chiplet interconnection interface is used for receiving second trial test information from the at least one other chiplet; the selection module receives at least one trial test information in the second trial test information from the at least one inter-chiplet interconnection interface, and selects the at least one trial test information. The chiplet is configured to transmit the at least one piece of trial test information to a processing module, and the processing module is configured to, when it is determined that the at least one piece of trial test information is trial test information for trial testing the chiplet, transfer the at least one piece of trial test information for trial testing the chiplet within the chiplet, and when it is determined that the at least one piece of trial test information is trial test information for trial testing at least one other chiplet, transmit the at least one piece of trial test information to at least one inter-chiplet interconnection interface, and transmit the at least one piece of trial test information to the corresponding at least one other chiplet via the at least one inter-chiplet interconnection interface.

[0005] In a second aspect, an embodiment of the present disclosure provides a chip including a first chiplet and one or more second chiplets, wherein the first chiplet includes one or more inter-chiplet interconnection interfaces corresponding to each second chiplet, and each second chiplet includes its own inter-chiplet interconnection interface, and the inter-chiplet interconnection interface of each second chiplet is connected to the inter-chiplet interconnection interface corresponding to the first chiplet for communication between the first chiplet and each second chiplet; the chip includes an external interface located on the first chiplet, the external interface is used to connect to an external trial test device and receive first trial test information from the external trial test device; the first chiplet further includes a selection module and a processing module, and the selection module of the first chiplet is connected to the external interface and receives the first trial test information. and transmits the first trial test information to a processing module of the first chiplet, the processing module of the first chiplet being connected to the selection module of the first chiplet and one or more inter-chiplet interconnection interfaces of the first chiplet, and configured to transfer the first trial test information within the first chiplet to trial test the first chiplet when it is determined that the first trial test information is trial test information for trial testing the first chiplet, and to transmit the first trial test information to an inter-chiplet interconnection interface corresponding to the second chiplet when it is determined that the first trial test information is trial test information for trial testing a second chiplet in one or more second chiplets, so as to transmit the first trial test information to the second chiplet for trial testing.

[0006] In a third aspect, an embodiment of the present disclosure is a chip trial testing method for trial testing a chip in the second aspect or any one possible embodiment of the second aspect, the method including the steps of: receiving first trial test information from an external trial testing device via an external interface located on a first chiplet of the chip; receiving the first trial test information from the external interface via a selection module of the first chiplet and transmitting the first trial test information to a processing module of the first chiplet; and selecting the first trial test information via the processing module of the first chiplet, the first trial test information being used to trial test the first chiplet. and if it is determined that the first trial test information is trial test information for trial testing a second chiplet in one or more second chiplets, transmitting the first trial test information to an inter-chiplet interconnection interface corresponding to the second chiplet in one or more inter-chiplet interconnection interfaces of the first chiplet, thereby transmitting the first trial test information to the second chiplet for trial testing the second chiplet.

[0007] In a fourth aspect, an embodiment of the present disclosure provides a computer-readable medium having stored thereon a computer program that, when executed by a processor, implements the third aspect and any one possible implementation of the third aspect. [Effects of the Invention]

[0008] In the embodiments of the present disclosure, a chiplet can receive trial test information from at least one other chiplet through at least one inter-chiplet interconnection interface connected to at least one other chiplet. Interaction of trial test information between chiplets having a communication connection can be realized through at least one inter-chiplet interconnection interface, thereby enhancing the trial test information acquisition method and improving the reliability of trial test information transmission, thereby reducing and even eliminating the impact of single point failures. Furthermore, the method of the present disclosure does not use a "JTAG daisy chain," thereby avoiding signal integrity issues, eliminating the need for additional dedicated trial test path wiring, reducing wiring complexity and cost, and theoretically supporting interconnection and trial testing of any number of chiplets and any topology structure, resulting in relatively high scalability. [Brief explanation of the drawings]

[0009] The drawings of the embodiments of the present disclosure are as follows: [Figure 1] FIG. 1 is a conceptual diagram of a trial test using a "JTAG daisy chain" method provided by an embodiment of the present disclosure. [Figure 2] FIG. 1 is a structural conceptual diagram of a chiplet provided by an embodiment of the present disclosure. [Figure 3] 1 is a structural conceptual diagram of a chip provided by an embodiment of the present disclosure. [Figure 4] 1 is a flowchart of a chip trial test method provided by an embodiment of the present disclosure. [Figure 5] FIG. 2 is a structural conceptual diagram of another chiplet provided by an embodiment of the present disclosure. [Figure 6] FIG. 1 is a structural conceptual diagram of another chip provided by an embodiment of the present disclosure. [Figure 7] FIG. 1 is a structural conceptual diagram of another chip provided by an embodiment of the present disclosure. [Figure 8] FIG. 1 is a structural conceptual diagram of another chip provided by an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0010] In order to make the technical solution of the present disclosure more easily understandable to those skilled in the art, the following detailed description of the chiplets, chips and chip trial test methods provided by the embodiments of the present disclosure in combination with the accompanying drawings will be given below.

[0011] The present disclosure will now be described more fully with reference to the drawings, but the examples presented may be embodied in different forms and should not be construed as being limited to the examples described below. On the contrary, the purpose of providing these examples is to make the disclosure clear and complete, and to fully convey the scope of the disclosure to those skilled in the art.

[0012] The drawings of the embodiments of the present disclosure are intended to provide a further understanding of the embodiments of the present disclosure, constitute a part of the specification, and are intended to explain the present disclosure together with the detailed embodiments, and are not intended to constitute limitations on the present disclosure. The above-mentioned and other features and advantages will become more apparent to those skilled in the art by describing the embodiments in detail with reference to the drawings.

[0013] Unless contradictory, each embodiment and each feature in each embodiment of the present disclosure may be combined with each other.

[0014] The terms used in this disclosure are used only to describe particular embodiments and are not intended to limit the disclosure. As used in this disclosure, the term "and / or" includes any and all combinations of one or more of the associated listed items. As used in this disclosure, the singular forms "a," "an," and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It will also be understood that the use of the terms "comprising" and / or "consisting of" in this disclosure specifies the presence of the stated features, wholes, steps, operations, elements, and / or assemblies, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, assemblies, and / or groups thereof.

[0015] Unless otherwise specified, the meanings of all terms (including technical and scientific terms) used in this disclosure are the same as those commonly understood by those skilled in the art. It will also be understood that terms defined in common dictionaries, unless expressly limited to such meaning in this disclosure, will be interpreted as having a meaning consistent with the meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning.

[0016] A conventional system-level chip (System on Chip, SoC) integrates different functional modules such as a processor core, memory controller, and I / O interface onto a single chip. On the other hand, an SoC that adopts a chiplet (also known as a "small chip") architecture is an emerging system-level chip. In this application, an SoC that adopts the chiplet architecture is referred to as a chiplet SoC. Using chiplet technology, a chiplet SoC is designed with multiple small, independent functional modules as independent chiplets, and each chiplet is connected via a high-speed interconnect interface from bare chip to bare chip (Die-to-Die, D2D) to form a complete system-level chip.

[0017] The chiplet SoC architecture not only significantly improves performance and efficiency in baseband and server CPU chip designs, but also enhances design flexibility and scalability, while reducing manufacturing costs and complexity, and optimizing thermal management. These advantages make the chiplet SoC architecture an essential key technology in baseband and server CPU chip designs.

[0018] With the development of semiconductor technology, the Chiplet architecture has been widely applied to various types of chip design fields due to its multifaceted advantages. The Chiplet architecture is not limited to CPU chips, but can also be applied to other types of chips. For example, graphics processing unit (GPU) chips, power management chips, and sensor chips can all adopt the Chiplet architecture. In this application, a chip using the Chiplet architecture is referred to as a Chiplet architecture chip.

[0019] Some related technologies use a "JTAG daisy chain" method to test chiplet architecture chips. In this test method, each chiplet has an independent JTAG interface, and the JTAG interface of each chiplet is serially connected to the JTAG interface of an adjacent chiplet to form a chain, allowing test of all chiplets in the chiplet architecture chip through a single JTAG interface. Referring to Figure 1, Figure 1 is a conceptual diagram of a test using the "JTAG daisy chain" method provided by an embodiment of the present disclosure. Figure 1 is merely a conceptual diagram and does not limit the application scenario of the technical solution provided by the present application. Figure 1 illustrates the test process using an example in which a chiplet architecture chip includes two chiplets. The external JTAG test data input (TDI) pin of the chiplet architecture chip accesses one chiplet, and then the test data output (TDO) pin of that chiplet is connected to the TDI pin of the next chiplet, repeating this process until the TDO pin of the last chiplet is output from the chiplet architecture chip. This method means that once a single point of failure (a failure of any chiplet or its JTAG interface on the chain) occurs, it affects the test of all chiplets in the entire chain. This single point of failure increases the complexity of test and fault diagnosis and limits the reliability of test of chiplet architecture chips.

[0020] In view of this, embodiments of the present disclosure provide chiplets, chips, and chip trial testing methods, which will be described in detail below in conjunction with the accompanying drawings.

[0021] In a first aspect, referring to FIG. 2, FIG. 2 is a structural conceptual diagram of a chiplet provided by an embodiment of the present disclosure, where the chiplet 200 can be applied to various types of chiplet architecture chips, such as system-level chips using the chiplet architecture, and the chiplet 200 includes at least one inter-chiplet interconnection interface 201_1 to 201_N, a selection module 202, and a processing module 203.

[0022] In the embodiment of the present disclosure, 201_i represents any inter-chiplet interconnection interface, where the value of i is 1 to N, and N is an integer equal to or greater than 1.

[0023] In some embodiments, the selection module 202, the at least one inter-chiplet interconnection interface 201_1 to 201_N, and the processing module 203 are connected to each other via a bus 204.

[0024] In some embodiments, bus 204 may be a Debug Module Interface (DMI) line, where the DMI line may be, for example, an Advanced Peripheral Bus (APB) line of an Advanced Reduced Instruction Set Machine (ARM) or a TileLink line of SiFive.

[0025] In an embodiment of the present disclosure, at least one inter-chiplet interconnection interface 201_1 to 201_N is connected to at least one other chiplet for communicating with at least one other chiplet, the selection module 202 is connected to the at least one inter-chiplet interconnection interface 201_1 to 201_N, and the processing module 203 is connected to the selection module 202.

[0026] In an embodiment of the present disclosure, the present chiplet and other chiplets may be connected and communicated with each other via an inter-chiplet interconnection interface, where "connection" includes both direct and indirect connection, and the connection and communication between the present chiplet and other chiplets via the inter-chiplet interconnection interface may include the present chiplet being directly connected and communicating with the other chiplets via the inter-chiplet interconnection interface, or the present chiplet being indirectly connected and communicating with the other chiplets via the inter-chiplet interconnection interface via one or more intermediate chiplets.

[0027] In the embodiments of the present disclosure, other chiplets refer to chiplets other than the chiplet 200 and are distinguished from the chiplet 200 .

[0028] In an embodiment of the present disclosure, at least one inter-chiplet interconnection interface 201_1 to 201_N is used to receive second trial test information from at least one other chiplet. In one example, each inter-chiplet interconnection interface 201_i can be connected to one other chiplet, and each inter-chiplet interconnection interface 201_i is used to receive the second trial test information from the corresponding one other chiplet.

[0029] In an embodiment of the present disclosure, the selection module 202 is configured to receive at least one trial test information in the second trial test information from at least one inter-chiplet interconnection interface 201_1 to 201_N, and send the at least one trial test information to the processing module 203.

[0030] In an embodiment of the present disclosure, the selection module 202 may be a multiplexer (MUX).

[0031] In some embodiments, the trial test information includes trial test data and / or trial test instructions.

[0032] In an embodiment of the present disclosure, the processing module 203 is configured to: transfer the at least one piece of trial test information for trial testing the chiplet 200 within the chiplet 200 when it determines that the at least one piece of trial test information is trial test information for trial testing the chiplet 200; and, when it determines that the at least one piece of trial test information is trial test information for trial testing at least one other chiplet, send the at least one piece of trial test information to at least one inter-chiplet interconnection interface 201_1 to 201_N to transmit the at least one piece of trial test information to the corresponding at least one other chiplet via the at least one inter-chiplet interconnection interface 201_1 to 201_N.

[0033] In an embodiment of the present disclosure, the processing module 203 can transfer at least one trial test information within the chiplet 200 via the bus 204 for use in trial testing of the chiplet 200 .

[0034] In an embodiment of the present disclosure, the processing module may be a DMI Interconnect (DMI_IC) module.

[0035] In the embodiments of the present disclosure, a chiplet can receive trial test information from at least one other chiplet through at least one inter-chiplet interconnection interface connected to at least one other chiplet. Interaction of trial test information between chiplets having communication connections through at least one inter-chiplet interconnection interface can be realized, extending the method for acquiring trial test information and improving the reliability of trial test information transmission, thereby reducing and even eliminating the impact of single-point failures. Furthermore, the method of the present disclosure does not use a "JTAG daisy chain," thereby avoiding signal integrity issues, eliminating the need for additional dedicated trial test path wiring, reducing wiring complexity and cost, and theoretically supporting interconnection and trial testing of any number of chiplets and any topology structure, resulting in relatively high scalability.

[0036] In some embodiments, when the processing module 203 determines that the at least one piece of trial test information is trial test information for trial testing a target chiplet in at least one other chiplet, it is configured to determine an inter-chiplet interconnection interface corresponding to the target chiplet in at least one inter-chiplet interconnection interface 201_1 to 201_N of the chiplet 200 based on the placement information, and send the at least one piece of trial test information to the corresponding inter-chiplet interconnection interface, where the placement information includes connection relationship information between the chiplet 200 and the at least one other chiplet and / or information generated based on the connection relationship information.

[0037] In an embodiment of the present disclosure, the connection relationship information between chiplets can be used to determine the connection path between chiplets, and may include, for example, direct connection information or indirect connection information, where the direct connection information may include the inter-chiplet interconnection interface information of the directly connected chiplets, and the indirect connection information may include the inter-chiplet interconnection interface information of the chiplets through which the connection path passes.

[0038] In some embodiments, each inter-chiplet interconnection interface 201_i is connected to a corresponding other chiplet, and each inter-chiplet interconnection interface 201_i includes at least two bidirectional transmission interface units, and each bidirectional transmission interface unit is used to receive second trial test information from the corresponding other chiplet and is further used to transmit at least one trial test information to the corresponding other chiplet.

[0039] In an embodiment of the present disclosure, the bidirectional transmission interface unit may be a bidirectional D2D high-speed interconnection interface. Here, the number of bidirectional D2D high-speed interconnection interfaces can be determined according to the actual data transmission bandwidth, and the larger the data transmission bandwidth, the more bidirectional D2D high-speed interconnection interfaces are determined to be used. Therefore, when a chiplet or its JTAG interface of a chip using the Chiplet architecture fails, trial test information can be obtained through the inter-chiplet interconnection interfaces of other non-failed chiplets. At the same time, even when some bidirectional D2D high-speed interconnection interfaces are blocked, trial test information can be obtained through the other non-blocked bidirectional D2D high-speed interconnection interfaces. This greatly improves the reliability of the trial test path, thereby reducing and even eliminating the impact of single-point failure on the trial test of a chiplet architecture chip.

[0040] In an embodiment of the present disclosure, the bidirectional D2D high-speed interconnection interface is a high-bandwidth, low-latency interconnection module between chiplets, and can support a chiplet high-speed interconnection protocol (e.g., Universal Chiplet Interconnect Express (UCIe)).

[0041] In the embodiments of the present disclosure, the bidirectional D2D high-speed interconnection interface may include only a data interface, or may include a data interface and a signaling interface. When only a data interface is included, the data interface can be multiplexed to transmit trial test data and trial test commands. When a data interface and a signaling interface are included, the data interface is used to transmit trial test data, and the signaling interface is used to transmit trial test commands. In this way, trial test data can be transmitted via the bidirectional D2D high-speed interconnection interface, and trial test commands can be transmitted at the same time. That is, the trial test path between each chiplet multiplexes the data path between each chiplet, eliminating the need for additional dedicated trial test path wiring. This can reduce the complexity and cost of wiring within the chiplet architecture chip and simplify the package format and requirements.

[0042] In some embodiments, the chiplet 200 further includes an external interface 205 for connecting to an external trial test device, and the selection module 202 is connected to the external interface 205, where the external interface 205 is used to receive first trial test information from the external trial test device, and the selection module 202 is configured to receive second trial test information from at least one inter-chiplet interconnection interface 201_1 to 201_N and at least one trial test information in the first trial test information from the external interface 205, and send the at least one trial test information to the processing module 203.

[0043] In an embodiment of the present disclosure, the first trial test information is trial test information sent by an external trial test device and not transferred via other chiplets, and the second trial test information is trial test information transferred via other chiplets.

[0044] In some embodiments, the selection module 202 includes at least one second port for receiving second trial test information, where each second port corresponds to one other chiplet, and each other chiplet is connected to one or more inter-chiplet interconnection interfaces in the at least one inter-chiplet interconnection interface 201_1 to 201_N of the chiplet 200, and the one or more inter-chiplet interconnection interfaces are connected to the second ports corresponding to each other chiplet, and are used to transmit the second trial test information from the corresponding other chiplet to the corresponding second port. As a possible example, the selection module 202 may further include a first port for receiving the first trial test information.

[0045] In the embodiments of the present disclosure, a chiplet architecture chip can package only one set of inter-chiplet interconnection interfaces, through which any chiplet in the chiplet architecture chip can be accessed, and through the inter-chiplet interconnection interfaces between each chiplet, interaction of trial test information between adjacent chiplets can be realized, and even trial testing of all chiplets can be realized.

[0046] In some embodiments, the external interface 205 is any one of a JTAG interface, a USB interface, an Ethernet interface, an SPI interface, or a UART interface.

[0047] In some embodiments, chiplet 200 further includes a conversion module 206, wherein selection module 202 is connected to external interface 205 via conversion module 206, and conversion module 206 and selection module 202 are connected via bus 204, and conversion module 206 receives first trial test information from external interface 205, converts the first trial test information into a format suitable for transmission via bus 204, and sends the converted first trial test information to selection module 202 via bus 204.

[0048] In one example, the external interface 205 is a JTAG interface, the bus 204 is a DMI line, the first trial test information received through the external interface 205 is in a JTAG interface protocol format, the conversion module 206 is used to convert the first trial test information received from the external interface 205 from the JTAG interface protocol format to a DMI protocol format, and sends the converted first trial test information to the selection module 202 through the bus 204, and the conversion module 206 generates trial test information that can be transmitted through the bus 204, and the conversion process ensures that the converted trial test information complies with the requirements of the DMI protocol format, so that it can be transmitted through the DMI line.

[0049] In an embodiment of the present disclosure, the conversion module may be a Debug Transport Module (DTM).

[0050] In addition, each module included in the chiplet in the embodiment of the present disclosure can be installed independently or together, and there is no limitation thereon. For example, the external interface 205 and the conversion module 206 of the chiplet 200 can be installed independently or together.

[0051] In a second aspect, referring to FIG. 3, FIG. 3 is a structural conceptual diagram of a chip provided by an embodiment of the present disclosure, where chip 300 is a chiplet architecture chip, and chip 300 includes a first chiplet 301 and one or more second chiplets 302_1 to 302_N.

[0052] In the embodiment of the present disclosure, 302_i represents any second chiplet, where the value of i is 1 to N, and N is an integer equal to or greater than 1.

[0053] Note that, for the second aspect, the same concept or realization as that of the first aspect can be referred to the description of the first aspect, and will not be further described in the second aspect.

[0054] In an embodiment of the present disclosure, the first chiplet 301 includes one or more inter-chiplet interconnection interfaces 301_1_1 to 301_1_N, each corresponding to each second chiplet 302_i, and each second chiplet 302_i includes its own inter-chiplet interconnection interface, and the inter-chiplet interconnection interface of each second chiplet 302_i is connected to the corresponding inter-chiplet interconnection interface of the first chiplet 301 for communication between the first chiplet 301 and each second chiplet 302_i.

[0055] In an embodiment of the present disclosure, the chip 300 includes an external interface 301_2 located on the first chiplet 301, which is used to connect with an external test device to receive first test information from the external test device.

[0056] In the embodiment of the present disclosure, the first chiplet 301 further includes a selection module 301_3 and a processing module 301_4.

[0057] In an embodiment of the present disclosure, the selection module 301_3 of the first chiplet 301 is connected to the external interface 301_2 and is configured to receive first trial test information received from an external trial test device from the external interface 301_2, and send the first trial test information to the processing module 301_4 of the first chiplet 301.

[0058] In some embodiments, the selection module 301_3 of the first chiplet 301, one or more inter-chiplet interconnection interfaces 301_1_1 to 301_1_N of the first chiplet 301, and the processing module 301_4 of the first chiplet 301 are connected via a bus 301_5.

[0059] In some embodiments, the first chiplet 301 further includes a conversion module 301_6, where the selection module 301_3 of the first chiplet 301 is connected to the external interface 301_2 via the conversion module 301_6, and the conversion module 301_6 is connected to the selection module 301_3 of the first chiplet 301 via the bus 301_5, and the conversion module 301_6 is configured to receive first trial test information received from the external interface 301_2, convert the first trial test information into a format suitable for transmission via the bus 301_5, and send the converted first trial test information to the selection module 301_3 of the first chiplet 301 via the bus 301_5.

[0060] In an embodiment of the present disclosure, the processing module 301_4 of the first chiplet 301 is connected to the selection module 301_3 of the first chiplet 301 and one or more inter-chiplet interconnection interfaces 301_1_1 to 301_1_N of the first chiplet 301. When it is determined that the first trial test information is trial test information for trial testing the first chiplet 301, the processing module 301_4 transfers the first trial test information within the first chiplet 301 to trial test the first chiplet 301, and or when it is determined that the first trial test information is for trial testing a second chiplet 302_i in a plurality of second chiplets 302_1 to 302_N, the first trial test information is configured to send the first trial test information to the inter-chiplet interconnection interface corresponding to the second chiplet 302_i in one or more inter-chiplet interconnection interfaces 301_1_1 to 301_1_N of the first chiplet 301, so as to send the first trial test information for trial testing the second chiplet to the second chiplet 302_i.

[0061] In the embodiment of the present disclosure, the processing module 301_4 can transfer first trial test information for trial testing the first chiplet 301 within the first chiplet 301 via the bus 301_5.

[0062] In embodiments of the present disclosure, chiplets in a chip can be connected via at least one inter-chiplet interconnection interface, and trial test information can be exchanged between chiplets that have a communication connection via the at least one inter-chiplet interconnection interface. This enhances the method for acquiring trial test information and improves the reliability of trial test information transmission, thereby reducing and even eliminating the impact of single-point failures. Furthermore, the chip disclosed herein does not use a "JTAG daisy chain," thereby avoiding signal integrity issues and eliminating the need for additional dedicated trial test path wiring, thereby reducing wiring complexity and cost. In theory, it can support interconnection and trial testing of any number of chiplets and any topology structure, resulting in relatively high scalability. Furthermore, the chiplet architecture chip disclosed herein can package only one set of inter-chiplet interconnection interfaces, through which any chiplet in the chiplet architecture chip can be accessed. Through the inter-chiplet interconnection interfaces between each chiplet, trial test information can be exchanged between adjacent chiplets, and trial testing of all chiplets can be achieved.

[0063] In some embodiments, when the processing module 301_4 of the first chiplet 301 determines that the first trial test information is trial test information for trial testing a second chiplet 302_i in one or more second chiplets 302_1 to 302_N, the processing module 301_4 of the first chiplet 301 is configured to: determine an inter-chiplet interconnection interface corresponding to the second chiplet 302_i in one or more inter-chiplet interconnection interfaces 301_1_1 to 301_1_N of the first chiplet 301 based on the arrangement information; and send the first trial test information to the inter-chiplet interconnection interface corresponding to the second chiplet 302_i in the one or more inter-chiplet interconnection interfaces 301_1_1 to 301_1_N of the first chiplet 301, where the arrangement information includes connection relationship information between the first chiplet 301 and the one or more second chiplets 302_1 to 302_N and / or information generated based on the connection relationship information.

[0064] In an embodiment of the present disclosure, the connection relationship information between chiplets is used to determine the connection path between chiplets, and may include, for example, direct connection information or indirect connection information, where the direct connection information may include the inter-chiplet interconnection interface information of the directly connected chiplets, and the indirect connection information may include the inter-chiplet interconnection interface information of the chiplets through which the connection path passes.

[0065] In some embodiments, each second chiplet 302_i further includes a selection module and a processing module, wherein the selection module of each second chiplet 302_i is connected to the inter-chiplet interconnection interface of the second chiplet 302_i and configured to receive first trial test information from the first chiplet 301 and send the first trial test information to the processing module of the second chiplet 302_i; and the processing module of each second chiplet 302_i is connected to the selection module of the second chiplet 302_i and the inter-chiplet interconnection interface of the second chiplet 302_i and is configured to transfer the first trial test information within the second chiplet 302_i to trial test the second chiplet 302_i when it is determined that the first trial test information is trial test information for trial testing the second chiplet 302_i.

[0066] In an embodiment of the present disclosure, the processing module of each second chiplet 302_i can transfer first trial test information within the second chiplet 302_i via the bus to trial test the second chiplet 302_i.

[0067] In some embodiments, the selection module of the second chiplet 302_i is connected to the inter-chiplet interconnection interface of the second chiplet 302_i via a bus, and one or more inter-chiplet interconnection interfaces 301_1_1 to 301_1_N of the first chiplet 301 are connected to the inter-chiplet interconnection interface of the second chiplet 302_i via a bus.

[0068] In some embodiments, the selection module of the first chiplet 301 further includes one or more second ports of the one or more inter-chiplet interconnection interfaces 301_1_1 to 301_1_N connected to the first chiplet 301, and the one or more second ports are configured to be in an energy prohibited state.

[0069] In some embodiments, each second chiplet 302_i further includes one or more inter-chiplet interconnection interfaces connected to other chiplets except the first chiplet 301, the selection module of each second chiplet 302_i further includes one or more second ports connected to one or more inter-chiplet interconnection interfaces of other chiplets except the first chiplet 301, and the one or more second ports of the selection module of each second chiplet 302_i are configured to be in an energy prohibited state.

[0070] In the embodiments of the present disclosure, a port being in an energy prohibited state means that the port is in a state that does not allow data transmission, and a port in an energy prohibited state cannot be used to receive or transmit data.

[0071] In some embodiments, chip 300 further includes a third chiplet 303 having an inter-chiplet interconnect interface for connecting to a corresponding inter-chiplet interconnect interface of second chiplet 302_i for communicating with second chiplet 302_i, where: the processing module 301_4 of the first chiplet 301 is further configured, when determining that the first trial test information is trial test information for trial testing the third chiplet 303, to send the first trial test information to an inter-chiplet interconnection interface corresponding to the second chiplet 302_i connected to the third chiplet 303 in one or more inter-chiplet interconnection interfaces 301_1_1 to 301_1_N of the first chiplet 301; The processing module of the second chiplet 302_i connected to the third chiplet 303 is further configured, when it determines that the first trial test information is trial test information for trial testing the third chiplet 303, to send the first trial test information to the inter-chiplet interconnection interface corresponding to the third chiplet 303 of the second chiplet 302_i, so as to send the first trial test information for trial testing the third chiplet 303 to the third chiplet 303.

[0072] In some embodiments, chip 300 further includes a fourth chiplet 304 having an inter-chiplet interconnection interface, and a fifth chiplet 305 having an inter-chiplet interconnection interface connected to second chiplet 302_i and an inter-chiplet interconnection interface connected to fourth chiplet 304, wherein the inter-chiplet interconnection interface of fourth chiplet 304 connects to a corresponding inter-chiplet interconnection interface of second chiplet 302_i via the inter-chiplet interconnection interface of fifth chiplet 305 to communicate with second chiplet 302_i, wherein: the processing module 301_4 of the first chiplet 301 is further configured, when determining that the first trial test information is trial test information for trial testing the fourth chiplet 304, to send the first trial test information to an inter-chiplet interconnection interface corresponding to the second chiplet 302_i connected to the fifth chiplet 305 in one or more inter-chiplet interconnection interfaces 301_1_1 to 301_1_N of the first chiplet 301; the processing module of the second chiplet 302_i connected to the fifth chiplet 305 is further configured, when determining that the first trial test information is trial test information for trial testing the fourth chiplet 304, to send the first trial test information to the inter-chiplet interconnection interface corresponding to the fifth chiplet 305 of the second chiplet 302_i, so as to send the first trial test information to the fifth chiplet 305; The fifth chiplet 305 further includes a selection module and a processing module, where: the selection module of the fifth chiplet 305 is connected to the inter-chiplet interconnection interface of the fifth chiplet 305, and is configured to receive first trial test information from the second chiplet 302_i and send the first trial test information to the processing module of the fifth chiplet 305; The processing module of the fifth chiplet 305 is connected to the selection module of the fifth chiplet 305 and the inter-chiplet interconnection interface of the fifth chiplet 305, and is configured to transfer the first trial test information within the fifth chiplet 305 for trial testing the fifth chiplet 305 when it is determined that the first trial test information is trial test information for trial testing the fifth chiplet 305; and to send the first trial test information to the inter-chiplet interconnection interface corresponding to the fourth chiplet 304, so as to send the first trial test information to the fourth chiplet 304 for trial testing the fourth chiplet 304.

[0073] In an embodiment of the present disclosure, the processing module of the fifth chiplet 305 may transfer the first trial test information within the fifth chiplet 305 via the bus to trial test the fifth chiplet 305.

[0074] In a third aspect, referring to FIG. 4, FIG. 4 is a flowchart of a chip trial testing method provided by an embodiment of the present disclosure, which may be used to trial test a chip 300 in the second aspect and any one possible embodiment of the second aspect, and the method includes the following steps:

[0075] S401, receiving first trial test information from an external trial test device via an external interface 301_2 located on the first chiplet 301 of the chip 300;

[0076] S402, receive first trial test information from the external interface 301_2 via the selection module 301_3 of the first chiplet 301, and send the first trial test information to the processing module 301_4 of the first chiplet 301;

[0077] In some embodiments, the method further includes receiving, via the conversion module 301_6 of the first chiplet 301, first trial test information received from the external interface 301_2, converting the first trial test information into a format suitable for transmission via the bus 301_5, and sending the converted first trial test information to the selection module 301_3 of the first chiplet 301 via the bus 301_5.

[0078] S403, executed via the processing module 301_4 of the first chiplet 301, if it is determined that the first trial test information is trial test information for trial testing the first chiplet 301, transferring the first trial test information within the first chiplet 301 to trial test the first chiplet 301; if it is determined that the first trial test information is trial test information for trial testing a second chiplet 302_i in one or more second chiplets 302_1 to 302_N, sending the first trial test information to an inter-chiplet interconnection interface corresponding to the second chiplet 302_i in one or more inter-chiplet interconnection interfaces 301_1_1 to 301_1_N of the first chiplet 301, so as to send the first trial test information for trial testing the second chiplet 302_i to the second chiplet 302_i.

[0079] In embodiments of the present disclosure, chiplets in a chip can be connected via at least one inter-chiplet interconnection interface, and trial test information can be exchanged between chiplets that have a communication connection via the at least one inter-chiplet interconnection interface. This enhances the method for acquiring trial test information and improves the reliability of trial test information transmission, thereby reducing and even eliminating the impact of single-point failures. Furthermore, the chip disclosed herein does not use a "JTAG daisy chain," thereby avoiding signal integrity issues and eliminating the need for additional dedicated trial test path wiring, thereby reducing wiring complexity and cost. In theory, it can support interconnection and trial testing of any number of chiplets and any topology structure, resulting in relatively high scalability. Furthermore, the chiplet architecture chip disclosed herein can package only one set of inter-chiplet interconnection interfaces, through which any chiplet in the chiplet architecture chip can be accessed. Through the inter-chiplet interconnection interfaces between each chiplet, trial test information can be exchanged between adjacent chiplets, and trial testing of all chiplets can be achieved.

[0080] In addition, for the same concept or realization of the third aspect as that of the first or second aspect, reference may be made to the description of the first or second aspect, and no further description of the third aspect will be given.

[0081] In some embodiments, the method further includes the steps of receiving first trial test information from the first chiplet 301 through a selection module of each second chiplet 302_i and sending the first trial test information to a processing module of the second chiplet 302_i; and, when the processing module of each second chiplet 302_i determines that the first trial test information is trial test information for trial testing the second chiplet 302_i, transferring the first trial test information within the second chiplet 302_i for trial testing the second chiplet.

[0082] In some embodiments, the method further includes the steps of: being executed via the processing module 301_4 of the first chiplet 301, and, when it is determined that the first trial test information is trial test information for trial testing the third chiplet 303, sending the first trial test information to an inter-chiplet interconnection interface corresponding to a second chiplet 302_i connected to the third chiplet 301 in one or more inter-chiplet interconnection interfaces 301_1_1 to 301_1_N of the first chiplet 301; and being executed via the processing module of the second chiplet 302_i connected to the third chiplet 303, when it is determined that the first trial test information is trial test information for trial testing the third chiplet 303, sending the first trial test information to the inter-chiplet interconnection interface of the second chiplet 302_i corresponding to the third chiplet 303, so as to send the first trial test information for trial testing the third chiplet 303 to the third chiplet 303.

[0083] In some embodiments, the method includes the steps of: executing via the processing module 301_4 of the first chiplet 301, when it is determined that the first trial test information is trial test information for trial testing the fourth chiplet 304, transmitting the first trial test information to an inter-chiplet interconnection interface of one or more inter-chiplet interconnection interfaces 301_1_1 to 301_1_N of the first chiplet 301 corresponding to the second chiplet 302_i connected to the fifth chiplet 305; and executing via the processing module of the second chiplet 302_i connected to the fifth chiplet 305, when it is determined that the first trial test information is trial test information for trial testing the fourth chiplet 304, transmitting the first trial test information to the inter-chiplet interconnection interface of the second chiplet 302_i corresponding to the fifth chiplet 305 of the second chiplet 302_i, to transmit the first trial test information to the inter-chiplet interconnection interface of the second chiplet 302_i corresponding to the fifth chiplet 305. receiving first trial test information from the second chiplet 302_i via the selection module of the fifth chiplet 305 and sending the first trial test information to the processing module of the fifth chiplet 305; and, if it is determined that the first trial test information is trial test information for trial testing the fifth chiplet 305, transferring the first trial test information within the fifth chiplet 305 to trial test the fifth chiplet 305; and, if it is determined that the first trial test information is for trial testing the fourth chiplet 304, sending the first trial test information to the inter-chiplet interconnection interface of the fifth chiplet 305 corresponding to the fourth chiplet 304 to send the first trial test information to the fourth chiplet 304 for trial testing the fourth chiplet 304.

[0084] In some embodiments, the method is executed via the processing module 301_4 of the first chiplet 301, and when it is determined that the first trial test information is trial test information for trial testing a second chiplet 302_i in one or more second chiplets 302_1 to 302_N, the method further includes the steps of: determining an inter-chiplet interconnection interface corresponding to the second chiplet 302_i in one or more inter-chiplet interconnection interfaces 301_1_1 to 301_1_N of the first chiplet 301 based on the arrangement information; and sending the first trial test information to the inter-chiplet interconnection interface corresponding to the second chiplet 302_i in the one or more inter-chiplet interconnection interfaces 301_1_1 to 301_1_N of the first chiplet 301, wherein the arrangement information includes connection relationship information between the first chiplet 301 and the one or more second chiplets 302_1 to 302_N and / or information generated based on the connection relationship information.

[0085] In the embodiments of the present disclosure, the application of the Chiplet architecture in baseband chips and CPU chips covers a wide range of scenarios, from wireless communication devices (e.g., base stations, terminal devices, etc.), ubiquitous network devices, and wireless access points to data centers, high-performance computing, enterprise applications, and edge computing. Through modularization and independent optimization design, chips adopting the Chiplet architecture meet the needs of high performance, low power consumption, flexible expansion, and high reliability, providing powerful technical support for modern communications and computing devices. For example, it can be applied to high-performance computing and data centers. When applied to servers and supercomputing nodes, by independently designing different modules of the multi-chip architecture (e.g., multi-core processing, memory controller, I / O interface, etc.), chips adopting the Chiplet architecture can provide outstanding computing power and data processing capabilities in high-performance computing and data centers. By adopting the chip trial testing method provided by this disclosure, it is possible to ensure the cooperative operation of each chiplet in a complex system, support flexible resource expansion, and improve overall performance and reliability. When applied to cloud computing and virtualization nodes, chips adopting the Chiplet architecture can achieve higher computing density and efficiency, support the detection and optimization of each functional module, and ensure the efficient operation of virtualization technology. It can also be used, for example, in mobile communications scenarios. When used in wireless communication devices, baseband chips need to process complex communication protocols such as 4G, 5G, Wi-Fi, and Bluetooth (registered trademark). By adopting the chip and chip trial testing method provided by the present disclosure, chips adopting the Chiplet architecture can individually optimize and upgrade processing modules for different communication standards (e.g., modems, radio frequency front ends, protocol processors, etc.), helping to provide efficient, low-power communication capabilities.Furthermore, for example, it can be used in ubiquitous networks (IoT) and edge computing scenarios. When applied to intelligent cities and industrial ubiquitous networks, chips adopting the Chiplet architecture can be used for data collection and edge computing, and the chip trial test method can ensure the accuracy and efficiency of each data processing module. When used in home ubiquitous network devices, the chip and chip trial test method can help ensure the normal operation of each function of smart home devices (e.g., smart door locks, surveillance cameras, etc.).

[0086] In order to make the technical solutions provided by the embodiments of the present disclosure more clearly understandable to those skilled in the art, the technical solutions provided by the embodiments of the present disclosure will be further described below through specific examples.

[0087] Referring to FIG. 5, FIG. 5 is a structural conceptual diagram of another chiplet provided by an embodiment of the present disclosure. In this embodiment, the chiplet is chiplet 0, the external interface is a JTAG interface, the conversion module is a Debug Transport Module (DTM), the selection module is a MUX, the inter-chiplet interconnection interface is a plurality of pairs of bidirectional D2D high-speed interconnection interfaces, the processing module is a DMI Interconnect (DMI_IC), the bus is a DMI line, and each module can realize the following functions:

[0088] The JTAG interface is used to receive first trial test information from an external trial test device.

[0089] The DTM is connected to the MUX via the DMI line and is used to receive first trial test information from an external trial test device via the JTAG interface and convert the first trial test information into a format suitable for transmission via the DMI line.

[0090] Multiple sets of bidirectional D2D high-speed interconnection interfaces (referred to as D2D in the drawings) are connected to the MUX and DMI_IC via DMI lines, and the multiple sets of bidirectional D2D high-speed interconnection interfaces are used to receive multiple second trial test information from multiple other chiplets (e.g., adjacent chiplets of chiplet 0) via the DMI lines.

[0091] The MUX is configured to receive at least one trial test information among the first trial test information after format conversion from the DTM and the second trial test information from multiple sets of bidirectional D2D high-speed interconnection interfaces, and send the at least one trial test information to the DMI_IC, and Figure 5 illustrates the at least one trial test information as trial test information received from the DTM.

[0092] When the DMI_IC determines that the trial test information received from the MUX is trial test information for trial testing chiplet 0 (i.e., this chiplet), the DMI_IC is configured to forward the trial test information received from the MUX within chiplet 0 to trial test chiplet 0; when the DMI_IC determines that the trial test information received from the MUX is trial test information for trial testing another chiplet, the DMI_IC is configured to send the trial test information received from the MUX to a bidirectional D2D high-speed interconnection interface corresponding to the other chiplet, and transmit the trial test information to the corresponding other chiplet via the bidirectional D2D high-speed interconnection interface, thereby trial testing the other chiplet based on the trial test information received via the bidirectional D2D high-speed interconnection interface.

[0093] Referring to Figure 6, Figure 6 is a structural conceptual diagram of another chip provided by an embodiment of the present disclosure, Figure 6 shows a structure in which the chip includes two chiplets, and the two chiplets in Figure 6 are chiplet 0 and chiplet 1 respectively, and the structure of each chiplet is the same as the chiplet structure in Figure 5, and the included component parts and the functions of each component part are the same, so they will not be further described here, but the differences will be described below.

[0094] In this embodiment, based on the chip shown in FIG. 6, the following chip trial test method can be realized.

[0095] S61 receives first trial test information from an external trial test device via a JTAG interface located on chiplet 0;

[0096] S62, via the DTM of chiplet 0, converts first trial test information received from an external trial test device through the JTAG interface into trial test information suitable for transmission over the DMI line.

[0097] S63: Receive the format-converted trial test information from the DTM via the MUX of chiplet 0, and send the trial test information to the DMI_IC of chiplet 0.

[0098] S64a: When it is determined via DMI_IC that the trial test information received from the MUX is trial test information for trial testing chiplet 0 (i.e., this chiplet), the trial test information received from the MUX is transferred within chiplet 0 to trial test chiplet 0.

[0099] S64b: If it is determined that the trial test information received from the MUX is trial test information for trial testing chiplet 1, send the trial test information received from the MUX to the bidirectional D2D high-speed interconnection interface corresponding to chiplet 1, and send the trial test information to the corresponding chiplet 1 via the bidirectional D2D high-speed interconnection interface, and the MUX in which chiplet 1 is located selects the trial test information output via DMI1 (connected to the bidirectional D2D high-speed interconnection interface corresponding to chiplet 0) as the trial test information of chiplet 1 (see bold line), and trial tests chiplet 1 based on the trial test information received via DMI1.

[0100] Referring to Figure 7, Figure 7 is a conceptual structural diagram of another chip provided by an embodiment of the present disclosure. Figure 7 shows a structure in which the chip includes four chiplets. The four chiplets in Figure 7 are chiplet 0, chiplet 1, chiplet 2, and chiplet 3, respectively. The structure of each chiplet is the same as the chiplet structure in Figure 5, and the included component parts and the functions of each component part are the same. This will not be described further here, but the differences will be described below.

[0101] In this embodiment, based on the chip shown in FIG. 7, the following chip trial test method can be realized.

[0102] S71 receives trial test information from an external trial test device via a JTAG interface located on chiplet 0.

[0103] S72, via the DTM of chiplet 0, converts first trial test information received from an external trial test device through the JTAG interface into trial test information suitable for transmission over the DMI line.

[0104] S73: Receive the format-converted trial test information from the DTM via the MUX of chiplet 0, and send the trial test information to the DMI_IC of chiplet 0.

[0105] S74a: When it is determined via DMI_IC that the trial test information received from the MUX is trial test information for trial testing chiplet 0 (i.e., this chiplet), the trial test information received from the MUX is transferred within chiplet 0 to trial test chiplet 0.

[0106] S74b: If it is determined that the trial test information received from the MUX is trial test information for trial testing chiplet 1, send the trial test information received from the MUX to the bidirectional D2D high-speed interconnection interface corresponding to chiplet 1, and send the trial test information to the corresponding chiplet 1 via the bidirectional D2D high-speed interconnection interface, and the MUX in which chiplet 1 is located selects the trial test information output via DMI1 (connected to the bidirectional D2D high-speed interconnection interface corresponding to chiplet 0) as the trial test information of chiplet 1 (see bold line), and trial tests chiplet 1 based on the trial test information received via DMI1.

[0107] S74c: If it is determined that the trial test information received from the MUX is trial test information for trial testing chiplet 2, send the trial test information received from the MUX to the bidirectional D2D high-speed interconnection interface corresponding to chiplet 2, and send the trial test information to the corresponding chiplet 2 via the bidirectional D2D high-speed interconnection interface, and the MUX in which chiplet 2 is located selects the trial test information output via DMI0 (connected to the bidirectional D2D high-speed interconnection interface corresponding to chiplet 0) as the trial test information of chiplet 2 (see bold line), and trial tests chiplet 2 based on the trial test information received via DMI0.

[0108] S74d: If it is determined that the trial test information received from the MUX is trial test information for trial testing chiplet 3, send the trial test information received from the MUX to the bidirectional D2D high-speed interconnection interface corresponding to chiplet 1 or chiplet 2 connected to chiplet 3, and send the trial test information to the corresponding chiplet 3 via the bidirectional D2D high-speed interconnection interface, and the MUX in which chiplet 3 is located selects the trial test information output via DMI0 (connected to the bidirectional D2D high-speed interconnection interface corresponding to chiplet 1) or DMI1 (connected to the bidirectional D2D high-speed interconnection interface corresponding to chiplet 2) as the trial test information of chiplet 3 (see bold line), and trial tests chiplet 3 based on the trial test information received via DMI0 or DMI1.

[0109] Figure 8 is a conceptual structural diagram of another chip provided by an embodiment of the present disclosure. Figure 8 shows a structure in which the chip includes six chiplets. The six chiplets in Figure 8 are chiplet 0, chiplet 1, chiplet 2, chiplet 3, chiplet 4, and chiplet 5, respectively. The structure of each chiplet is the same as the chiplet structure in Figure 5, and the included components and the functions of each component are the same. This will not be described further here, but the differences will be described below.

[0110] In this embodiment, based on the chip shown in FIG. 8, the following chip trial test method can be realized.

[0111] S81 receives trial test information from an external trial test device via a JTAG interface located on chiplet 0.

[0112] S82, via the DTM of chiplet 0, converts first trial test information received from an external trial test device through the JTAG interface into trial test information suitable for transmission over the DMI line.

[0113] S83: Receive the format-converted trial test information from the DTM via the MUX of chiplet 0, and send the trial test information to the DMI_IC of chiplet 0.

[0114] S84a: When it is determined via the DMI_IC that the trial test information received from the MUX is trial test information for trial testing chiplet 0 (i.e., this chiplet), the trial test information received from the MUX is transferred within chiplet 0 to trial test chiplet 0.

[0115] S84b: If it is determined that the trial test information received from the MUX is trial test information for trial testing chiplet 1, send the trial test information received from the MUX to the bidirectional D2D high-speed interconnection interface corresponding to chiplet 1, and send the trial test information to the corresponding chiplet 1 via the bidirectional D2D high-speed interconnection interface, and the MUX in which chiplet 1 is located selects the trial test information output via DMI1 (connected to the bidirectional D2D high-speed interconnection interface corresponding to chiplet 0) as the trial test information of chiplet 1 (see bold line), and trial tests chiplet 1 based on the trial test information received via DMI1.

[0116] S84c: If it is determined that the trial test information received from the MUX is trial test information for trial testing chiplet 3, the trial test information received from the MUX is sent to the bidirectional D2D high-speed interconnection interface corresponding to chiplet 3, and the trial test information is sent to the corresponding chiplet 3 via the bidirectional D2D high-speed interconnection interface, and the MUX in which chiplet 3 is located selects the trial test information output via DMI0 (connected to the bidirectional D2D high-speed interconnection interface corresponding to chiplet 0) as the trial test information of chiplet 3 (see bold line), and trial tests chiplet 3 based on the trial test information received via DMI0.

[0117] S84d: If it is determined that the trial test information received from the MUX is trial test information for trial testing chiplet 2, the trial test information received from the MUX is sent to the bidirectional D2D high-speed interconnection interface corresponding to chiplet 1 connected to chiplet 2, and the trial test information is sent to the corresponding chiplet 2 via the bidirectional D2D high-speed interconnection interface, and the MUX in which chiplet 2 is located selects the trial test information output via DMI1 (connected to the bidirectional D2D high-speed interconnection interface corresponding to chiplet 1) as the trial test information of chiplet 2 (see bold line), and trial tests chiplet 2 based on the trial test information received via DMI1. In addition, when a fault exists in the Chiplet 0-Chiplet 1-Chiplet 2 path, the trial test information can also be transmitted to Chiplet 2 via the Chiplet 0-Chiplet 3-Chiplet 4-Chiplet 5-Chiplet 2 path. The method of transmitting the trial test information is similar to the method of transmitting via the Chiplet 0-Chiplet 1-Chiplet 2 path, and therefore, the explanation is omitted here.

[0118] S84e: If it is determined that the trial test information received from the MUX is trial test information for trial testing chiplet 4, send the trial test information received from the MUX to the bidirectional D2D high-speed interconnection interface corresponding to chiplet 1 or chiplet 3 connected to chiplet 4, and send the trial test information to the corresponding chiplet 4 via the bidirectional D2D high-speed interconnection interface, and the MUX in which chiplet 4 is located selects the trial test information output via DMI0 (connected to the bidirectional D2D high-speed interconnection interface corresponding to chiplet 1) or DMI1 (connected to the bidirectional D2D high-speed interconnection interface corresponding to chiplet 3) as the trial test information of chiplet 4 (see bold line), and trial tests chiplet 4 based on the trial test information received via DMI0 or DMI1.

[0119] S84f: If it is determined that the trial test information received from the MUX is trial test information for trial testing chiplet 5, send the trial test information received from the MUX to the bidirectional D2D high-speed interconnection interface corresponding to chiplet 1 or chiplet 3 connected to chiplet 2 or chiplet 4 connected to chiplet 5, and send the trial test information to the corresponding chiplet 5 via the bidirectional D2D high-speed interconnection interface, and the MUX in which chiplet 5 is located selects the trial test information output via DMI0 (connected to the bidirectional D2D high-speed interconnection interface corresponding to chiplet 2) or DMI1 (connected to the bidirectional D2D high-speed interconnection interface corresponding to chiplet 4) as the trial test information of chiplet 5 (see bold line), and trial tests chiplet 5 based on the trial test information received via DMI0 or DMI1.

[0120] In the above embodiment, the external JTAG interface can access any chiplet included in the chip, thereby enabling trial test access to all chiplets. Furthermore, adjacent chiplets are interconnected via D2D modules. Even if the D2D module between any two chiplets is blocked, a trial test can be initiated via another interconnected chiplet. For example, if the D2D module between chiplet 0 and chiplet 1 is blocked, a trial test for chiplet 3 can be initiated via the D2D modules from chiplet 1 to chiplet 3. This significantly improves the reliability of the trial test path, thereby reducing or even eliminating the impact of single-point failures on chip trial tests. The chip-to-chip trial test method provided by the present disclosure enables trial test information to be transmitted in stages between multiple chiplets, enabling chip trial tests using a chiplet architecture with any number and topology structure.

[0121] In a fourth aspect, an embodiment of the present disclosure further provides a computer-readable medium having stored thereon a computer program that, when executed by a processor, implements the third aspect and any one possible implementation of the third aspect.

[0122] Those skilled in the art will understand that all or some of the steps, systems, and functional modules / units in the devices disclosed above may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0123] In hardware embodiments, the division between the functional modules / units described above does not necessarily correspond to the division of physical components, for example, one physical component may include multiple functions, or one function or step may be performed by multiple physical components working together.

[0124] Some or all of the physical components may be implemented as hardware or software executed by a processor, such as a central processor (CPU), digital signal processor, or microprocessor, or as an integrated circuit, such as a dedicated integrated circuit. Such software may be distributed on computer-readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). As known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (e.g., computer-readable instructions, data structures, program modules, or other data). Computer storage media may be any medium that stores the desired information and is accessible by a computer, including, but not limited to, random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH) or other disk memory, read-only optical disk (CD-ROM), digital versatile disk (DVD) or other optical disk memory, magnetic cassette, magnetic tape, magnetic disk storage, or other magnetic storage device. Additionally, communication media typically includes computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and can include any information delivery media as known to those skilled in the art.

[0125] Although illustrative embodiments are disclosed herein and specific terms are used, they are to be used and interpreted in a general descriptive sense only and not for purposes of limitation. It will be apparent to those skilled in the art that, in some embodiments, features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise specified. Accordingly, those skilled in the art will recognize that various changes in form and detail may be made without departing from the scope of the present disclosure, as defined by the appended claims.

Claims

1. A chiplet including: at least one inter-chiplet interconnection interface for connecting to at least one other chiplet and communicating with the at least one other chiplet; a selection module connected to the at least one inter-chiplet interconnection interface; and a processing module connected to the selection module, the at least one inter-chiplet interconnection interface is used to receive second trial test information from the at least one other chiplet; the selection module is configured to receive at least one trial test information in the second trial test information from the at least one inter-chiplet interconnection interface, and send the at least one trial test information to the processing module; the processing module is configured to, when it is determined that the at least one piece of trial test information is trial test information for trial testing the present chiplet, transfer the at least one piece of trial test information for trial testing the present chiplet within the present chiplet; and, when it is determined that the at least one piece of trial test information is trial test information for trial testing the at least one other chiplet, send the at least one piece of trial test information to the at least one inter-chiplet interconnection interface, and send the at least one piece of trial test information to the corresponding at least one other chiplet via the at least one inter-chiplet interconnection interface; The chiplet further includes an external interface for connecting to an external trial test device, and the selection module is connected to the external interface; the external interface is used to receive first trial test information from the external trial test device; The selection module is configured to receive second trial test information from the at least one inter-chiplet interconnection interface and at least one trial test information in the first trial test information of the external interface, and to send the at least one trial test information to the processing module. Chiplets.

2. The selection module, the at least one inter-chiplet interconnection interface, and the processing module are connected to each other via a bus. The chiplet of claim 1 .

3. The chiplet further includes a conversion module, the selection module is connected to the external interface through the conversion module, and the conversion module and the selection module are connected through the bus; The conversion module receives the first trial test information from the external interface, converts the first trial test information into a format suitable for transmission via the bus, and transmits the converted first trial test information to the selection module via the bus. The chiplet of claim 2 .

4. The selection module includes at least one second port for receiving the second trial test information, each second port corresponding to one of the other chiplets, each of the other chiplets being connected to one or more inter-chiplet interconnection interfaces of the at least one inter-chiplet interconnection interface of the chiplet, the one or more inter-chiplet interconnection interfaces being connected to the second port corresponding to each of the other chiplets, and being used to transmit the second trial test information from the corresponding other chiplet to the corresponding second port. The chiplet of claim 1 .

5. When the processing module determines that the at least one piece of trial test information is trial test information for trial testing a target chiplet in the at least one other chiplet, the processing module is configured to determine an inter-chiplet interconnection interface corresponding to the target chiplet in the at least one inter-chiplet interconnection interface of the present chiplet based on configuration information, and transmit the at least one piece of trial test information to the corresponding inter-chiplet interconnection interface, wherein the configuration information includes connection relationship information between the present chiplet and the at least one other chiplet and / or information generated based on the connection relationship information. The chiplet of claim 1 .

6. Each of the inter-chiplet interconnection interfaces is connected to a corresponding other chiplet, and each of the inter-chiplet interconnection interfaces includes at least two bidirectional transmission interface units; Each of the bidirectional transmission interface units is used to receive the second trial test information from the corresponding other chiplet, and is further used to transmit the at least one trial test information to the corresponding other chiplet. The chiplet of claim 1 .

7. A chip including a first chiplet and one or more second chiplets, The first chiplet includes one or more inter-chiplet interconnection interfaces respectively corresponding to each second chiplet, and each second chiplet includes its own inter-chiplet interconnection interface, and the inter-chiplet interconnection interface of each second chiplet is connected to the inter-chiplet interconnection interface corresponding to the first chiplet for communication between the first chiplet and each second chiplet; The chip includes an external interface located on a first chiplet, the external interface being used to connect with an external test device and receive first test information from the external test device; the first chiplet further includes a selection module and a processing module; a selection module of the first chiplet connected to the external interface and configured to receive first trial test information and send the first trial test information to the processing module of the first chiplet; the processing module of the first chiplet is connected to the selection module of the first chiplet and the one or more inter-chiplet interconnection interfaces of the first chiplet, and is configured to: when it is determined that the first trial test information is trial test information for trial testing the first chiplet, transfer the first trial test information within the first chiplet to trial test the first chiplet; and when it is determined that the first trial test information is trial test information for trial testing a second chiplet in the one or more second chiplets, send the first trial test information to an inter-chiplet interconnection interface corresponding to the second chiplet in the one or more inter-chiplet interconnection interfaces of the first chiplet, so as to send the first trial test information for trial testing the second chiplet to the second chiplet; Each second chiplet further includes a selection module and a processing module; the selection module of each second chiplet is connected to the inter-chiplet interconnection interface of the second chiplet, and is configured to receive first trial test information from the first chiplet and send the first trial test information to the processing module of the second chiplet; The processing module of each second chiplet is connected to the selection module of the second chiplet and the inter-chiplet interconnection interface of the second chiplet, and is configured to transfer the first trial test information within the second chiplet to trial test the second chiplet when it is determined that the first trial test information is trial test information for trial testing the second chiplet. Tips.

8. The selection module of the first chiplet, the one or more inter-chiplet interconnection interfaces of the first chiplet, and the processing module of the first chiplet are connected to each other via a bus, the selection module of the second chiplet and the inter-chiplet interconnection interface of the second chiplet are connected via a bus, and the one or more inter-chiplet interconnection interfaces of the first chiplet and the inter-chiplet interconnection interface of the second chiplet are connected via a bus. The chip of claim 7.

9. The first chiplet further includes a conversion module, wherein a selection module of the first chiplet is connected to the external interface via the conversion module, and the conversion module and the selection module of the first chiplet are connected via the bus, and the conversion module is configured to receive the first trial test information received from the external interface, convert the first trial test information into a format suitable for transmission via the bus, and transmit the converted first trial test information to the selection module of the first chiplet via the bus. The chip of claim 8.

10. a chip further including a third chiplet having an inter-chiplet interconnection interface for connecting to a corresponding inter-chiplet interconnection interface of the second chiplet for communicating with the second chiplet, the processing module of the first chiplet is further configured, when determining that the first trial test information is trial test information for trial testing a third chiplet, to send the first trial test information to an inter-chiplet interconnection interface corresponding to a second chiplet connected to the third chiplet in the one or more inter-chiplet interconnection interfaces of the first chiplet; The processing module of the second chiplet connected to the third chiplet is further configured, when determining that the first trial test information is trial test information for trial testing the third chiplet, to send the first trial test information to an inter-chiplet interconnection interface of the second chiplet corresponding to the third chiplet, so as to send the first trial test information for trial testing the third chiplet to the third chiplet. The chip of claim 7.

11. a fourth chiplet having an inter-chiplet interconnection interface; and a fifth chiplet having an inter-chiplet interconnection interface connected to the second chiplet and an inter-chiplet interconnection interface connected to the fourth chiplet, wherein the inter-chiplet interconnection interface of the fourth chiplet is connected to a corresponding inter-chiplet interconnection interface of the second chiplet via the inter-chiplet interconnection interface of the fifth chiplet connected to the fourth chiplet, to communicate with the second chiplet; the processing module of the first chiplet is configured, when determining that the first trial test information is trial test information for trial testing the fourth chiplet, to send the first trial test information to an inter-chiplet interconnection interface corresponding to the second chiplet connected to the fifth chiplet in the one or more inter-chiplet interconnection interfaces of the first chiplet; The processing module of the second chiplet connected to the fifth chiplet is further configured, when determining that the first trial test information is trial test information for trial testing the fourth chiplet, to send the first trial test information to an inter-chiplet interconnection interface of the second chiplet corresponding to the fifth chiplet, so as to send the first trial test information to the fifth chiplet; the fifth chiplet further includes a selection module and a processing module; the selection module of the fifth chiplet is connected to the inter-chiplet interconnection interface of the fifth chiplet, and is configured to receive first trial test information from the second chiplet and send the first trial test information to the processing module of the fifth chiplet; The processing module of the fifth chiplet is connected to the selection module of the fifth chiplet and the inter-chiplet interconnection interface of the fifth chiplet, and is configured to transfer the first trial test information within the fifth chiplet for trial testing the fifth chiplet when it is determined that the first trial test information is trial test information for trial testing the fifth chiplet, and to send the first trial test information to the inter-chiplet interconnection interface connected to the fourth chiplet when it is determined that the first trial test information is for trial testing the fourth chiplet, so as to send the first trial test information to the fourth chiplet for trial testing the fourth chiplet. The chip of claim 7.

12. The processing module of the first chiplet is configured, when determining that the first trial test information is trial test information for trial testing a second chiplet in the one or more second chiplets, to determine an inter-chiplet interconnection interface corresponding to the second chiplet in the one or more inter-chiplet interconnection interfaces of the first chiplet based on the configuration information, and send the first trial test information to the inter-chiplet interconnection interface corresponding to the second chiplet in the one or more inter-chiplet interconnection interfaces of the first chiplet, where the configuration information includes connection relationship information between the first chiplet and the one or more second chiplets and / or information generated based on the connection relationship information. The chip of claim 7.

13. A chip trial test method for trial testing the chip according to claim 7, comprising: receiving first trial test information from an external trial test device via an external interface located on a first chiplet of the chip; receiving first trial test information from the external interface via a selection module of a first chiplet, and sending the first trial test information to a processing module of the first chiplet; the first trial test information is executed via a processing module of the first chiplet, and when it is determined that the first trial test information is trial test information for trial testing the first chiplet, the first trial test information is transferred within the first chiplet to trial test the first chiplet; and when it is determined that the first trial test information is trial test information for trial testing a second chiplet in the one or more second chiplets, the first trial test information is transferred to the one or more inter-chiplet interconnection interfaces of the first chiplet corresponding to the second chiplet, so as to transmit the first trial test information for trial testing the second chiplet to the second chiplet; receiving first trial test information from the first chiplet via a selection module of each second chiplet, and sending the first trial test information to a processing module of the second chiplet; and transmitting the first trial test information within the second chiplet for trial testing when the first trial test information is determined to be trial test information for trial testing the second chiplet, the first trial test information being executed via the processing module of each second chiplet. Chip trial test method.

14. receiving the first trial test information received from the external interface via a conversion module of the first chiplet, converting the first trial test information into a format suitable for transmission via a bus, and transmitting the converted first trial test information to a selection module of the first chiplet via the bus; The method of claim 13.

15. a step of executing the first trial test information through a processing module of the first chiplet, and when determining that the first trial test information is trial test information for trial testing a third chiplet, sending the first trial test information to an inter-chiplet interconnection interface corresponding to a second chiplet connected to the third chiplet in the one or more inter-chiplet interconnection interfaces of the first chiplet; The method further includes: executing the first trial test information through a processing module of a second chiplet connected to a third chiplet; and, when it is determined that the first trial test information is trial test information for trial testing the third chiplet, transmitting the first trial test information to an inter-chiplet interconnection interface of the second chiplet corresponding to the third chiplet, so as to transmit the first trial test information for trial testing the third chiplet to the third chiplet. The method of claim 13.

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