Analytical method and apparatus for evaluating electrical properties of vertical sidewalls in three-dimensional semiconductor gate stack structures

Abstract

The present disclosure relates to an analytical method and apparatus for evaluating electrical characteristics of vertical sidewalls in a semiconductor gate stack structure having a three-dimensional structure. [Solution] A plurality of three-dimensional semiconductor gate stack structures are provided, each having a different area and each including the same vertical sidewall within its area, and the electrical characteristics of each of the three-dimensional semiconductor gate stack structures are measured, and the electrical characteristics of the vertical sidewalls are detected by extrapolation from the relationship between the area and the electrical characteristics.

Description

[Technical Field]

[0001] This disclosure relates to a general technique for analyzing electrical characteristics of memory devices, and more particularly to an analysis method and apparatus for evaluating electrical characteristics of vertical sidewalls in a three-dimensional semiconductor gate stack structure. This patent was supported by the Ministry of Science and ICT under grant RS-2023-00280841 from the Korea Research Foundation. [Background technology]

[0002] In the 3D gate stack structure of semiconductor devices, various physical structures such as vertical sidewalls, flat areas, and corners have a complex effect on the electrical characteristics. As semiconductor devices become smaller, the effect of vertical sidewalls increases, but it is difficult to measure these effects individually. Summary of the Invention [Problem to be solved by the invention]

[0003] This disclosure proposes a technique for analyzing the electrical characteristics of the entire area of ​​a 3D semiconductor gate stack and isolating only the vertical sidewall characteristics through extrapolation, which allows accurate understanding of the vertical sidewall characteristics and allows for optimization of the gate dielectric and structure to improve device performance and reliability. [Means for solving the problem]

[0004] The present disclosure provides analytical methods and apparatus for evaluating the electrical properties of vertical sidewalls in three-dimensional semiconductor gate stack structures.

[0005] In the present disclosure, a method for operating a computing device may include providing a plurality of three-dimensional semiconductor gate stack structures each having a different area and each including identical vertical sidewalls within the area, measuring electrical characteristics of each of the three-dimensional semiconductor gate stack structures, and detecting the electrical characteristics of the vertical sidewalls from the relationship between the area and the electrical characteristics by extrapolation.

[0006] In the present disclosure, a computing device may include a memory and a processor connected to the memory and configured to execute at least one instruction word stored in the memory, wherein the processor may be configured to provide a plurality of three-dimensional semiconductor gate stack structures each having a different area and each including identical vertical sidewalls within the area, measure electrical characteristics of the three-dimensional semiconductor gate stack structures, and detect the electrical characteristics of the vertical sidewalls from the relationship between the area and the electrical characteristics by extrapolation. [Effects of the Invention]

[0007] According to the present disclosure, it is possible to precisely detect only the electrical characteristics of the vertical sidewalls of a small 3D semiconductor gate stack structure. Therefore, the electrical characteristics of the vertical sidewalls can be utilized to optimize semiconductor devices implemented as the 3D semiconductor gate stack structure. Specifically, it is possible to accurately grasp the changes in leakage current and effective oxide thickness (EOT) at the vertical sidewalls, thereby deriving an optimal gate insulating film with stable electrical characteristics. This allows for the provision of a semiconductor device with an improved capacitive effective thickness (CET), thereby improving the overall performance and reliability of the semiconductor device. [Brief explanation of the drawings]

[0008] [Figure 1] 1A-1D are cross-sectional views of three-dimensional semiconductor gate stacks to which various embodiments may be applied. [Figure 2] FIG. 1 is a schematic diagram of a computing device according to various embodiments. [Figure 3] 3 is a diagram for illustratively explaining the operating characteristics of the processor in FIG. 2. FIG. [Figure 4] FIG. 1 illustrates a schematic diagram of a method of operation of a computing device in accordance with various embodiments. [Figure 5] 5A and 5B show in detail the steps of detecting the electrical properties of the vertical sidewalls of FIG. 4. [Figure 6]5 is a diagram for illustratively explaining the step of detecting electrical characteristics of the vertical sidewall of FIG. 4. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0009] In the following, the present disclosure provides analytical methods and apparatus for evaluating electrical properties for vertical sidewalls in three-dimensional semiconductor gate stack structures.

[0010] Various embodiments of the present disclosure will now be described with reference to the accompanying drawings.

[0011] FIG. 1 is a cross-sectional view of a three-dimensional semiconductor gate stack to which various embodiments may be applied.

[0012] Referring to FIG. 1 , the three-dimensional semiconductor gate stack structure may include a substrate, a channel, a gate insulating film, and a gate metal, which may be realized as a stacked structure. In some embodiments, although not shown, additional components may be stacked between two of the substrate, channel, gate insulating film, or gate metal. For example, the three-dimensional semiconductor gate stack structure may include a FinFET as shown in FIG. 1( a) or a nano-sheet FET as shown in FIG. 1( b). Such a three-dimensional semiconductor gate stack structure may have vertical sidewalls. The vertical sidewall indicates the lateral surface of the three-dimensional semiconductor gate stack structure and may refer to a region that extends vertically from the channel to the gate metal.

[0013] Here, three directions may be defined for the three-dimensional semiconductor gate stack structure: a first direction (x-direction), a second direction (y-direction), and a third direction (z-direction). The first direction may define the length and vertical sidewalls of the three-dimensional semiconductor gate stack structure, particularly the thickness of the oxide layer on the vertical sidewall, e.g., from the channel to the gate metal. That is, the first direction may correspond to the horizontal stacking direction of the three-dimensional semiconductor gate stack structure, in other words, the stacking direction of the oxide layer on the vertical sidewall. The second direction may define the width of the three-dimensional semiconductor gate stack structure. The third direction may define the height of the three-dimensional semiconductor gate stack structure. That is, the third direction may correspond to the vertical stacking direction of the three-dimensional semiconductor gate stack structure.

[0014] Figure 2 is a schematic diagram of a computing device 200 according to various embodiments. Figure 3 is a diagram illustrating exemplary operational characteristics of a processor 270 of Figure 2, where different areas of a three-dimensional semiconductor gate stack are shown.

[0015] 2 , computing device 200 is for evaluating electrical properties for vertical sidewalls in a three-dimensional semiconductor gate stack structure and may include at least one of a camera module 210, a communication module 220, an input module 230, an output module 240, a measurement module 250, a memory 260, or a processor 270. In some embodiments, at least one of the components of computing device 200 (e.g., camera module 210, communication module 220) may be omitted, and at least one other component may be added. In some embodiments, at least two of the components of computing device 200 may be implemented as a single integrated circuit. In some embodiments, the components of computing device 200 may be distributed across at least two devices, where these devices may be communicatively connected to each other.

[0016] The camera module 210 may capture images in the computing device 200. Here, the camera module 210 may be, but is not limited to, an RGB camera. For example, the camera module 210 may include at least one of a lens, an image sensor, an image signal processor, and a flash.

[0017] The communication module 220 may enable the computing device 200 to communicate with an external device (not shown). The communication module 220 may establish a communication channel between the computing device 200 and the external device and communicate with the external device via the communication channel. For example, the external device may include at least one of an electronic device, a base station, a server, or a satellite. The communication module 220 may include at least one of a wired communication module and a wireless communication module. For example, the wireless communication module may communicate with the external device via at least one of a telecommunications network and a short-range communication network.

[0018] The input module 230 may input instructions for use to at least one component of the computing device 200. The input module 230 may include at least one of an input unit configured for a user to directly input instructions or data to the computing device 200, or a sensor unit configured to sense the surrounding environment and generate data. For example, the input unit may include at least one of a microphone, a mouse, or a keyboard. In some embodiments, the input unit may include at least one of touch circuitry configured to detect a touch or a sensor circuit configured to measure the intensity of a force generated by a touch.

[0019] The output module 240 may output information outside the computing device 200. The output module 240 may include at least one of a display module that visually outputs information or an audio module that audibly outputs information. For example, the display module may include at least one of a display, a holographic device, or a projector. In one embodiment, the display module may be combined with at least one of the touch circuitry or sensor circuitry of the input module 230 and implemented as a touch screen. For example, the audio module may include at least one of a speaker or a receiver.

[0020] The measurement module 250 may perform measurements on the three-dimensional semiconductor gate structure. Specifically, the measurement module 250 may apply a voltage to a gate electrode of the three-dimensional semiconductor gate structure and measure at least one of current-voltage (IV) characteristics or capacitance-voltage (CV) characteristics.

[0021] Memory 260 may store various data used by at least one component of computing device 200. For example, memory 260 may include volatile and / or non-volatile memory. The data may include input or output data for a program or its associated instructions. The program may be stored in memory 260 as software and may include an operating system, middleware, or / and / or an application.

[0022] The processor 270 may execute programs in the memory 260 to control at least one component of the computing device 200. This allows the processor 270 to process data or perform calculations. In doing so, the processor 270 may execute instructions stored in the memory 260.

[0023] In various embodiments, the processor 270 may evaluate electrical characteristics for vertical sidewalls in a three-dimensional semiconductor gate stack. Specifically, the processor 270 may analyze the electrical characteristics of the entire area of ​​the three-dimensional semiconductor gate stack and isolate only the electrical characteristics of the vertical sidewalls by extrapolation. The area may be defined as a first direction and a second direction (e.g., x-direction and y-direction) (i.e., length x width). The vertical sidewall indicates the lateral surface of the three-dimensional semiconductor gate stack and refers to the region extending vertically from the channel to the gate metal. The vertical sidewall, particularly the thickness of the oxide layer on the vertical sidewall, may be defined in the first direction. Here, the electrical characteristics may include at least one of leakage current, capacitance, or dielectric constant.

[0024] More specifically, the processor 270 may measure changes in electrical characteristics of the three-dimensional semiconductor gate stack structure with a decrease in area, as shown in FIG. 2. In this manner, the processor 270 may extract electrical characteristics for the three-dimensional semiconductor gate stack structure when the area is zero by extrapolation, and detect electrical characteristics of the vertical sidewalls from the extracted electrical characteristics. The processor 270 may derive a slope indicating the relationship between the area and electrical characteristics of the three-dimensional semiconductor gate stack structure by extrapolation as shown in Equation (1) below, and detect the electrical characteristics of the vertical sidewalls from the intercept of the slope as shown in Equation (2) below.

[0025]

number

[0026]

number

[0027] where m is the slope, n is the number of data points, i.e., the number of areas or electrical properties, x is the area at each data point, y is the electrical property at each data point, and y0 may represent the electrical property of the vertical sidewall as the y-intercept of the slope.

[0028] Therefore, the electrical properties of vertical sidewalls can be utilized to optimize semiconductor devices realized with 3D semiconductor gate stacks, thereby improving the performance and reliability of the semiconductor devices.

[0029] FIG. 4 is a diagram that schematically illustrates how computing device 200 operates, in accordance with various embodiments.

[0030] Referring to FIG. 4 , first, in step 410, a plurality of three-dimensional semiconductor gate stack structures may be provided, each having a different area and each including identical vertical sidewalls within the area. The area may be defined as a direction (e.g., x-direction and y-direction) perpendicular to the stacking direction (e.g., z-direction) (i.e., height) of the three-dimensional semiconductor gate stack structure (i.e., length x width). The vertical sidewall is defined as the stacking direction (e.g., z-direction) (i.e., height) of the three-dimensional semiconductor gate stack structure, and may refer to a region extending vertically from the channel to the gate metal, indicating a lateral surface of the three-dimensional semiconductor gate stack structure. Here, a three-dimensional semiconductor gate stack structure having a relatively small area may be identical to a portion of a three-dimensional semiconductor gate stack structure having a relatively large area.

[0031] Next, in step 420, the computing device 200 may measure electrical characteristics of each of the three-dimensional semiconductor gate stack structures. Specifically, the processor 270 may measure the electrical characteristics of each of the three-dimensional semiconductor gate stack structures via the measurement module 250. Here, the electrical characteristics may include at least one of leakage current, capacitance, or dielectric constant. In one embodiment, for each of the three-dimensional semiconductor gate stack structures, with the source electrode and the drain electrode combined, the processor 270 may apply a voltage to the gate electrode and measure current-voltage (IV) characteristics, and based on this, measure the leakage current due to the voltage. In another embodiment, for each of the three-dimensional semiconductor gate stack structures, with the source electrode and the drain electrode combined, the processor 270 may apply a voltage to the gate electrode and measure capacitance-voltage (CV) characteristics, and based on this, measure the capacitance due to the voltage. In yet another embodiment, for each of the three-dimensional semiconductor gate stack structures, the processor 270 may derive the dielectric constant using the measured capacitance. At this time, the processor 270 may calculate the permittivity according to the following equation (3).

[0032]

number

[0033] where ε may represent the dielectric constant, C the capacitance, A the area, and t the thickness of the oxide layer on the vertical sidewalls.

[0034] Next, in step 430, the computing device 200 may use an extrapolation method to detect the electrical characteristics of the vertical sidewalls from the relationship between the area and the electrical characteristics of the three-dimensional semiconductor gate stack structure. Specifically, the processor 270 may use an extrapolation method to detect the electrical characteristics of the vertical sidewalls as the electrical characteristics when the area is zero from the relationship between the area and the electrical characteristics. Here, the electrical characteristics may include at least one of leakage current, capacitance, or dielectric constant. In one embodiment, the processor 270 may detect the leakage current of the vertical sidewalls from the relationship between the area and the leakage current of the three-dimensional semiconductor gate stack structure. In another embodiment, the processor 270 may detect the capacitance of the vertical sidewalls from the relationship between the area and the capacitance of the three-dimensional semiconductor gate stack structure. In yet another embodiment, the processor 270 may detect the dielectric constant of the vertical sidewalls from the relationship between the area and the dielectric constant of the three-dimensional semiconductor gate stack structure. This will be described in more detail with reference to FIG. 4.

[0035] Figure 5 is a diagram illustrating in detail the step of detecting the electrical characteristics of the vertical sidewalls (step 430) of Figure 4. Figure 6 is a diagram for illustratively explaining the step of detecting the electrical characteristics of the vertical sidewalls (step 430) of Figure 4.

[0036] 5 and 6 , first, in step 531, processor 270 may set the area and electrical characteristics of the three-dimensional semiconductor gate stack structure on the x-axis and y-axis, respectively. Specifically, processor 270 may set the area on the x-axis and the electrical characteristics on the y-axis. Next, in step 533, processor 270 may extract the electrical characteristics when the area is 0 using the y-intercept by extrapolation. Specifically, processor 270 may derive a slope indicating the relationship between the area and the electrical characteristics of the three-dimensional semiconductor gate stack structure using the same extrapolation method as in Equation (1) above, and detect the electrical characteristics of the vertical sidewalls using the intercept of the slope, i.e., the y-intercept, as in Equation (2) above. Next, in step 535, processor 270 may detect the electrical characteristics of the vertical sidewalls using the electrical characteristics when the area is 0. Here, FIG. 6 illustrates an example of detecting leakage current using electrical characteristics, but this is not limiting. That is, in the same manner as described with reference to FIG. 6, processor 270 may detect the capacitance or permittivity of the vertical sidewalls.

[0037] Therefore, the electrical properties of vertical sidewalls can be utilized to optimize semiconductor devices realized with 3D semiconductor gate stacks, thereby improving the performance and reliability of the semiconductor devices.

[0038] According to the present disclosure, it is possible to precisely detect the electrical characteristics of only the vertical sidewalls of a small 3D semiconductor gate stack structure. Therefore, the electrical characteristics of the vertical sidewalls can be utilized to optimize semiconductor devices implemented with the 3D semiconductor gate stack structure. Specifically, it is possible to accurately grasp the changes in leakage current and EOT at the vertical sidewalls, thereby deriving an optimal gate insulating film with stable electrical characteristics. This allows for the provision of semiconductor devices with improved CET, thereby improving the overall performance and reliability of the semiconductor devices.

[0039] In summary, the present disclosure provides analytical methods and apparatus for evaluating the electrical properties of vertical sidewalls in three-dimensional semiconductor gate stack structures.

[0040] In the present disclosure, a method of operating computing device 200 may include providing a plurality of three-dimensional semiconductor gate stack structures each having a different area and each including identical vertical sidewalls within the area (step 410), measuring electrical characteristics of each of the three-dimensional semiconductor gate stack structures (step 420), and detecting the electrical characteristics of the vertical sidewalls from the relationship between the area and the electrical characteristics by extrapolation (step 430).

[0041] In the present disclosure, a vertical sidewall refers to a lateral surface of a three-dimensional semiconductor gate stack structure and may refer to a region extending vertically from the channel to the gate metal within the three-dimensional semiconductor gate stack structure.

[0042] In the present disclosure, the electrical properties of the three-dimensional semiconductor gate stack and the electrical properties of the vertical sidewalls may include at least one of leakage current, capacitance, or dielectric constant.

[0043] In the present disclosure, the step of detecting the electrical characteristics of the vertical sidewall (step 430) may include steps of extracting the electrical characteristics when the area is 0 from the relationship between the area and the electrical characteristics by extrapolation (steps 531 and 533), and a step of detecting the electrical characteristics of the vertical sidewall using the electrical characteristics when the area is 0 (step 535).

[0044] In the present disclosure, the steps of extracting the electrical characteristic when the area is 0 (step 531 and step 533) may include the steps of setting the area on the x-axis and the electrical characteristic on the y-axis (step 531), and extracting the electrical characteristic when the area is 0 by the y-intercept (step 533).

[0045] In the present disclosure, the step of measuring the electrical properties of each of the three-dimensional semiconductor gate stack structures (step 420) may include at least one of measuring at least one of a leakage current or a capacitance for each of the three-dimensional semiconductor gate stack structures, or deriving a dielectric constant using the measured capacitance for each of the three-dimensional semiconductor gate stack structures.

[0046] In the present disclosure, the computing device 200 includes a memory 260 and a processor 270 connected to the memory 260 and configured to execute at least one instruction word stored in the memory 260, and the processor 270 may be configured to provide a plurality of three-dimensional semiconductor gate stack structures each having a different area and each including identical vertical sidewalls within the area, measure electrical characteristics of the three-dimensional semiconductor gate stack structures, and detect the electrical characteristics of the vertical sidewalls from the relationship between the area and the electrical characteristics by extrapolation.

[0047] In the present disclosure, a vertical sidewall refers to a lateral surface of a three-dimensional semiconductor gate stack structure and may refer to a region extending vertically from the channel to the gate metal within the three-dimensional semiconductor gate stack structure.

[0048] In the present disclosure, the electrical properties of the three-dimensional semiconductor gate stack and the electrical properties of the vertical sidewalls may include at least one of leakage current, capacitance, or dielectric constant.

[0049] In the present disclosure, the processor 270 may be configured to extract the electrical characteristics when the area is 0 from the relationship between the area and the electrical characteristics by extrapolation, and detect the electrical characteristics of the vertical sidewalls based on the electrical characteristics when the area is 0.

[0050] The above-described devices may be implemented using hardware components, software components, and / or a combination of hardware and software components. For example, the devices and components described in the embodiments may be implemented using one or more general-purpose or special-purpose computers, such as a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a programmable logic unit (PLU), a microprocessor, or various devices capable of executing and responding to instructions. The processing device may execute an operating system (OS) and one or more software applications running on the OS. The processing device may also access, record, manipulate, process, and generate data in response to the execution of the software. For ease of understanding, a single processing device may be described. However, those skilled in the art will recognize that a processing device may include multiple processing elements and / or multiple types of processing elements. For example, a processing device may include multiple processors or one processor and one controller. Other processing configurations, such as parallel processors, are also possible.

[0051] Software may include computer programs, codes, instructions, or a combination of one or more of these, which may configure a processing device to operate as desired or may independently or collectively instruct the processing device. The software and / or data may be embodied in any type of machine, component, physical device, computer storage medium, or device to be interpreted by the processing device or to provide instructions or data to the processing device. The software may be distributed and stored and executed in a distributed manner on computer systems connected by a network. The software and data may be stored on one or more computer-readable storage media.

[0052] The methods according to various embodiments may be implemented in the form of program instructions executable by various computer means and recorded on a computer-readable medium. In this case, the medium may continuously record the computer-executable program or may temporarily record the program for execution or download. The medium may be a variety of recording or storage means, including a single or multiple hardware components, and may be directly connected to a computer system or distributed over a network. Examples of media include magnetic media such as hard disks, floppy disks, and magnetic tapes; optical media such as CD-ROMs and DVDs; magneto-optical media such as floptical disks; and media configured to record program instructions, such as ROMs, RAMs, and flash memories. Other examples of media include recording media or storage media managed by app stores that distribute applications, or by websites or servers that provide or distribute various software.

[0053] The various embodiments described herein and the terminology used therein are not intended to limit the technology described herein to a particular embodiment, but should be understood to encompass various modifications, equivalents, and / or alternatives of the relevant embodiment. In connection with the description of the drawings, like reference numerals are used to refer to like elements. A singular expression may also include a plural expression unless the context clearly dictates otherwise. In this specification, expressions such as "A or B," "at least one of A and / or B," "A, B, or C," or "at least one of A, B, and / or C" may include all possible combinations of the listed items. Expressions such as "first," "second," "first," or "second" modify the corresponding element, regardless of order or importance, and are used merely to distinguish one element from other elements, not to limit the corresponding element. When a (e.g., first) component is described as being "(functionally or communicatively) coupled" or "connected" to another (e.g., second) component, such component may be directly coupled to such other component or may be coupled through another component (e.g., third component).

[0054] According to various embodiments, each of the components described above (e.g., modules or programs) may include one or more entities. According to various embodiments, one or more of the components or steps described above may be omitted, or one or more other components or steps may be added. Alternatively or additionally, multiple components (e.g., modules or programs) may be integrated into a single component. In this case, the integrated component may perform one or more functions of each of the multiple components in a manner that is the same as or similar to that performed by the corresponding component among the multiple components before integration. According to various embodiments, the steps performed by a module, program, or other component may be performed sequentially, in parallel, iteratively, or heuristically, and one or more of the steps may be performed in a different order, omitted, or one or more other steps may be added. [Explanation of symbols]

[0055] 200 Computing Devices 210 Camera Module 220 Communication Module 230 Input Module 240 Output Module 250 Measurement Modules 260 memory 270 processor

Claims

1. 1. A method of operating a computing device, comprising: providing a plurality of three-dimensional semiconductor gate stacks each having a different area and each including identical vertical sidewalls within said area; measuring electrical characteristics of each of the three-dimensional semiconductor gate stacks; detecting an electrical characteristic of the vertical sidewall from the relationship between the area and the electrical characteristic by extrapolation; Including, A method of operating a computing device.

2. The vertical sidewall indicates a lateral surface of the three-dimensional semiconductor gate stack structure and refers to a region extending vertically from the channel to the gate metal within the three-dimensional semiconductor gate stack structure.

10. A method of operating a computing device as claimed in claim 1.

3. the electrical characteristics of the three-dimensional semiconductor gate stack and the electrical characteristics of the vertical sidewalls include at least one of leakage current, capacitance, or dielectric constant.

10. A method of operating a computing device as claimed in claim 1.

4. The step of detecting the electrical characteristics of the vertical sidewalls includes: extracting, by the extrapolation method, the electrical characteristics when the area is 0 from the relationship between the area and the electrical characteristics; detecting the electrical characteristic of the vertical sidewall by the electrical characteristic when the area is zero; Including, 10. A method of operating a computing device as claimed in claim 1.

5. The step of extracting the electrical characteristics when the area is 0 includes: setting the area on the x-axis and the electrical property on the y-axis; extracting the electrical characteristic when the area is zero by a y-intercept; Including, 5. A method of operating a computing device as claimed in claim 4.

6. measuring the electrical characteristics of the three-dimensional semiconductor gate stack, measuring at least one of leakage current or capacitance for each of the three-dimensional semiconductor gate stacks; or deriving a dielectric constant using the measured capacitance for each of the three-dimensional semiconductor gate stacks. at least one of:

4. A method of operating a computing device as claimed in claim 3.

7. 1. A computing device comprising: Memory and a processor coupled to the memory and configured to execute at least one instruction stored in the memory; Including, The processor: providing a plurality of three-dimensional semiconductor gate stack structures each having a different area and each including identical vertical sidewalls within said area; measuring electrical characteristics of each of the three-dimensional semiconductor gate stacks; and detecting the electrical characteristics of the vertical sidewalls from the relationship between the area and the electrical characteristics by an extrapolation method. Computing equipment.

8. The vertical sidewall indicates a lateral surface of the three-dimensional semiconductor gate stack structure and refers to a region extending vertically from the channel to the gate metal within the three-dimensional semiconductor gate stack structure. The computing device of claim 7.

9. the electrical characteristics of the three-dimensional semiconductor gate stack and the electrical characteristics of the vertical sidewalls include at least one of leakage current, capacitance, or dielectric constant. The computing device of claim 7.

10. The processor: extracting, by the extrapolation method, electrical characteristics when the area is 0 from the relationship between the area and the electrical characteristics; configured to detect the electrical characteristic of the vertical sidewall by the electrical characteristic when the area is zero. The computing device of claim 7.

Images