Semiconductor Devices

Abstract

To provide a semiconductor device that suppresses self-turn-on.SOLUTION: A semiconductor device of this embodiment has a drain electrode, a source electrode, a semiconductor region disposed between the drain electrode and the source electrode, a gate electrode disposed in the semiconductor region via a first insulating film, a second insulating film disposed between the gate electrode and the source electrode and having a relative dielectric constant higher than that of the first insulating film.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] In MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), a phenomenon called self-turn-on is known, in which the device transitions from the off state to the on state unintentionally. Self-turn-on occurs when the voltage between the drain and source electrodes changes suddenly over time while the MOSFET is in the off state, causing the capacitance C between the gate and drain electrodes to increase. gd The capacitance C between the gate electrode and the source electrode gs This is because a voltage higher than the gate threshold voltage is induced when the

[0003] One way to suppress self-turn-on is to increase the gate resistance and slow down the switching speed of the MOSFET, but there are cases where changing the gate resistance is not desirable due to design constraints.

[0004] Another way to suppress self-turn-on is to use the capacitance C between the gate and source electrodes. gs However, it is possible to increase the capacitance C gs If the thickness of the interlayer insulating film between the gate electrode and the source electrode is reduced in order to increase the capacitance, the dielectric strength of the interlayer insulating film will decrease, which will result in a short circuit between the gate electrode and the source electrode. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-129226 [Patent Document 2] Patent No. 5612830 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-263095 Summary of the Invention [Problem to be solved by the invention]

[0006] SUMMARY OF THE INVENTION An embodiment of the present invention provides a semiconductor device capable of suppressing self-turn-on. [Means for solving the problem]

[0007] The semiconductor device according to this embodiment comprises a drain electrode, a source electrode, a semiconductor region disposed between the drain electrode and the source electrode, a gate electrode disposed in the semiconductor region via a first insulating film, and a second insulating film disposed between the gate electrode and the source electrode and having a higher dielectric constant than the first insulating film. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Figure 2A] 3A to 3C are cross-sectional views illustrating an example of some steps in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 2B] 2B is a cross-sectional view illustrating an example of a part of a process of the method for manufacturing the semiconductor device according to the first embodiment, following FIG. 2A. FIG. [Figure 2C] 2C is a cross-sectional view illustrating an example of a part of a process of the method for manufacturing the semiconductor device according to the first embodiment, following FIG. 2B. [Figure 2D] 2D is a cross-sectional view illustrating an example of a part of a process of the method for manufacturing the semiconductor device according to the first embodiment, following FIG. 2C. [Figure 2E] 2D, a cross-sectional view illustrating an example of a partial process of the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 2F] 2F is a cross-sectional view illustrating an example of a partial process of the method for manufacturing the semiconductor device according to the first embodiment, following FIG. 2E. [Figure 2G]2F is a cross-sectional view illustrating an example of a partial process of the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 3] FIG. 4 is a cross-sectional view showing another configuration example of the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a cross-sectional view of a semiconductor device according to a second embodiment. [Figure 5] FIG. 10 is a cross-sectional view showing another configuration example of the semiconductor device according to the second embodiment. [Figure 6] FIG. 10 is a cross-sectional view of a semiconductor device according to a third embodiment. [Figure 7] FIG. 10 is a cross-sectional view showing another configuration example of the semiconductor device according to the third embodiment. [Figure 8] FIG. 10 is a cross-sectional view showing a semiconductor device according to a fourth embodiment. [Figure 9] FIG. 10 is a cross-sectional view showing another configuration example of the semiconductor device according to the fourth embodiment. [Figure 10] FIG. 10 is a cross-sectional view showing a semiconductor device according to a fifth embodiment. [Figure 11] FIG. 10 is a cross-sectional view showing another configuration example of the semiconductor device according to the fifth embodiment. [Figure 12] FIG. 10 is a plan view illustrating a semiconductor device according to a sixth embodiment. [Figure 13] FIG. 13 is a plan view illustrating another configuration example of the semiconductor device according to the sixth embodiment. [Figure 14] FIG. 13 is a plan view showing a semiconductor device according to a seventh embodiment. [Figure 15] FIG. 13 is a plan view showing another configuration example of the semiconductor device according to the seventh embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The embodiments do not limit the present invention. The drawings are schematic or conceptual, and the proportions of each part are not necessarily the same as those in reality. In the specification and drawings, elements similar to those described above with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0010] For convenience of explanation, an XYZ Cartesian coordinate system is used as shown in the drawings. The Z-axis direction is the stacking direction (thickness direction) of the semiconductor device. In addition, in the Z direction, the source region 21 side is also referred to as "upper" and the drain electrode 7 side is also referred to as "lower." However, these expressions are for convenience and are unrelated to the direction of gravity.

[0011] In the following description, n is used to indicate the relative level of impurity concentration in each conductivity type. + , n, n - , and p + , p, p - The notation n is sometimes used. + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than that of p. In the configuration of the semiconductor device described below, the n-type and p-type may be reversed.

[0012] (First embodiment) A semiconductor device 1 according to a first embodiment will be described with reference to Fig. 1. In this embodiment, the semiconductor device 1 is a vertical MOSFET having a trench gate.

[0013] Fig. 1 is a cross-sectional view of a semiconductor device 1 according to the first embodiment. As shown in Fig. 1, the semiconductor device 1 includes a semiconductor region 2, an insulating film 3, a gate electrode 4, an insulating film 5, a source electrode 6, a drain electrode 7, and an insulating film 8. Each element will be described in detail below with reference to Fig. 1.

[0014] The semiconductor region 2 includes a source region 21, a base region 22, a drift region 23, and a drain region 24. The semiconductor region 2 is disposed on the drain electrode 7. For convenience of explanation, the surface of the semiconductor region 2 will be referred to as a substantially flat surface, and the upper surface will be referred to as a main surface 2s. Note that this does not limit the shape of the semiconductor region 2.

[0015] The source region 21 is a semiconductor region that functions as a source of the MOSFET. As shown in FIG. 1, the source region 21 is disposed at the top of the semiconductor region 2. The source region 21 may be, for example, an n + It is a semiconductor area of ​​the shape.

[0016] The base region 22 is a semiconductor region that functions as the base of the MOSFET. The base region 22 is disposed between the drift region 23 and the source region 21. When a voltage is applied to the gate electrode 4, the base region 22 forms a channel, allowing carriers to flow between the drift region 23 and the source region 21. The base region 22 is, for example, a p-type semiconductor region.

[0017] The drift region 23 is a semiconductor region that functions as a drift of the MOSFET. - It is a semiconductor area of ​​the shape.

[0018] The drain region 24 is a semiconductor region that functions as the drain of the MOSFET. The drain region 24 is disposed between the drain electrode 7 and the drift region 23. The drain region 24 is, for example, an n + It is a semiconductor area of ​​the shape.

[0019] The semiconductor region 2 may include semiconductor regions having functions other than those of the above regions 21 to 24.

[0020] The semiconductor region 2 may be an epitaxial layer, or may be at least a part of a semiconductor substrate, or may be composed of an epitaxial layer and a semiconductor substrate.

[0021] The semiconductor region 2 is made of, for example, silicon (Si), but may also be made of a compound semiconductor such as SiC or GaN. When silicon (Si) is used as the semiconductor material, arsenic (As), phosphorus (P), or antimony (Sb) is used as the n-type impurity. When silicon (Si) is used as the semiconductor material, boron (B) is used as the p-type impurity.

[0022] The insulating film 3 electrically insulates the gate electrode 4 from the semiconductor region 2. The insulating film 3 is made of an insulating material (hereinafter referred to as a "first insulating material") such as silicon oxide (SiO2).

[0023] The insulating film 3 is disposed, for example, on the inner wall of the trench T. The trench T is a trench provided so as to extend from the main surface 2s to the drift region 23. As shown in FIG. 1, the insulating film 3 provided on the inner wall of the trench T is provided so as to contact the source region 21, the base region 22, and the drift region 23. The trench T has a virtual opening surface s formed by the opening of the trench T, which is substantially flush with the main surface 2s. The opening surface s is indicated by a dotted line in FIG. 1. An insulating film 5, which will be described later, is formed on this opening surface s. For convenience of explanation, it is assumed that the trench T is provided in the main surface 2s of the semiconductor region 2, but this does not limit the shape of the semiconductor region 2.

[0024] The gate electrode 4 is an electrode that functions as the gate electrode of the MOSFET. The gate electrode 4 is disposed in the insulating film 3. That is, the gate electrode 4 is disposed in the semiconductor region 2 via the insulating film 3. More specifically, the gate electrode 4 is adjacent to at least the base region 22 in the Y direction via the insulating film 3. The gate electrode 4 is made of, for example, polysilicon. In the following description, the upper surface of the gate electrode 4 is assumed to be covered with the insulating film 3 as shown in FIG. 1. Note that the upper surface of the gate electrode 4 may be exposed to the opening surface s.

[0025] The insulating film 5 is disposed between the gate electrode 4 and a source electrode 6, which will be described later. As shown in Fig. 1, the insulating film 5 is disposed on the opening surface s and on the semiconductor region 2 (main surface 2s). The insulating film 5 functions as an etching stopper in the manufacturing process of the semiconductor device 1, which will be described later, and therefore the insulating film 5 on the opening surface s is thinner than the insulating film 5 on the main surface 2s.

[0026] The insulating film 5 only needs to be disposed on at least the opening surface s of the trench T, and does not necessarily have to be disposed on the semiconductor region 2 (main surface 2s).

[0027] The dielectric constant of the insulating film 5 is higher than the dielectric constant of the insulating film 3. The insulating film 5 is made of an insulating material (hereinafter referred to as a "second insulating material") such as silicon nitride.

[0028] The source electrode 6 is disposed above the insulating film 5. The source electrode 6 is electrically connected to the source region 21 via a source contact (not shown).

[0029] 1, when the insulating film 3 is disposed on the gate electrode 4, the insulating film 3 and the insulating film 5 insulate the gate electrode 4 from the source electrode 6. When the insulating film 3 is not disposed on the gate electrode 4 (that is, when the gate electrode 4 is exposed to the opening surface s of the trench T), the insulating film 5 insulates the gate electrode 4 from the source electrode 6.

[0030] The source electrode 6 is made of a metal such as titanium (Ti), tungsten (W), or aluminum (Al).

[0031] The drain electrode 7 is an electrode that functions as a drain electrode of the MOSFET. The drain electrode 7 is disposed below the semiconductor region 2. The drain electrode 7 is electrically connected to the drain region 24. The drain electrode 7 is made of a metal such as titanium, tungsten, or aluminum.

[0032] The insulating film 8 is disposed on the insulating film 5. The insulating film 8 has an opening OP at the bottom thereof, through which the insulating film 3 is exposed. As shown in FIG. 1, the source electrode 6 is disposed not only on the insulating film 8 but also in the opening OP.

[0033] The insulating film 8 is made of an insulating material (hereinafter referred to as a "third insulating material") such as silicon oxide.

[0034] The effects of the semiconductor device 1 according to this embodiment will be described. A gate-source capacitance C gs The insulating film 5 disposed between the gate electrode 4 and the source electrode 6 has a higher dielectric constant than the insulating film 3. Therefore, the capacitance C gs can be made larger.

[0035] In this manner, in this embodiment, by disposing the insulating film 5 having a higher dielectric constant than the insulating film 3 between the gate electrode 4 and the source electrode 6, the gate-source capacitance C gs In other words, the semiconductor device 1 can increase the ratio C gd / C gs As a result, the semiconductor device 1 can suppress self-turn-on.

[0036] In this embodiment, the gate-source capacitance C gs In order to increase the capacitance C , it is not necessary to reduce the distance between the gate electrode 4 and the source electrode 6. In other words, by disposing the insulating film 5 having a relatively high relative dielectric constant between the gate electrode 4 and the source electrode 6, the semiconductor device 1 can reduce the gate-source capacitance C while maintaining the insulating film thickness that realizes a predetermined dielectric strength. gs Therefore, the semiconductor device 1 can suppress self-turn-on while ensuring the dielectric strength between the gate and source.

[0037] Therefore, according to the first embodiment, the semiconductor device 1 can suppress self-turn-on without increasing the gate resistance while ensuring the dielectric strength between the gate and source. Furthermore, the semiconductor device 1 can suppress self-turn-on even when the gate resistance is reduced for the purpose of increasing the switching speed, etc.

[0038] <Method of Manufacturing Semiconductor Device 1> 2A to 2G, an example of a method for manufacturing the semiconductor device 1 will be described. 2A to 2G are cross-sectional views illustrating the steps of the method for manufacturing the semiconductor device 1.

[0039] First, as shown in Fig. 2A, a semiconductor region 2 having a principal surface 2s is prepared. The semiconductor region 2 includes a source region 21, a base region 22, a drift region 23, and a drain region 24. A trench T is provided in the semiconductor region 2, extending from the principal surface 2s to the drift region 23, and an insulating film 3 is disposed on the inner wall of the trench T. A gate electrode 4 is disposed in the insulating film 3.

[0040] 2B, a second insulating material is deposited on the insulating film 3 and the semiconductor region 2 (source region 21) by, for example, a CVD method. The second insulating material has a higher relative dielectric constant than the first insulating material constituting the insulating film 3. As a result, an insulating film 5 is formed.

[0041] 2C, a third insulating material is deposited on the insulating film 5 by, for example, a CVD method, thereby forming an insulating film 8.

[0042] Next, as shown in FIG. 2D, a photoresist R is applied onto the insulating film 8, and is selectively exposed and developed to form a photoresist mask on the insulating film 8.

[0043] Next, as shown in FIG. 2E, etching is performed by, for example, RIE (Reactive Ion Etching) or the like to remove the portion of the insulating film 8 that is not masked by the photoresist. As a result, an opening OP is formed in the insulating film 8. During this etching, the insulating film 5 acts as an etching stopper, preventing unintended etching of the insulating film 3. Furthermore, the final film thickness of the insulating film 5 is determined by this etching. In other words, the capacitance C gs The RIE speed for silicon nitride is slower than that for silicon oxide, so the thickness of the insulating film 5 can be easily controlled. gs This can suppress variations in the

[0044] Next, as shown in FIG. 2F, the photoresist R is stripped using, for example, a developer.

[0045] 2G, a metal is deposited on the insulating film 5 exposed in the opening OP and on the insulating film 8 by, for example, sputtering to form a source electrode 6. Thereafter, a metal is also deposited on the underside of the semiconductor region 2 to form a drain electrode 7. The drain electrode 7 may be formed in the step of forming the source electrode.

[0046] Through the above steps, the semiconductor device 1 according to the first embodiment is manufactured.

[0047] As described above, in the step of etching the insulating film 8, the insulating film 5 serves as an etching stopper. This prevents the insulating film 3 from being unintentionally etched. In addition, since the RIE speed for the insulating film 5 is relatively slow, the gate-source capacitance C gs Easily adjust the capacitance C gs As a result, the yield of the semiconductor device 1 can be improved.

[0048] The above description is merely one example of a manufacturing method. For example, the insulating film 8 does not need to be formed. In this case, the opening OP is not formed, and therefore the steps of forming and removing the photoresist R are not necessary. Also, the insulating film 5 does not need to be formed on the main surface 2s. In other words, the insulating film 5 may be formed only on the insulating film 3.

[0049] (Modification of the first embodiment) Next, a modification of the first embodiment will be described with reference to Fig. 3. As shown in Fig. 3, in this modification, the semiconductor device 1 further includes an insulating film 8a.

[0050] As shown in FIG. 3, the insulating film 8a is partially disposed on the insulating film 5 exposed in the opening of the insulating film 3. The insulating film 8a is made of an insulating material (third insulating material) such as silicon oxide. The insulating film 8a may be formed in the same process as the insulating film 8. That is, the insulating film 8 may be formed by forming the insulating film 8 on the insulating film 5, and then etching the insulating film 8 to form two openings OP on the left and right, thereby forming the insulating film 8a.

[0051] The insulating film 8a increases the distance between the gate electrode 4 and the source electrode 6 at the location where the insulating film 8a is disposed, thereby reducing the capacitance C gs By adjusting the width of the insulating film 8a (the length in the Y-axis direction), the capacitance C gs In other words, the width of the insulating film 8a can be adjusted to gs It is determined based on the design value.

[0052] According to this modification, the capacitance C gs can be easily adjusted.

[0053] (Second embodiment) Next, a second embodiment will be described with reference to Fig. 4. Fig. 4 is a cross-sectional view of a semiconductor device 1A according to the second embodiment. In Fig. 4, elements with the same names or functions as those in the drawings described in the previous embodiments are given the same reference numerals. Hereinafter, explanations will be omitted except for changes or additions.

[0054] One of the differences between the second embodiment and the first embodiment is the configuration of the electrodes arranged in the insulating film 3. As shown in FIG. 4, the semiconductor device 1A according to the second embodiment further includes a field plate (FP) electrode 9 in addition to the gate electrode 4 in the insulating film 3.

[0055] The FP electrode 9 is arranged to reduce the concentration of a reverse electric field between the gate electrode 4 and the drain electrode 7 and increase the breakdown voltage. The FP electrode 9 is arranged in the insulating film 3 so as to be located lower than the gate electrode 4. That is, the FP electrode 9 is spaced apart from the gate electrode 4 and is arranged in the semiconductor region 2 via the insulating film 3 at a position farther from the opening surface s of the trench T than the gate electrode 4. The FP electrode 9 is made of, for example, polysilicon.

[0056] The FP electrode 9 and the gate electrode 4 are electrically insulated from the semiconductor region 2 by the insulating film 3 .

[0057] The FP electrode 9 is electrically connected to the source electrode 6 via a source contact (not shown). Therefore, a gate-source capacitance C gs Therefore, according to the second embodiment, the capacitance C gs The capacitance C gs This allows for greater freedom in adjusting the

[0058] As described above, in the second embodiment, by disposing the insulating film 5 having a relatively high dielectric constant between the gate electrode 4 and the source electrode 6, it is possible to suppress self-turn-on without increasing the gate resistance while ensuring the dielectric strength between the gate and source, as in the first embodiment.

[0059] Furthermore, in the second embodiment, the FP electrode 9 is disposed in the insulating film 3, so that the capacitance C gs Therefore, the thickness of the insulating film between the gate electrode 4 and the source electrode 6 can be increased, and the withstand voltage of the semiconductor device 1A can be improved.

[0060] (Modification of the second embodiment) Next, a modification of the second embodiment will be described with reference to Fig. 5. As shown in Fig. 5, in this modification, similar to the modification of the first embodiment, the semiconductor device 1A further includes an insulating film 8a.

[0061] 5, the insulating film 8a is partially disposed on the insulating film 5 exposed in the opening of the insulating film 3. As in the modification of the first embodiment, by adjusting the width of the insulating film 8a, the capacitance C gs In other words, the width of the insulating film 8a can be adjusted to gs It is determined based on the design value.

[0062] According to this modification, the semiconductor device 1A is provided with the insulating film 8a, and therefore the capacitance C gs can be easily adjusted.

[0063] (Third embodiment) Next, a third embodiment will be described with reference to Fig. 6. Fig. 6 is a cross-sectional view of a semiconductor device 1B according to the third embodiment. Elements with the same names or functions as those in the drawings described in the previous embodiments are given the same reference numerals. Hereinafter, explanations will be omitted except for changes or additions.

[0064] One difference between the third embodiment and the previously described embodiments is the configuration of the gate electrode. As shown in FIG. 6, the semiconductor device 1B according to the third embodiment includes two electrodes (gate electrode portion 4a and gate electrode portion 4b) arranged opposite each other as a gate electrode. In FIG. 6, the gate electrode portion 4a and gate electrode portion 4b extend apart from each other along the direction in which the insulating film 3 extends (the X-axis direction). Hereinafter, a structure including the gate electrode portion 4a and gate electrode portion 4b as a gate electrode will be referred to as a separate gate structure. The separate gate structure facilitates adjustment of the width of the gate electrode (the length in the Y-axis direction), thereby facilitating adjustment of the gate capacitance and gate resistance. The gate electrode portion 4a and gate electrode portion 4b are examples of the first gate electrode portion and second gate electrode portion, respectively, in the claims.

[0065] Although not shown, the separate gate structure of this embodiment is also applicable to a case where the FP electrode 9 is not disposed.

[0066] In the third embodiment, similarly to the first embodiment, an insulating film 5 having a relatively high dielectric constant is disposed between the gate electrode 4 and the source electrode 6. This allows the semiconductor device 1B to suppress self-turn-on without increasing the gate resistance while ensuring the dielectric strength between the gate and source.

[0067] Furthermore, since the third embodiment employs a separate gate structure, the width of the gate electrode can be easily adjusted, and a semiconductor device having a desired gate width can be provided. That is, according to the third embodiment, a semiconductor device having a desired gate resistance and / or gate capacitance can be provided.

[0068] (Modification of the third embodiment) Next, a modification of the third embodiment will be described with reference to Fig. 7. As shown in Fig. 7, in this modification, the semiconductor device 1B further includes an insulating film 8a.

[0069] 7, the insulating film 8a is disposed on the insulating film 5 immediately above the insulating film 3 between the gate electrode portion 4a and the gate electrode portion 4b. Therefore, in the insulating film consisting of the insulating film 8 and the insulating film 8a, openings OP1 and OP2 are provided immediately above the gate electrode portion 4a and the gate electrode portion 4b, respectively.

[0070] In the separate gate structure, as shown in FIG. 6 described in the third embodiment, the capacitance C gs The capacitance C gs When designing, the capacitance C gs The influence of the ingredients must be considered.

[0071] In contrast to this, in this modification, the insulating film 8a increases the distance between the gate electrode portions 4a, 4b and the source electrode 6 in the diagonally above portions of the gate electrode portions 4a, 4b. Therefore, in the semiconductor device 1B, the capacitance C gs As a result, the semiconductor device 1B can reduce the capacitance C generated diagonally above the gate electrode portion 4a and the gate electrode portion 4b. gs Since the effect of capacitance C gs This makes it easier to design.

[0072] (Fourth embodiment) Next, a fourth embodiment will be described with reference to Fig. 8. Fig. 8 is a cross-sectional view of a semiconductor device 1C according to the fourth embodiment. Elements with the same names or functions as those in the drawings described in the previous embodiments are given the same reference numerals. Hereinafter, explanations will be omitted except for changes or additions.

[0073] One difference between the fourth embodiment and the previously described embodiments is that the gate-source capacitance C gs In the above-described embodiment, the insulating film 5 is disposed between the gate electrode 4 and the source electrode 6, thereby increasing the gate-source capacitance C gs In this embodiment, the capacitance Cgs We will explain a method to increase this.

[0074] The fourth embodiment employs a separate gate structure, similar to the third embodiment. As shown in Fig. 8, the source electrode 6 includes an inter-gate electrode portion 6a disposed between the gate electrode portion 4a and the gate electrode portion 4b. The insulating film 3 is disposed to insulate the source electrode 6 from the gate electrode portion 4a and the source electrode from the gate electrode portion 4b.

[0075] 8, the semiconductor device 1C may include an insulating film 8 that is disposed on the semiconductor region 2 (main surface 2s) and has an opening OP provided at a position corresponding to the upper side of the insulating film 3. The source electrode 6 is disposed not only on the insulating film 8 but also in the opening OP of the insulating film 8. In the opening OP of the insulating film 8, the insulating film 3 is not exposed as shown in FIG. 8. The insulating film 3 may be exposed in the opening OP. The insulating film 8 may be made of the same insulating material (first insulating material) as the insulating film 3, or may be integrated with the insulating film 3. In this case, the insulating film 8 may be formed in the same process as the insulating film 3.

[0076] In this embodiment, in the separate gate structure, the source electrode 6 includes an inter-gate electrode portion 6a disposed between the gate electrode portion 4a and the gate electrode portion 4b. Therefore, the semiconductor device 1C has a gate-source capacitance C gs As a result, the semiconductor device 1C can reduce the capacitance C gs can be made larger.

[0077] Therefore, the semiconductor device 1C can reduce the capacitance C gs can be made larger.

[0078] As described above, in the separate gate structure, by disposing the inter-gate electrode portion 6a of the source electrode 6 between the gate electrode portion 4a and the gate electrode portion 4b, the semiconductor device 1C can reduce the gate-source capacitance C gs Therefore, according to the fourth embodiment, it is possible to suppress self-turn-on without using the insulating film 5, while ensuring the dielectric strength between the gate and the source, and without increasing the gate resistance.

[0079] Furthermore, according to the fourth embodiment, there is no need to form the insulating film 5, and therefore the manufacturing process of the semiconductor device can be simplified.

[0080] (Modification of the fourth embodiment) Next, a modification of the fourth embodiment will be described with reference to Fig. 9. As shown in Fig. 9, in this modification, the semiconductor device 1C further includes an FP electrode 9, similar to the second embodiment.

[0081] 9, the FP electrode 9 is disposed in the insulating film 3 so as to be located below the gate electrode portion 4a and the gate electrode portion 4b. This allows the semiconductor device 1C to have a larger insulating film thickness between the gate electrode portion 4a and the source electrode 6 and between the gate electrode portion 4b and the source electrode 6, thereby improving the dielectric strength of the semiconductor device 1C.

[0082] (Fifth embodiment) Next, a fifth embodiment will be described with reference to FIG. 10. FIG. 10 is a cross-sectional view of a semiconductor device 1D according to the fifth embodiment. Elements with the same names or functions as those in the drawings described in the previous embodiments are given the same reference numerals. Hereinafter, explanations will be omitted except for changes or additions. Note that the PP line and QQ line shown in FIG. 10 are used for explaining the embodiments described later, and will not be explained in this embodiment.

[0083] In the fourth embodiment, the inter-gate electrode portion 6a of the source electrode 6 is disposed between the gate electrode portion 4a and the gate electrode portion 4b, thereby reducing the capacitance C gs In the fifth embodiment, the capacitance C gs Make it bigger.

[0084] 10, in the fifth embodiment, the source electrode 6 includes an inter-gate electrode portion 6a disposed between the gate electrode portion 4a and the gate electrode portion 4b. The insulating film 5 is disposed between the gate electrode portion 4a and the inter-gate electrode portion 6a and between the gate electrode portion 4b and the inter-gate electrode portion 6a. The insulating film 5 is also disposed on the bottom surface of the opening OP. The insulating film 3 does not necessarily have to be disposed between the gate electrode portion 4a and the inter-gate electrode portion 6a and between the gate electrode portion 4b and the inter-gate electrode portion 6a.

[0085] In this way, in the separate gate structure, the inter-gate electrode portion 6a of the source electrode 6 is disposed between the gate electrode portion 4a and the gate electrode portion 4b, and further, the insulating film 5 is disposed between the gate electrode portions 4a, 4b and the inter-gate electrode portion 6a. As a result, according to the fifth embodiment, the gate-source capacitance C gs can be made larger.

[0086] (Modification of the fifth embodiment) A modification of the fifth embodiment will be described with reference to Fig. 11. As shown in Fig. 11, a semiconductor device 1D according to this modification further includes an FP electrode 9, similar to the modification of the fourth embodiment.

[0087] 11, the FP electrode 9 is disposed in the insulating film 3 so as to be located below the gate electrode 4. By disposing the FP electrode 9, the thickness of the insulating film between the gate electrode portion 4a and the source electrode 6 and between the gate electrode portion 4b and the source electrode 6 can be increased, and the semiconductor device 1D can improve its dielectric strength voltage.

[0088] (Sixth embodiment) Next, a sixth embodiment will be described with reference to FIGS. 12 and 13. FIGS. 12 and 13 are plan views of a semiconductor device 1E according to the sixth embodiment. Elements with the same names or functions as those in the drawings described in the previous embodiments are given the same reference numerals. Hereinafter, explanations will be omitted except for changes or additions. FIGS. 12 and 13 are views showing a cross section (horizontal cross section) passing through an insulating film 8 and parallel to the XY plane, for example, a cross section taken along line PP shown in FIG. 10.

[0089] As described above, the capacitance C gs In the sixth embodiment, the capacitance C is adjusted by devising the planar layout of the source electrode 6. gs A method for adjusting the above will be described.

[0090] 12, in the semiconductor device 1E according to this embodiment, a plurality of openings are partially provided in the insulating film 8 along the direction in which the insulating film 3 (trench T, gate electrode 4) extends (longitudinal direction; X-axis direction), and a source electrode 6 is disposed in each opening. That is, a plurality of source electrodes 6 are partially disposed along the longitudinal direction of the insulating film 3. In other words, in this embodiment, in a horizontal cross section passing through the insulating film 8, portions where the source electrodes 6 are disposed and portions where the insulating film 8 are disposed alternate along the longitudinal direction.

[0091] 13, the openings in the insulating film 8 may be partially provided along the width direction of the insulating film 3 (a direction perpendicular to the longitudinal direction; the Y-axis direction). In this case, a plurality of source electrodes 6 are partially arranged along the width direction. Furthermore, insulating films 8a are arranged between the source electrodes 6 partially arranged along the width direction of the trench T. When the openings in the insulating film 8 are partially provided along the width direction of the insulating film 3, the openings do not have to be provided along the longitudinal direction.

[0092] Furthermore, the semiconductor device 1E may employ a separate gate structure (gate electrode portions 4a and 4b).

[0093] As described above, in the sixth embodiment, the openings OP are partially provided along the longitudinal direction and / or width direction of the trench T, and the source electrode 6 is disposed in each opening OP, thereby reducing the capacitance C gs That is, in the portion where the source electrode 6 is arranged, the distance between the gate electrode 4 (gate electrode portions 4a and 4b) and the source electrode 6 is small, so that the capacitance C gs On the other hand, in the portion where the insulating film (insulating film 8, insulating film 8a) is arranged, the distance between the gate electrode 4 (gate electrode portions 4a, 4b) and the source electrode 6 increases, so that the capacitance C gs becomes smaller.

[0094] In the sixth embodiment, the capacitance C of the entire MOSFET can be reduced by adjusting the layout (arrangement density) of the source electrode 6 in the horizontal plane. gs In other words, the total area and arrangement density of the source electrodes 6 arranged in the openings OP (openings OP1 and OP2) can be adjusted to control the capacitance C gs 12 and 13, the layout on the right side has a higher density of source electrodes 6 than the layout on the left side, and therefore the capacitance C gs is large.

[0095] The shape of the source electrode 6 disposed in the opening OP (openings OP1, OP2) of the insulating film 8 is not limited to a rectangular shape, and may be any shape such as a circular shape or a polygonal shape.

[0096] (Seventh embodiment) Next, a seventh embodiment will be described with reference to FIGS. 14 and 15. FIGS. 14 and 15 are plan views showing a semiconductor device 1F according to the seventh embodiment. FIGS. 14 and 15 respectively show horizontal cross-sectional views (e.g., cross-sectional views taken along line QQ shown in FIG. 10) passing through the gate electrodes provided in the semiconductor devices described in the fourth and fifth embodiments. Elements with the same names or functions as those in the drawings described in the above embodiments are given the same reference numerals. Hereinafter, explanations will be omitted except for changes or additions.

[0097] In this embodiment, the inter-gate electrode portion 6a described in the fourth and fifth embodiments is partially provided along the extending direction of the insulating film 3 (trench T), thereby reducing the capacitance C gs Adjust.

[0098] 14, in a horizontal cross section passing through the gate electrode 4, the gate electrode 4 is provided with a plurality of through holes (three through holes in the figure) along the direction (X-axis direction) in which the insulating film 3 (gate electrode 4, trench T) extends. The source electrode 6 includes a plurality of inter-gate electrode portions 6a arranged in each through hole. The insulating film 3 is arranged between the gate electrode 4 and the plurality of inter-gate electrode portions 6a.

[0099] In this way, the semiconductor device 1F has a configuration in which the structure described in the fourth embodiment is partially arranged. That is, a plurality of inter-gate electrode portions 6a are partially provided along the direction in which the insulating film 3 (trench T) extends (X-axis direction). Also, as shown in FIG. 14, the gate electrode 4 is arranged between the plurality of inter-gate electrode portions 6a when viewed in the X-axis direction. As a result, the semiconductor device 1F has a capacitance C gs It is possible to increase the gate width of the entire semiconductor device 1F, that is, to adjust the gate resistance and gate capacitance.

[0100] As shown in FIG. 15, the semiconductor device 1F may further include an insulating film 5. The insulating film 5 is disposed between the gate electrode 4 and the plurality of inter-gate electrode portions 6a. In this case, the insulating film 3 may or may not be disposed between the gate electrode 4 and the inter-gate electrode portions 6a. In any case, by disposing the insulating film 5, the semiconductor device 1F can reduce the capacitance C gs can be made even larger.

[0101] Furthermore, in the semiconductor device 1F, gate electrode portions 4a and 4b may be provided as the gate electrode instead of the gate electrode 4.

[0102] Although the embodiments of the present invention have been described, these embodiments and examples are presented as examples and are not intended to limit the scope of the invention. These embodiments and examples can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and examples and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. [Explanation of symbols]

[0103] 1, 1A, 1B, 1C, 1D, 1E, 1F Semiconductor device 2. Semiconductor field 2s main surface s Opening surface 3. Insulating film 4 gate electrode 4a Gate electrode part 4b Gate electrode part 5. Insulating film 6 Source electrode 6a Inter-gate electrode 7. Drain electrode 8. Insulating film 9 FP electrode 21 Source Region 22 Base Area 23 Drift Region 24 Drain region OP, OP1, OP2 opening R Photoresist T-Trench

Claims

1. A drain electrode; A source electrode; a semiconductor region disposed between the drain electrode and the source electrode; a gate electrode disposed in the semiconductor region via a first insulating film; a second insulating film disposed between the gate electrode and the source electrode and having a higher dielectric constant than the first insulating film; A semiconductor device comprising: a third insulating film provided between the second insulating film and the source electrode, the third insulating film having an opening at its bottom surface through which the second insulating film is exposed; The opening is located between the gate electrode and the source electrode, and a portion of the source electrode is disposed within the opening.

2. 2. The semiconductor device according to claim 1, wherein said second insulating film is made of silicon nitride.

3. The semiconductor device according to claim 1 , further comprising a fourth insulating film partially disposed on the second insulating film located in the opening.

4. the gate electrode extends in a second direction perpendicular to a first direction from the drain electrode toward the source electrode; The semiconductor device according to claim 1 , wherein a plurality of the openings are provided in the second direction and a third direction perpendicular to the first direction and the second direction.

5. The semiconductor device according to claim 1 , further comprising a field plate electrode located between said gate electrode and said drain electrode and disposed in said first insulating film.

6. the gate electrode extends in a second direction perpendicular to a first direction from the drain electrode toward the source electrode; the gate electrode has a first gate electrode portion and a second gate electrode portion; the first gate electrode portion and the second gate electrode portion are spaced apart in a third direction perpendicular to the first direction and the second direction, 2. The semiconductor device according to claim 1, wherein a part of the first insulating film is provided between the first gate electrode portion and the second gate electrode portion.

7. a third insulating film provided between the second insulating film and the source electrode, the third insulating film having a plurality of openings at the bottom thereof through which the second insulating film is exposed; the openings are provided between the first gate electrode portion and the source electrode and between the second gate electrode portion and the source electrode, The semiconductor device according to claim 6 , wherein a portion of the source electrode is disposed within the opening.

8. the source electrode includes an inter-gate electrode portion disposed between the first gate electrode portion and the second gate electrode portion; The second insulating film is disposed between the first gate electrode portion and the inter-gate electrode portion, and between the second gate electrode portion and the inter-gate electrode portion. The semiconductor device according to claim 6.

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