Radio frequency interface transmitting and receiving apparatus and method, chip, base station and terminal

Abstract

The embodiments of the present disclosure relate to a transmitting device and a transmitting method for a radio frequency interface, a receiving device and a receiving method for a radio frequency interface, and a chip. [Solution] The radio frequency interface transmitter includes a transmission controller having a traffic data interleaving means, a delay adjustment amount determining means, and a framer means. The traffic data interleaving means is configured to serially interleave data of a plurality of data channels based on a current interleaving pattern to form interleaved data including one or more periods. The delay adjustment amount determining means is configured to determine a delay adjustment amount for each data channel corresponding to the current interleaving pattern. The framer means is configured to form a traffic frame based on the interleaved data, and the framer means is further configured to form a management frame.

Description

[Technical Field]

[0001] The present disclosure relates to the field of wireless communication technology, and in particular to a radio frequency interface transmitting device, a radio frequency interface transmitting method, a radio frequency interface receiving device, a radio frequency interface receiving method, a chip, a base station, and a terminal device. [Background technology]

[0002] Related art radio frequency (RF) interface devices, such as a JESD204B interface or a JESD204C interface, can solve transmission delay jitter and reduce transmission delay, but due to the basic characteristics of the transmission technology, such interface devices cannot automatically adapt to changes in transmission speed due to changes in traffic while ensuring that the transmission delay remains unchanged.

[0003] In addition, other RF interface devices, such as a DigRF V4 interface, can adaptively adjust the transmission bandwidth to accommodate changes in transmission speed due to traffic changes, but due to the basic characteristics of their transmission technology, such interface devices cannot reduce transmission delays or solve the problem of fixed transmission delays. Summary of the Invention [Problem to be solved by the invention]

[0004] The present disclosure provides an RF interface transmitting device, an RF interface transmitting method, an RF interface receiving device, an RF interface receiving method, a chip, a base station, and a terminal device. [Means for solving the problem]

[0005] In a first aspect, an embodiment of the present disclosure is a radio frequency RF interface transmitting device including a transmission controller having traffic data interleaving means, delay adjustment amount determining means, and framer means, wherein the traffic data interleaving means is configured to serially interleave data of a plurality of data channels based on a current interleaving pattern to form interleaved data including one or more periods, the data of each data channel including a plurality of unit data blocks, the interleaving pattern indicating the corresponding number of unit data blocks of each data channel included in one period of interleaved data and the arrangement order of the unit data blocks of the plurality of data channels within one period, the data of the plurality of data channels being serially interleaved in the one or more periods with the same interleaving pattern, and the delay adjustment amount determining means determines the delay adjustment amount of each data channel corresponding to the current interleaving pattern. and determining, when a position of a unit data block of one data channel among the plurality of data channels in the current interleaving pattern is offset by m unit data blocks along a first direction with respect to a position in a previous interleaving pattern, a historical delay adjustment amount corresponding to the previous interleaving pattern of the one data channel as a delay adjustment amount corresponding to the current interleaving pattern of the one data channel after offsetting by m unit data blocks in a direction opposite to the first direction, where m is an integer greater than or equal to 1; and the framer means is configured to form a traffic frame based on the interleaved data filled as payload data in a payload area of ​​the traffic frame, and to form a management frame including information of the delay adjustment amount of each data channel corresponding to the current interleaving pattern.

[0006] In a second aspect, an embodiment of the present disclosure provides a radio frequency RF interface receiving device including a receiving controller having a deframer means, a traffic data deinterleave means, and a plurality of delay means, wherein the traffic data deinterleave means is configured to receive payload data of a traffic frame provided by the deframer means, and deinterleave the payload data based on an interleaving pattern to obtain data of a plurality of data channels, the payload data including one or more cycles of interleaved data, the data of each data channel including a plurality of unit data blocks, the interleaving pattern indicating a corresponding number of unit data blocks of each data channel included in one cycle of interleaved data and an arrangement order of the unit data blocks of the plurality of data channels within one cycle, and the data of the plurality of data channels is deinterleaved in the same interleaving pattern within the one or more cycles. and the deframer means is configured to deframe input data based on a traffic frame structure or a management frame structure to obtain a traffic frame or a management frame, and when the input data is deframed to obtain the traffic frame, the deframer means transmits the payload data of the traffic frame to the traffic data deinterleaving means, and when the input data is deframed to obtain the management frame, the management frame includes information on the interleaving pattern and information on a delay adjustment amount for each data channel corresponding to the interleaving pattern, and the plurality of delay means respectively correspond to the plurality of data channels, and each delay means is configured to delay data of the corresponding data channel by a time corresponding to the delay adjustment amount, based on the delay adjustment amount for the corresponding data channel, and output the data.

[0007] In a third aspect, an embodiment of the present disclosure provides a method for serially interleaving data of a plurality of data channels based on a current interleaving pattern to form interleaved data including one or more periods, wherein the data of each data channel includes a plurality of unit data blocks, and the interleaving pattern indicates the corresponding number of unit data blocks of each data channel included in one period of interleaved data and the arrangement order of the unit data blocks of the plurality of data channels within one period, and serially interleaving the data of the plurality of data channels with the same interleaving pattern within the one or more periods; and determining a delay adjustment amount for each data channel corresponding to the current interleaving pattern, wherein a position of the unit data block of one data channel in the current interleaving pattern is determining a historical delay adjustment amount corresponding to the previous interleaving pattern of the one data channel as a delay adjustment amount corresponding to the current interleaving pattern of the one data channel after offsetting the previous interleaving pattern by m unit data blocks in a direction opposite to the first direction when the previous interleaving pattern is offset by m unit data blocks in a first direction with respect to a position in the previous interleaving pattern, where m is an integer greater than or equal to 1; forming a traffic frame based on the interleaved data filled as payload data in a payload area of ​​the traffic frame; forming a management frame including information on the delay adjustment amount of each data channel corresponding to the current interleaving pattern; and transmitting the traffic frame or the management frame.

[0008] In a fourth aspect, an embodiment of the present disclosure includes a step of deframing input data based on a traffic frame structure or a management frame structure to obtain a traffic frame or a management frame; and when the traffic frame is obtained by deframing the input data, a step of deinterleaving payload data of the traffic frame based on an interleaving pattern to obtain data of a plurality of data channels, wherein the payload data includes one or more cycles of interleaved data, the data of each data channel includes a plurality of unit data blocks, and the interleaving pattern is a step of deinterleaving the unit data blocks of each data channel included in one cycle of interleaved data. and a receiving method for an RF interface, the receiving method including: specifying a corresponding number of data blocks and an arrangement order of unit data blocks of the plurality of data channels within one period, and serially interleaving data of the plurality of data channels with the same interleaving pattern within the one or more periods; when the management frame is obtained by deframing the input data, obtaining the interleaving pattern and delay adjustment amounts of each data channel corresponding to the interleaving pattern based on the management frame; and delaying data of each data channel by a time corresponding to the delay adjustment amount based on the delay adjustment amount of each of the plurality of data channels, and outputting the data. In a fifth aspect, an embodiment of the present disclosure provides a chip including an RF interface transmitting device according to the present disclosure and an RF interface receiving device according to the present disclosure.

[0009] In a sixth aspect, an embodiment of the present disclosure provides a base station including a chip according to the present disclosure. In a seventh aspect, an embodiment of the present disclosure provides a terminal device including a chip according to the present disclosure. [Effects of the Invention]

[0010] According to the embodiment of the present disclosure, data of multiple data channels are serially interleaved based on a current interleaving pattern to form interleaved data, and a delay adjustment amount for each data channel corresponding to the current interleaving pattern is determined, so that the data of each data channel can be delayed by a time corresponding to the delay adjustment amount based on the delay adjustment amount of each of the multiple data channels before being output. Thus, while maintaining a constant transmission delay, it is possible to effectively solve the problem of crosstalk between traffic signals introduced by operations such as traffic chain release, chain establishment, or transmission stop / restart. At the same time, it is possible to adaptively adjust the carrier bandwidth of the RF interface according to changes in the actual transmission speed of traffic signals, thereby improving the utilization efficiency of the carrier bandwidth, thereby reducing the power consumption of the RF interface and improving the stability and reliability of data transmission.

[0011] The drawings of the embodiments of the present disclosure are as follows: [Brief explanation of the drawings]

[0012] [Figure 1] 1 illustrates a schematic block diagram of a transmit controller of an RF interface transmitter device according to an embodiment of the present disclosure. [Figure 2] 1 illustrates another schematic block diagram of a transmit controller of an RF interface transmitter device according to an embodiment of the present disclosure. [Figure 3] 1 illustrates a schematic block diagram of a traffic frame according to an embodiment of the present disclosure. [Figure 4] 1 shows a schematic block diagram of a management frame according to an embodiment of the present disclosure. [Figure 5] 1 illustrates another schematic block diagram of a transmit controller of an RF interface transmitter device according to an embodiment of the present disclosure. [Figure 6] 10 illustrates an example of management frame transmission timing according to an embodiment of the present disclosure. [Figure 7] 1 shows a schematic block diagram of an RF interface transmitter according to an embodiment of the present disclosure. [Figure 8]1 illustrates a flowchart of a transmission method for an RF interface according to an embodiment of the present disclosure. [Figure 9] 10 shows a detailed flowchart of step S120 in a transmission method for an RF interface according to an embodiment of the present disclosure. [Figure 10] 10 illustrates another flowchart of a transmission method for an RF interface according to an embodiment of the present disclosure. [Figure 11] 10 illustrates another flowchart of a transmission method for an RF interface according to an embodiment of the present disclosure. [Figure 12] 10 shows a detailed flowchart of step S150 in a transmission method for an RF interface according to an embodiment of the present disclosure. [Figure 13] 1 illustrates a schematic block diagram of a receive controller of an RF interface receiver according to an embodiment of the present disclosure. [Figure 14] 1 illustrates another schematic block diagram of a receive controller of an RF interface receiver according to an embodiment of the present disclosure. [Figure 15] 10 illustrates an example of delay adjustment according to an embodiment of the present disclosure. [Figure 16] 1 illustrates another conceptual block diagram of a receive controller of an RF interface receiver according to an embodiment of the present disclosure. [Figure 17] 1 shows a schematic block diagram of an RF interface receiver according to an embodiment of the present disclosure. [Figure 18] 1 illustrates a flowchart of a receiving method for an RF interface according to an embodiment of the present disclosure. [Figure 19] 10 shows a detailed flowchart of step S240 in a receiving method for an RF interface according to an embodiment of the present disclosure. [Figure 20] 1 illustrates a typical application scenario of an RF interface device according to an embodiment of the present disclosure. [Figure 21] 1 illustrates a connection relationship between a transmission controller and a transmission physical layer of an RF interface transmission device according to an embodiment of the present disclosure. [Figure 22]1 illustrates a connection relationship between a receiving controller and a receiving physical layer of an RF interface receiving device according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0013] In order to make the technical solution of the present disclosure more easily understandable to those skilled in the art, the following detailed description of the embodiments of the present disclosure will be given in conjunction with the accompanying drawings.

[0014] In the following specification, the present disclosure will be described more fully with reference to the drawings, but exemplary embodiments may be embodied in different forms, and the present disclosure should not be construed as being limited to the embodiments described below. Rather, the purpose of providing these embodiments is to make the disclosure clear and complete, and to allow those skilled in the art to fully understand the scope of the disclosure. The drawings of the embodiments of the present disclosure are intended to provide a further understanding of the embodiments of the present disclosure, constitute a part of the specification, and, together with the detailed embodiments, explain the present disclosure and are not intended to limit the disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing the detailed embodiments with reference to the drawings.

[0015] The present disclosure may be described with reference to plan views and / or cross-sectional views using idealized conceptual diagrams of the present disclosure. Therefore, the exemplary drawings may be modified based on manufacturing techniques and / or margins.

[0016] Where not inconsistent, the embodiments and features of the embodiments of the present disclosure may be combined with each other.

[0017] The terms used in this disclosure are used only to describe particular embodiments and are not intended to limit the disclosure. As used in this disclosure, the term "and / or" includes any and all combinations of at least one of the associated listed items. As used in this disclosure, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It is also understood that the terms "comprising," "comprising," and "consisting of" specify the presence of such features, wholes, steps, operations, elements, and / or assemblies, but do not exclude the presence or addition of at least one other feature, whole, step, operation, element, assembly, and / or group thereof.

[0018] Unless otherwise specified, the meanings of all terms (including technical and scientific terms) used in this disclosure are the same as those commonly understood by those skilled in the art. It will also be understood that terms defined in common dictionaries, unless expressly limited in this disclosure, will be interpreted as having a meaning consistent with the meaning in the context of the relevant technology and this disclosure, and will not be interpreted as having an ideal or overly formal meaning.

[0019] Related art RF interface devices, such as JESD204B or JESD204C interfaces, can solve transmission delay jitter and reduce transmission delay. However, due to the basic characteristics of the transmission technology of such interface devices, the distribution pattern of different transmission traffic in the frame structure cannot be changed. If the distribution pattern changes, the chain must be disconnected and re-established. However, disconnecting and re-establishing the chain causes the delay relationship under the original traffic link to disappear. This means that for all traffic transmissions on the link, each chain disconnection and re-establishment generates a single latency jitter, and it is not possible to automatically adapt to changes in transmission speed due to changes in traffic while ensuring that transmission delay does not change. Therefore, such interfaces can only adopt a fixed-speed transmission mode, and RF interfaces using this technology must configure the traffic distribution pattern in the data frame structure based on the maximum transmission traffic combination and peak flow rate from the beginning of chain construction. Currently, when there is no actual data transmission request for certain traffic, or when discontinuously transmitted traffic is in a quiescent state, these traffic also transmit invalid data on the JESD204B or JESD204C interface to ensure that the RF interface can operate stably and reliably when a data transmission request occurs for these traffic. These invalid transmissions waste a large amount of bearer bandwidth and power consumption.

[0020] Other RF interface devices, such as the DigRF V4 interface, can adaptively adjust their transmission bandwidth to accommodate changes in transmission speed due to traffic fluctuations. However, due to the fundamental characteristics of the transmission technology of such interface devices, they are unable to reduce transmission delays or resolve the fixed transmission delay issue. This is because the basic unit of transmission requests in the DigRF V4 interface is a data frame, and buffering data frames increases transmission delays. Furthermore, the DigRF V4 interface transmits data frames in a polling manner. In applications where multiple traffic flows simultaneously, adjustments or discontinuous transmissions of any traffic result in jitter in the transmission and reception delays of other traffic flows. For example, currently, two equal-rate subcarriers (cc) (cc0 and cc1) need to transmit data. Since the payload area of ​​each data frame in the DigRF V4 interface only carries traffic data for the same cc traffic, the poller that distributes transmission time slices monitors the data cache for each cc traffic in real time. After it is determined that the data cache for cc0 traffic is full, it immediately sends this data to the downstream framing module for processing. After the data transmission for cc0 traffic is complete, the data for cc1 traffic is sent to the framing module for processing, and then the data for cc0 traffic, the data for cc1 traffic, and so on. If the system deletes a transmission connection for cc0 traffic, the data frames for cc1 traffic are sent early because there is no blocking for cc0 traffic. Conversely, if the system adds a transmission connection for cc2 traffic, the cc0 and cc1 traffic transmit data frames at a certain time interval backward due to the influence of cc2 traffic. The larger the transmission bandwidth of the newly added cc2 traffic, the greater the impact on cc0 and cc1 traffic.Therefore, any change in transmission traffic (removal of transmission traffic or increase in transmission traffic) means that the time transmission position of the data frame of the existing traffic has changed, which is a single delay jitter from the receiving side, and traffic transmission at the system level is not acceptable.

[0021] 5G mobile communication physical layer baseband signals are constantly faced with operations such as traffic increase / decrease or discontinuous transmission / reception during transmission, which results in problems of transmission speed changes and delay jitter, which seriously hinder the stable and reliable data transmission required for mobile communications.In addition, since the real-time nature of data transmission is also an important indicator for considering the performance of RF interface devices, whether they are base stations or mobile terminals, RF interface devices that can adapt to transmission speed changes, eliminate delay jitter, and at the same time minimize transmission delay are required.

[0022] To solve the problems existing in related high-speed interfaces, this disclosure proposes a new private frame structure and, by optimizing the implementation method of protocol processing, proposes a large-bandwidth, low-latency RF interface device that supports variable rates and has fixed delay.

[0023] An embodiment of the present disclosure provides an RF interface transmitter. FIG. 1 shows a schematic block diagram of a transmit controller of an RF interface transmitter according to an embodiment of the present disclosure.

[0024] As shown in FIG. 1, the RF interface transmitting device according to the embodiment of the present disclosure includes a transmission controller 100 having a traffic data interleaving means 101, a delay adjustment amount determining means 102, and a framer means 103.

[0025] The traffic data interleaving means 101 is configured to serially interleave data of multiple data channels based on a current interleaving pattern to form interleaved data including one or more periods. The data of each data channel includes multiple unit data blocks. The interleaving pattern indicates the corresponding number of unit data blocks of each data channel included in one period of interleaved data and the arrangement order of the unit data blocks of the multiple data channels within one period. The data of the multiple data channels is serially interleaved using the same interleaving pattern within one or more periods.

[0026] According to an embodiment of the present disclosure, data of each data channel may include multiple data blocks in sample point units, and one sample point may be composed of a set of in-phase / quadrature (I / Q) data. For example, since the sampling precision of the I / Q data is 12 bits, one sample point may be data represented by 24 bits. In the same product, the precision represented by the sample point is the same.

[0027] The interleaving pattern can include the number of unit data blocks of each data channel included in one period of interleaved data and the arrangement order of the unit data blocks of each data channel within one period. For example, three cc traffics, cc0, cc1, and cc2, need to transmit data, that is, data needs to be transmitted on three data channels, and the interleaving pattern can be: It can be expressed as s0, s1, s1, s2.

[0028] s0 represents a sample point of the data channel corresponding to cc0 traffic, s1 represents a sample point of the data channel corresponding to cc1 traffic, and s2 represents a sample point of the data channel corresponding to cc2 traffic. This example interleaving pattern indicates that one period of interleaved data includes one sample point of cc0 traffic, two sample points of cc1 traffic, and one sample point of cc2 traffic, arranged in the order of cc0 traffic, cc1 traffic, and cc2 traffic. If there is no change in the transmission traffic, the interleaving pattern does not change, and the data of the data channels corresponding to these transmission traffics are serially interleaved using the same interleaving pattern within each period.

[0029] The delay adjustment amount determining means 102 is configured to determine a delay adjustment amount of each data channel corresponding to a current interleaving pattern, and when the position of a unit data block of one data channel in the current interleaving pattern is offset by m unit data blocks along a first direction with respect to its position in a previous interleaving pattern, determine the historical delay adjustment amount corresponding to the previous interleaving pattern of the one data channel as the delay adjustment amount corresponding to the current interleaving pattern of the one data channel after offsetting by m unit data blocks in a direction opposite to the first direction, where m is an integer greater than or equal to 1.

[0030] For example, if two CC traffic streams, cc0 and cc1, originally need to transmit data and the interleaving pattern is, for example, s0, s1, s1, one cycle of interleaved data includes one sample point of the cc0 traffic stream and two sample points of the cc1 traffic stream, arranged in the order from the cc0 traffic stream to the cc1 traffic stream. If one cc2 traffic stream is newly added and its position is between the cc0 traffic stream and the cc1 traffic stream, the interleaving pattern can be changed to, for example, s0, s2, s2, s2, s2, s1, s1, which means one cycle of interleaved data includes one sample point of the cc0 traffic stream, four sample points of the cc2 traffic stream, and two sample points of the cc1 traffic stream, arranged in the order from the cc0 traffic stream to the cc2 traffic stream, and then to the cc1 traffic stream. That is, the position of the data of the data channel corresponding to the cc1 traffic stream in the current interleaving pattern is offset backward (i.e., in the first direction) by four sample points relative to its position in the previous interleaving pattern. If the delay of the data channel corresponding to the cc1 traffic is not adjusted, then from the receiving side, the delay of the cc0 traffic remains unchanged, and the cc1 traffic is delayed backward by four sample points. To achieve delay locking, the delay of the data channel corresponding to the cc1 traffic needs to be adjusted forward (i.e., in the opposite direction to the first direction) by four sample points.

[0031] According to an embodiment of the present disclosure, the delay adjustment amount determining means 102 is further configured to: determine the delay adjustment amount of each data channel corresponding to the current interleaving pattern as a designated value when there is no previous interleaving pattern; and determine the delay adjustment amount of the one data channel corresponding to the current interleaving pattern as a designated value when there is no historical delay adjustment amount corresponding to a previous interleaving pattern for one data channel among the multiple data channels.

[0032] In the above example, since the data channel corresponding to the newly added CC2 traffic does not have a historical delay adjustment amount corresponding to the previous interleaving pattern, the delay adjustment amount of the data channel can be determined as a specified value according to traffic demand.

[0033] The framer means 103 is configured to form a traffic frame based on the interleaved data to be filled as payload data in the payload area of ​​the traffic frame, and is further configured to form a management frame including information on the delay adjustment amount of each data channel corresponding to the current interleaving pattern.

[0034] As shown in FIG. 1, the traffic data interleaving means 101 transmits interleaved data to the framer means 103 to form a traffic frame, and the delay adjustment amount determining means 102 transmits the delay adjustment amount of each data channel corresponding to the current interleaving pattern to the framer means 103 to form a management frame.

[0035] 1 as being directly connected to the framer means 103, those skilled in the art will understand that the delay adjustment amount determination 102 can be indirectly connected to the framer means 103, for example, via a memory or register component, i.e., the delay adjustment amount determination 102 can send the delay adjustment amount to the memory or register, and the framer means 103 can obtain the delay adjustment amount by reading the memory or register. Note that the arrows in the drawings of the present disclosure are intended to indicate the flow of data and / or signals between each component, and do not necessarily imply that a direct connection relationship exists between two components connected by an arrow.

[0036] According to an embodiment of the present disclosure, a delay adjustment amount for each data channel corresponding to a current interleaving pattern can be transmitted to a receiving side by a management frame, and the receiving side can delay the data of the data channel by a time corresponding to the delay adjustment amount based on the received delay adjustment amount and output the data.

[0037] According to an embodiment of the present disclosure, the delay adjustment amounts include a first delay adjustment amount and a second delay adjustment amount, and the previous delay adjustment amount determiner 102 is configured to, when a position of a unit data block of one data channel in a current interleaving pattern among the multiple data channels is offset by m unit data blocks along a first direction from a position of the unit data block in a previous interleaving pattern, offset the historical first delay adjustment amount corresponding to the previous interleaving pattern of the one data channel by m unit data blocks in a direction opposite to the first direction. When the historical first delay adjustment amount after the offset is a negative number, the first delay adjustment amount corresponding to the current interleaving pattern of the one data channel is set to 0, and the second delay adjustment amount corresponding to the current interleaving pattern of the one data channel is set to a difference in size between the historical second delay adjustment amount corresponding to the previous interleaving pattern of the one data channel and a first number of unit data blocks, which is an absolute value of the negative number. If the offset historical first delay adjustment amount is not a negative number, the offset historical first delay adjustment amount is set to a first delay adjustment amount corresponding to the current interleaving pattern of the one data channel, and the second delay adjustment amount corresponding to the current interleaving pattern of the one data channel is set to be equal to the historical second delay adjustment amount corresponding to the previous interleaving pattern.

[0038] According to an embodiment of the present disclosure, the delay adjustment amount of a data channel can include two parts: a first delay adjustment amount and a second delay adjustment amount. That is, the embodiment of the present disclosure can provide two delay adjustment forms: one delay adjustment form that can be realized by a delay line and another delay adjustment form that can be realized by a delay storage means (e.g., realized as a cache). The first delay adjustment amount and the second delay adjustment amount for each data channel corresponding to the current interleaving pattern can be transmitted to the receiving side via a management frame. Based on the received first delay adjustment amount, the receiving side delays the data of the data channel by a time corresponding to the first delay adjustment amount, and then transmits the data to the delay storage means corresponding to the data channel. The receiving side outputs the data when the storage capacity of the delay storage means for the data channel reaches the storage capacity corresponding to the second delay adjustment amount.

[0039] According to an embodiment of the present disclosure, the delay line can delay the data of the data channel by a time corresponding to the first delay adjustment amount, for example, the delay line can delay the data of the data channel by a number of beats corresponding to the first delay adjustment amount, and each beat has a fixed time length, so that the data of the data channel can be delayed by a time corresponding to the first delay adjustment amount.

[0040] Those skilled in the art will understand that the first delay adjustment amount can be expressed as the number of sample points, and the second delay adjustment amount can be expressed as the expected storage capacity of the delay storage means. Continuing with the above example, if the delay amount of the data channel corresponding to cc1 traffic needs to be adjusted forward by four sample points, it can be adjusted first by the first delay adjustment amount, i.e., the historical first delay adjustment amount corresponding to the previous interleaving pattern can be adjusted forward by four sample points. Adjusting the historical first delay adjustment amount forward by four sample points means subtracting four from the historical first delay adjustment amount. If the difference value obtained by subtracting four from the historical first delay adjustment amount is negative, the first delay adjustment amount corresponding to the current interleaving pattern is set to 0 because a negative number is meaningless for the number of beats in the delay line. In this case, the delay storage means needs to further adjust the delay based on the second delay adjustment amount to achieve delay fixation. Specifically, the second delay adjustment amount corresponding to the current interleaved pattern is set to the difference between the historical second delay adjustment amount corresponding to the previous interleaved pattern and the size (e.g., 24 bits) of a first number of unit data blocks (e.g., sample points), where the first number is the absolute value of the negative number. For example, since the difference value obtained by subtracting 4 from the historical first delay adjustment amount is −3, the first delay adjustment amount corresponding to the current interleaved pattern is set to 0, and the size of three (i.e., the absolute value of −3) sample points (e.g., 3 × 24 = 72 bits) is subtracted from the historical second delay adjustment amount, and the result is set to the second delay adjustment amount corresponding to the current interleaved pattern. On the other hand, if the difference value obtained by subtracting 4 from the historical first delay adjustment amount is not negative, the difference value is set to the first delay adjustment amount corresponding to the current interleaved pattern, and the historical second delay adjustment amount corresponding to the previous interleaved pattern is still used as the second delay adjustment amount corresponding to the current interleaved pattern.

[0041] According to an embodiment of the present disclosure, the delay adjustment amount determining means 102 is further configured to, when there is no previous interleaving pattern, determine the first delay adjustment amount and the second delay adjustment amount of each data channel corresponding to the current interleaving pattern as a first specified value and a second specified value, respectively; and, when there is no historical delay adjustment amount corresponding to a previous interleaving pattern for one data channel among the multiple data channels, determine the first delay adjustment amount and the second delay adjustment amount of the one data channel corresponding to the current interleaving pattern as the first specified value and the second specified value, respectively.

[0042] In the above example, the data channel corresponding to the newly added cc2 traffic does not have a historical delay adjustment amount corresponding to the previous interleaving pattern, so the first delay adjustment amount and the second delay adjustment amount of the data channel can be determined as the first specified value and the second specified value, respectively, according to the traffic demand.

[0043] The RF interface device according to the embodiment of the present disclosure can effectively solve the problem of crosstalk between traffic signals introduced by operations such as traffic chain release, chain establishment, or transmission stop / restart while ensuring a constant transmission delay, and can adaptively adjust the carrier bandwidth of the RF interface according to changes in the actual transmission speed of the traffic signals, thereby improving the utilization efficiency of the carrier bandwidth, thereby reducing the power consumption of the RF interface and improving the stability and reliability of data transmission.

[0044] FIG. 2 illustrates another schematic block diagram of a transmit controller of an RF interface transmitter device according to an embodiment of the present disclosure.

[0045] As shown in FIG. 2, the transmission controller 100 of the RF interface transmission device according to the embodiment of the present disclosure may further include an interleaving pattern determining means 104.

[0046] The interleaving pattern determining means 104 is configured to determine an interleaving pattern based on at least one of information of a plurality of traffics respectively corresponding to a plurality of data channels and user configuration information. The management frame can further include information of a current interleaving pattern.

[0047] As shown in FIG. 2, the interleave pattern determining means 104 transmits the interleave pattern to the traffic data interleave means 101, the delay adjustment amount determining means 102, and the framer means 103, respectively, so that the traffic data interleave means 101 can perform data interleaving based on the interleave pattern, the delay adjustment amount determining means 102 can determine the delay adjustment amount for each data channel based on the current interleave pattern and the previous interleave pattern, and the framer means 103 can form a management frame including the interleave pattern.

[0048] It should be noted that although the interleaving pattern determining means 104 is shown in FIG. 2 to be directly connected to the traffic data interleaving means 101, the delay adjustment amount determining means 102, and the framer means 103, those skilled in the art will understand that the interleaving pattern determining means 104 can be indirectly connected to one or more of the traffic data interleaving means 101, the delay adjustment amount determining means 102, and the framer means 103, for example, via a memory or register component, i.e., the interleaving pattern determining means 104 can send the interleaving pattern to the memory or register, and one or more of the traffic data interleaving means 101, the delay adjustment amount determining means 102, and the framer means 103 can obtain the interleaving pattern by reading the memory or register.

[0049] According to an embodiment of the present disclosure, an interleaving pattern can be determined based on the actual situation of multiple traffics and / or based on the user configuration, and the current interleaving pattern can be transmitted to the receiving side via a management frame.

[0050] According to an embodiment of the present disclosure, the interleaving pattern determination means 104 is configured to determine an interleaving image so that the proportion of the data volume of the multiple data channels in the interleaving pattern matches the proportion of the transmission bandwidth of the multiple traffics, specifically, to determine the interleaving image so that the proportion of the corresponding number of unit data blocks of the multiple data channels in the interleaving pattern matches the proportion of the transmission bandwidth of the multiple traffics.

[0051] For example, if three cc traffics cc0, cc1, and cc2 need to transmit data, and the transmission bandwidth of cc1 traffic is twice that of cc0 traffic, and the transmission bandwidth of cc2 traffic is the same as that of cc0 traffic, the interleaving pattern can be expressed as s0, s1, s1, s2.

[0052] This exemplary interleaving pattern represents that one period of interleaved data includes one sample point of cc0 traffic, two sample points of cc1 traffic, and one sample point of cc2 traffic, where the ratio of the number of sample points of each traffic matches the ratio of the transmission bandwidth of each traffic.

[0053] According to an embodiment of the present disclosure, the traffic frame may further include validity indication information used to indicate whether data of each data channel in the interleaved data is valid. The traffic data interleaving means 101 is further configured to, when there is no data in one of the multiple data channels, fill the corresponding position of the unit data block of the one data channel with invalid data as data of the one data channel in the interleaving pattern to obtain interleaved data. The framer means 103 is further configured so that the validity information is set to indicate that the data of the one data channel is invalid.

[0054] After completing the interleaving pattern based on the traffic of data waiting to be transmitted and the transmission bandwidth configuration of each traffic, the traffic data interleaving means 101 can serially interleave the data of multiple data channels based on the current interleaving pattern. However, the arrival times of data for different traffic may be different. For example, data for CC0 traffic has arrived, but data for CC1 traffic has not yet arrived. To ensure real-time transmission of traffic frames when the time boundary of a traffic frame is reached (i.e., data does not need to be cached in the RF interface transmission device), the traffic data interleaving means 101 may fill invalid data in the corresponding positions of the unit data blocks of the data channel as data for CC1 traffic when serially interleaving the data of each data channel to form interleaved data. The framer means 103 may mark the data for the data channel corresponding to CC1 traffic as invalid using valid information when forming a traffic frame. The invalid data may be implemented based on a specific data format, and this disclosure is not limited thereto.

[0055] According to an embodiment of the present disclosure, a traffic frame may further include a traffic frame header feature used to indicate that the frame is a traffic frame.

[0056] FIG. 3 illustrates a schematic block diagram of a traffic frame according to an embodiment of the present disclosure. As shown in FIG. 3, a traffic frame according to an embodiment of the present disclosure may include a Start of Frame (SOF), a traffic frame header feature, validity indication information, interleaved data, an End of Frame (EOF), or an End of Transmission (EOT).

[0057] SOF represents the position of the start of frame seen on each lane, EOF represents the position where the current frame ends, and EOT represents the end of the current frame and the end of the current burst. The code type descriptions of SOF, EOF, and EOT may be defined with reference to the DigRF V4 protocol or may be defined based on the Physical Coding Sublayer (PCS) protocol.

[0058] The traffic frame header feature word is used to indicate that the frame is a traffic frame and distinguish it from a management frame. The validity indicator information is used to indicate whether the data of each data channel in the interleaved data is valid, so that the receiving side can discard the data of the data channel indicated as invalid based on the validity indicator information. The traffic header feature word and the validity indicator information can be realized based on various coding forms that can achieve the above purposes, and the present disclosure is not limited thereto.

[0059] According to an embodiment of the present disclosure, the management frame may further include management frame length information and traffic frame length information, where the management frame length is used to indicate the length of the management frame, and the traffic frame length is used to indicate the length of the traffic frame.

[0060] According to an embodiment of the present disclosure, a management frame may further include a management frame header feature used to designate the frame as a management frame.

[0061] According to an embodiment of the present disclosure, the management frame may further include information for identifying a data channel, and in the interleaving pattern, the arrangement form for identifying the data channels of the multiple data channels indicates the corresponding number of unit data blocks of each data channel included in one period of interleaved data and the arrangement order of the unit data blocks of the multiple data channels within one period.

[0062] FIG. 4 shows a schematic block diagram of a management frame according to an embodiment of the present disclosure. As shown in FIG. 4, a management frame according to an embodiment of the present disclosure may include an SOF, a management frame header feature word, a management frame length, a traffic frame length, a data channel identification, an interleaving pattern, a delay adjustment amount (including a first delay adjustment amount and a second delay adjustment amount), a cyclic redundancy check (CRC), an EOF, or an EOT.

[0063] The meanings of SOF, EOF and EOT respectively correspond to those of the traffic frame and will not be further explained here.

[0064] The management frame header feature is used to designate the frame as a management frame and distinguish it from a traffic frame. The management frame length and traffic frame length are used to indicate the length of the management frame and the length of the traffic frame, respectively. The data channel identification is used to indicate each currently activated data channel, and an interleaved pattern can be formed by arranging the data channel identifications. The management frame header feature, management frame length, traffic frame length, and data channel identification can be realized based on various encoding forms that can achieve the above objectives, and the present disclosure is not limited thereto.

[0065] FIG. 5 illustrates another schematic block diagram of a transmit controller of an RF interface transmitter device according to an embodiment of the present disclosure.

[0066] 5 , the transmission controller 100 of the RF interface transmission apparatus according to the embodiment of the present disclosure may further include a mapping and caching means 105. The mapping and caching means 105 is configured to receive a plurality of subcarrier data streams corresponding to a plurality of traffic streams, respectively, map the plurality of subcarrier data streams to a cache of a plurality of data channels, and provide the data in the cache to the traffic data interleaving means 101.

[0067] According to an embodiment of the present disclosure, the mapping and caching means 105 can route multiple traffic data streams to caches of data channels corresponding to each traffic stream based on the system configuration. These caches are primarily intended to solve the problem of blocking the traffic frame transmission path, which may occur when transmitting a management frame. As shown in FIG. 5 , after forming a management frame, the framer means 103 can, for example, send management frame validity information to the mapping and caching means 105 and the traffic data interleaving means 101, respectively, to notify the mapping and caching means 105 and the traffic data interleaving means 101 that it is currently ready to transmit the management frame, causing the mapping and caching means 105 to cache the received traffic data and the traffic data interleaving means 101 to suspend data interleaving. If not blocked, as long as data exists in the cache of each data channel, the mapping and caching means 105 can transmit data to the traffic data interleaving means 101 in real time for data interleaving.

[0068] 5, the transmission controller 100 of the RF interface transmission device according to the embodiment of the present disclosure may further include a transmission frame selecting means 106. The transmission frame selecting means 106 is configured to select a traffic frame or a management frame as the transmission frame.

[0069] As shown in FIG. 5, after receiving the traffic frame and management frame transmitted by the framer means 103, the transmission frame selection means 106 can select either the traffic frame or the management frame as the transmission frame based on the system configuration.

[0070] According to an embodiment of the present disclosure, the transmission frame selection means 106 is configured to select a management frame as a transmission frame at the start position of the first burst when system initialization is completed and the first chain is constructed, and to select a management frame as a transmission frame when the contents of the management frame change at the start position of another burst after chain construction is completed.

[0071] By selecting a management frame as a transmission frame only when the contents of the management frame have changed, the impact of the transmission of the management frame on the transmission of traffic frames can be minimized, thereby minimizing the problem of blocking the traffic frame transmission path that may occur when transmitting a management frame.

[0072] According to another embodiment of the present disclosure, the transmission frame selection means 106 is configured to select a management frame as the transmission frame at the start position of each burst after the chain construction is completed.

[0073] By selecting a management frame as the transmission frame at the start of each burst, it is possible to ensure that the receiving side can deinterleave data, discard invalid data in the data channel, and delay output of data based on the contents of the management frame corresponding to the burst.

[0074] According to an embodiment of the present disclosure, the transmission frame selection means 106 is configured to, when selecting a management frame as a transmission frame, repeatedly transmit the management frame n times consecutively, where n is an integer greater than one.

[0075] By transmitting the management frame multiple times in succession, it is possible to ensure that the receiving side can receive the management frame reliably.

[0076] According to an embodiment of the present disclosure, the transmission frame selection means 106 is configured such that the transmission priority of management frames is higher than the transmission priority of traffic frames.

[0077] When the contents of a management frame change, the receiving side needs to be able to process the received data based on the updated contents in the management frame, so the transmission priority of the management frame needs to be set higher than the transmission priority of the traffic frame.

[0078] FIG. 6 illustrates an example of management frame transmission timing according to an embodiment of the present disclosure. As shown in Figure 6, when the burst state is Idle, data transmission on the channel is stopped, and when the burst state is Work, after system initialization is complete and the initial chain construction is performed, the system may choose to transmit three consecutive management frames at the start of the first burst (Burst 1) followed by multiple (K) data frames, or to transmit three consecutive management frames at the start of a new burst (Burst 2) followed by multiple (M) data frames, or to directly transmit multiple (N) traffic frames without transmitting management frames if the contents of the management frames remain unchanged (Burst 3). As shown in Figure 6, when it is selected to transmit management frames (Burst 1 and Burst 2), the management frames are transmitted first, followed by the traffic frames, i.e., the transmission priority of the management frames is higher than that of the traffic frames.

[0079] 5, the transmission controller 100 of the RF interface transmission device according to the embodiment of the present disclosure may further include a Lane mapping and encoding means 107 connected to the transmission frame selecting means 106. The Lane mapping and encoding means 107 is configured to receive the transmission frame provided by the transmission frame selecting means 106, and map and encode the transmission frame to a Lane.

[0080] The lane mapping and encoding means 107 can perform a mapping process of a custom frame (e.g., a traffic frame or a management frame) to a frame on a lane, and the mapping format can refer to the lane mapping process described in the DigRF V4 interface specification of the Mobile Industry Processor Interface (MIPI), and the encoding format can adopt the related technical specifications of PCS encoding.

[0081] As shown in FIG. 5 , the RF interface transmitting device according to the embodiment of the present disclosure may further include a transmitting physical layer 200 connected to the transmitting controller 100 .

[0082] According to the embodiment of the present disclosure, the final transmission process can be completed on each lane, where data after lane mapping and PCS encoding is delivered to the transmitting physical layer 200. The implementation of the transmitting physical layer 200 is not limited by the present disclosure.

[0083] FIG. 7 shows a schematic block diagram of an RF interface transmitter according to an embodiment of the present disclosure. 7, the framer means 103 may include a management frame framer 1031 and a traffic frame framer 1032. The cc0 traffic data stream, the cc1 traffic data stream, and the cc2 traffic data stream may be three traffic data streams after digital intermediate frequency processing. If not blocked, the three traffic data streams are sent to the traffic data interleaving means 101 via the mapping and caching means 105 for data interleaving.

[0084] The traffic data interleaving means 101 serially interleaves the three traffic data streams to form interleaved data based on the interleaving pattern provided (directly or indirectly) by the interleaving pattern determining means 104, thereby ensuring that each data stream has the same transmission opportunity within a data frame and a transmission capability consistent with the corresponding data bandwidth, thereby minimizing the transmission delay of all data streams. The traffic data interleaving means 101 supplies the interleaved data to a traffic frame framer 1032.

[0085] The traffic frame framer 1032 adds a traffic frame header feature word and valid indication information to an appropriate position based on the traffic frame structure and traffic frame length according to the embodiment of the present disclosure, and fills the payload area with interleaved data provided by the traffic data interleaving means 101 to form a traffic frame. The traffic frame framer 1032 transmits the traffic frame and a traffic frame valid signal to the transmission frame selection means 106.

[0086] The delay adjustment amount determining means 102 determines the delay adjustment amount for each traffic based on the interleave pattern provided (directly or indirectly) by the interleave pattern determining means 104, and transmits the delay adjustment amount to the framer 1031 of the management frame.

[0087] The management frame framer 1031 forms a management frame based on the interleave pattern provided (directly or indirectly) by the interleave pattern determination means 104, the delay adjustment amount provided (directly or indirectly) by the delay adjustment amount determination means 102, various configuration parameters provided by the master CPU, and the management frame structure and management frame length according to an embodiment of the present disclosure. The management frame framer 1031 can be configured to transmit the management frame and a management frame valid signal to the transmission frame selection means 106 in response to a management frame transmission instruction provided by the master CPU.

[0088] The transmission frame selection means 106 can be implemented, for example, as a merging frame multiplexer (MUX) to realize time-division multiplexing of traffic frames and management frames. The transmission frame selection means 106 can be configured so that the transmission priority of management frames is higher than that of traffic frames. At the start of each burst, the transmission frame selection means 106 can select whether to transmit a management frame based on the configuration state of a register. When a new link is established, the transmission frame selection means 106 can forcibly transmit multiple management frames in succession. If necessary, a management frame can also be forcibly inserted in the middle of a burst. In this case, the transmission frame selection means 106 must ensure the integrity of the traffic frames.

[0089] An embodiment of the present disclosure further provides a transmission method applied to an RF interface according to the present disclosure.

[0090] FIG. 8 illustrates a flowchart of a transmission method for an RF interface according to an embodiment of the present disclosure.

[0091] As shown in FIG. 8, the transmission method for an RF interface according to the embodiment of the present disclosure includes the following steps S110 to S150.

[0092] In step S110, data of multiple data channels is serially interleaved based on the current interleaving pattern to form interleaved data including one or more periods.

[0093] The data of each data channel includes a plurality of unit data blocks, and the interleave pattern indicates the corresponding number of unit data blocks of each data channel included in one cycle of interleaved data and the arrangement order of the unit data blocks of the plurality of data channels within one cycle. Within one or more cycles, the data of the plurality of data channels is serially interleaved using the same interleave pattern.

[0094] In step S120, the delay adjustment amount for each data channel corresponding to the current interleaving pattern is determined.

[0095] When the position of a unit data block of one data channel in a current interleaving pattern is offset by m unit data blocks along a first direction with respect to the position of the unit data block in a previous interleaving pattern, a historical delay adjustment amount corresponding to the previous interleaving pattern of the one data channel is determined as the delay adjustment amount corresponding to the current interleaving pattern of the one data channel after being offset by m unit data blocks in a direction opposite to the first direction, where m is an integer greater than or equal to 1.

[0096] In step S130, a traffic frame is formed based on the interleaved data, and the interleaved data is filled into the payload area of ​​the traffic frame as payload data.

[0097] In step S140, a management frame is formed that includes information on the delay adjustment amount for each data channel corresponding to the current interleaving pattern.

[0098] In step S150, a traffic frame or a management frame is transmitted. According to the disclosed embodiment, the delay adjustment amount for each data channel is used to instruct the receiving side to delay and output the data of each data channel obtained after deinterleaving the interleaved data by a time corresponding to the delay adjustment amount.

[0099] According to an embodiment of the present disclosure, the step of determining the delay adjustment amount of each data channel corresponding to the current interleaving pattern (i.e., step S120) includes the steps of: determining the delay adjustment amount of each data channel corresponding to the current interleaving pattern as a specified value when there is no previous interleaving pattern; and determining the delay adjustment amount of the one data channel corresponding to the current interleaving pattern as a specified value when there is no previous interleaving pattern for the one data channel among the multiple data channels.

[0100] FIG. 9 shows a detailed flowchart of step S120 in the transmission method for the RF interface according to an embodiment of the present disclosure.

[0101] According to an embodiment of the present disclosure, the delay adjustment amount may include a first delay adjustment amount and a second delay adjustment amount. As shown in Figure 9, the step of determining the delay adjustment amount of each data channel corresponding to the current interleaving pattern (i.e., step S120) includes the following steps S121 to S123.

[0102] In step S121, when the position of a unit data block of one data channel among the multiple data channels in the current interleaving pattern is offset by m unit data blocks along the first direction from the position of the unit data block in the previous interleaving pattern, the historical first delay adjustment amount corresponding to the previous interleaving pattern of the one data channel is offset by m unit data blocks in the direction opposite to the first direction.

[0103] In step S122, if the historical first delay adjustment amount after offset is a negative number, the first delay adjustment amount corresponding to the current interleaving pattern of the one data channel is set to 0, and the difference in size between the historical second delay adjustment amount corresponding to the previous interleaving pattern of the one data channel and the first number of unit data blocks, which is the absolute value of the negative number, is set as the second delay adjustment amount corresponding to the current interleaving pattern of the one data channel.

[0104] In step S123, if the offset historical first delay adjustment amount is not a negative number, the offset historical first delay adjustment amount is set to the first delay adjustment amount corresponding to the current interleaving pattern of the one data channel, and the second delay adjustment amount corresponding to the current interleaving pattern of the one data channel is set to be equal to the historical second delay adjustment amount corresponding to the previous interleaving pattern.

[0105] According to an embodiment of the present disclosure, the first delay adjustment amount of each data channel is used to instruct the receiving side, and the data of the data channel obtained after deinterleaving is delayed by a time corresponding to the first delay adjustment amount and transmitted to the delay storage means corresponding to the data channel.

[0106] According to an embodiment of the present disclosure, the second delay adjustment amount of each data channel is used to instruct the receiving side, and is output when the storage of data of the data channel in the delay storage means corresponding to the data channel reaches a storage capacity corresponding to the second delay adjustment amount.

[0107] According to an embodiment of the present disclosure, the step of determining the delay adjustment amount of each data channel corresponding to the current interleaving pattern (i.e., step S120) determines the first delay adjustment amount and the second delay adjustment amount of each data channel corresponding to the current interleaving pattern as a first specified value and a second specified value, respectively, when there is no previous interleaving pattern; and determines the first delay adjustment amount and the second delay adjustment amount of one data channel corresponding to the current interleaving pattern as a first specified value and a second specified value, respectively, when there is no previous interleaving pattern for one data channel among the multiple data channels.

[0108] FIG. 10 illustrates another flowchart of a transmission method for an RF interface according to an embodiment of the present disclosure.

[0109] As shown in FIG. 10, the transmission method for an RF interface according to the embodiment of the present disclosure may further include step S101 before step S110 and step S120.

[0110] In step S101, an interleaving pattern is determined based on at least one of a plurality of pieces of traffic information corresponding to a plurality of data channels, respectively, and user configuration information.

[0111] The management frame further includes information of the current interleaving pattern. According to an embodiment of the present disclosure, the step of determining an interleaving pattern (i.e., step S101) is a step of determining an interleaving image so that the ratio of the data amounts of multiple data channels in the interleaving pattern matches the ratio of the transmission bandwidths of multiple traffics, and specifically includes a step of determining an interleaving image so that the ratio of the corresponding numbers of unit data blocks of multiple data channels in the interleaving pattern matches the ratio of the transmission bandwidths of multiple traffics.

[0112] According to an embodiment of the present disclosure, the traffic frame may further include validity indication information used to indicate whether the data of each data channel in the interleaved data is valid. The step of serially interleaving the data of the multiple data channels based on the current interleaving pattern (i.e., step S110) includes, when there is no data in one of the multiple data channels, filling invalid data as the data of the one data channel into the corresponding position of the unit data block of the one data channel in the interleaving pattern to obtain interleaved data. The step of forming the traffic frame based on the interleaved data (i.e., step S130) includes setting the validity information to indicate that the data of the one data channel is invalid.

[0113] FIG. 11 shows another flowchart of a transmission method for an RF interface according to an embodiment of the present disclosure.

[0114] As shown in FIG. 11, the transmission method for an RF interface according to the embodiment of the present disclosure may further include steps S103 to S105 before step S110.

[0115] In step S103, a plurality of subcarrier data streams respectively corresponding to a plurality of traffic streams are received.

[0116] In step S105, the multiple subcarrier data streams are mapped to a cache of multiple data channels.

[0117] FIG. 12 shows a detailed flowchart of step S150 in the transmission method for the RF interface according to an embodiment of the present disclosure.

[0118] As shown in FIG. 12, the step of transmitting a traffic frame or a management frame (that is, step S150) includes steps S151 to S152.

[0119] In step S151, a traffic frame or a management frame is selected as a frame to be transmitted.

[0120] In step S152, the transmission frame is transmitted. According to an embodiment of the present disclosure, the step of selecting a traffic frame or a management frame as a transmission frame (i.e., step S151) includes the steps of selecting a management frame as a transmission frame at the start of the first burst when system initialization is completed and the first chain construction is performed, and selecting a management frame as a transmission frame when the contents of the management frame change at the start of another burst after chain construction is completed.

[0121] According to another embodiment of the present disclosure, the step of selecting a traffic frame or a management frame as a transmission frame (i.e., step S151) includes a step of selecting a management frame as the transmission frame at the start position of each burst after chain construction is completed.

[0122] According to an embodiment of the present disclosure, when a management frame is selected as a transmission frame, the management frame is repeatedly transmitted n times in succession, where n is an integer greater than one.

[0123] According to an embodiment of the present disclosure, the transmission priority of management frames is higher than the transmission priority of traffic frames.

[0124] The transmitting method for RF interface provided by each embodiment of the present disclosure can be performed by the RF interface transmitting device according to each embodiment of the present disclosure, and for clarity, the corresponding technical details and technical effects will not be described herein.

[0125] An embodiment of the present disclosure further provides an RF interface receiving device. FIG. 13 illustrates a schematic block diagram of a receive controller of an RF interface receiver according to an embodiment of the present disclosure.

[0126] As shown in FIG. 13, the RF interface receiving device according to the embodiment of the present disclosure includes a receiving controller 300 having a deframer means 301, a traffic data deinterleaving means 302, and a plurality of delay means 303.

[0127] The traffic data deinterleaving means 302 is configured to receive payload data of the traffic frame provided by the deframer means 301, and deinterleave the payload data based on an interleaving pattern to obtain data of multiple data channels. The payload data includes interleaved data of one or more periods, and the data of each data channel includes multiple unit data blocks. The interleaving pattern indicates the corresponding number of unit data blocks of each data channel included in one period of interleaved data and the arrangement order of the unit data blocks of the multiple data channels within one period, and serially interleaves the data of the multiple data channels with the same interleaving pattern within one or more periods.

[0128] The deframer means 301 is configured to deframe input data based on the traffic frame structure or the management frame structure to obtain a traffic frame or a management frame. When the input data is deframed to obtain a traffic frame, the deframer means 301 transmits payload data of the traffic frame to the traffic data deinterleaving means 302, and when the input data is deframed to obtain a management frame, the management frame includes information on an interleaving pattern and information on a delay adjustment amount for each data channel corresponding to the interleaving pattern.

[0129] The plurality of delay means 303 correspond to the plurality of data channels, respectively, and each delay means 303 is configured to delay the data of the corresponding data channel by a time corresponding to the delay adjustment amount based on the delay adjustment amount of the corresponding data channel and output the data.

[0130] 12, the deframer means 301 is shown as being directly connected to the traffic data deinterleaving means 302 and each of the plurality of delay means 303, but those skilled in the art will understand that the deframer means 301 can be indirectly connected to the traffic data deinterleaving means 302 and / or the delay means 303, for example, via a memory or register component, that is, the deframer means 301 can transmit the interleaving pattern and the delay adjustment amount included in the management frame to the memory or register, and the traffic data deinterleaving means 302 and the delay means 303 can respectively obtain the interleaving pattern and the delay adjustment amount by reading the memory or register. Similar situations have been described many times in this specification and will not be described in detail below.

[0131] FIG. 14 illustrates another schematic block diagram of a receive controller of an RF interface receiver according to an embodiment of the present disclosure.

[0132] According to an embodiment of the present disclosure, the delay adjustment amount may include a first delay adjustment amount and a second delay adjustment amount. As shown in FIG. 14 , each of the plurality of delay means 303 includes a delay line means 3031 and a delay storage means 3032.

[0133] The traffic data deinterleaving means 302 is configured to provide data of each data channel in the obtained plurality of data channels to the delay line means 3031 of the delay means 303 corresponding to that data channel.

[0134] The delay line means 3031 is configured to delay the data of the corresponding data channel by a time corresponding to the first delay adjustment amount based on the first delay adjustment amount of the corresponding data channel, and store the delay in the delay memory means 3032 of the delay means 303 corresponding to the data channel.

[0135] The delay storage means 3032 is configured to output the stored data based on the second delay adjustment amount of the corresponding data channel when the data storage of the data channel reaches a storage capacity corresponding to the second delay adjustment amount.

[0136] According to an embodiment of the present disclosure, the traffic data deinterleaving means 302 deinterleaves payload data in the traffic frames transmitted by the deframer means 301 based on the interleaving pattern obtained through the management frame, separates all traffic data streams corresponding to the data channels, and provides the data streams to the delay line means 3031 of the corresponding data channel. The delay line means 3031 on each data channel receives the data stream output from the traffic data deinterleaving means 302, completes delay processing based on the first delay adjustment amount of each data channel obtained through the management frame, and then transmits the delayed data to the corresponding delay storage means 3032 for caching. If the amount of data cached by the delay storage means 3032 is greater than the second delay adjustment amount of each data channel obtained through the management frame, the delay storage means 3032 transmits the read data to the subsequent processing module in response to a data read request from the subsequent processing module in the clock domain of the subsequent processing module to complete subsequent processing.

[0137] The delay adjustment according to the embodiment of the present disclosure will be described in detail below using a specific example. FIG. 15 illustrates an example of delay adjustment according to an embodiment of the present disclosure.

[0138] In the example of Figure 15, when a subsystem of a system on chip (SoC) issues cc0 traffic and cc1 traffic, the transmitting side cannot guarantee a specific timing relationship between the two traffics. Therefore, when either traffic (cc0 traffic shown in Figure 15) arrives, the group frame process of the traffic frame according to the embodiment of the present disclosure can be initiated. As shown in Figure 15, if the cc1 traffic has not arrived at the group frame module at the time boundary of the first traffic frame, the data of the cc1 traffic must be cached and postponed to the start time of the next traffic frame to join the group frame of the traffic frame. As shown in Figure 15, in the first traffic frame output after the group frame, the data of cc0 is valid data and the data of cc1 is invalid data, as indicated by the validity indication information included in the first traffic frame.

[0139] At the receiving end, as shown in Figure 15, the traffic frames are processed by a traffic data deinterleaving means to separate different traffic data streams, with each traffic data stream being aligned to a traffic frame boundary. To restore the relative timing of each traffic data stream at the transmitting end, first, the delay line means on each data channel at the receiving end must restore the time relationship within the frame of each traffic data stream based on the first delay adjustment amount of each data channel, and then the delay storage means on each data channel must restore the relative time relationship within the frame of the cc0 traffic data stream and the cc1 traffic data stream based on the second delay adjustment amount of each data channel.

[0140] The above example is merely an example of using a delay line means and a delay storage means together to achieve a fixed delay. In practice, various functions can be achieved by using a delay line means and a delay storage means together depending on the specific application scenario, such as adjusting the demodulated data stream forward / backward on the time axis.

[0141] According to an embodiment of the present disclosure, the delay storage means can be realized as a mailbox, and the second delay adjustment amount can be realized as a ready threshold value of the mailbox.

[0142] Delay lines and mailboxes are two mechanisms for achieving delay adjustment. Delay lines achieve delay by beating the output of a register, and the delay range of the delay line is usually relatively small to prevent the logic scale of the delay line from becoming too large. Mailboxes are usually realized by first-in, first-out (FIFO) memories as clock domain conversion devices between an RF interface device and a subsequent digital front end (DFE) module. In the embodiment of the present disclosure, the FIFO memory is used to achieve delay adjustment in relation to the "water level" of cache data at the start of traffic transmission. In the context of this application, the term "water level" embodies the concept that a FIFO memory has one input port with a write clock wr_clk on the input port, and one output port with a read clock rd_clk on the output port, where the write clock wr_clk and the read clock rd_clk may be clocks in two different clock domains, and when the input port writes data to the FIFO memory with the write clock wr_clk, the water level of the FIFO memory rises, and when the output port reads data from the FIFO memory with the read clock rd_clk, the water level of the FIFO memory falls.

[0143] After the chain construction is completed, the delay storage means (mailbox) raises the Ready output signal when the water level reaches the Mailbox Ready threshold based on the cache data water level and the second delay adjustment amount (Mailbox Ready threshold) set in the management frame. After each chain construction, the Ready output signal is raised and maintained at a high level until the chain is disconnected and the Ready output signal is lowered. After detecting that the Ready output signal has been raised, the subsequent module (e.g., DFE module) begins reading data from the corresponding Mailbox and performs the subsequent processing flow.

[0144] One of the functions of a mailbox is to realize clock domain conversion, which requires absorbing the frequency offset and jitter of the write clock wr_clk and read clock rd_clk of the FIFO memory. To ensure that abnormal states such as "empty / full" do not occur in the FIFO memory, a data safety level is typically reserved for the FIFO memory, and this data safety level can be determined based on the clock indicators of the write clock wr_clk and read clock rd_clk in the system design. In embodiments of the present disclosure, the data safety level is superimposed with the traffic delay jitter range level to form the mailbox ready threshold, thereby performing delay adjustment on the data using the mailbox to achieve delay locking or to realize various functions such as adjusting the data stream forward / backward on the time axis based on specific application scenarios.

[0145] According to an embodiment of the present disclosure, the delay storage means 3032 is configured to receive and store delayed data from the delay line means 3031 corresponding to the delay storage means 3032 in the clock domain of the RF interface, and when the amount of data stored in the delay storage means 3032 is equal to or greater than the storage capacity corresponding to the second delay adjustment amount, to output the stored data to the subsequent module in the clock domain of the subsequent module in response to a data read request from the subsequent module.

[0146] According to an embodiment of the present disclosure, the interleaved image is determined so that the proportion of the data volume of the multiple data channels in the interleaved pattern matches the proportion of the transmission bandwidth of the multiple traffics, and specifically, the interleaved image is determined so that the proportion of the corresponding number of unit data blocks of the multiple data channels in the interleaved pattern matches the proportion of the transmission bandwidth of the multiple traffics.

[0147] FIG. 16 illustrates another conceptual block diagram of a receive controller of an RF interface receiver according to an embodiment of the present disclosure.

[0148] 16, according to an embodiment of the present disclosure, the receiving controller 300 may further include a control register group 304. When the input data is deframed to obtain a management frame, the control register group 304 is refreshed based on the management frame.

[0149] The traffic data deinterleaving means 302 can obtain the interleaving pattern by reading the registers in the control register group 304. The delay storage means 303 (including the delay line means 3031 and the delay storage means 3032) can obtain the delay adjustment amounts (including the first delay adjustment amount and the second delay adjustment amount) by reading the registers in the control register group 304.

[0150] 16, according to an embodiment of the present disclosure, the receiving controller 300 may further include a decoding and lane processing means 305 connected to the deframer means 301. The decoding and lane processing means 305 is configured to decode data on each lane, align delays of all active lanes, perform lane integration and lane resolution functions, and provide the physical frame obtained by the lane resolution to the deframer means 301.

[0151] After completing PCSS decoding for each lane, the decoding and lane processing means 305 aligns the delays of all activated lanes, and then completes lane integration and lane solution functions. The lane integration and lane solution process can refer to the lane demapping process described in the MIPI DigRF V4 interface specification, and the physical frame after lane solution can be output to the deframer means 301.

[0152] As shown in FIG. 16 , the RF interface receiving device according to the embodiment of the present disclosure may further include a receiving physical layer 400 connected to the receiving controller 300 .

[0153] According to an embodiment of the present disclosure, the receiving physical layer 400 completes functions such as equalization, clock recovery, receive filtering, serial / parallel conversion, and bit width conversion on each lane, and the outputs of all lanes activated by the receiving physical layer 400 are connected to the decoding and lane processing means 305. The present disclosure does not limit the implementation of the receiving physical layer 400.

[0154] FIG. 17 shows a schematic block diagram of an RF interface receiver according to an embodiment of the present disclosure.

[0155] 17, the deframer means 301 transmits the traffic frame obtained by deframing to the traffic data interleaving means 302, and when the management frame is obtained by deframing, refreshes the control register group 304 based on the management frame. The traffic data interleaving means 302 obtains an interleaving pattern by reading the registers in the control register group 304, deinterleaves the traffic frame provided by the deframer means 301 based on the interleaving pattern, and provides the data of each data channel obtained after deinterleaving to the delay line means corresponding to each data channel. The delay line means and delay storage means corresponding to each data channel obtain first and second delay adjustment amounts by reading the registers in the control register group 304, and perform delay adjustment based on the obtained first and second delay adjustment amounts, respectively.

[0156] An embodiment of the present disclosure further provides a receiving method applied to the RF interface according to the present disclosure.

[0157] FIG. 18 illustrates a flowchart of a receiving method for an RF interface according to an embodiment of the present disclosure.

[0158] As shown in FIG. 18, the receiving method for an RF interface according to an embodiment of the present disclosure includes the following steps S210 to S240.

[0159] Step S210 is configured to deframe the input data based on the traffic frame structure or the management frame structure to obtain a traffic frame or a management frame.

[0160] In step S220, if the input data is deframed to obtain a traffic frame, the payload data of the traffic frame is deinterleaved based on the interleaving pattern to obtain data of multiple data channels.

[0161] The payload data includes one or more cycles of interleaved data, and the data of each data channel includes multiple unit data blocks. The interleaving pattern indicates the corresponding number of unit data blocks of each data channel included in one cycle of interleaved data and the arrangement order of the unit data blocks of the multiple data channels within one cycle, and the data of the multiple data channels is serially interleaved with the same interleaving pattern within one or more cycles.

[0162] In step S230, when the input data is deframed to obtain a management frame, an interleaving pattern and a delay adjustment amount for each data channel corresponding to the interleaving pattern are obtained based on the management frame.

[0163] In step S240, based on the delay adjustment amount of each of the plurality of data channels, the data of each data channel is delayed by a time corresponding to the delay adjustment amount and output.

[0164] FIG. 19 shows a detailed flowchart of step S240 in the receiving method for the RF interface according to an embodiment of the present disclosure.

[0165] According to an embodiment of the present disclosure, the delay adjustment amount includes a first delay adjustment amount and a second delay adjustment amount. As shown in Fig. 19, the step of delaying and outputting data of each data channel by a time corresponding to the delay adjustment amount based on the delay adjustment amount of each of the multiple data channels (i.e., step S240) includes the following steps S241 to S242.

[0166] In step S241, based on the first delay adjustment amount of the data channel, the data of the data channel is delayed by a time corresponding to the first delay adjustment amount via the delay line means, and then stored in the delay storage means corresponding to the data channel.

[0167] In step S242, when the storage capacity of the data of the data channel in the delay storage means reaches a storage capacity corresponding to the second delay adjustment amount, the stored data is output based on the second delay adjustment amount of the data channel.

[0168] According to an embodiment of the present disclosure, the interleaved image is determined so that the proportion of the data volume of the multiple data channels in the interleaved pattern matches the proportion of the transmission bandwidth of the multiple traffics, and specifically, the interleaved image is determined so that the proportion of the corresponding number of unit data blocks of the multiple data channels in the interleaved pattern matches the proportion of the transmission bandwidth of the multiple traffics.

[0169] According to an embodiment of the present disclosure, when the input data is deframed to obtain a management frame, the method further includes refreshing a group of control registers based on the management frame.

[0170] According to an embodiment of the present disclosure, in the clock domain of the RF interface, the delay storage means receives and stores delayed data from the delay line means corresponding to the delay storage means, and when the amount of data stored in the delay storage means is equal to or greater than the storage capacity corresponding to the second delay adjustment amount, outputs the stored data to the subsequent module in response to a data read request from the subsequent module in the clock domain of the subsequent module.

[0171] The receiving method for an RF interface provided by each embodiment of the present disclosure can be performed by an RF interface receiving device according to each embodiment of the present disclosure, and for clarity, the corresponding technical details and technical effects will not be described herein.

[0172] The embodiments of the present disclosure further provide a chip including an RF interface transmitting device according to each embodiment of the present disclosure and an RF interface receiving device according to each embodiment of the present disclosure.

[0173] FIG. 20 illustrates a typical application scenario of an RF interface device according to an embodiment of the present disclosure.

[0174] 20, a chip according to an embodiment of the present disclosure may include at least one of a digital intermediate frequency chip and a radio frequency chip. The digital intermediate frequency chip and the radio frequency chip each include an RF interface transmitting device according to each embodiment of the present disclosure and an RF interface receiving device according to each embodiment of the present disclosure. The RF interface transmitting device of the digital intermediate frequency chip is connected to the RF interface receiving device of the radio frequency chip, and the RF interface transmitting device of the radio frequency chip is connected to the RF interface receiving device of the digital intermediate frequency chip.

[0175] The RF interface device according to the embodiment of the present disclosure is a variable-speed, fixed-latency, large-bandwidth, low-latency RF interface device that can be applied to a 5G base station physical layer processing chip group. A 5G base station physical layer processing chip group typically includes a baseband chip, a digital intermediate frequency chip, a radio frequency (Radio Frequency Integrated Circuit, RFIC) chip, and a radio frequency front end (RFFE) chip. The modulation and demodulation processing of 5G traffic physical layer signals is completed in the baseband chip, while functions such as digital up-conversion (DUC), digital down-conversion (DDC), power detection, crest factor reduction (CFR), and digital pre-distortion (DPD) are completed in the digital intermediate frequency chip. The radio frequency chip completes functions such as RF signal amplification, shaping and filtering, mixing / frequency selection and filtering, radio frequency switch control, analog-to-digital conversion (ADC) / digital-to-analog conversion (DAC), etc. The radio frequency front-end chip mainly completes functions such as antenna transmission and reception. As shown in FIG. 20 , the RF interface device according to the embodiment of the present disclosure is a high-speed interface for data communication between the digital intermediate frequency chip and the radio frequency chip.

[0176] In the typical application scenario shown in Figure 20, the downlink direction in the figure is the transmission direction, and the baseband chip of the base station transmits modulated and demodulated traffic data of multiple CCs to the digital intermediate frequency chip via a Common Public Radio Interface (CPRI) for processing. The digital intermediate frequency processing module in the digital intermediate frequency chip completes processes such as upconversion, peak cut, and digital predistortion, and then transmits the traffic data to the radio frequency chip via an RF interface for processing. In the embodiment of Figure 20, the digital front-end processing module in the radio frequency chip receives traffic data of k component carriers (CCs) cc1 to cck of different traffic groups in the downlink direction, where k is an integer greater than or equal to 1. In the uplink direction, the digital intermediate frequency processing module in the digital intermediate frequency chip receives traffic data of n component carriers cc1 to ccn output from the digital front-end processing module in the radio frequency chip via the RF interface, where n is an integer greater than or equal to 1. Because the uplink and downlink traffic processing by the base station physical layer is completely asymmetric, k and n are independent of each other.

[0177] The RF interface transmitter according to the embodiment of the present disclosure is located on a chip where a source is present, such as a digital intermediate frequency chip on the downlink and a radio frequency chip on the uplink in a base station system. The RF interface receiver according to the embodiment of the present disclosure is located on a chip where a sink is present, such as a radio frequency chip on the downlink and a digital intermediate frequency chip on the uplink in a base station system. Each RF interface device includes a controller and a physical layer (PHY). The RF interface transmitter includes a transmit controller and a transmit physical layer (Tx_PHY), and FIG. 21 shows the connection relationship between the transmit controller and the transmit physical layer. The RF interface receiver includes a receive controller and a receive physical layer (Rx_PHY), and FIG. 22 shows the connection relationship between the receive controller and the receive physical layer.

[0178] An embodiment of the present disclosure further provides a base station including a chip according to an embodiment of the present disclosure. An embodiment of the present disclosure further provides a terminal device including a chip according to an embodiment of the present disclosure. [Industrial Applicability]

[0179] The RF interface device according to the embodiment of the present disclosure can be applied not only to base stations but also to point-to-point traffic data transmission between a digital baseband chip and a radio frequency chip in a mobile terminal device.

[0180] Those skilled in the art will understand that all or some of the steps, systems, and functional modules / means in the devices disclosed above can be implemented as software, firmware, hardware, or a suitable combination thereof.

[0181] In hardware embodiments, the division between the functional modules / means described above does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, and one function or step may be performed by multiple physical components working together.

[0182] Some or all of the physical components may be implemented as software executed by a processor, such as a central processor (CPU), digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on computer-readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). As known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (e.g., computer-readable instructions, data structures, program modules, or other data). Computer storage media may include, but are not limited to, random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH) or other disk memory, read-only optical disks (CD-ROMs), digital versatile disks (DVDs) or other optical disk memory, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that stores the desired information and is accessible by a computer. Additionally, as known to those skilled in the art, communication media typically includes computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism and may include any information delivery media.

[0183] In this disclosure, exemplary embodiments are disclosed, and specific terms are used; however, they are to be used and interpreted in a general, illustrative sense only, and not for purposes of limitation. It will be apparent to those skilled in the art that, in some embodiments, features, characteristics, and / or elements described in connection with a particular embodiment may be used alone, or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise specified. Accordingly, those skilled in the art will recognize that various modifications in form and detail may be made without departing from the scope of the present disclosure, as defined by the appended claims.

Claims

1. 1. A radio frequency RF interface transmitter including a transmission controller having a traffic data interleaving means, a delay adjustment amount determining means, and a framer means, The traffic data interleaving means The data of the plurality of data channels is serially interleaved according to a current interleaving pattern to form interleaved data including one or more periods, the data of each data channel including a plurality of unit data blocks, the interleaving pattern indicating the corresponding number of unit data blocks of each data channel included in one period of interleaved data and the arrangement order of the unit data blocks of the plurality of data channels within one period, and the data of the plurality of data channels corresponding to multiple traffics within the one or more periods is serially interleaved according to the same interleaving pattern; The delay adjustment amount determining means determining a delay adjustment amount for each data channel corresponding to the current interleaving pattern, wherein when a position of a unit data block of one data channel in the plurality of data channels in the current interleaving pattern is offset by m unit data blocks along a first direction with respect to a position in a previous interleaving pattern, determining a history delay adjustment amount corresponding to the previous interleaving pattern of the one data channel as a delay adjustment amount corresponding to the current interleaving pattern of the one data channel after offsetting by m unit data blocks in a direction opposite to the first direction, where m is an integer equal to or greater than 1; The framer means forming a traffic frame based on the interleaved data filled as payload data in a payload area of ​​the traffic frame; configured to form a management frame including information on a delay adjustment amount of each data channel corresponding to the current interleaving pattern; Radio frequency RF interface transmitter.

2. The delay adjustment amount includes a first delay adjustment amount and a second delay adjustment amount, and the delay adjustment amount determining means when a position of a unit data block of one data channel among the plurality of data channels in the current interleaving pattern is offset by m unit data blocks along the first direction with respect to a position of the unit data block in the previous interleaving pattern, offsetting a historical first delay adjustment amount corresponding to the previous interleaving pattern of the one data channel by m unit data blocks in a direction opposite to the first direction; If the historical first delay adjustment amount after the offset is a negative number, set the first delay adjustment amount corresponding to the current interleaving pattern of the one data channel to 0, and set the difference in size between the historical second delay adjustment amount corresponding to the previous interleaving pattern of the one data channel and a first number of unit data blocks, which is the absolute value of the negative number, as the second delay adjustment amount corresponding to the current interleaving pattern of the one data channel; configured to set the offset historical first delay adjustment amount to a first delay adjustment amount corresponding to the current interleaving pattern of the one data channel when the offset historical first delay adjustment amount is not a negative number, and to set the offset historical first delay adjustment amount to be equal to a first delay adjustment amount corresponding to the current interleaving pattern of the one data channel, and to set the offset historical second delay adjustment amount corresponding to the previous interleaving pattern.

2. The RF interface transmitter of claim 1.

3. The first delay adjustment amount of each data channel is used to indicate the receiving side, and the data of the data channel obtained after deinterleaving is delayed by a time corresponding to the first delay adjustment amount and transmitted to a delay storage means corresponding to the data channel; the second delay adjustment amount of each data channel is used to instruct the receiving side, and is output when the storage of the data of the data channel in the delay storage means corresponding to the data channel reaches a storage capacity corresponding to the second delay adjustment amount; 3. The RF interface transmitter of claim 2.

4. the transmission controller further comprises an interleaving pattern determining means; The interleaving pattern determining means information of the plurality of traffics corresponding to the plurality of data channels, respectively; and user configuration information; and The management frame further includes information of the current interleaving pattern.

2. The RF interface transmitter of claim 1.

5. The interleaving pattern determining means determining the interleaving pattern so that a ratio of data amounts of the plurality of data channels in the interleaving pattern matches a ratio of transmission bandwidths of the plurality of traffics; 5. The RF interface transmitter of claim 4.

6. The traffic frame further includes validity indication information used to indicate whether data of each data channel in the interleaved data is valid; The traffic data interleaving means When there is no data in one of the plurality of data channels, invalid data is used as data of the one data channel, and a corresponding position of the unit data block of the one data channel in the interleaving pattern is filled to obtain the interleaved data; The framer means The validity indication information is further configured to indicate that the data of the one data channel is invalid.

2. The RF interface transmitter of claim 1.

7. 1. A radio frequency RF interface receiver including a receiver controller having a deframer means, a traffic data deinterleaver means, and a plurality of delay means, The traffic data deinterleaving means receiving payload data of a traffic frame provided by said deframer means; The payload data is deinterleaved based on an interleave pattern to obtain data of a plurality of data channels, the payload data including interleave data of one or more periods, and the data of each data channel including a plurality of unit data blocks, the interleave pattern indicating the corresponding number of unit data blocks of each data channel included in one period of interleave data and the arrangement order of the unit data blocks of the plurality of data channels within one period, and serially interleaving the data of the plurality of data channels corresponding to a plurality of traffics within the one or more periods using the same interleave pattern; The deframer means configured to deframe input data based on a traffic frame structure or a management frame structure to obtain a traffic frame or a management frame; when the input data is deframed to obtain the traffic frame, the deframer means transmits the payload data of the traffic frame to the traffic data deinterleaver means; When the management frame is obtained by deframing the input data, the management frame includes information on the interleaving pattern and information on a delay adjustment amount of each data channel corresponding to the interleaving pattern; The plurality of delay means correspond to the plurality of data channels, respectively, and each delay means comprises: based on the delay adjustment amount of the corresponding data channel, delaying the data of the corresponding data channel by a time corresponding to the delay adjustment amount and outputting the delayed data; Radio frequency RF interface receiver.

8. a step of serially interleaving data of a plurality of data channels based on a current interleave pattern to form interleaved data including one or more periods, the data of each data channel including a plurality of unit data blocks, the interleave pattern indicating the corresponding number of unit data blocks of each data channel included in one period of interleaved data and the arrangement order of the unit data blocks of the plurality of data channels within one period, and serially interleaving data of the plurality of data channels corresponding to a plurality of traffics, respectively, within the one or more periods, using the same interleave pattern; determining a delay adjustment amount for each data channel corresponding to the current interleaving pattern, wherein, when a position of a unit data block of one data channel in the plurality of data channels in the current interleaving pattern is offset by m unit data blocks along a first direction with respect to a position in a previous interleaving pattern, determining a history delay adjustment amount corresponding to the previous interleaving pattern of the one data channel as a delay adjustment amount corresponding to the current interleaving pattern of the one data channel after offsetting the history delay adjustment amount by m unit data blocks in a direction opposite to the first direction, where m is an integer greater than or equal to 1; forming a traffic frame based on the interleaved data, the interleaved data being filled as payload data into a payload area of ​​the traffic frame; forming a management frame including information on delay adjustment amounts for each data channel corresponding to the current interleaving pattern; transmitting the traffic frame or the management frame. A transmission method for a radio frequency RF interface.

9. The delay adjustment amounts include a first delay adjustment amount and a second delay adjustment amount, and the step of determining the delay adjustment amount of each data channel corresponding to the current interleaving pattern includes: offsetting a historical first delay adjustment amount corresponding to the previous interleaving pattern of the one data channel by m unit data blocks in a direction opposite to the first direction when a position of the unit data block of the one data channel in the current interleaving pattern is offset by m unit data blocks along the first direction with respect to a position of the unit data block in the previous interleaving pattern; when the historical first delay adjustment amount after the offset is a negative number, setting the first delay adjustment amount corresponding to the current interleaving pattern of the one data channel to 0, and setting the difference in size between the historical second delay adjustment amount corresponding to the previous interleaving pattern of the one data channel and a first number of unit data blocks, which is the absolute value of the negative number, as the second delay adjustment amount corresponding to the current interleaving pattern of the one data channel; if the offset historical first delay adjustment amount is not a negative number, setting the offset historical first delay adjustment amount to a first delay adjustment amount corresponding to the current interleaving pattern of the one data channel, and setting the second delay adjustment amount corresponding to the current interleaving pattern of the one data channel to be equal to the historical second delay adjustment amount corresponding to the previous interleaving pattern, The transmission method according to claim 8.

10. The first delay adjustment amount of each data channel is used to indicate the receiving side, and the data of the data channel obtained after deinterleaving is delayed by a time corresponding to the first delay adjustment amount and transmitted to a delay storage means corresponding to the data channel; the second delay adjustment amount of each data channel is used to instruct the receiving side, and is output when the storage of the data of the data channel in the delay storage means corresponding to the data channel reaches a storage capacity corresponding to the second delay adjustment amount; The transmission method according to claim 9.

11. information of the plurality of traffics corresponding to the plurality of data channels, respectively; User configuration information; and determining the interleaving pattern based on at least one of: The management frame further includes information of the current interleaving pattern. The transmission method according to claim 8.

12. The step of determining an interleaving pattern comprises: determining an interleaving pattern such that a ratio of data amounts of the plurality of data channels in the interleaving pattern matches a ratio of transmission bandwidths of the plurality of traffics; The transmission method according to claim 11.

13. deframing the input data based on a traffic frame structure or a management frame structure to obtain a traffic frame or a management frame; a step of deinterleaving payload data of the traffic frame based on an interleave pattern to obtain data of a plurality of data channels when the input data is deframed to obtain the traffic frame, the payload data including one or more cycles of interleaved data, the data of each data channel including a plurality of unit data blocks, the interleave pattern indicating the corresponding number of unit data blocks of each data channel included in one cycle of interleaved data and the arrangement order of the unit data blocks of the plurality of data channels within one cycle, and serially interleaving the data of the plurality of data channels, each corresponding to a plurality of traffics, using the same interleave pattern within the one or more cycles; When the management frame is obtained by deframing the input data, a step of obtaining the interleaving pattern and a delay adjustment amount of each data channel corresponding to the interleaving pattern based on the management frame; and delaying the data of each data channel by a time corresponding to the delay adjustment amount based on the delay adjustment amount of each of the plurality of data channels, and outputting the delayed data. A receiving method for a radio frequency RF interface.

14. the delay adjustment amount includes a first delay adjustment amount and a second delay adjustment amount; The step of delaying and outputting data of each data channel by a time corresponding to the delay adjustment amount based on the delay adjustment amount of each of the plurality of data channels includes: delaying the data of the data channel by a time corresponding to the first delay adjustment amount through a delay line means based on the first delay adjustment amount of the data channel, and then storing the delayed data in a delay storage means corresponding to the data channel; and outputting the stored data when the storage capacity of the data of the data channel in the delay storage means reaches a storage capacity corresponding to the second delay adjustment amount, based on the second delay adjustment amount of the data channel. The receiving method according to claim 13.

15. An RF interface transmitter according to any one of claims 1 to 6 and an RF interface receiver according to claim 7. Tips.

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