Semiconductor Devices

Abstract

To provide a semiconductor device capable of securing a creepage distance between a positive electrode terminal and a negative electrode terminal and of improving the insulation performance, in a laminate wiring structure in which the positive and negative electrode terminals are laminated via an insulation sheet.SOLUTION: A semiconductor device comprises: an insulation sheet 83 that has a first principal surface and a second principal surface; a plate-like first terminal 82 provided so as to be opposed to the first principal surface of the insulation sheet 83, having a first projection 82a protruded to the outside of the first principal surface of the insulation sheet 83; and a plate-like second terminal 81 provided so as to be opposed to the second principal surface of the insulation sheet 83, having a second projection 81a protruded to the outside of the second principal surface of the insulation sheet 83 side by side with the first projection 82a. At a position intersecting an end part 83a of the insulation sheet 83, of the first projection 82a, a first recess 82x where a lateral face opposed to the second projection 81a is recessed toward a direction separating from the second projection 81a is provided.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device (power semiconductor module) that incorporates a power semiconductor element. [Background technology]

[0002] In recent years, the global trend toward decarbonization has attracted attention to electrically powered vehicles such as electric cars and electric railway vehicles. Electrically powered vehicles require efficient motor control using power conversion devices such as inverters and converters, and power semiconductor modules are generally used for these power conversion devices. Power semiconductor modules convert DC power to AC power and vice versa. Power semiconductor modules are equipped with multiple power semiconductor elements (switching elements) such as insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs), and diodes, and perform power conversion by switching these power semiconductor elements on and off.

[0003] Power semiconductor elements incur losses during switching. Switching losses can be reduced by switching as quickly as possible. However, high-speed switching can sometimes result in overvoltage. Overvoltage not only increases losses but can also damage the power semiconductor module. Reducing the parasitic inductance of wiring—a so-called low-inductance design—is known to be an effective way to suppress overvoltage during high-speed switching. In a 2-in-1 module, in which power semiconductor elements such as IGBTs and MOSFETs are connected in series, with positive and negative terminals connected to both ends of the series and AC output terminals connected between the power semiconductor elements, low inductance can be achieved by using a laminated wiring structure in which the positive and negative terminals are laminated with an insulating sheet between them so that current flows in opposite directions.

[0004] Patent Document 1 discloses a semiconductor device having a terminal stack portion in which a first power terminal, a first insulating sheet, and a second power terminal are stacked in this order, the first power terminal having a first junction region conductively connected to a first connection terminal of a capacitor, the second power terminal having a second junction region conductively connected to a second connection terminal of the capacitor, and having a terrace portion extending in a direction from the second junction region toward the first junction region in a planar view. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent Publication No. 2021-106235 Summary of the Invention [Problem to be solved by the invention]

[0006] In a power semiconductor module with a laminated wiring structure, inside a case that houses a power semiconductor element, the positive and negative terminals protrude inward beyond the ends of an insulating sheet, and the protruding portions are electrically connected to the power semiconductor element. The positive and negative terminals are sealed with a resin filled inside the case. However, if the resin sealing the positive and negative terminals peels off, the creepage distance of the positive and negative terminals may become insufficient.

[0007] In view of the above problems, an object of the present invention is to provide a semiconductor device that can ensure a creepage distance between a positive electrode terminal and a negative electrode terminal in a laminate wiring structure in which a positive electrode terminal and a negative electrode terminal are stacked via an insulating sheet, thereby improving insulation performance. [Means for solving the problem]

[0008] One aspect of the present invention is a semiconductor device comprising: (a) an insulating sheet having a first main surface and a second main surface; (b) a plate-shaped first terminal provided opposite the first main surface of the insulating sheet and having a first protrusion that protrudes outward from the first main surface of the insulating sheet; and (c) a plate-shaped second terminal provided opposite the second main surface of the insulating sheet and having a second protrusion that protrudes alongside the first protrusion outward from the second main surface of the insulating sheet, wherein a first recess is provided at a position where the first protrusion intersects with an end of the insulating sheet, where the side surface facing the second protrusion is recessed in a direction away from the second protrusion. [Effects of the Invention]

[0009] According to the present invention, it is possible to provide a semiconductor device that can ensure the creepage distance between the positive electrode terminal and the negative electrode terminal in a laminate wiring structure in which the positive electrode terminal and the negative electrode terminal are stacked via an insulating sheet, thereby improving insulation performance. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a plan view of a semiconductor device according to a first embodiment. [Figure 2] 2 is a plan view of a positive electrode terminal of the semiconductor device according to the first embodiment. FIG. [Figure 3] FIG. 2 is a plan view of a negative electrode terminal of the semiconductor device according to the first embodiment. [Figure 4] FIG. 2 is a cross-sectional view taken along the AA direction in FIG. [Figure 5] FIG. 2 is a cross-sectional view seen from the direction BB in FIG. [Figure 6] FIG. 2 is a cross-sectional view seen from the CC direction in FIG. [Figure 7] 1 is a circuit diagram of a semiconductor device according to a first embodiment. [Figure 8] FIG. 10 is a plan view of a semiconductor device according to a comparative example. [Figure 9] FIG. 9 is a cross-sectional view seen from the CC direction in FIG. 8. [Figure 10] FIG. 10 is a plan view of a semiconductor device according to a second embodiment. [Figure 11]FIG. 11 is a cross-sectional view taken along the AA direction in FIG. [Figure 12] FIG. 11 is a cross-sectional view seen from the direction BB in FIG. [Figure 13] FIG. 11 is a cross-sectional view taken along the CC direction in FIG. [Figure 14] FIG. 10 is a cross-sectional view of a semiconductor device according to a third embodiment. [Figure 15] FIG. 10 is another cross-sectional view of the semiconductor device according to the third embodiment. [Figure 16] FIG. 10 is a plan view of a semiconductor device according to a fourth embodiment. [Figure 17] FIG. 17 is a cross-sectional view taken along the AA direction in FIG. [Figure 18] FIG. 17 is a cross-sectional view seen from the direction BB in FIG. 16. [Figure 19] FIG. 10 is a plan view of a semiconductor device according to a fifth embodiment. [Figure 20] FIG. 20 is a cross-sectional view taken along the AA direction in FIG. 19. [Figure 21] FIG. 20 is a cross-sectional view seen from the direction BB in FIG. 19. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, first to fifth embodiments of the present invention will be described with reference to the drawings. In the drawings referred to in the following description, the same or similar parts are designated by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc., differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. Furthermore, it goes without saying that the drawings also include parts with different dimensional relationships and ratios.

[0012] In addition, the definitions of directions such as "up," "down," "up and down," "left," "right," and "left and right" in the following description are merely definitions for the convenience of explanation and do not limit the technical concept of the present invention. For example, if an object is rotated 90 degrees and observed, "up and down" is converted and read as "left and right," and of course, if it is rotated 180 degrees and observed, "up and down" is read inverted. Furthermore, "top surface" and "bottom surface" may be read as "front surface" and "back surface," respectively.

[0013] Furthermore, in this specification, a "first terminal" refers to either the positive or negative terminal of a power semiconductor module, and a "second terminal" refers to the other of the positive and negative terminals of a power semiconductor module, which is different from the "first terminal." That is, if the "first terminal" is the positive terminal of a power semiconductor module, the "second terminal" is the negative terminal of the power semiconductor module, and if the "first terminal" is the negative terminal of a power semiconductor module, the "second terminal" is the positive terminal of the power semiconductor module. Furthermore, the "first main surface" and the "second main surface" of each member are main surfaces that face each other; for example, if the "first main surface" is the upper surface, the "second main surface" is the lower surface.

[0014] (First embodiment) <Structure of semiconductor device> As shown in Fig. 1, the semiconductor device (power semiconductor module) according to the first embodiment includes an insulating circuit board 1, power semiconductor elements (semiconductor chips) 3a to 3l mounted on the insulating circuit board 1, and a case 7 arranged to surround the insulating circuit board 1 and the power semiconductor elements 3a to 3l. Fig. 1 does not show the sealing material arranged inside the case 7 to seal the power semiconductor elements 3a to 3l, etc. Also, in Fig. 1, connection points of bonding wires connected to the power semiconductor elements 3a to 3l, etc. are schematically shown by black circles.

[0015] In the plan view shown in Fig. 1, the longitudinal direction of the semiconductor device according to the first embodiment is defined as the X-axis, and the rightward direction in Fig. 1 is defined as the positive direction of the X-axis. The lateral direction of the semiconductor device according to the embodiment, which is orthogonal to the X-axis, is defined as the Y-axis, and the upward direction in Fig. 1 is defined as the positive direction of the Y-axis. The direction orthogonal to the X-axis and Y-axis is defined as the Z-axis, and the front side in Fig. 1 is defined as the positive direction of the Z-axis. The same applies to Fig. 2 and subsequent figures.

[0016] 1 illustrates a 2-in-1 power semiconductor module in which two pairs of six parallel MOSFETs are connected in series as the power semiconductor elements 3a-3l. The power semiconductor elements 3a-3f form an upper arm for one phase of a three-phase inverter circuit, and the power semiconductor elements 3g-3l form a lower arm. Note that the semiconductor device according to the first embodiment is not limited to a 2-in-1 semiconductor module as long as it is a power semiconductor module having a positive terminal 81 and a negative terminal 82, and may also be, for example, a 1-in-1 or 6-in-1 semiconductor module.

[0017] The power semiconductor elements 3a to 3l each have a semiconductor substrate, a first main electrode (drain electrode) provided on the lower surface of the semiconductor substrate, and a second main electrode (source electrode) and a control electrode (gate electrode) provided on the upper surface of the semiconductor substrate. The semiconductor substrate is made of, for example, silicon (Si), silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), or the like. The arrangement positions and number of the power semiconductor elements 3a to 3l are not particularly limited. The power semiconductor elements 3a to 3l may be field effect transistors (FETs) such as MOSFETs, as well as insulated gate bipolar transistors (IGBTs), static induction (SI) thyristors, gate turn-off (GTO) thyristors, or the like.

[0018] The insulating circuit board 1 is formed, for example, by a direct copper bonding (DCB) substrate or an active matrix solder (AMD) substrate. The insulating circuit board 1 includes an insulating substrate 10, conductor foils (upper conductor foils) 11a-11j arranged on the upper surface of the insulating substrate 10, and a conductor foil (lower conductor foil) 12 arranged on the lower surface of the insulating substrate 10 (see FIGS. 4 and 5 for the lower conductor foil 12). The insulating substrate 10 can be a ceramic plate mainly made of aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4), boron nitride (BN), or the like, or a resin insulating layer made of a polymer material or the like. When a resin insulating layer is used as the insulating substrate 10, the lower conductor foil 12 on the lower surface of the insulating substrate 10 may be omitted. The upper conductor foils 11a-11j and the lower conductor foil 12 are made of, for example, copper (Cu), aluminum (Al), or the like. The upper conductor foils 11a to 11j are formed in an arbitrary pattern and constitute a circuit pattern.

[0019] 1, power semiconductor elements 3a to 3f are bonded to upper conductor foil 11b of insulating circuit board 1 via a bonding material such as solder or a sintered material. Power semiconductor elements 3g to 3l are bonded to upper conductor foil 11h of insulating circuit board 1 via a bonding material such as solder or a sintered material.

[0020] A case 7 is disposed so as to surround the power semiconductor elements 3a to 3f and the insulating circuit board 1. The case 7 can be made of a resin material such as polyphenylene sulfide (PPS), polybutylene terephthalate (PBT), polybutylene succinate (PBS), epoxy, or phenol.

[0021] Control terminals 7a to 7i are provided on the case 7. The control terminal 7c is connected to the upper conductor foil 11f via a bonding wire. The upper conductor foil 11f is electrically connected to the source electrodes of the power semiconductor elements 3a to 3f via bonding wires. The control terminal 7c detects the current flowing through the source electrodes of the power semiconductor elements 3a to 3f.

[0022] The control terminal 7d is connected to the upper conductor foil 11g via a bonding wire. The upper conductor foil 11g is electrically connected to the gate electrodes of the power semiconductor elements 3a to 3f via bonding wires. The control terminal 7d applies a control signal to the gate electrodes of the power semiconductor elements 3a to 3f.

[0023] The control terminal 7g is connected to the upper conductor foil 11i via a bonding wire. The upper conductor foil 11i is connected to the source electrodes of the power semiconductor elements 3g to 3l via bonding wires. The control terminal 7g detects the current flowing through the source electrodes of the power semiconductor elements 3g to 3l.

[0024] The control terminal 7h is connected to the upper conductor foil 11j via a bonding wire. The upper conductor foil 11j is electrically connected to the gate electrodes of the power semiconductor elements 3g to 3l via a bonding wire. A control signal is applied to the gate electrodes of the power semiconductor elements 3g to 3l via the control terminal 7h.

[0025] Case 7 is provided with a plate-shaped output terminal 80, and plate-shaped positive and negative terminals 81 and 82 arranged opposite output terminal 80. Output terminal 80 is connected to upper conductor foil 11b. Upper conductor foil 11b is electrically connected to the drain electrodes of power semiconductor elements 3a to 3f. Upper conductor foil 11b is also electrically connected to the source electrodes of power semiconductor elements 3g to 3l via lead frames 6g to 6l.

[0026] The positive electrode terminal 81 and the negative electrode terminal 82 are used as terminals with different potentials. The positive electrode terminal 81 is electrically connected to the upper conductor foil 11h. The upper conductor foil 11h is electrically connected to the drain electrodes of the power semiconductor elements 3e to 3h. The negative electrode terminal 82 is electrically connected to the upper conductor foils 11a and 11e. The upper conductor foil 11a is electrically connected to the source electrodes of the power semiconductor elements 3a to 3c via the lead frames 6a to 6c. The upper conductor foil 11e is electrically connected to the source electrodes of the power semiconductor elements 3d to 3f via the lead frames 6d to 6f.

[0027] FIG. 2 shows the planar pattern of the positive electrode terminal 81. As shown in FIG. 2, the positive electrode terminal 81 has, in the planar pattern, protrusions 81a and 81b extending parallel to and spaced from each other, and a main body 81c connected to the protrusions 81a and 81b. A recess (cutout) 81x is provided on the side surface opposite to the side facing the protrusion 81b in the direction (short side) perpendicular to the extension direction of the protrusion 81a. A recess (cutout) 81y is provided on the side surface opposite to the side facing the protrusion 81a in the direction (short side) perpendicular to the extension direction of the protrusion 81b. The recesses 81x and 81y have a semicircular planar pattern. The planar pattern shape of the recesses 81x and 81y is not particularly limited, and may be, for example, a polygonal planar pattern shape such as a rectangle.

[0028] 1, protrusions 81a and 81b extend from inside case 7 to the outside of insulating sheet 83 and are electrically connected to upper conductor foil 11h. Recess 81x of protrusion 81a is provided at a position where protrusion 81a intersects with end 83a of insulating sheet 83, such that the side surface facing protrusion 82a is recessed in a direction away from protrusion 82a. Recess 81y of protrusion 81b is provided at a position where protrusion 81b intersects with end 83a of insulating sheet 83, such that the side surface facing protrusion 82b is recessed in a direction away from protrusion 82b.

[0029] FIG. 3 shows the planar pattern of the negative electrode terminal 82. As shown in FIG. 3, the negative electrode terminal 82 has, in the planar pattern, protrusions 82a and 82b extending parallel to and spaced from each other, and a main body 82c connected to the protrusions 82a and 82b. A recess (cutout) 82x is provided on the side surface of the protrusion 82a facing the protrusion 82b in the direction perpendicular to the extension direction (short side direction). A recess (cutout) 82y is provided on the side surface of the protrusion 82b facing the protrusion 82a in the direction perpendicular to the extension direction (short side direction). The recesses 82x and 82y have a semicircular planar pattern. The planar pattern shape of the recesses 82x and 82y is not particularly limited and may be a polygonal planar pattern shape such as a rectangle. The planar pattern shape of the recesses 82x and 82y may be the same as or different from the planar pattern shape of the recesses 81x and 81y.

[0030] 1, protrusions 82a and 82b extend from the insulating sheet 83 inside the case 7 and are electrically connected to the upper conductor foil 11e. Recess 82x of protrusion 82a is provided at the position where protrusion 82a intersects with end 83a of insulating sheet 83, such that the side surface facing protrusion 81a is recessed in the direction away from protrusion 81a. Recess 82y of protrusion 82b is provided at the position where protrusion 82b intersects with end 83a of insulating sheet 83, such that the side surface facing protrusion 81b is recessed in the direction away from protrusion 81b.

[0031] The shape of the planar pattern of the insulating sheet 83 corresponds to the shape of the planar patterns of the positive electrode terminal 81 and the negative electrode terminal 82. In order to ensure the necessary insulation creepage distance between the positive electrode terminal 81 and the negative electrode terminal 82, the outer edge (end) of the insulating sheet 83 has dimensions larger than the outer edges (ends) of the positive electrode terminal 81 and the negative electrode terminal 82.

[0032] FIG. 4 shows a cross section seen from the direction AA passing through the protruding portion 81a of the positive electrode terminal 81 in FIG. 1. As shown in FIG. 4, the insulating circuit board 1 and the power semiconductor elements 3a-3l inside the case 7 are sealed with a sealing material 9. The sealing material 9 can be an insulating sealing resin such as a thermosetting silicone gel or an epoxy resin. A cooling body (base) 2 is disposed on the underside of the insulating circuit board 1. The cooling body 2 can be made of a material with high thermal conductivity, such as copper (Cu), aluminum (Al), a composite material of Al and silicon carbide (AlSiC), or a composite material of magnesium (Mg) and silicon carbide (MgSiC).

[0033] As shown in FIG. 4 , an insulating sheet 83 is disposed between the upper surface of the positive terminal 81 and the lower surface of the negative terminal 82. That is, the positive terminal 81 and the negative terminal 82 are stacked from the inside to the outside of the power semiconductor module via the insulating sheet 83 to form a laminated wiring structure. At least a portion of the main body 81c of the positive terminal 81 and at least a portion of the main body 82c of the negative terminal 82 face each other via the insulating sheet 83. The facing distance between the positive terminal 81 and the negative terminal 82 is constant by the thickness of the insulating sheet 83. Currents flow in opposite directions through the positive terminal 81 and the negative terminal 82, which reduces the parasitic inductance of the wiring.

[0034] The positive electrode terminal 81 and the negative electrode terminal 82 can be made of copper (Cu), a Cu alloy, aluminum (Al), an Al alloy, or the like. The positive electrode terminal 81 is electrically connected to the upper conductor foil 11h via a conductive block (spacer) 5a made of copper (Cu) or the like for height adjustment. The protrusion 81a of the positive electrode terminal 81 and the main body 82c of the negative electrode terminal 82 are separated by a creepage distance L11. The creepage distance L11 is the sum of the distance from the end of the main body 82c to the end 83a of the insulating sheet 83 and the thickness of the insulating sheet 83.

[0035] As the insulating sheet 83, a sheet having high insulating and heat-resistant properties, such as insulating paper or polyimide or polyamide, can be used. The thickness of the insulating sheet 83 depends on the rated voltage of the power semiconductor module, but when the rated voltage is 1200 V, it is set to 0.1 mm or more and 1.0 mm or less. More preferably, by setting the thickness to 0.2 mm or more and 0.6 mm or less, the wiring inductance between the positive electrode terminal 81 and the negative electrode terminal 82 can be significantly reduced.

[0036] FIG. 5 shows a cross section of the negative terminal 82 of FIG. 1, viewed from the direction BB passing through the protruding portion 82a. As shown in FIG. 5, the negative terminal 82 is electrically connected to the upper conductor foil 11e via a conductive block (spacer) 5b made of copper (Cu) or the like for height adjustment. Because the distance between the negative terminal 82 and the insulating circuit board 1 is greater than the distance between the positive terminal 81 and the insulating circuit board 1, the height of the spacer 5b connected to the negative terminal 82 is greater than the height of the spacer 5a connected to the positive terminal 81. The main body 81c of the positive terminal 81 and the protruding portion 82a of the negative terminal 82 are separated by a creepage distance L12. The creepage distance L12 is the sum of the distance from the end of the main body 81c to the end 83a of the insulating sheet 83 and the thickness of the insulating sheet 83.

[0037] FIG. 6 shows a cross section seen from the CC direction passing through the recesses 81x of the protrusion 81a, the recesses 81y of the protrusion 81b, the recesses 82x of the protrusion 82a, and the recesses 82y of the protrusion 82b in FIG. 1. As shown in FIG. 6, the protrusion 81a of the positive electrode terminal 81 and the protrusion 82a of the negative electrode terminal 82 are spaced apart by a creepage distance L13. The creepage distance L13 is the sum of the horizontal distance between the side surface of the portion of the protrusion 81a where the recess 81x is not present and the side surface of the portion of the protrusion 82a where the recess 82x is not present, a distance r1 which is the radius of the semicircle formed by the recess 81x of the protrusion 81a, a distance r2 which is the radius of the semicircle formed by the recess 82x of the protrusion 82a, and the thickness of the insulating sheet 83. The protrusion 81b of the positive electrode terminal 81 and the protrusion 82b of the negative electrode terminal 82 are spaced apart by a creepage distance L14. Creepage distance L14 is the sum of the horizontal distance between the side surface of the portion of protrusion 81b where recess 81y is not present and the side surface of the portion of protrusion 82b where recess 82y is not present, distance r1 which is the radius of the semicircle formed by recess 81y of protrusion 81b, distance r2 which is the radius of the semicircle formed by recess 82y of protrusion 82b, and the thickness of insulating sheet 83. Distances r1 and r2 are, for example, about 0.5 mm or more and 2 mm or less, but are not limited to this.

[0038] The creepage distances L11 to L14 are set to the same value and are the shortest distance along the surface of the insulating sheet 83 between the positive terminal 81 and the negative terminal 82. The creepage distances L11 to L14 are, for example, approximately 2 mm or more and 15 mm or less, but can be adjusted appropriately depending on the withstand voltage of the semiconductor device according to the first embodiment. For example, the creepage distances L11 to L14 may be 3 mm or more and 14.5 mm or less. Alternatively, the creepage distances L11 to L14 may be 6 mm or more and 12.5 mm or less. Furthermore, this distance may be 7.5 mm plus a tolerance of 0.5 mm when the withstand voltage is 750 V, or 12 mm plus a tolerance of 0.5 mm when the withstand voltage is 1200 V. Note that the creepage distances L11 to L14 do not have to be equal to each other. For example, the creepage distances L11 and L12 may be set to the shortest distance, and the creepage distances L13 and L14 may be longer than the creepage distances L11 and L12.

[0039] FIG. 7 shows an equivalent circuit of the semiconductor device according to the first embodiment. As shown in FIG. 7, the semiconductor device according to the embodiment constitutes part of a three-phase bridge circuit. The drain electrode of the upper arm transistor T1 is connected to the positive terminal P, and the source electrode of the lower arm transistor T2 is connected to the negative terminal N. The source electrode of the transistor T1 and the drain electrode of the transistor T2 are connected to the output terminal U and the auxiliary source terminal S1, respectively. The source electrode of the transistor T2 is connected to the auxiliary source terminal S2. The gate electrodes of the transistors T1 and T2 are connected to the gate control terminals G1 and G2. The transistors T1 and T2 have built-in body diodes D1 and D2 connected in anti-parallel and serving as freewheeling diodes (FWD).

[0040] The output terminal U, the positive terminal P, and the negative terminal N shown in Fig. 7 correspond to the output terminal 80, the positive terminal 81, and the negative terminal 82 shown in Fig. 1. The transistor T1 and the body diode D1 shown in Fig. 7 correspond to the power semiconductor elements 3a to 3f shown in Fig. 1. The transistor T2 and the body diode D2 shown in Fig. 7 correspond to the power semiconductor elements 3g to 3l shown in Fig. 1. The gate control terminals G1 and G2 shown in Fig. 7 correspond to the control terminals 7d and 7h shown in Fig. 1, and the auxiliary source terminals S1 and S2 shown in Fig. 7 correspond to the control terminals 7c and 7g shown in Fig. 1.

[0041] Here, a semiconductor device according to a comparative example will be described. As shown in FIG. 8 , the semiconductor device according to the comparative example differs from the semiconductor device according to the first embodiment in that no recesses are provided on the protrusions 81a and 81b of the positive terminal 81 and the protrusions 82a and 82b of the negative terminal 82. A cross section viewed from the CC direction in FIG. 8 is shown in FIG. 9. As shown in FIG. 9 , the protrusion 81a of the positive terminal 81 and the protrusion 82a of the negative terminal 82 are spaced apart by a creepage distance L21. The creepage distance L21 is the sum of the horizontal distance between the side surfaces of the protrusions 81a and 82a and the thickness of the insulating sheet 83. The protrusion 81b of the positive terminal 81 and the protrusion 82b of the negative terminal 82 are spaced apart by a creepage distance L22. The creepage distance L22 is the sum of the distance between the protrusions 81b and 82b and the thickness of the insulating sheet 83. In the semiconductor device according to the comparative example, when the sealing material 9 sealing the protrusions 81a, 81b, 82a, and 82b peels off, the creepage distances L22 and L23 may become insufficient.

[0042] In contrast, according to the semiconductor device of the first embodiment, recesses 81x and 81y are provided in the protrusions 81a and 81b of the positive terminal 81, and recesses 82x and 82y are provided in the protrusions 82a and 82b of the negative terminal 82. As a result, as shown in FIG. 6, the creepage distance L13 between the protrusion 81a of the positive terminal 81 and the protrusion 82a of the negative terminal 82, and the circular distance L14 between the protrusion 81b of the positive terminal 81 and the protrusion 82b of the negative terminal 82 can be increased by the distance r1 of the recess 81y and the distance r2 of the recess 82y, respectively, thereby improving the insulation performance.

[0043] <Method of manufacturing a semiconductor device> Next, an example of a method for manufacturing the semiconductor device according to the first embodiment will be described with reference to Figures 1 to 6. The lower conductor foil 12 of the insulating circuit board 1 shown in Figures 4 and 5 is joined to the cooling body 2 using a joining material such as solder or a sintered material. Furthermore, the drain electrodes on the lower surfaces of the power semiconductor elements 3a to 3l are joined to the upper conductor foils 11b and 11h of the insulating circuit board 1 shown in Figure 1 using a joining material such as solder or a sintered material.

[0044] Next, the source electrodes on the upper surfaces of the power semiconductor elements 3a to 3l are electrically connected to the upper conductor foils 11a, 11b, and 11e using lead frames 6a to 6l made of copper (Cu), aluminum (Al), or the like, with a bonding material such as solder or a sintered material. This electrical connection may be achieved by ultrasonic bonding of wires, ribbons, or the like. The gate electrodes on the upper surfaces of the power semiconductor elements 3a to 3l have a small current capacity, so they are electrically connected to the upper conductor foils 11g and 11j by wire bonding of aluminum (Al) or the like.

[0045] Next, an insulating sheet 83 is prepared, and using a mold or the like, the insulating sheet 83 is formed into a shape corresponding to the shapes of the positive electrode terminal 81 and the negative electrode terminal 82. The positive electrode terminal 81 and the negative electrode terminal 82 are formed by punching out using a mold from a copper (Cu) plate or the like. At this time, recesses 81x and 81y in the protruding portions 81a and 81b of the positive electrode terminal 81 and recesses 82x and 82y in the protruding portions 82a and 82b of the negative electrode terminal 82 are also formed.

[0046] Next, insulating sheet 83 is sandwiched between positive terminal 81 and negative terminal 82, and the laminated structure is attached to a molding die, and at the same time, output terminal 80 and control terminals 7a to 7i are attached to the molding die. Then, using a resin material, case 7 is molded into which positive terminal 81, negative terminal 82, output terminal 80, and control terminals 7a to 7i are inserted, and positive terminal 81, negative terminal 82, output terminal 80, and control terminals 7a to 7i are integrated with case 7.

[0047] Next, the case 7, into which the positive terminal 81, the negative terminal 82, the output terminal 80, etc. are insert-molded, and the cooling body 2 are bonded to surround the insulated circuit board 1 and the power semiconductor elements 3a-3l. The positive terminal 81, the negative terminal 82, and the output terminal 80 are joined to the upper conductor foils 11a, 11b, 11e, and 11h via the spacers 5a, 5b, etc. For example, a joining material such as solder may be used to join the spacers 5a, 5b, etc. to the upper conductor foils 11a, 11b, 11e, and 11h, and laser welding may be used to join the spacers 5a, 5b, etc. to the positive terminal 81, the negative terminal 82, and the output terminal 80. The control terminals 7c, 7d, 7g, and 7h are electrically connected to the upper conductor foils 11f, 11g, 11i, and 11j by wire bonding or the like.

[0048] Next, the area surrounded by the cooling body 2 and the case 7 is sealed with a sealing material 9 such as a sealing resin so as to protect the insulating circuit board 1 and the power semiconductor elements 3a to 3l, etc. This completes the semiconductor device according to the first embodiment.

[0049] (Second embodiment) 10, the semiconductor device according to the second embodiment differs from the semiconductor device according to the first embodiment in that the positive terminal 81 has one protrusion 81a. The width and thickness of the one protrusion 81a can be adjusted appropriately depending on the current capacity of the power semiconductor elements 3a to 3l. Furthermore, in the semiconductor device according to the second embodiment, the end 83a of the insulating sheet 83 extends further toward the inside of the case 7 than in the semiconductor device according to the first embodiment.

[0050] Recesses 81x and 81y are provided at the position where protrusion 81a intersects with end 83a of insulating sheet 83. Recess 81x has a shape in which the side surface of protrusion 81a facing protrusion 82a is recessed in a direction away from protrusion 82a. Recess 81y has a shape in which the side surface of protrusion 81a facing protrusion 82b is recessed in a direction away from protrusion 82b.

[0051] Fig. 11 shows a cross section seen from the direction AA passing through the protruding portion 81a of the positive terminal 81 in Fig. 10. As shown in Fig. 11, the protruding portion 81a of the positive terminal 81 and the main body portion 82c of the negative terminal 82 are separated by a creepage distance L31. Because the end portion 83a of the insulating sheet 83 extends toward the inside of the case 7, the creepage distance L31 is longer than the creepage distance L11 in the semiconductor device according to the first embodiment.

[0052] 12 shows a cross section seen from the direction BB passing through the protrusion 82a of the negative electrode terminal 82 in Fig. 10. As shown in Fig. 12, the main body 81c of the positive electrode terminal 81 and the protrusion 82a of the negative electrode terminal 82 are separated by a creepage distance L32. Because the end 83a of the insulating sheet 83 extends toward the inside of the case 7, the creepage distance L32 is longer than the creepage distance L12 in the semiconductor device according to the first embodiment.

[0053] 13 shows a cross section seen from the AA direction passing through the recesses 81x and 81y of the protrusion 81a, the recess 82x of the protrusion 82a, and the recess 82y of the protrusion 82b in FIG. 10. As shown in FIG. 13, the protrusion 81a of the positive electrode terminal 81 and the protrusion 82a of the negative electrode terminal 82 are separated by a creepage distance L33. The creepage distance L33 is the sum of the horizontal distance between the side surface of the portion of the protrusion 81a where the recess 81x is not present and the side surface of the portion of the protrusion 82a where the recess 82x is not present, the radius r1 of the semicircle formed by the recess 81x of the protrusion 81a, the radius r2 of the semicircle formed by the recess 82x of the protrusion 82a, and the thickness of the insulating sheet 83. The protrusion 81a of the positive electrode terminal 81 and the protrusion 82b of the negative electrode terminal 82 are separated by a creepage distance L34. Creepage distance L34 is the sum of the horizontal distance between the side surface of the portion of protrusion 81a where there is no recess 81y and the side surface of the portion of protrusion 82b where there is no recess 82y, the radius r1 of the semicircle formed by recess 81y of protrusion 81a, the radius r2 of the semicircle formed by recess 82y of protrusion 82b, and the thickness of insulating sheet 83. Because there is one protrusion 81, creepage distances L33 and L34 are longer than creepage distances L13 and L14 in the semiconductor device according to the first embodiment.

[0054] For example, the creepage distances L33 and L34 are set to be greater than the creepage distances L31 and L32. Alternatively, the creepage distances L31, L32, L33, and L34 may be set to be equal to each other. Other configurations of the semiconductor device according to the second embodiment are substantially the same as those of the semiconductor device according to the first embodiment, and therefore, redundant description will be omitted.

[0055] The semiconductor device according to the second embodiment has the same effects as the semiconductor device according to the first embodiment. Furthermore, compared to the semiconductor device according to the first embodiment, the semiconductor device according to the second embodiment has only one protrusion 81a of the positive electrode terminal 81, so that the creepage distances L33 and L34 can be made longer. Therefore, by extending the insulating sheet 83 toward the inside of the case 7 in conjunction with the increase in the creepage distances L33 and L34, the creepage distances L31 and L32 can also be made longer.

[0056] (Third embodiment) 14, the semiconductor device according to the third embodiment differs from the semiconductor device according to the first embodiment in that the protruding portion 82a of the negative electrode terminal 82 is bent in an N-shape or a Z-shape and is directly joined to the upper conductor foil 11e without a spacer. The protruding portion 82a is bent downward from the position of the recess 82x of the end portion 83a of the insulating sheet 83 shown in FIG.

[0057] Protrusion 82a is joined to upper conductor foil 11e by, for example, ultrasonic bonding or laser welding. When ultrasonic bonding is used, the joint between protrusion 82a and upper conductor foil 11e can be shaped like comb teeth, thereby reducing damage to insulating circuit board 1 caused by ultrasonic bonding. When laser welding is used, the thickness of the joint between protrusion 82a and upper conductor foil 11e can be made thinner than the thickness of upper conductor foil 11e, thereby reducing damage to insulating circuit board 1 caused by laser welding.

[0058] 15, the semiconductor device according to the third embodiment may have a configuration in which a recess 13 is provided in the upper conductor foil 11e. The joint portion of the protrusion 82a is embedded in and joined to the recess 13 of the upper conductor foil 11e. Other configurations of the semiconductor device according to the third embodiment are substantially the same as those of the semiconductor device according to the first embodiment, and therefore, redundant explanations will be omitted.

[0059] The semiconductor device according to the third embodiment has the same effects as the semiconductor device according to the first embodiment. Furthermore, by bending the protrusion 82a starting from the position of the recess 82x of the protrusion 82a, the protrusion 82a can be easily bent. Furthermore, by providing the recess 13 in the upper conductor foil 11e, the joint of the protrusion 82a can be easily aligned with the recess 13.

[0060] (Fourth embodiment) 16, the semiconductor device according to the fourth embodiment differs from the semiconductor device according to the first embodiment in that the inner edge of the case 7 extends to the positions of the recess 81x of the protrusion 81a, the recess 81y of the protrusion 81b, the recess 82x of the protrusion 82a, and the recess 82y of the protrusion 82b so as to cover the edge of the insulating sheet 83. Note that in FIG. 16, the inner edge of the case 7 may be further extended to cover the recess 81x of the protrusion 81a, the recess 81y of the protrusion 81b, the recess 82x of the protrusion 82a, and the recess 82y of the protrusion 82b.

[0061] FIG. 17 shows a cross section seen from the AA direction in FIG. 16 . As shown in FIG. 17 , the end of the case 7 coincides with the end 83a of the insulating sheet 83 and covers the end of the main body 82 of the negative electrode terminal 82. Note that in FIG. 17 , the end of the case 7 may extend further inward beyond the end 83a of the insulating sheet 83 to cover the end 83a of the insulating sheet 83. FIG. 18 shows a cross section seen from the BB direction in FIG. 16 . As shown in FIG. 18 , the end of the case 7 coincides with the end 83a of the insulating sheet 83 and covers the main body 81c of the positive electrode terminal 81. Note that in FIG. 18 , the end of the case 7 may extend further inward beyond the end 83a of the insulating sheet 83 to cover the end 83a of the insulating sheet 83. Other configurations of the semiconductor device according to the fourth embodiment are substantially similar to those of the semiconductor device according to the first embodiment, and therefore, redundant description will be omitted.

[0062] The semiconductor device according to the fourth embodiment has the same effects as the semiconductor device according to the first embodiment. Furthermore, the case 7 can insulate the protrusion 81 a of the positive terminal 81 from the main body 82 c of the negative terminal 82, and the main body 81 c of the positive terminal 81 from the protrusion 82 a of the negative terminal 82.

[0063] (Fifth embodiment) 19, the semiconductor device according to the fifth embodiment differs from the semiconductor device according to the second embodiment in that a recess 82z is provided in a main body 82c of a negative electrode terminal 82. The recess 82z is provided so as to recess the side surface of the main body 82c facing the protrusion 81a in a direction away from the protrusion 81a in a planar pattern.

[0064] Fig. 20 shows a cross section seen from the direction AA in Fig. 19. As shown in Fig. 20, by providing the recess 82z in the main body 82c of the negative electrode terminal 82, the creepage distance L51 between the protrusion 81a of the positive electrode terminal 81 and the main body 82c of the negative electrode terminal 82 can be made longer than the creepage distance L31 in the semiconductor device according to the second embodiment.

[0065] 21 shows a cross section seen from the direction BB in FIG. 19. As shown in FIG. 21, a recess 81z is also provided in the main body 81c of the positive electrode terminal 81. The planar pattern shape of the recess 81z is the same as the planar pattern shape of the recess 82z shown in FIG. 19. In the planar pattern, the recess 81z is provided such that the side surface facing the protrusion 82a of the main body 81c is recessed in a direction away from the protrusion 82a. By providing the recess 81z in the main body 81c of the positive electrode terminal 81, the creepage distance L52 between the main body 81c of the positive electrode terminal 81 and the protrusion 82a of the negative electrode terminal 82 can be made longer than the creepage distance L32 in the semiconductor device according to the second embodiment.

[0066] A recess similar to recess 81z is also provided on the side surface of main body 81c of positive terminal 81 shown in Fig. 19 facing protrusion 82b, so as to be recessed in a direction away from protrusion 82b. The other configurations of the semiconductor device according to the fifth embodiment are substantially the same as those of the semiconductor device according to the second embodiment, and therefore, redundant explanations will be omitted.

[0067] The semiconductor device according to the fifth embodiment has the same effects as the semiconductor device according to the second embodiment. Furthermore, according to the semiconductor device according to the fifth embodiment, the recess 82z is provided in the main body 82c of the negative terminal 82, and the recess 81z is provided in the main body 81c of the positive terminal 81, thereby making it possible to lengthen the creepage distances L51 and L52.

[0068] (Other embodiments) As described above, the present invention has been described with reference to the first to fifth embodiments, but the descriptions and drawings that form part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

[0069] For example, in the first to fifth embodiments, a laminate wiring structure in which the positive electrode terminal 81 is on the lower side and the negative electrode terminal 82 is on the upper side is exemplified, but the positional relationship between the positive electrode terminal 81 and the negative electrode terminal 82 may be reversed, and a laminate wiring structure in which the positive electrode terminal 81 is on the upper side and the negative electrode terminal 82 is on the lower side may also be used.

[0070] In the first embodiment, either the recesses 81x, 81y of the protrusions 81a, 81b of the positive electrode terminal 81 or the recesses 82x, 82y of the protrusions 82a, 82b of the negative electrode terminal 82 may be absent. In the second embodiment, either the recesses 81x, 81y of the protrusion 81a of the positive electrode terminal 81 or the recesses 82x, 82y of the protrusions 82a, 82b of the negative electrode terminal 82 may be absent.

[0071] As such, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention-specifying matters according to the scope of the claims that are appropriate from the above description. [Explanation of symbols]

[0072] 1...Insulated circuit board 2...Cooling body (base) 3a to 3l: Power semiconductor elements (semiconductor chips) 5a, 5b...Spacer 6a~6l...Lead frame 7. Case 7a~7i...Control terminals 9...Sealing material 10...Insulating substrate 11a to 11j...Conductor foil (upper conductor foil) 12...Conductor foil (lower conductor foil) 13...Recess 80...Output terminal 81...Positive terminal 81a, 81b, 82a, 82b...Protruding part 81c, 82c...Main body 81x~81z, 82x~82z...concave 82...Negative terminal 83...Insulation sheet 83a...end part D1, D2...Body diode G1, G2...Gate control terminals N...Negative terminal P…Positive terminal S1, S2...Auxiliary source terminals T1, T2...Transistors U: Output terminal

Claims

1. an insulating sheet having a first main surface and a second main surface; a plate-shaped first terminal provided opposite the first main surface of the insulating sheet and having a first protruding portion protruding outward from the first main surface of the insulating sheet; a plate-shaped second terminal provided opposite the second main surface of the insulating sheet and having a second protruding portion protruding outward from the second main surface of the insulating sheet alongside the first protruding portion; Equipped with A semiconductor device in which a first recess is provided at a position where the first protrusion intersects with the end of the insulating sheet, the side surface facing the second protrusion being recessed in a direction away from the second protrusion.

2. 2. The semiconductor device according to claim 1, wherein a second recess is provided at the position where the second protrusion intersects with the end of the insulating sheet, the side surface facing the first protrusion being recessed in a direction away from the first protrusion.

3. the first terminal further includes a third protruding portion that protrudes alongside the first and second protruding portions on an outer side of the first main surface of the insulating sheet, on an opposite side of the second protruding portion from the side on which the first protruding portion is provided, a third recess is provided at a position where the second protrusion intersects with the end of the insulating sheet, the third recess being recessed in a direction away from the third protrusion on a side surface facing the third protrusion; A fourth recess is provided at a position where the third protrusion intersects with the end of the insulating sheet, the fourth recess being formed by recessing a side surface facing the second protrusion in a direction away from the second protrusion.

3. The semiconductor device according to claim 1.

4. the first terminal further includes a third protruding portion that protrudes alongside the first and second protruding portions on an outer side of the first main surface of the insulating sheet, on an opposite side of the second protruding portion from the side on which the first protruding portion is provided, the second terminal further includes a fourth protruding portion that protrudes between the second protruding portion and the third protruding portion and is located outside the second main surface of the insulating sheet alongside the first to third protruding portions; a third recess is provided at a position where the fourth protrusion intersects with the end of the insulating sheet, the third recess being recessed in a direction away from the third protrusion on a side surface facing the third protrusion; A fourth recess is provided at a position where the third protrusion intersects with the end of the insulating sheet, the fourth recess being recessed in a direction away from the fourth protrusion on a side surface facing the fourth protrusion.

3. The semiconductor device according to claim 1.

5. 5. The semiconductor device according to claim 1, wherein the first and second terminals are used as terminals having different potentials.

6. the first terminal further includes a first body portion connected to the first protrusion, the second terminal further includes a second body portion connected to the second protrusion, At least a portion of the first body portion and at least a portion of the second body portion face each other via the insulating sheet. The semiconductor device according to any one of claims 1 to 5.

7. 7. The semiconductor device of claim 6, wherein a first creepage distance along the insulating sheet between the first protrusion and the second protrusion at the end of the insulating sheet is longer than a second creepage distance along the insulating sheet between the first main body and the second protrusion, and a third creepage distance along the insulating sheet between the second main body and the first protrusion.

8. 8. The semiconductor device according to claim 6, wherein a fifth recess is provided in a side surface of the first body portion facing the second protrusion portion, the side surface being recessed in a direction away from the second protrusion portion.

9. The semiconductor device according to any one of claims 6 to 8, wherein a sixth recess is provided in the side surface of the second body portion facing the first protrusion portion, the side surface being recessed in a direction away from the first protrusion portion.

10. an insulating circuit board; a power semiconductor element mounted on the insulating circuit board; a case that houses the insulating circuit board and the power semiconductor element and to which the first terminal, the second terminal, and the insulating sheet are attached; a sealing material provided inside the case and sealing the insulating circuit board and the power semiconductor element; Further provided with The first terminal and the second terminal are electrically connected to the power semiconductor element. The semiconductor device according to any one of claims 1 to 9.

11. The semiconductor device according to claim 10 , wherein the first terminal is joined to the insulating circuit board via a spacer.

12. The semiconductor device according to claim 10 , wherein the first terminal is bent from the first recess and directly bonded to the insulating circuit board.

13. a seventh recess is provided on a main surface of the insulating circuit board to which the first terminal is joined; The first terminal is bonded to the seventh recess. The semiconductor device according to claim 12.

14. a case to which the first terminal, the second terminal, and the insulating sheet are attached; The case covers an end portion of the first body portion and an end portion of the second body portion. The semiconductor device according to any one of claims 6 to 9.

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