Access controller and data transfer method

Abstract

To provide an access controller and a data transfer method.SOLUTION: An access controller includes a holding register that holds an address when receiving an input of an address of an MRAM which is a reading destination, a multiplexer that reads and outputs a plurality of specification destination of the MRAM held in the address holding register to the MRAM, a plurality of data holding register that holds the data read from the MRAM, and a comparator when the reading destination is specified and a receiving instruction is received, compares the address related to the specification of the reading destination with the reading address held in the address holding register. When receiving the specification of the reading destination and the reading instruction, if comparator determines to be read from the MRAM in advance, data already read and held in any of register of the plurality of data holding register is output in response to the reading instruction.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The present invention relates to a device, a sensor node, an access controller, a data transfer method, and a processing method in a microcontroller, and more particularly to a microcontroller unit (MCU) and a sensor node as devices that can be used with lower power consumption and higher performance in IoT (Internet-of-Things) applications, an access controller, a data transfer method, and a processing method in a microcontroller. [Background technology]

[0002] There is a growing demand for low-power, high-performance microcontroller units that can be applied to sensor nodes that require a power supply. To meet this demand, research and development has been conducted into the use of non-volatile memory installed in MCUs (Non-Patent Documents 1 to 5). For example, Non-Patent Document 1 discloses a non-volatile MCU that has demonstrated 32-bit operation at 30 MHz, and Non-Patent Document 2 discloses a non-volatile MCU that has demonstrated 8-bit operation at 100 MHz. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] T. Onuki, et al., "Embedded Memory and ARM Cortex-M0 Core Using 60-nm C-Axis Aligned Crystalline Indium-Gallium-Zinc Oxide FET Integrated With 65-nm Si CMOS," JSSC, vol.52, Iss.4, pp.925-932, 2017. [Non-patent document 2] Y. Liu, et al., "A 65nm ReRAM-Enabled Nonvolatile Processor with 6× Reduction in Restore Time and 4× Higher Clock Frequency Using Adaptive Data Retention and Self-Write-Termination Nonvolatile Logic," ISSCC, pp.84-86, 2016. [Non-patent document 3] Y. Tsuji, et al., "Sub-μW Standby Power, <18 μW / DMIPS@25MHz MCU with Embedded Atom-switch Programmable Logic and ROM," Symp. VLSI Tech., pp.T86-T87, 2015. [Non-patent document 4] V. Singhal, et al., "A 10.5μA / MHz at 16MHz Single-Cycle Non-Volatile Memory Access Microcontroller with Full State Retention at 108nA in a 90nm Process," ISSCC, pp.148-150, 2015. [Non-patent document 5] N. Sakimura, et al., "A 90nm 20MHz Fully Nonvolatile Microcontroller for Standby-Power-Critical Applications," ISSCC, pp.184-186, 2014. Summary of the Invention [Problem to be solved by the invention]

[0004] However, the performance of the MCUs disclosed in these documents is not suitable for sensor nodes that process large amounts of received signals and extract useful information, because it is not possible to reduce the amount of data transferred to the data center.

[0005] Therefore, an object of the present invention is to provide a low-power, high-performance device applicable to a sensor node, a sensor node using the same, and an access controller, a data transfer method, and a processing method in a microcontroller related thereto. [Means for solving the problem]

[0006] The concept of the present invention is as follows. [1] MRAM in which multiple memory cells are divided into multiple regions, each containing a select transistor and an MTJ; a non-volatile CPU configured to include a non-volatile memory; a non-volatile FPGA-ACC configured to include a non-volatile memory and to execute a part of the arithmetic processing of the non-volatile CPU; a power gating control unit that controls power supply to each memory cell in the MRAM, the nonvolatile CPU, and the nonvolatile FPGA-ACC; A device comprising: [2] The device described in [1], wherein the non-volatile CPU sends data to the MRAM, causing the non-volatile FPGA-ACC to read the data from the MRAM, and the non-volatile FPGA-ACC sends data to the MRAM, causing the non-volatile CPU to read the data from the MRAM. [3] The device described in [1] or [2], wherein the non-volatile FPGA has a non-volatile memory function that stores configuration data. [4] A device described in any one of [1] to [3], wherein each memory cell of the MRAM is composed of a 2T-2MTJ including two of the select transistors and two of the MTJs. [5] A device described in any one of [1] to [4], wherein each of the multiple regions in the MRAM is configured in divided block units, and power gating is performed on a block unit basis. [6] A device according to any one of [1] to [5], wherein the non-volatile FPGA has tiles that perform some of the calculations on the non-volatile CPU, and a DSP (Digital Signal Processor) that performs some of the calculations on the non-volatile CPU at a faster speed than the tiles. [7] The device described in any one of [1] to [6], further comprising an access controller that controls access to the MRAM by reading and storing data in advance when reading from the MRAM. [8] The device described in [7], wherein when the access controller receives a data read command from the non-volatile CPU, it determines whether the data has already been read from the MRAM, and if it has, sends the stored data to the non-volatile CPU. [9] The access controller: an address holding register for holding an address of the MRAM to be read when the address is received; a multiplexer that outputs to the MRAM so as to read out a plurality of destinations of the MRAM held in the address holding register; a plurality of data holding registers for holding data read from the MRAM; a comparator that, upon receiving a read command together with a designation of a read destination, compares an address related to the designation of the read destination with a read address held in the address holding register; Equipped with The device according to [7] or [8], wherein when a read command is received together with a specification of a read destination, if the comparator determines that data has already been read from the MRAM, the device outputs data that has already been read and stored in one of the plurality of data holding registers in response to the read command.

[10] The access controller further comprises a prefetch address generator connected to the multiplexer; The access controller according to [9], wherein the prefetch address generator generates an address including the address of the read destination held in the address holding register.

[11] The device according to any one of [1] to

[10] above, which can be used with an average power of 100 μW or less.

[12] The device according to any one of [1] to

[11] , wherein the intermittent operation interval can be set to 100 ms or less.

[13] A sensor node configured to include the device described in any one of [1] to

[12] above.

[14] An address holding register that holds the address when it receives an input of the address of the MRAM that is the read destination; a multiplexer that outputs to the MRAM so as to read out a plurality of destinations of the MRAM held in the address holding register; a plurality of data holding registers for holding data read from the MRAM; a comparator that, upon receiving a read command together with a designation of a read destination, compares an address related to the designation of the read destination with a read address held in the address holding register; Equipped with When a read command is received together with a read destination specification, if the comparator determines that data has already been read from the MRAM, the access controller outputs data that has already been read and stored in one of the plurality of data holding registers in response to the read command.

[15] further comprising a prefetch address generator connected to the multiplexer; The access controller according to

[14] , wherein the prefetch address generator generates an address including the address of the read destination held in the address holding register.

[16] A data transfer method between a CPU and MRAM via an access controller, When the access controller receives a data read command together with a read address from the CPU, the access controller reads data from a plurality of addresses including the read address from the MRAM in advance; When a data read command is received from the CPU along with the next read address, the data transfer method determines whether the data has already been read, and if the command is to read data that has already been read, the data that has already been read is used as a response to the read command without reading from the MRAM.

[17] A processing method in a microcontroller having a non-volatile CPU, an MRAM, and a non-volatile FPGA-ACC as a reconfigurable computing module, an area for storing data exchanged between the non-volatile CPU and the non-volatile FPGA-ACC is set in the MRAM; Data input from the non-volatile CPU to the non-volatile FPGA-ACC is written to the area, A signal indicating that preparation for starting the writing and calculation has been completed is passed from the non-volatile CPU to the non-volatile FPGA-ACC; The non-volatile FPGA-ACC starts an operation using the data written in the area, After the calculation is completed, the calculation result of the non-volatile FPGA-ACC is passed to the non-volatile CPU using the area. Processing method in microcontroller.

[18] The processing method for the microcontroller according to

[17] , wherein the non-volatile CPU and the non-volatile FPGA-ACC are subjected to power gating control.

[19] The processing method for a microcontroller according to

[18] , wherein the power gating control does not include data saving and restoration operations.

[20] A processing method in a microcontroller according to any one of

[17] to

[19] , wherein the arithmetic processing by the non-volatile FPGA-ACC is any one of a Laplacian filter, a DCT (Discrete Cosine Transform), an FIR (Finite Impulse Response) filter, and an FFT (Fast Fourier Transform).

[21] A processing method for a microcontroller according to any one of

[17] to

[20] , in which sequential processing by a sequence is processed in parallel by the non-volatile CPU and a non-volatile FPGA-based accelerator. [Effects of the Invention]

[0007] According to the present invention, the MRAM, NV-CPU, and NV-FPGA are configured using nonvolatile memory cells. Therefore, without evacuating data stored in the MRAM, NV-CPU, and NV-FPGA memory cells, the power gating control unit can shut off the power supply to each of the MRAM, NV-CPU, and NV-FPGA modules, i.e., non-operating units, thereby eliminating unnecessary power consumption. Furthermore, the reconfigurable computing module equipped with the NV-FPGA can achieve various signal processing at high speed. Furthermore, by improving the efficiency of data transfer between the NV-CPU and MRAM using the access controller, the overall system speed can be increased. Thus, according to the present invention, a low-power, high-performance device and a sensor node using the same can be provided. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a configuration diagram of a device according to an embodiment of the present invention. [Figure 2]2A and 2B are diagrams for explaining the concept of the present invention, in which FIG. 2A is a diagram showing power consumption over time when configured based on a conventional CMOS, FIG. 2B is a diagram showing power consumption over time when power gating is performed in FIG. 2A, and FIG. 2C is a diagram showing power consumption over time when power gating is performed after the volatile memory portion in FIG. 2A is replaced with nonvolatile memory. [Figure 3] FIG. 3 is a diagram for explaining the concept of the present invention. FIG. 3A is a diagram showing power consumption over time when sequential processing is performed on a CPU with power gating, and FIG. 3B is a diagram showing power consumption over time when the processing is performed by an FPGA incorporated in a device. [Figure 4] FIG. 4 is a diagram showing the configuration of a system using sensor nodes. [Figure 5] FIG. 5 is a diagram showing the configuration of a sensor node. [Figure 6] FIG. 6 is a diagram showing the configuration of FIG. [Figure 7] FIG. 7 is a diagram showing a specific configuration of STT-MRAM. [Figure 8] FIG. 8 is a diagram showing the operating waveforms of the STT-MRAM. [Figure 9] FIG. 9 is a diagram for explaining an access controller (Accelerator) between the CPU and the MRAM. [Figure 10] FIG. 10 is a diagram showing the data transfer transition, and FIGS. 10A to 10F are diagrams showing the various states. [Figure 11] FIG. 11 shows an example of data flow, where FIG. 11A shows the case of 16-bit instructions allocated to consecutive memory addresses, and FIG. 11B shows the case of 32-bit instructions allocated to consecutive memory addresses. [Figure 12] FIG. 12 shows a simulation waveform in the access controller. [Figure 13] Figure 13 is a chart comparing the power consumption of a system consisting of an access controller, MRAM, and NV-CPU with that of a conventional system. [Figure 14]FIG. 14 is a cross-sectional view showing an MTJ device used in an NV-CPU. [Figure 15] FIG. 15 shows an example of a nonvolatile flip-flop circuit. [Figure 16] FIG. 16 is a diagram showing a simulation waveform. [Figure 17] FIG. 17 is a diagram showing the operation of a flip-flop. [Figure 18] FIG. 18 is a diagram showing a write operation. [Figure 19] FIG. 19 is a diagram showing a read operation. [Figure 20] FIG. 20 shows the details of the NV-FPGA. [Figure 21] FIG. 21 is a diagram showing the configuration of one tile in the NV-FPGA. [Figure 22] FIG. 22 is a diagram showing an example of a circuit including a wiring switch circuit. [Figure 23] FIG. 23 is a block diagram of a 6-input LUT circuit. [Figure 24] FIG. 24 is a diagram showing an example of a nonvolatile flip-flop circuit. [Figure 25A] FIG. 25A illustrates the THROUGH phase (CLK=1 and CLK′=0) of operation of the circuit of FIG. [Figure 25B] FIG. 25B illustrates the HOLD phase (CLK=0 and CLK′=1) of operation of the circuit of FIG. [Figure 25C] FIG. 25C illustrates the STORE phase of operation of the circuit of FIG. [Figure 25D] FIG. 25D illustrates the RESTORE phase of operation of the circuit of FIG. [Figure 26] FIG. 26 is a diagram showing the circuit configuration of the DSP core. [Figure 27] FIG. 27 is an image of a chip fabricated as an example. [Figure 28] FIG. 28 shows the measured waveform. [Figure 29]FIG. 29 is a diagram showing a Shmoo Plot. [Figure 30] FIG. 30 is a diagram showing the relationship between the intermittent operation interval and the average power. [Figure 31] FIG. 31 is a diagram showing the power obtained by energy harvesting for each energy source. [Figure 32] FIG. 32 is a diagram showing the power required for each of the processes of a Laplacian filter, a DCT (Discrete Cosine Transform), an FIR (Finite Impulse Response) filter, and an FFT (Fast Fourier Transform). [Figure 33] FIG. 33 is a chart comparing this embodiment with the conventional examples (Non-Patent Documents 1 to 5). [Figure 34] FIG. 34 is a diagram showing the relationship between the operating frequency and the average power consumption when an IoT application is assumed, from the chart in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0009] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the accompanying drawings. The details of the preferred embodiments of the present invention may be modified without departing from the scope of the present invention.

[0010] 1 is a block diagram of a device according to an embodiment of the present invention. As shown in FIG. 1, the device 1 according to the embodiment of the present invention includes an STT-MRAM (Spin Transfer Torque-Magnetoresistive Random Access Memory) 2 as an MRAM, an NV-CPU (Nonvolatile Central Processing Unit) 3, an NV-FPGA (Nonvolatile Field-Programmable Gate Array) 4, a power gating control unit 5 that controls the supply of power to each memory cell in the STT-MRAM 2, the NV-CPU 3, and the NV-FPGA 4, and an access controller 6 that controls access to the STT-MRAM 2 by reading and storing data in advance when reading from the STT-MRAM 2. The access controller 6 is involved in access to the STT-MRAM 2, and these modules are connected by a bus 7.

[0011] In the device 1 according to the embodiment of the present invention, specifically in the MCU (Microcontroller Unit), the NV-CPU 3 sends data to the STT-MRAM 2, which causes the NV-FPGA 4 to read the data from the STT-MRAM 2, and the NV-FPGA 4 sends data to the STT-MRAM 2, which causes the NV-CPU 3 to read the data from the STT-MRAM 2. This means the following: the results of the calculations performed by the NV-CPU 3 are stored in the STT-MRAM 2, the NV-FPGA 4 performs further calculations using the results stored in the STT-MRAM 2 and returns the results to the STT-MRAM 2, and the NV-CPU 3 receives the results of the calculations performed by the NV-FPGA 4 from the STT-MRAM 2.

[0012] Embodiments of the present invention provide a microcontroller that simultaneously achieves high computing performance (e.g., several hundred MHz, such as 200 to 300 MHz) and low power consumption (e.g., 100 μW or less), suitable for sensor nodes, etc. Low power consumption may be somewhat effective because standby power can be reduced by using non-volatile memory other than MRAM. However, using non-volatile memory other than MRAM does not allow for high-speed writing or reading.

[0013] Therefore, in an embodiment of the present invention, in order to achieve a computing performance of several hundred MHz, the MCU as device 1 employs MRAM, preferably STT-MRAM2, as an area for storing data related to computations by the CPU and FPGA.

[0014] The device 1 can also be called a non-volatile microcomputer chip, a non-volatile microcomputer, or a non-volatile microcontroller unit.

[0015] The STT-MRAM2 is configured by dividing a plurality of memory cells into a plurality of regions, each including a select transistor and a magnetic tunneling junction (MTJ). Preferably, the STT-MRAM2 is configured by a plurality of sub-array blocks, and each block is provided with a switch for turning on / off power from a power supply unit (not shown). The power gating control unit 5 can perform power gating on the STT-MRAM2 in block units. The block units here refer to block units into which each of the plurality of regions in the MRAM is divided, and refer to the MRAM sub-arrays that constitute MRAM0 and MRAM1 in FIG. 9.

[0016] The memory portion of the NV-CPU3 mounted on this module is entirely composed of nonvolatile memory. The NV-CPU3 is provided with a switch for turning on / off power from a power supply unit (not shown) for the entire module. Because the NV-CPU3 is composed of nonvolatile memory, power gating control can be performed without the need to save and write data within the CPU when turning the switch on / off (i.e., for each power gating). Naturally, since data is not saved and written, there is no power consumption. This is particularly effective for devices that perform a certain amount of operation intermittently and enter a standby state between processes, particularly IoT sensor nodes, because it does not require saving and writing data when performing power gating control.

[0017] The NV-FPGA 4 includes a nonvolatile memory. The NV-FPGA 4 is provided with a power gating switch for each tile, which can turn on / off power from a power supply unit (not shown). Furthermore, if the NV-FPGA 4 includes a DSP, the DSP is provided with a switch for turning on / off power from the power supply unit (not shown). Because the NV-FPGA 4 includes a nonvolatile memory, there is no need to save or write data within the FPGA when turning on / off the switch (i.e., for each power gating), and there is no need to save or write configuration data. Since there is no need to save or write data or configuration data, there is no power consumption. In a conventional system that includes a volatile FPGA but not a nonvolatile FPGA, saving and writing data and configuration data are required for each power gating. However, in an embodiment of the present invention, the FPGA is nonvolatile, so there is no need to save or write data and configuration data for each power gating.

[0018] The power gating control unit 5 controls the power supply to each MRAM sub-array in the STT-MRAM 2, each tile in the NV-CPU 3 and the NV-FPGA 4, and the DSP, and supplies power only when a specified module is operating.

[0019] In STT-MRAM2, each memory cell is preferably configured as a 2T-2MTJ, including two select transistors and two MTJs. STT-MRAM includes 1T-1MTJs, 2T-2MTJs, and 4T-4MTJs. 4T-4MTJs are undesirable because power gating requires additional peripheral devices, which consumes power. In contrast, 1T-1MTJs and 2T-2MTJs are suitable because the cell configuration itself has power gating capabilities, but 2T-2MTJs are preferable from the perspective of bit count for improved performance. While 2T-2MTJs may also have WL, BL, / BL, SL, and / SL per cell, having WL, BL, / BL, and SL per cell, with SL and / SL shared, is preferred to reduce layout size. Furthermore, the write pulse width can be set according to the MTJ write characteristics, thereby suppressing and optimizing the write current.

[0020] A concept of a device 1 according to an embodiment of the present invention will now be described. FIG. 2 is a diagram illustrating the concept of the present invention. FIG. 2A is a diagram illustrating power versus time when configured using a conventional CMOS-based architecture. In the active state, the power consumption is the sum of the dynamic and static power components, while in the standby state, only the static power component is present. By implementing power gating, as shown in FIG. 2B, static power is consumed only when the dynamic power component is present, and no static power is consumed when no dynamic power is present. However, additional power is consumed before and after the active state to back up data from the volatile memory and to write data to the volatile memory component. Therefore, if the volatile memory component is replaced by nonvolatile memory, the data back-up and writing required in FIG. 2B are no longer necessary, as shown in FIG. 2C.

[0021] As described above, in an embodiment of the present invention, this is achieved by making all modules within device 1 nonvolatile. Typically, IoT sensor nodes perform a certain amount of operations intermittently and enter a standby state between each process. In conventional CMOS-based architectures, internal memory is volatile, so data transfer between internal memory and external memory is required to back up data before powering off. This data backup is no longer necessary. Furthermore, in a completely nonvolatile device (MCU), all modules are nonvolatile, so external memory is not required and stored data does not need to be transferred. Therefore, power gating technology can be effectively applied with fine granularity, actively eliminating unnecessary power consumption. Because the NV-FPGA 4 is configured to include nonvolatile memory, there is no need to save and write data within the FPGA for each power gating, and there is no need to save and write configuration data. This is particularly effective for devices that perform a certain amount of operations intermittently and enter a standby state between each process, particularly IoT sensor nodes, because power gating control does not require saving and writing data.

[0022] Figure 3 further explains the concept of this invention. As shown in Figure 3A, sequential processing on a CPU can only reduce power consumption through power gating. However, as shown in Figure 3B, by executing part of the CPU's computational processing on the FPGA, processing is accelerated and performance is improved. In this way, sequential processing at each operation interval (sequential processing by sequence) is parallelized between the CPU and an FPGA-based accelerator (FPGA-ACC). Because parallel processing significantly reduces processing time ("Processing time reduction by FPGA-ACC" in Figure 3B), the power gating time (PG) is extended, and the increase in power gating time due to parallel processing, i.e., the reduction in processing time due to FPGA-ACC, both static and dynamic power consumption, is eliminated. This reduced power consumption is far greater than the increase in power consumption due to FPGA-ACC computational processing. In this way, by incorporating FPGA-ACC into a non-volatile microcontroller consisting of an NV-CPU and MRAM, high computational performance and low power consumption can be achieved. Shortening the process time shortens the usage time of the MRAM, which accounts for most of the power consumption, and further reduces power consumption. Thus, by connecting the NV-FPGA 4 to the NV-CPU 3 via the bus 7, sequence processing can be performed by the NV-CPU 3 and the NV-FPGA 4 in parallel. In particular, in an IoT sensor node, as will be described later with reference to FIGS. 4 and 5 , it is preferable to reduce the amount of data by, for example, calculating feature values ​​or performing image processing in the end-sensor node 110, so that the sensor data does not need to be processed by the cloud device 140, and then transmit the data to the cloud device 140, which is a host device. In an embodiment of the present invention, sequence processing is performed by parallel processing using the NV-CPU 3 and the NV-FPGA 4, achieving high computational performance and low power consumption, making it preferable for application to an IoT sensor node.

[0023] This reduces the processing time for sequences at each operation interval, further reducing power consumption. By configuring the FPGA with MTJs on CMOS, an ultra-low power consumption non-volatile FPGA can be realized.

[0024] As mentioned above, one concept of the present invention is to realize a microcontroller that simultaneously achieves high computing performance (e.g., several hundred MHz, e.g., 200 to 300 MHz) and low power consumption (e.g., 100 μW or less), suitable for applications such as sensor nodes. From the perspective of low power consumption, using nonvolatile memory other than MRAM offers a certain advantage by reducing standby power consumption. However, nonvolatile memory other than MRAM cannot simultaneously achieve computing performance of several hundred MHz because it cannot achieve high write and read speeds. In contrast, using MRAM achieves high speed due to its high write and read speeds, while also achieving low power consumption due to its nonvolatile nature. Therefore, a microcontroller as a device comprising an NV-CPU, NV-FPGA, and MRAM memory according to an embodiment of the present invention is particularly effective.

[0025] In this way, in order to realize a microcomputer that combines high computing performance and low power consumption performance suitable for sensor nodes, particularly effective results can be achieved by implementing MRAM as memory in a microcomputer that requires high computing performance and is equipped with a CPU and FPGA.

[0026] Next, we will explain a sensor node using the device in Fig. 1 and a system using the same. Fig. 4 is a configuration diagram of a system using the sensor node, and Fig. 5 is a configuration diagram of the sensor node. The system 100 is composed of one or more sensor nodes 110 that are attached to indoor or outdoor structures or worn by people or animals, a gateway (GW) 120 for connecting the sensor nodes 110 to a communication network 130 such as the Internet, and higher-level equipment such as a cloud device 140 that stores and processes various information transmitted from the sensor nodes 110 via the communication network 130.

[0027] The sensor node 110 comprises a sensor element 111 that measures various physical quantities, an MCU 112 that processes data from the sensor element 111 and processes it into information, a communication unit 113 that outputs the information processed by the MCU 112 and various control data to the outside, and a power supply unit 114 that converts natural energy, artificially created vibrations, etc. into electricity and stores it.

[0028] 1, the MCU 112 is low-power and capable of data processing, eliminating the need to process sensor data in the cloud device 140. Instead, the sensor node 110 at the end can obtain features or perform image processing, for example, to reduce the amount of data before transmitting it to the host device, the cloud device 140. This allows for a significant reduction in traffic volume.

[0029] Next, a specific configuration of the device 1 will be described. FIG. 6 is a configuration diagram that embodies the configuration of FIG. 1. As shown in FIG. 6, the MCU 10 as a device includes an STT-MRAM 11, an NV-CPU 12, an NV-FPGA 13, a MEM4X access controller 14, a bus 15, a PMU (Performance Monitoring Unit) 16, a system control (SYS CONTROL) 17, a bus matrix (AHB-MATRIX) 18, and, as CPU peripherals in the MCU, an ADC (Analog-Digital Converter) 19, a timer 20, a WDT (Watchdog Timer) 21, a UART (Universal Asynchronous Receiver / Transmitter) 22, a serial bus (e.g., I2C) 23, an SPI (Serial Peripheral Interface) 24, a GPIO (General-Purpose Input / Output) 25, and a BIAS 26. The CPU peripherals are merely examples, and other configurations are also possible.

[0030] Figure 7 is a specific configuration diagram of the STT-MRAM 11. As shown in Figure 7, the STT-MRAM 11 has a left-side array (Left-Side Array) composed of MRAM sub-arrays and a right-side array (Right-Side Array) also composed of MRAM sub-arrays, and the MRAM itself is controlled by the Control. To access data stored at a specific address in the memory, the location (coordinates) of the memory cell where the data is stored is specified based on the input data, which is the address. Xpredec and Ypredec generate signals corresponding to the coordinates indicating the memory cell location based on the address, and Xdec and Ydec further convert these signals into complementary signals required for actual access before accessing the target memory cell. In this way, the conversion from address to memory location is performed in two stages.

[0031] A Ydec is placed on the left and right of each of the left-side and right-side arrays, as the operation when reading memory data differs between the left and right sides. The outer Ydec injects a constant current into the memory cell to be read, generating a voltage signal corresponding to the state of the cell (i.e., the resistance state of the MTJ). This voltage signal is amplified by the sense amplifier (SA) attached to the inner Ydec, and the data from the memory cell to be read is extracted. In the diagram, the solid arrows represent control signals, and the dotted arrows represent data signals.

[0032] In this STT-MRAM 11, there is no power supply line for each memory cell, and therefore no power gating switch is provided.

[0033] In this STT-MRAM 11, as shown on the right side of FIG. 7, each cell has a WBT shared between the left and right sides, so that the cell area can be reduced.

[0034] 8 is a diagram showing the operation waveforms of the STT-MRAM 11. Data is written in response to a write enable signal relative to the clock (CLK), and data is read out in response to a read enable signal.

[0035] As explained with reference to FIG. 1, when the access controller 6 receives a data read command from the NV-CPU 3, it determines whether the data has already been read from the STT-MRAM 2. If the data has already been read, it transmits the stored data to the NV-CPU 3. Specifically, the access controller 6 includes an address register, a multiplexer, multiple data registers, and a comparator (not shown in FIG. 1). When the access controller 6 receives an address input from the NV-CPU 3 in the STT-MRAM 2 as the read destination, it stores the address in the address register. The multiplexer reads the multiple destinations in the STT-MRAM 2 specified by the address and stores the data read from the STT-MRAM 2 in each data register. When the access controller 6 receives a new read command from the NV-CPU 3 together with the destination address, it compares the address stored in the address register with the address of the destination using a comparator to determine whether the destination address has already been read from the STT-MRAM 2. If the data has already been read and stored in the data holding register, the stored data is sent to the NV-CPU 3 as a response to the read command.

[0036] FIG. 9 is a diagram illustrating the access controller (Accelerator) 14 between the CPU and the MRAM. Both 16-bit and 32-bit instructions are included. All data is 32-bit. In FIG. 9, HADDR is the memory address of the MRAM 11 accessed by the CPU 12, and HRDATA is the data stored at the accessed address. The access controller (Accelerator) 14 includes a register (reg) that holds HADDR, a comparator (cmp) that compares the next HADDR with the previous HADDR, a prefetch address generator, a MUX (Multiplexer) that selects and outputs either HADDR or the output of the address generator, registers (reg0, reg1) that hold data read from the MRAM 11, and a MUX (Multiplexer) that selects and outputs either of the read data. Here, "prefetch" refers to fetching data in advance, i.e., capturing data, prior to its actual use. As shown in Figure 9, the MUX has a function where an arrow entering from the top or bottom of the circuit block is a control input that takes on a value of "0" or "1", and depending on whether the value is "0" or "1", it selects one of the two inputs entering from either the left or right and outputs it as is.

[0037] In this way, the access controller 14 is provided on the input side of the STT-MRAM 11, and has an address holding register (reg) that holds the address when it receives an input of an address in the STT-MRAM 11 that is the read destination, a multiplexer that reads out multiple destinations in the STT-MRAM 11 specified by the address holding register (reg), multiple data holding registers (reg0, reg1) that hold data read from the STT-MRAM 11, and a comparator (cmp) that compares the address of the read destination held in the address holding register (reg) when it receives a read command together with the specified read destination.

[0038] The address of the data to be used is passed from the CPU 12 to the access controller (Accelerator) 14 via HADDR. At this time, that address is held in the register (reg) on ​​the left side of the Accelerator in Figure 9. The MUX on the right side of the Accelerator compares the data passed from HADDR with the data held in reg, and if they do not match, it uses the value of HADDR as the value of MRAM_ADDR as is, reads out data for two 16-bit instructions each from MRAM0 and MRAM1 (16 bits x 2 = 32 bits in two parallel for one MRAM), and takes this data into reg0 and reg1.

[0039] When consecutive 16-bit instructions stored in consecutive memory addresses are executed, the data for four instructions is loaded into reg0 and reg1 through the above process. The data passed from CPU 12 via HADDR is compared with the data stored in reg. If the above conditions are met, the data previously loaded into reg0 and reg1, corresponding to the address specified by HADDR, is designated by the Output control calculation unit in the figure and output as HRDATA, i.e., in response to a read command from CPU 12. In this case, data is passed from reg0 or reg1, not MRAM 11, in response to a read command from CPU 12 via HADDR. Therefore, data is returned at the transfer rate available between CPU 12 and Accelerator (e.g., 200 MHz), not the transfer rate available between Accelerator and MRAM (e.g., 50 MHz). This process is shown in Figure 11A. The values ​​of 50 MHz and 200 MHz shown here are for illustrative purposes only.

[0040] When 32-bit instructions stored in consecutive memory addresses are executed consecutively, the data for the two instructions is loaded into reg0 and reg1 through the above process, and the same process as above is carried out. In this case, the data is returned at 100 MHz. Figure 11B shows this series of steps. The value of 100 MHz shown here is an example.

[0041] Access from the CPU 12 to the MRAM 11 is performed in a multiplexed manner, and the read data is temporarily stored in registers (reg0, reg1). When the same memory address is accessed repeatedly, the data held in the registers is reused instead of the data in the memory. Figure 10 shows an example of the data transfer transition in Figure 9. A data request is executed before the CPU needs the data, and when the next instruction ready to be fetched is executed, the 16-bit instruction held in the register is executed. Therefore, high-speed instruction fetching is performed without interruption.

[0042] In Figure 10, Figure 10A shows the initial state, and in Figure 10B, a prefetch data request, data storage in a register in the access controller (accelerator circuit), and the fetch operation of instruction A are executed simultaneously. In Figure 10C, the fetch operation of instruction B is executed. In Figure 10D, the fetch operation of instruction C is executed. In Figure 10E, the fetch operation of instruction D is executed. The prefetch data requested in Figure 10B is ready at this point. In Figure 10F, a prefetch data request, data storage in a register in the access controller (accelerator circuit), and the fetch operation of instruction E are executed simultaneously. In the previous state, preparations for fetching the next instruction to be executed were completed, so high-speed instruction fetching can be performed without interruption.

[0043] Figure 11 shows an example of data flow, where Figure 11A shows the case of 16-bit instructions allocated to consecutive memory addresses, and Figure 11B shows the case of 32-bit instructions allocated to consecutive memory addresses. As shown in Figure 11A, 16-bit instructions allocated to consecutive memory addresses are fetched serially, allowing data for four instructions to be prefetched into registers in advance. This enables instruction fetching at four times the access speed to the MRAM, as shown in Figure 11A. In addition, for 32-bit instructions allocated to consecutive memory addresses, by performing the same control with interleaving as shown in Figure 11B, the data for two 32-bit instructions can be stored in registers, doubling the memory access speed. As a result, it is possible to hide the bottleneck in memory access, and high-speed instruction fetching can be adaptively performed according to the length of the instruction to be fetched.

[0044] In this way, speed is increased using a so-called best-effort method. The actual degree of performance improvement varies depending on the program being executed. Specifically, although it can be used in programs that frequently access memory to random addresses due to conditional branching, it is preferably effective for processes that execute a certain sequence sequentially, such as MCUs for sensor node applications. In such processes, memory access is also regular, so it functions very effectively. As a result, it is possible to achieve the same effect as a cache without increasing the area or power overhead.

[0045] We now explain this access controller in more detail. As an example, we fabricated a test chip for a nonvolatile VLSI processor using a 40nm MOS / MTJ process. It can be designed using an automated design flow and cell library for MTJ-based NV-LIM LSIs. Based on the number of gates in each block, the area overhead due to the introduction of the accelerator circuit is estimated to be 13.6%. Note that although each block is designed separately for overhead evaluation, it is also possible to integrate these blocks and layout them as a single circuit block. In this case, the area overhead is expected to be even smaller.

[0046] Figure 12 shows the simulation waveforms in the access controller (accelerator circuit). In this example, (1) 16-bit instructions assigned to consecutive memory addresses, (2) branch instructions for accessing non-consecutive memory addresses, and (3) 32-bit instructions assigned to consecutive memory addresses are executed sequentially. Figure 12 shows that the operating frequency dynamically changes from 50 MHz to 200 MHz depending on whether the transition of the memory addresses to be accessed satisfies the conditions for instruction fetch acceleration.

[0047] Figure 13 is a chart comparing the power consumption of a system consisting of an access controller (accelerator circuit) and a CPU incorporating MRAM with that of a conventional system. Here, we confirmed the effect of relaxing the performance requirements for MRAM in the following manner. Low-performance MRAM (LP-MRAM) reads and writes at 50MHz. Intermediate performance MRAM (MP-MRAM) with read / write speeds of 100MHz. High-performance MRAM (HP-MRAM) with read / write speeds of 200MHz. All MRAM is designed the same.

[0048] From Figure 13, we can see that the power consumption of MRAM accounts for a large portion of the total power consumption, and the higher the required performance, the higher the ratio becomes. By using an access controller (accelerator circuit), there is no need to change the performance required for MRAM, so the system performance can be improved with only the power overhead of the accelerator circuit.

[0049] Here, we compare the performance of systems with and without this accelerator circuit built in. In the evaluation, we evaluated the area, power consumption, and processing performance of three types of systems using MRAM with different performance described above, a system using cache, and a system using an accelerator circuit.

[0050] [Table 1]

[0051] As shown in Table 1, in implementations using medium-performance or high-performance MRAM, efficiency decreases as the MRAM's power consumption increases, narrowing the temperature range over which operation is guaranteed. Implementations using a cache are expected to improve performance, but at the expense of significant area overhead. On the other hand, by using an accelerator circuit, an acceleration unit can be embedded with minimal area overhead, enabling the CPU operating frequency to be increased without changing the performance required of the MRAM. As a result, area efficiency can be improved. Therefore, compared to implementations using a conventional cache, performance efficiency (MIPS / mW) is improved by 2.29 times, increasing to 3.71 times, and read / write operation can be guaranteed over a wide temperature range.

[0052] The access controller's performance depends on the content of the program to be executed. Through benchmarking using several sample programs, we confirmed that it can operate at 100 MHz or higher even in filter operations involving relatively large amounts of memory access, and that it operates very effectively in programs with relatively few memory accesses and branches.

[0053] Next, we will explain the NV-CPU. All flip-flops used in the NV-CPU are MTJ-based non-volatile flip-flops. Because they are non-volatile, there is no need for data backup for power gating.

[0054] Figure 14 shows a cross-sectional view of an MTJ device used in an NV-CPU. It is realized by constructing an MTJ consisting of a pinned layer, a barrier layer, and a free layer on a CMOS substrate, on top of a metal layer and the top layer of a CMOS substrate. The MTJ element has two different resistance values ​​depending on the spin direction. The MTJ element can maintain its resistance state without a continuous power supply. Therefore, the MTJ device can be used as a 1-bit nonvolatile memory.

[0055] Figure 15 is an example of a nonvolatile flip-flop circuit. Figures 16 to 19 are diagrams showing simulation waveforms, flip-flop operation, write operation, and read operation, respectively. This flip-flop is a master-slave flip-flop, and is divided into a master section, a slave section, and a nonvolatile memory section. In an embodiment of the present invention, an MTJ element is used to configure the nonvolatile memory section.

[0056] In Figure 15, DATA indicates the input signal, Q and QB indicate output signals (complementary, B is Bar = negation), CLK and CLKB indicate clock signals (complementary), LB is a read control signal which is normally "1" and when "0" a read process is performed from the MTJ element to the memory section of the FF. WB is a write control signal which is normally "1" and when "0" a write process is performed from the memory section of the FF to the MTJ element. SB is a set signal which is normally "1" and when "0" the memory state of the FF is set to "1" regardless of the input.

[0057] The FF circuit can be broadly divided into three parts: a master part, a slave part, and a non-volatile memory part. The master part takes in the input signal DATA when the clock is "0" and passes it to the slave part when it is "1". The slave part takes in data from the master part when the clock is "1" and simultaneously outputs that value to Q and QB. When it is "0", it does nothing. The master and slave parts combined operate as a normal master-slave D flip-flop.

[0058] The non-volatile memory unit consists of two MTJ elements that store one bit complementary to each other, and a write circuit that generates a current to write to the MTJ elements. Depending on the control signals LB and WB, the data stored in the slave unit is written to the non-volatile memory, or read from the non-volatile memory to the slave unit.

[0059] Next, the NV-FPGA will be described in detail. Figure 20 is a diagram showing the details of the NV-FPGA. In Figure 20, the NV-FPGA has 8 columns and 21 rows, but this can be set arbitrarily. The FPGA has a power switch (PS) and a controller for each tile, and can turn on / off the power supply for each tile, enabling power gating.

[0060] Figure 21 shows the configuration of one tile. A tile consists of a configurable logic block (CLB) with several logic elements (LEs), a connection block (CB) for connecting the CLBs to wiring tracks, a switch block (SB) for signal routing, a configuration circuit (CFGC), and a controller. For example, a logic element LE consists of a six-input LUT circuit, a flip-flop (FF) circuit, and a multiplexer (MUX). Configuration data for the CLBs, SBs, and CBs is written via the CFGC. Truth table values ​​for a specific logical operation are written to the MTJ elements in each LUT circuit. The FF circuit consists of a CMOS-FF section and an MTJ element section. During normal operation, data is read / written using the CMOS-FF. Just before power-off, the value of the CMOS-FF is written to the MTJ element section. After power-on, the value stored in the MTJ element section is written back to the CMOS-FF. The CB connects any input / output pin of the CLB to any wiring track based on the configuration data, and the SB connects each wiring track to any adjacent Tile based on the configuration data.

[0061] The wiring switch is a basic component of the CB and SB mentioned above. It is a circuit that controls the on / off of pass transistors based on the stored data. The stored data is stored in an area-efficient MTJ-based latch, and the pass transistor is implemented using an NMOS switch. Block-level power gating is performed using a controller, and each functional block is turned off optimally.

[0062] The switch block SB and the connection block CB each consist of a basic component called a routing switch, which contains a nonvolatile storage area. Figure 22 shows an example of a circuit including a routing switch. The output (Q) of the nonvolatile storage element is used to turn on / off the NMOS pass switch. The nonvolatile storage element consists of two inverters, two local write control transistors, and a sense amplifier using two MTJ devices, and the routing information is programmed in a complementary manner. The sense amplifier is used to read the stored state M and retain it as Q during the power-on state without generating a steady DC current path. Once the configuration data is programmed, it does not change, so no additional control transistors are required.

[0063] The tiles are equipped with a decoder and driver, which enable them to be reconfigured into a computing module after manufacturing.

[0064] The configurable logic block CLB is composed of basic components called logic elements, and each logic element is composed of a non-volatile lookup table circuit (non-volatile LUT circuit) and a non-volatile flip-flop (non-volatile FF), each of which has a non-volatile storage function. Figure 23 is a diagram showing an example of a lookup table circuit.

[0065] A block diagram of the 6-input LUT circuit is shown in Figure 23. The 6-input LUT circuit consists of five elements: a sense amplifier, a 64-to-1 NMOS selector, an MTJ configuration array, an NMOS reference tree, and a programmable reference resistor.

[0066] The truth table of any six-input logic function is given by (R0, R 64 ), (R1, R 65 ), (R 63 , R 127 ) in 64 pairs of series-connected MTJ devices. The write operation to store logical function information in the MTJ devices is performed by activating the word lines (WL) and bit lines (BL), which is similar to the write operation of conventional magnetic random access memory (MRAM). BL0 and BL2 are shared between the MTJ-configured array and the programmable reference resistor, and the write access transistor MWC is also shared among the 64 MTJ pairs in the MTJ-configured array. The logical operation of the LUT circuit is completely different from the read operation of MRAM because both BL and WL are not used in the operation.

[0067] When EN is set high and the NMOS selector and NMOS reference tree are activated by the complementary logic input X, currents I and I pass through the corresponding MTJ pairs in the MTJ array and the programmable reference resistor, respectively. F and I REF The difference between Z and Z' is sensed and complementary full-swing outputs (Z, Z') are generated by a sense amplifier.

[0068] To ensure a sufficient sensing margin, the configuration of the series / parallel connected MTJ devices in the MTJ configuration array and the programmable reference resistor is performed as follows: first, in the MTJ configuration array, if the stored data Y is 0, then (R AP , R AP ), if Y is 1, then (R P , R P ) are configured. The resistance of the MTJ device is distributed as a Gaussian distribution N(R,σ R 2 ) (where R is the mean value, σ R is the standard deviation), the total resistance of the series-connected MTJ devices is N(2R,2σ R 2), which means that (R P , R P ) state and (R AP , R AP ) states, the resistance distribution can be narrowed to avoid overlap between the

[0069] Next, the programmable reference resistor is I(R P , R P ) and I(R AP , R AP ) in the middle of REF The total resistance is adjusted so that the MTJ device has two different resistance values. r0 , R r1 , R r2 , R r3 ) can be used to obtain 16 different reference resistance values, and the total resistance value can be adjusted according to the current level variation of IF due to process variation. P represents the low resistance in the MTJ device, and R AP means high resistance.

[0070] Figure 24 shows an example of a nonvolatile flip-flop circuit. The nonvolatile flip-flop circuit (nonvolatile FF circuit) consists of an NMOS-based differential-pair circuit (DPC), a cross-coupled CMOS inverter, two MTJ devices, and an MTJ write circuit. Complementary inputs (D, D') from the NV-LUT circuit are stored in the cross-coupled CMOS inverter during normal operation. They are also stored in the MTJ devices (M, M') in the master latch when WCKB is activated at a low level. The behavior of the master latch is as follows.

[0071] 25A shows the THROUGH phase (CLK=1 and CLK'=0). Since M1 and M4 are turned on, the load capacitance Cq' is discharged to GND, and M6 is turned on. As a result, the load capacitance Cq is charged, the voltage at the output node q becomes VDD, and the voltage at the output node q' becomes 0V.

[0072] Figure 25B shows the HOLD phase (CLK=0 and CLK'=1). M3 is turned on, so the voltage at the output node (q, q') is held by the cross-coupled CMOS inverter. At the same time, M1 and M2 are turned off so that the DPC does not operate. As a result, there is no DC current path from VDD to GND.

[0073] 25C shows the STORE phase. When the inputs (D, D') are (1, 0) and WCKB is activated low, M10 and M13 are turned on by the NOR gate, and the write current I W is applied to the MTJ device.

[0074] Figure 25D shows the RESTORE phase. When RESB is activated low, M9 is turned on, balancing the voltages at the output nodes q and q', and thus applying a clamp voltage to each MTJ device. Then, the sensing current I M and I M’ pass through M and M', respectively. When RESB is activated high, M9 is turned off and I M and I M’ The difference between is amplified by a cross-coupled CMOS inverter.

[0075] In a nonvolatile FF circuit such as that shown in Figure 24, the stored data of the FF held in the cross-coupled CMOS inverter is written to the MTJ element immediately before power is turned off, and after power is turned on again, the data is reloaded from the MTJ element into the cross-coupled CMOS inverter as the stored data of the FF. This eliminates the need for data save / restore operations via an external nonvolatile memory, making it possible to quickly perform power on / off transitions.

[0076] Preferably, a DSP (Digital Signal Processor) is also installed. This allows the DSP to be used for calculations even when a relatively large amount of calculation is required. The DSP also has a power switch (PS) and a controller, which can turn on / off the power supply for each tile, enabling power gating. In the DSP, as with tiles, the switch block and connection block are composed of a basic component called a wiring switch, and the wiring switch includes a non-volatile storage area.

[0077] As mentioned above, each basic component of the NV-FPGA contains non-volatile memory, which stores configuration data. The memory state of the flip-flops is also stored in non-volatile memory. This eliminates the need to save data to external non-volatile memory just before powering off or to write the data back after powering on again. This makes it easy to turn the power on and off. By writing specific operations to the non-volatile FPGA in advance and turning the power on as needed, operations can be started immediately, accelerating CPU processing. Furthermore, by turning the power off when not in use, unnecessary standby power consumption can be avoided.

[0078] In the circuit configuration of the DSP core in Figure 26, SEL[0] and SEL[1] are control signals for function selection, A, B, and C are inputs, and OUT is the output. It operates as a circuit that performs the following calculations: When (SEL[0],SEL[1])=(0,0), OUT=A×B, When (SEL[0],SEL[1])=(0,1), OUT=A×B+C, When (SEL[0],SEL[1])=(1,0), OUT=A+B, (SEL[0],SEL[1])=(1,1) is not used Here, the circuit configuration is arbitrary and other configurations are also possible.

[0079] In this way, it is preferable that the NV-FPGA 4 has tiles that perform some of the calculations on the CPU 3, and a DSP (Digital Signal Processor) that performs some of the calculations on the CPU 3 at a higher speed than the tiles, which satisfies both low power consumption and high performance, as shown in Fig. 3B. [Example]

[0080] Next, an example will be described. Table 2 shows the specifications of the chip that was actually fabricated.

[0081] [Table 2]

[0082] Figure 27 shows an image of the fabricated chip. The chip includes STT-MRAM, NV-CPU and peripheral circuits, and NV-FPGA.

[0083] Figure 28 shows measured waveforms. The program counter operates according to a 200 MHz clock (CLK). An enable signal from NV-CPU3 to NV-FPGA4 transfers data from NV-CPU3 to NV-FPGA4 via MRAM2. An enable signal from NV-FPGA4 to NV-CPU3 transfers data from NV-FPGA4 to NV-CPU3 via MRAM2. The enable signal is a control signal between NV-CPU3 and NV-FPGA4. Data flows from NV-CPU3 to NV-FPGA4 via MRAM2, or from NV-FPGA4 to NV-CPU3 via MRAM2. In this example, data exchange between NV-CPU3 and NV-FPGA4 was achieved at 200 MHz. A specific address area in MRAM2 is reserved for storing data exchanged between NV-CPU3 and NV-FPGA4. The data to be input from the NV-CPU3 to the NV-FPGA4 is written to this area, and the NV-CPU3 sends a signal to the NV-FPGA4 indicating that writing is complete and that preparations to start calculations are complete. The NV-FPGA4 then begins calculations using the data written to the above area. A similar process occurs when the calculation results of the NV-FPGA4 are passed to the NV-CPU3 after completion. The addresses where the data exchanged between the NV-CPU3 and NV-FPGA4 are stored are predetermined, so the only communication between the two is a signal indicating that writing is complete and that preparations to start calculations are complete; there is no need to pass information about the memory address where the data required for processing is stored.

[0084] Figure 29 shows a Shmoo Plot. The vertical axis represents the voltage (V) associated with the NV-CPU, NV-FPGA, and STT-MRAM cores, and the horizontal axis represents frequency (MHz). From the Shmoo Plot, operation was confirmed at each combination of frequency and voltage, with core voltages ranging from 1.05V to 1.30V in 2MHz increments and 0.1V increments, over the range of 100MHz to 204MHz. The white areas in Figure 29 indicate confirmed operation. At 100MHz, operation was confirmed in 0.1V increments from 1.07V to 1.3V, and at 202MHz, operation was confirmed at 1.3V. Therefore, since operation was confirmed at a frequency of 100MHz and a voltage of 1.1V, and at a frequency of 200MHz and a voltage of 1.3V, operation is guaranteed if a curved or straight approximation line is drawn through these two points and a voltage higher than the approximation line is applied to each core. As an approximation line, for example, a straight line of 2×10 −3 f − V + 0.9 = 0 can be obtained, where f is the frequency (MHz) and V is the voltage (V).

[0085] Figure 30 shows the relationship between the intermittent operation interval (IOI) and average power consumption for the cases without power gating (without PG), with power gating (with PG), and with power gating and FPGA-accelerated processing (with PG & FPGA-ACC). The horizontal axis represents the IOI time, and average power consumption was calculated for IOI times of 10 ms, 20 ms, 30 ms, 40 ms, 50 ms, 60 ms, 70 ms, 80 ms, 90 ms, and 100 ms. A Laplacian filter was used for data processing. The NV-CPU and NV-FPGA alternate between active and inactive states of computational processing. The interval between the start of one IOI and the start of the next IOI is called the "IOI."

[0086] Without power gating, the average power consumed was high at 1000 μW regardless of the intermittent operation interval. In contrast, with power gating, the average power decreased as the intermittent operation interval increased. Power gating also significantly reduced power consumption. Furthermore, when power gating was performed and FPGA acceleration processing was performed, the average power decreased as the intermittent operation interval increased, and even at the same intermittent operation interval, using FPGA reduced power consumption even more significantly compared to not using FPGA.

[0087] When the intermittent operation interval is 50 msec, power gating reduces the average power consumption to 100 μW, and by using an FPGA, the average power consumption is reduced to 47.14 μW, which is a 54% reduction in power consumption compared to when power gating is not used.

[0088] The results shown in FIG. 30 indicate that the microcontroller unit as a device according to this embodiment can be manufactured with an intermittent operation interval of 100 ms or less. From another perspective, it was also found that the microcontroller unit as a device according to this embodiment can be used with an average power of 100 μW or less. More specifically, FIG. 30 indicates that an intermittent operation time of 100 ms or less is appropriate. This is because the average power can be kept within a predetermined range for each of the intermittent operation times of 10 ms, 20 ms, 30 ms, 40 ms, 50 ms, 60 ms, 70 ms, 80 ms, 90 ms, and 100 ms. An appropriate range can be determined within these numerical ranges. The intermittent operation time is preferably 10 ms or more and 100 ms or less, more preferably 10 ms or more and 60 ms or less, and even more preferably 10 ms or more and 50 ms or less. Considering that the average power is 100 μW or less, this range is appropriate depending on whether power gating alone is adopted or whether power gating and FPGA are adopted.

[0089] Fig. 31 shows the power obtained by energy harvesting for each energy source. From this figure, and also from the power obtained from light such as sunlight, heat, various vibrations such as mechanical vibration, natural vibration, artificial vibration, high frequency, etc., in an MCU used in an IoT sensor node driven by power obtained by energy harvesting, it is estimated that 100 (μW / cm 2 or μW / cm 3 ) can be considered as the standard.

[0090] Therefore, as can be seen from Figure 30, with an average power consumption of 100 μW, by using a non-volatile CPU, MRAM, and non-volatile FPGA, and by using power gating and FPGA processing, the intermittent operation interval can be made approximately 20 ms or more. The upper limit of the intermittent operation interval can be set arbitrarily. Also, as can be seen from Figure 30, by using power gating and FPGA processing, it is possible to achieve an average power consumption of 100 μW or less, and a device with an intermittent operation interval of 20 ms or more can be realized, providing a device for IoT.

[0091] These results demonstrate that the MRAM, NV-CPU, and NV-FPGA fabricated in this example are configured using MTJs as nonvolatile memory in the non-operating parts. Power gating, which stops the power supply to each MRAM, NV-CPU, and NV-FPGA module (i.e., the non-operating parts) using the power control unit without saving the data stored in the MRAM, NV-CPU, and NV-FPGA memory cells, can eliminate unnecessary power consumption. Furthermore, the FPGA's reconfigurable computing module can achieve various signal processing at high speed. Furthermore, the access controller can improve the efficiency of data transfer between the NV-CPU and MRAM, thereby enabling the overall system to operate at high speed. This demonstrates the feasibility of providing a microcontroller as a low-power, high-performance device.

[0092] Figure 32 shows the power required for each process: Laplacian filter, DCT (Discrete Cosine Transform), FIR (Finite Impulse Response) filter, and FFT (Fast Fourier Transform). In each process, if FPGA processing is not performed, the power consumption of the MRAM as memory is large, but by using FPGA processing, the power consumption of the MRAM can be significantly reduced. Moreover, the reduction is greater than the power consumption of the FPGA, so the effect is enormous.

[0093] Table 3 summarizes the number of tiles, DSPs, LUTs, and FFs used, the maximum operating frequency, and the power consumption at 200 MHz for each of the following processes: Laplacian filter, DCT (Discrete Cosine Transform), FIR (Finite Impulse Response) filter, and FFT (Fast Fourier Transform).

[0094] [Table 3]

[0095] Regardless of the type of processing, the maximum operating frequency exceeds 200 MHz, and for DCT it exceeds 250 MHz. At 200 MHz, the power consumption also decreases in the order of FIR filter, DCT, Laplacian filter, and FFT. In terms of the type of function used in processing, the frequency of use is most frequent in the order of DSP, tile, FFs, and LUTs.

[0096] This example will be compared with other conventional examples. FIG. 33 is a chart comparing this example with conventional examples (Non-Patent Documents 1 to 5). FIG. 34 is a diagram of the chart in FIG. 33 showing the relationship between operating frequency and average power when IoT applications are assumed. The use of FPGA is the technology of Non-Patent Document 3, and while the operating frequency in Non-Patent Document 3 is 25 MHz, this example is 200 MHz, enabling high data processing. Regarding average power, this example is 47.14 μW, while the conventional examples are several orders of magnitude higher. Therefore, with devices according to this example and embodiments of the present invention, it is possible for the first time to provide low-power, high-performance devices and sensor nodes using such devices.

[0097] In this specification, the terms NV-CPU and NV-FPGA are used, but they may also be written as non-volatile CPU and non-volatile FPGA, respectively. Furthermore, the term "memory cell" is used in the NV-CPU, NV-FPGA, and MRAM, but they may also be called "storage area." The NV-FPGA is an FPGA-ACC, i.e., an FPGA-based accelerator, as shown in FIG. 30. It goes without saying that various data stored in the non-volatile area of ​​the non-volatile CPU and non-volatile FPGA (non-volatile FPGA-ACC) would be saved and written during power gating if they were volatile.

[0098] The concept of the embodiment of the present invention is as follows. First, the device: an MRAM configured by dividing a plurality of memory cells into a plurality of regions, each including a select transistor and an MTJ; a non-volatile CPU configured to include a non-volatile memory; a non-volatile FPGA-ACC configured to include a non-volatile memory and to execute a part of the arithmetic processing of the non-volatile CPU; a power gating control unit that controls power supply to each memory cell in the MRAM, the nonvolatile CPU, and the nonvolatile FPGA-ACC; Equipped with.

[0099] This allows the FPGA-based accelerator to be configured so that computational processing is performed separately by the non-volatile FPGA-ACC and the non-volatile CPU. Data related to computations by the non-volatile FPGA-ACC and the non-volatile CPU is stored in MRAM. First, because both the FPGA and the CPU are non-volatile, there is no need to save and write data and configuration data within the FPGA each time the power gating control unit performs power gating. There is also no need to save and write data within the CPU (see Figures 2A to 2C). Second, sequence processing (sequential processing by sequence) at each operation interval is performed in parallel between the CPU and the FPGA-based accelerator (FPGA-ACC). Because parallel processing significantly reduces processing time, the power gating PG time is lengthened, and the increase in power gating time due to parallel processing, i.e., the time reduced by the FPGA-ACC, both the static power portion and the dynamic power portion, are unnecessary. This reduction in unnecessary power is far greater than the increase in power consumption due to the FPGA-ACC's calculation processing (see Figures 3A and 3B). Thus, by incorporating a non-volatile FPGA-ACC into a non-volatile microcontroller consisting of a non-volatile CPU and MRAM, high calculation performance and low power consumption can be achieved. The shorter process time shortens the usage time of the MRAM, which accounts for most of the power consumption, and further reduces power consumption. By making the non-volatile CPU and non-volatile FPGA-ACC connectable, sequential processing can be performed in parallel by the non-volatile CPU and non-volatile FPGA-ACC (see Figure 28). In particular, FPGAs can be reconfigured to support calculation processing and are suitable for parallel processing with CPUs, allowing them to flexibly handle various calculation processes in sensor nodes.

[0100] Second, the device further includes an access controller that controls access to the MRAM by reading and storing data in advance when reading from the MRAM. When receiving a data read command from the non-volatile CPU, this access controller determines whether data has already been read from the MRAM, and if so, transmits the stored data to the non-volatile CPU. This allows access from the CPU to the MRAM in a multiplexed manner, and the read data is temporarily stored in the accelerator. When the same memory address is repeatedly accessed, the temporarily stored data is reused without being read from the MRAM (see Figure 10). An example of such an accelerator configuration is shown in Figure 9. The access controller: an address holding register for holding an address of the MRAM to be read when the address is received; a multiplexer that outputs to the MRAM so as to read out a plurality of destinations of the MRAM held in the address holding register; a plurality of data holding registers for holding data read from the MRAM in response to input from the multiplexer; a comparator that, upon receiving a read command together with a designation of a read destination, compares an address related to the designation of the read destination with a read address held in the address holding register; By providing When a read command is received along with a read destination specification, if the comparator determines that data has already been read from the MRAM, the data that has already been read and is held in one of the multiple data holding registers can be output in response to the read command. Furthermore, the access controller may further include a prefetch address generator connected to the multiplexer, whereby the prefetch address generator generates an address including the address of the read destination stored in the address holding register.

[0101] Third, regarding a data transfer method between a CPU and MRAM via an access controller, When the access controller receives a data read command together with a read address from the CPU, the access controller reads data from a plurality of addresses including the read address from the MRAM in advance; When a data read command is received from the CPU along with the next read address, it is determined whether the data has already been read, and if it is a read command for data that has already been read, the data that has already been read is used as the response to the read command without reading from the MRAM. In other words, prefetch data requests, data storage in the access controller, and fetch operations are performed simultaneously, and the fetch operations are performed sequentially (see Figure 10). This allows for high-speed instruction fetching without interruption. This is effective in applications where a sequence is executed sequentially, such as sensor node applications, where memory accesses are regular. Without changing the performance required for MRAM, the CPU operating frequency can be increased, improving system performance with only the power overhead of the access controller. The access controller can be embedded on the chip as an acceleration unit with little area overhead, enabling the CPU operating frequency to be increased and read / write operations to be guaranteed over a wide temperature range.

[0102] Fourth, a processing method for a microcontroller equipped with a non-volatile CPU, MRAM, and a non-volatile FPGA-ACC as a reconfigurable computing module, an area for storing data exchanged between the non-volatile CPU and the non-volatile FPGA-ACC is set in the MRAM; Data input from the non-volatile CPU to the non-volatile FPGA-ACC is written to the area, A signal indicating that preparation for starting the writing and calculation has been completed is passed from the non-volatile CPU to the non-volatile FPGA-ACC; The non-volatile FPGA-ACC starts an operation using the data written in the area, After the calculation is completed, the calculation result of the non-volatile FPGA-ACC is passed to the non-volatile CPU using the area. This method eliminates the need to pass information about which memory address holds the data required for processing between the non-volatile CPU, non-volatile FPGA-ACC, and MRAM, allowing processing to be carried out efficiently by the microcontroller.

[0103] In particular, in the above-mentioned processing method, it is preferable that the non-volatile CPU and the non-volatile FPGA-ACC are subjected to power gating control. Power gating control means that power is supplied only when arithmetic processing is performed and power is not supplied when arithmetic processing is not performed. By using a non-volatile CPU and a non-volatile FPGA-ACC, it is not necessary to save and write data when turning the power on and off, and power gating can reduce average power consumption as the intermittent operation interval increases (with PG&FPGA-ACC in Figure 30).

[0104] In particular, in the above-mentioned processing method, it is preferable that the arithmetic processing by the non-volatile FPGA-ACC is related to any one of processing of a Laplacian filter, a Discrete Cosine Transform (DCT), a Finite Impulse Response (FIR) filter, and a Fast Fourier Transform (FFT). In particular, assuming a processing method in a microcontroller as an IoT sensor node, as described with reference to Figures 4 and 5, it is preferable to reduce the amount of data by, for example, obtaining feature values ​​or performing image processing in the terminal sensor node 110 so that the sensor data does not need to be processed in the cloud device 140, and then transmit the data to the upper device, the cloud device 140. Therefore, any one of these processes is suitable.

[0105] In particular, in the above-mentioned processing method, it is preferable that sequential processing by the sequence is performed in parallel by the non-volatile CPU and the non-volatile FPGA-based accelerator. Since the sequence processing is performed in parallel by the non-volatile CPU and the non-volatile FPGA-ACC, high calculation performance and low power consumption performance are realized, and it is preferable to apply it to IoT sensor nodes. [Explanation of symbols]

[0106] 1: Device 2,11:STT-MRAM (MRAM) 3,12:NV-CPU 4,13:NV-FPGA 5: Power gating control unit 6,14: Access controller 7: Bus 100: System 110: Sensor node 120: Gateway (GW) 130: Communication Network 140: Cloud device

Claims

1. an address holding register for holding an address of the MRAM to be read when the address is received; a first multiplexer that outputs to the MRAM so as to read out a plurality of destinations of the MRAM held in the address holding register; a plurality of data holding registers for holding data read from the MRAM for each of the designated destinations; a comparator that, upon receiving a read command together with a designation of a read destination, compares an address related to the designation of the read destination with a read address held in the address holding register; a second multiplexer connected to the plurality of data holding registers; an output control connected to the second multiplexer; Equipped with an access controller that, when receiving a read command together with a read destination specification, if the comparator determines that data has already been read from the MRAM, outputs data that has already been read and held in one of the plurality of data holding registers from the second multiplexer under the control of the output control unit in response to the read command, without reading the address of the MRAM related to the read destination specification received together with the read command.

2. a prefetch address generator coupled to the first multiplexer; 2. The access controller according to claim 1, wherein said prefetch address generator generates an address including a read destination address held in said address holding register.

3. A data transfer method between a CPU and an MRAM via the access controller according to claim 1 or 2, When the access controller receives a data read command together with a read address from the CPU, the access controller reads data at a plurality of addresses including the read address from the MRAM in advance; When a data read command is received from the CPU along with the next read address, the data transfer method determines whether the data has already been read, and if the command is to read data that has already been read, the data that has already been read is used as a response to the read command without reading from the MRAM.

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