Semiconductor device with built-in electrical components in a circuit board

Abstract

To reduce the inductance of the current path in a semiconductor device that incorporates electrical components within the circuit board.SOLUTION: A semiconductor device 10 comprises a substrate body 12 having a first side 12a and a second side 12b, electrical components 21, 22, 31, 32 disposed within the substrate body, first terminals 42 and second terminals 40 provided on the first or second side, a first internal conductor pattern 64 provided in a circuit layer L2 located between the electrical components and the first side and electrically connected to the first terminal and the electrical components, and a second internal conductor pattern 67 provided in circuit layer L5 between the electrical component and the second surface and electrically connected to the second terminal and the electrical component. The first internal conductor pattern and the second internal conductor pattern are at least partially opposite each other inside the substrate body.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a semiconductor device that incorporates electrical components in a circuit board.

[0002] Patent Document 1 discloses a semiconductor device. This semiconductor device includes a substrate body, an electrical component disposed within the substrate body, a first conductor pattern located on the upper surface of the substrate body, and a second conductor pattern located on the lower surface of the substrate body. The first conductor pattern is connected to the electrical component from above via a plurality of vias, and the second conductor pattern is connected to the electrical component from below via a plurality of vias. The first conductor pattern and the second conductor pattern function as a current path for a current passing through the electrical component. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 10,229,895 Summary of the Invention [Problem to be solved by the invention]

[0004] In semiconductor devices, it is necessary to reduce the inductance of the current paths in order to suppress losses in the current paths. To reduce the inductance of the current paths, it is effective to have two or more current paths connected to electrical components run parallel to each other in opposite directions. However, when two current paths are distributed on the top and bottom surfaces of a substrate body, as in conventional semiconductor devices, the effect of running the two current paths parallel to each other cannot be fully achieved due to the presence of a certain distance between the two current paths.

[0005] In view of the above, the present specification provides a technique that can reduce the inductance of a current path in a semiconductor device that has an electric component built into a circuit board. [Means for solving the problem]

[0006] The semiconductor device (10) disclosed in this specification comprises a substrate body (12) having a first surface (12a) and a second surface (12b), electrical components (21, 22, 31, 32) disposed within the substrate body, a first terminal (42) and a second terminal (40) provided on the first surface or the second surface, a first internal conductor pattern (64) provided on a circuit layer (L2) located between the electrical components and the first surface and electrically connected to the first terminal and the electrical components, and a second internal conductor pattern (67) provided on a circuit layer (L5) located between the electrical components and the second surface and electrically connected to the second terminal and the electrical components. The first internal conductor pattern and the second internal conductor pattern at least partially face each other within the substrate body.

[0007] In the above-described configuration, the first and second internal conductor patterns function as two current paths connected to the electrical component. Because the first and second internal conductor patterns are provided on circuit layers within the board body, the distance between the first and second internal conductor patterns is relatively small. This allows the two current paths connected to the electrical component to run parallel in opposite directions while being relatively close to each other. Additionally, the first internal conductor pattern is located between the first surface of the board body and the electrical component, and the second internal conductor pattern is located between the second surface of the board body and the electrical component. Distributing the first and second internal conductor patterns on both sides of the electrical component in this manner allows the structure of the board body to be designed symmetrically in the thickness direction, thereby suppressing uneven thermal deformation of the board body, such as warping and undulation. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view showing a semiconductor device 10 according to a first embodiment. [Figure 2] 1 is a circuit diagram showing a circuit structure of a semiconductor device 10 according to a first embodiment. [Figure 3]1. For clarity, hatching of the substrate body 12 has been omitted. Also, some overlapping components have been intentionally shown at different positions. [Figure 4] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device 110 according to a second embodiment. [Figure 5] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device 210 according to a third embodiment. [Figure 6] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device 310 according to a fourth embodiment. [Figure 7] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device 410 according to a fifth embodiment. [Figure 8] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device 510 according to a sixth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] In one embodiment of the present technology, the semiconductor device (10) may further include a third internal conductor pattern (65; 66) provided in a circuit layer located in the same depth range as the electrical component, and a first connection via (74; 78) electrically connecting one of the first internal conductor pattern and the second internal conductor pattern to the third internal conductor pattern. In this case, the third internal conductor pattern may at least partially oppose the other of the first internal conductor pattern and the second internal conductor pattern inside the substrate body. With this configuration, the third internal conductor pattern functions as the same current path as the first internal conductor pattern or the second internal conductor pattern, thereby allowing the two current paths connected to the electrical component to run side by side in an even closer positional relationship.

[0010] In the above embodiment, the semiconductor device may further include a fourth internal conductor pattern (66; 65) located in the same depth range as the electrical component but at a different depth from the third internal conductor pattern, and a second connection via (77) electrically connecting the third internal conductor pattern and the fourth internal conductor pattern. In this case, the fourth internal conductor pattern may at least partially face the other of the first internal conductor pattern and the second internal conductor pattern inside the substrate body. With this configuration, in addition to the third internal conductor pattern, the fourth internal conductor pattern also functions as the same current path as the first internal conductor pattern or the second internal conductor pattern. This allows the two current paths connected to the electrical component to run parallel to each other in closer positional relationship.

[0011] Alternatively, the semiconductor device may include, instead of the second connection via, a third connection via (78) that electrically connects the other of the first and second internal conductor patterns to the fourth internal conductor pattern. With this configuration, the third and fourth internal conductor patterns that are close to each other can function as two current paths connected to an electrical component. This allows the two current paths connected to the electrical component to run parallel to each other in an even closer positional relationship.

[0012] In one embodiment of the present technology, at least one of the thickness of the first internal conductor pattern and the thickness (TH) of the second internal conductor pattern may be greater than the thickness of other internal conductor patterns within the substrate body. With this configuration, it is possible to expect a reduction in inductance due to an increase in cross-sectional area in at least one of two current paths connected to an electrical component. Furthermore, it is possible to expect a cooling effect for the electrical component due to improved thermal conductivity by increasing the thickness of the internal conductor pattern.

[0013] In one embodiment of the present technology, at least one of the first internal conductor pattern and the second internal conductor pattern may have an opening (67a) in a region facing the electrical component. In a region where an electrical component is interposed between the two current paths, the effect of running the two current paths parallel to each other is reduced. Therefore, by eliminating the current path in the region facing the electrical component, more current may be concentrated in other portions where the effect of running parallel to each other is expected.

[0014] In one embodiment of the present technology, the semiconductor device may further include a surface electric component (52) provided on the first surface and controlling the operation of the electric component. According to the configuration of the present technology, loss in the current path is reduced, thereby suppressing a temperature rise in the semiconductor device. Therefore, even when the surface electric component is disposed on the first surface of the substrate body, it is possible to prevent the surface electric component from overheating.

[0015] In one embodiment of the present technology, the electrical component may include a power semiconductor element (21, 22) and a heat sink plate (31, 32) to which the power semiconductor element is joined. Because a relatively large current flows through the power semiconductor element, it is highly desirable to reduce impedance in the current path. The configuration disclosed in this specification can be suitably adopted for a semiconductor device including such a power semiconductor element. [Example]

[0016] (Example 1) A semiconductor device 10 of Example 1 will be described with reference to the drawings. The semiconductor device 10 of this example can be employed, for example, in a power control unit of an electric vehicle, and can constitute part of a power conversion circuit for converting power between a power source and a traction motor. The term "electric vehicle" as used herein broadly refers to a vehicle having a traction motor that drives the wheels, and includes, for example, an electric vehicle that is charged by external power, a hybrid vehicle that has an engine in addition to a traction motor, and a fuel cell vehicle that uses a fuel cell as its power source. However, the application of the semiconductor device 10 of this example is not limited to electric vehicles, and it can be employed in various electrical devices.

[0017] As shown in FIGS. 1 to 3 , a semiconductor device 10 includes a substrate body 12, two semiconductor elements 21 and 22, and two heat sink plates 31 and 32. The substrate body 12 has a plate-like shape and includes an upper surface 12a and a lower surface 12b opposite the upper surface 12a. The substrate body 12 is made of an insulating material such as epoxy resin or other resin material. From the upper surface 12a to the lower surface 12b, the substrate body 12 includes an upper layer 14, an intermediate layer 16, and a lower layer 18. The upper layer 14 includes the upper surface 12a of the substrate body 12. The lower layer 18 includes the lower surface 12b of the substrate body 12. The intermediate layer 16 is located between the upper layer 14 and the lower layer 18.

[0018] Here, the X direction and Y direction in the drawing are directions parallel to the upper surface 12a and lower surface 12b of the substrate body 12 and are perpendicular to each other. The Z direction is a direction perpendicular to the upper surface 12a and lower surface 12b of the substrate body 12 and is a direction perpendicular to both the X direction and the Y direction. That is, the above-mentioned upper layer 14, intermediate layer 16, and lower layer 18 are stacked along the Z direction.

[0019] The semiconductor elements 21 and 22 and the heat sink plates 31 and 32 are each a pair of electrical components that constitute part of an electrical circuit in the semiconductor device 10 and are electrically connected to each other inside the substrate body 12. The two semiconductor elements 21 and 22 are disposed on the intermediate layer 16 of the substrate body 12 together with the two heat sink plates 31 and 32. Each of the semiconductor elements 21 and 22 is a power semiconductor element, particularly a switching element. This switching element may be, for example, an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). Each of the semiconductor elements 21 and 22 has an upper electrode 21 a and a lower electrode 21 b and a lower electrode 22 b, and can establish or interrupt electrical conduction between the upper electrode 21 a and the lower electrode 21 b.

[0020] As an example, the two semiconductor elements 21, 22 include a first semiconductor element 21 and a second semiconductor element 22. The first semiconductor element 21 and the second semiconductor element 22 are electrically connected in series inside the substrate body 12. As described above, the two semiconductor elements 21, 22 are switching elements such as IGBTs or MOSFETs. The semiconductor device 10 of this embodiment can constitute, for example, a part of an inverter circuit or a DC-DC converter circuit. The number of semiconductor elements 21, 22 is not limited to two. Furthermore, the semiconductor device 10 may include at least one other electrical component instead of the semiconductor elements 21, 22 and the heat sink plates 31, 32.

[0021] The two heat sink plates 31, 32 each have a plate-like shape and are arranged parallel to the substrate body 12. Each of the heat sink plates 31, 32 is made of a conductor such as copper or another metal. As an example, the two heat sink plates 31, 32 are arranged along the X direction. The two heat sink plates 31, 32 include a first heat sink plate 31 and a second heat sink plate 32. The first semiconductor element 21 is arranged on the first heat sink plate 31, and the lower surface electrode 21b of the first semiconductor element 21 is electrically connected to the first heat sink plate 31. Similarly, the second semiconductor element 22 is arranged on the second heat sink plate 32, and the lower surface electrodes 21b, 22b of the second semiconductor element 22 are electrically connected to the second heat sink plate 32.

[0022] The semiconductor device 10 includes a plurality of terminals 40, 42, and 44. These terminals 40, 42, and 44 are external connection terminals for connecting to an external circuit. The plurality of terminals 40, 42, and 44 are made of a conductor such as copper or another metal. As an example, the plurality of terminals 40, 42, and 44 include a P terminal 40, an N terminal 42, and an O terminal 44. The plurality of terminals 40, 42, and 44 are located on the lower surface 12b of the substrate body 12. However, some or all of the plurality of terminals 40, 42, and 44 may be located on the upper surface 12a of the substrate body 12.

[0023] The P terminal 40 is electrically connected to the first heat sink plate 31 inside the substrate body 12 and is electrically connected to the lower electrode 21b of the first semiconductor element 21 via the first heat sink plate 31. The N terminal 42 is electrically connected to the upper electrode 22a of the second semiconductor element 22 inside the substrate body 12. The O terminal 44 is electrically connected to the upper electrode 21a of the first semiconductor element 21 and the second heat sink plate 32 inside the substrate body 12. That is, the O terminal 44 is electrically connected to each of the upper electrode 21a of the first semiconductor element 21 and the lower electrode 22b of the second semiconductor element 22. As a result, when the first semiconductor element 21 is turned on, the P terminal 40 and the O terminal 44 are electrically connected. On the other hand, when the second semiconductor element 22 is turned on, the N terminal 42 and the O terminal 44 are electrically connected.

[0024] The substrate body 12 is provided with multiple circuit layers L1-L6, forming a multilayer substrate structure. The multiple circuit layers L1-L6 include a first circuit layer L1, a second circuit layer L2, a third circuit layer L3, a fourth circuit layer L4, a fifth circuit layer L5, and a sixth circuit layer L6. The first circuit layer L1 is located on the top surface 12a of the substrate body 12. The second circuit layer L2 is located within the upper layer 14 of the substrate body 12. The third circuit layer L3 is located at the boundary between the upper layer 14 and the middle layer 16 of the substrate body 12. The fourth circuit layer L4 is located at the boundary between the substrate body 12, the middle layer 16, and the lower layer 18. The fifth circuit layer L5 is located within the lower layer 18 of the substrate body 12. The sixth circuit layer L6 is located on the bottom surface 12b of the substrate body 12.

[0025] The first circuit layer L1 has a first conductor pattern 61. The first conductor pattern 61 is made of a conductor such as copper or another metal. The first conductor pattern 61 constitutes a control circuit 50 that controls the two semiconductor elements 21 and 22. To this end, a plurality of surface electrical components 52 are mounted on the first conductor pattern 61. The plurality of surface electrical components 52 includes, for example, a gate drive circuit that controls the switching of the semiconductor elements 21 and 22.

[0026] The first conductor pattern 61 here is a general term for one or more conductor patterns required to configure the control circuit 50. That is, the first conductor pattern 61 may be a single conductor pattern or a combination of multiple conductor patterns. The same applies to the second conductor pattern 62 to the ninth conductor pattern 69 described below. Each of the second conductor pattern 62 to the ninth conductor pattern 69 is a general term for one or more conductor patterns having a common function, and may be a single conductor pattern or a combination of multiple conductor patterns.

[0027] The second circuit layer L2 has a plurality of conductor patterns 62, 63, and 64. Each of the conductor patterns 62, 63, and 64 is made of a conductor such as copper or another metal. The plurality of conductor patterns 62, 63, and 64 includes a second conductor pattern 62, a third conductor pattern 63, and a fourth conductor pattern 64. Although the plurality of conductor patterns 62, 63, and 64 are actually located on the same plane, in FIG. 3 , the second conductor pattern 62 is intentionally displaced relative to the third conductor pattern 63 and the fourth conductor pattern 64 for the purpose of clarity of illustration.

[0028] The second conductor pattern 62 extends over most of the second circuit layer L2 and is disposed so as to face the multiple semiconductor elements 21, 22. This allows heat generated in the semiconductor elements 21, 22 to be diffused over a wide area of ​​the board body 12 through the second conductor pattern 62. The second conductor pattern 62 also functions as a shielding layer that blocks electromagnetic noise radiated from the semiconductor elements 21, 22. Although not particularly limited, the second conductor pattern 62 may be connected to a ground potential, thereby improving the function of the second conductor pattern 62 as a shielding layer.

[0029] The third conductor pattern 63 is connected to the O terminal 44 via the first via 71. In addition, the third conductor pattern 63 is connected to the upper surface electrode 21a of the first semiconductor element 21 and the second heat sink plate 32 via two second vias 72. The first via 71 and the second via 72 are made of a conductor such as copper or another metal. As a result, the two semiconductor elements 21, 22 are electrically connected in series by the second conductor pattern 62, and are also electrically connected to the O terminal 44 via the second conductor pattern 62. The third conductor pattern 63 forms part of a current path through which a current flows through the semiconductor elements 21, 22 and the heat sink plates 31, 32, which are a set of electrical components.

[0030] The fourth conductor pattern 64 is connected to the upper surface electrode 22a of the second semiconductor element 22 via the third via 73. In addition, the fourth conductor pattern 64 is connected to the N terminal 42 via the fourth via 74. The third via 73 and the fourth via 74 are made of a conductor such as copper or another metal. As a result, the upper surface electrode 22a of the second semiconductor element 22 is electrically connected to the N terminal 42 via the fourth conductor pattern 64.

[0031] The semiconductor elements 21, 22 and heat sink plates 31, 32 are arranged on the third circuit layer L3 and the fourth circuit layer L4. The heat sink plates 31, 32 have a thickness equal to the distance from the third circuit layer L3 to the fourth circuit layer L4. The semiconductor elements 21, 22 arranged on the heat sink plates 31, 32 are located on the third circuit layer L3. In addition, a fifth conductor pattern 65 and a sixth conductor pattern 66 are provided on the third circuit layer L3 and the fourth circuit layer L4, respectively. Each of the conductor patterns 65, 66 is made of a conductor such as copper or another metal. The use of the fifth conductor pattern 65 and the sixth conductor pattern 66 in this embodiment is not particularly limited. The fifth conductor pattern 65 and the sixth conductor pattern 66 may be connected to a ground potential, for example.

[0032] The fifth conductor pattern 65 of the third circuit layer L3 is located in the same depth range in the board body 12 as the heat sink plates 31, 32. The depth range here refers to the range in the Z direction. Therefore, two openings 65a, 65b are provided in the fifth conductor pattern 65, corresponding to the two heat sink plates 31, 32. That is, although the fifth conductor pattern 65 is shown in FIG. 3 as being divided at the positions of the two heat sink plates 31, 32, the fifth conductor pattern 65 is actually formed integrally over a wide range of the third circuit layer L3.

[0033] Similarly, the sixth conductor pattern 66 of the fourth circuit layer L4 is located in the same depth range in the board body 12 as the heat sink plates 31, 32. The depth range here refers to the range in the Z direction. Therefore, the sixth conductor pattern 66 also has two openings 66a, 66b aligned with the two heat sink plates 31, 32. That is, although the sixth conductor pattern 66 is shown in FIG. 3 as being divided at the positions of the two heat sink plates 31, 32, the actual sixth conductor pattern 66 is integrally formed over a wide range of the fourth circuit layer L4.

[0034] The fifth circuit layer L5 has a plurality of conductor patterns 67, 68. Each of the conductor patterns 67, 68 is made of a conductor such as copper or another metal. The plurality of conductor patterns 67, 68 includes a seventh conductor pattern 67 and an eighth conductor pattern 68. Although the plurality of conductor patterns 67, 68 are actually located on the same plane, in FIG. 3 the seventh conductor pattern 67 is intentionally displaced relative to the eighth conductor pattern 68 for the purpose of clarity of illustration.

[0035] The seventh conductor pattern 67 is connected to the first heat sink plate 31 via a fifth via 75. In addition, the seventh conductor pattern 67 is connected to the P terminal 40 via a sixth via 76. The fifth via 75 and the sixth via 76 are made of a conductor such as copper or another metal. As a result, the bottom electrode 21b of the first semiconductor element 21 is electrically connected to the P terminal 40 via the first heat sink plate 31 and the seventh conductor pattern 67. The seventh conductor pattern 67 forms part of a current path through which a current passes through the semiconductor elements 21, 22 and the heat sink plates 31, 32, which are a set of electrical components.

[0036] The eighth conductor pattern 68 extends over most of the fifth circuit layer L5 and is disposed so as to face the multiple semiconductor elements 21, 22. This allows heat generated in the semiconductor elements 21, 22 to be diffused over a wide area of ​​the board body 12 through the eighth conductor pattern 68. The eighth conductor pattern 68 also functions as a shielding layer that blocks electromagnetic noise radiated from the semiconductor elements 21, 22. Although not particularly limited, the eighth conductor pattern 68 may be connected to ground potential, thereby improving the function of the eighth conductor pattern 68 as a shielding layer.

[0037] The sixth circuit layer L6 has a ninth conductor pattern 69. The ninth conductor pattern 69 extends over most of the sixth circuit layer L6 and faces the eighth conductor pattern 68 on the fifth circuit layer L5. The ninth conductor pattern 69 is made of a conductor such as copper or another metal. Heat generated in the semiconductor elements 21 and 22 is diffused over a wide area of ​​the board body 12 not only through the eighth conductor pattern 68 but also through the ninth conductor pattern 69. The ninth conductor pattern 69 also functions as a shielding layer that blocks electromagnetic noise radiated from the semiconductor elements 21 and 22. Like the eighth conductor pattern 68, the ninth conductor pattern 69 may be connected to ground potential, thereby improving the ninth conductor pattern 69's function as a shielding layer.

[0038] As described above, in the semiconductor device 10 of this embodiment, a set of electrical components including the semiconductor elements 21 and 22 and the heat sink plates 31 and 32 are disposed on the intermediate layer 16 of the substrate body 12. The P terminal 40 and the N terminal 42 are provided on the lower surface 12b of the substrate body 12. Inside the substrate body 12, the fourth conductor pattern 64 is provided on the second circuit layer L2 located between the intermediate layer 16 and the upper surface 12a, and the seventh conductor pattern 67 is provided on the fifth circuit layer L5 located between the intermediate layer 16 and the lower surface 12b. The fourth conductor pattern 64 is electrically connected to the N terminal 42 and the second semiconductor element 22, and functions as a current path for current flowing through the electrical components of the substrate body 12. The seventh conductor pattern 67 is also electrically connected to the P terminal 40 and the first heat sink plate 31, and functions as a current path for current flowing through the electrical components (i.e., the semiconductor elements 21 and 22 and the heat sink plates 31 and 32) within the substrate body 12. The fourth conductor pattern 64 and the seventh conductor pattern 67 are at least partially opposed to each other inside the substrate body 12.

[0039] As described above, the semiconductor device 10 has a circuit structure in which two semiconductor elements 21 and 22, which are switching elements, are connected in series. This can constitute part of an inverter circuit or a DC-DC converter circuit. In an inverter circuit or a DC-DC converter circuit, the two semiconductor elements 21 and 22 are controlled to be turned on alternately, resulting in currents passing through the fourth conductor pattern 64 and the seventh conductor pattern 67 in opposite directions. At this time, the fourth conductor pattern 64 and the seventh conductor pattern 67 are at least partially opposed to each other within the substrate main body 12, resulting in two current paths running parallel but in opposite directions. This reduces the impedance in the two conductor patterns 64 and 67. In particular, the fourth conductor pattern 64 and the seventh conductor pattern 67 are provided on circuit layers L2 and L5, respectively, within the substrate main body 12, and the distance between the two conductor patterns 64 and 67 is relatively short. Therefore, the impedance in the two conductor patterns 64 and 67 is effectively reduced.

[0040] Here, in order to position the fourth conductor pattern 64 and the seventh conductor pattern 67 close to each other, it is possible to arrange these two conductor patterns 64, 67 on the same upper layer 14 (or the same lower layer 18). However, if the two conductor patterns 64, 67 were arranged on the same side of a set of electrical components including the semiconductor elements 21, 22 and the heat sink plates 31, 32, the structure of the substrate body 12 would be asymmetric in the thickness direction, which could lead to uneven thermal deformation of the substrate body 12, such as warping or undulation. In contrast, in the semiconductor device 10 of this embodiment, the fourth conductor pattern 64 and the seventh conductor pattern 67 are located on the upper layer 14 and the lower layer 18 of the substrate body 12, respectively, and are distributed on both sides of the set of electrical components. With this configuration, the structure of the substrate body 12 can be designed symmetrically in the thickness direction, for example, by making the thicknesses of the upper layer 14 and the lower layer 18 equal, thereby suppressing uneven thermal deformation of the substrate body 12.

[0041] The semiconductor device 10 according to the first embodiment is an example of the technology disclosed in the present specification and does not particularly limit the content of the technology. The substrate body 12 in the first embodiment is an example of the substrate body in the present technology. The upper surface 12a and the lower surface 12b of the substrate body 12 in the present embodiment are examples of the first surface and the second surface of the substrate body in the present technology, respectively. The first semiconductor element 21, the second semiconductor element 22, the first heat sink plate 31, and the second heat sink plate 32 in the present embodiment are examples of the electrical component in the present technology. The N terminal 42 and the P terminal 40 in the present embodiment are examples of the first terminal and the second terminal in the present technology, respectively. The fourth conductor pattern 64 in the present embodiment is an example of the first internal conductor pattern in the present technology. The seventh conductor pattern 67 in the present embodiment is an example of the second internal conductor pattern in the present technology. The surface electrical component 52 in the present embodiment is an example of the surface electrical component in the present technology.

[0042] (Example 2) A semiconductor device 110 of Example 2 will be described with reference to Figure 4. In the semiconductor device 110 of Example 2, the fifth conductor pattern 65 of the third circuit layer L3 and the sixth conductor pattern 66 of the fourth circuit layer L4 are electrically connected to the fourth conductor pattern 64, and in this respect, the semiconductor device 110 differs from the semiconductor device 10 of Example 1. Below, differences from Example 1 will be mainly described, and components common to Example 1 will be denoted by the same reference numerals and will not be described again.

[0043] The fifth conductor pattern 65 and the sixth conductor pattern 66 are provided on the third circuit layer L3 or the fourth circuit layer L4, and are located at the same depth as the semiconductor elements 21, 22 and the heat sink plates 31, 32. The fifth conductor pattern 65 and the sixth conductor pattern 66 are connected to the fourth conductor pattern 64 via a fourth via 74. At least one seventh via 77 is provided in the intermediate layer 16 of the substrate body 12. The seventh via 77 is made of a conductor such as copper or another metal. This electrically connects the fifth conductor pattern 65 and the sixth conductor pattern 66. As is clear from FIG. 4 , the fifth conductor pattern 65 and the sixth conductor pattern 66 are closer to the seventh conductor pattern 67 than the fourth conductor pattern 64. That is, the distance from the fifth conductor pattern 65 or the sixth conductor pattern 66 to the seventh conductor pattern 67 is shorter than the distance from the fourth conductor pattern 64 to the seventh conductor pattern 67.

[0044] According to the configuration of this embodiment, the fifth conductor pattern 65 and the sixth conductor pattern 66 function as the same current path as the fourth conductor pattern 64. The fifth conductor pattern 65 and the sixth conductor pattern 66, which function as current paths, are located close to the seventh conductor pattern 67, which is a current path running parallel to the fifth conductor pattern 65 but in the opposite direction. This further reduces the impedance in the semiconductor device 110.

[0045] The semiconductor device 110 according to the second embodiment is an example of the technology disclosed in the present specification, and does not particularly limit the content of the technology. The fifth conductor pattern 65 in the present embodiment is an example of the third inner conductor pattern in the present technology. The sixth conductor pattern 66 in the present embodiment is an example of the fourth inner conductor pattern in the present technology. The fourth via 74 in the present embodiment is an example of the first connection via in the present technology. The seventh via 77 in the present embodiment is an example of the second connection via in the present technology.

[0046] (Example 3) A semiconductor device 210 of Example 3 will be described with reference to Figure 5. In the semiconductor device 210 of Example 3, the fifth conductor pattern 65 of the third circuit layer L3 and the sixth conductor pattern 66 of the fourth circuit layer L4 are electrically connected to the seventh conductor pattern 67, and in this respect, the semiconductor device 210 differs from the semiconductor devices 10 and 110 of Examples 1 and 2. Below, differences from Examples 1 and 2 will be mainly described, and components common to Examples 1 and 2 will be denoted by the same reference numerals and will not be described again.

[0047] The semiconductor device 210 of this embodiment further includes at least one eighth via 78. The eighth via 78 is located between the fourth circuit layer L4 and the fifth circuit layer L5 and connects the sixth conductor pattern 66 and the seventh conductor pattern 67 to each other. The eighth via 78 is made of a conductor such as copper or another metal. This electrically connects the sixth conductor pattern 66 and the seventh conductor pattern 67. In addition, as in the second embodiment, at least one seventh via 77 is provided in the intermediate layer 16 of the substrate main body 12. As is clear from FIG. 4 , the fifth conductor pattern 65 and the sixth conductor pattern 66 are closer to the fourth conductor pattern 64 than the seventh conductor pattern 67. That is, the distance from the fifth conductor pattern 65 or the sixth conductor pattern 66 to the fourth conductor pattern 64 is shorter than the distance from the seventh conductor pattern 67 to the fourth conductor pattern 64.

[0048] According to the configuration of this embodiment, the fifth conductor pattern 65 and the sixth conductor pattern 66 function as the same current path as the seventh conductor pattern 67. The fifth conductor pattern 65 and the sixth conductor pattern 66, which function as current paths, are located close to the fourth conductor pattern 64, which is a current path running parallel to the fifth conductor pattern 64 in the opposite direction. This further reduces the impedance in the semiconductor device 210.

[0049] The semiconductor device 110 according to the third embodiment is an example of the technology disclosed in the present specification, and does not particularly limit the content of the technology. The sixth conductor pattern 66 in this embodiment is an example of the third inner conductor pattern in the technology. The fifth conductor pattern 65 in this embodiment is an example of the fourth inner conductor pattern in the technology. The eighth via 78 in this embodiment is an example of the first connection via in the technology. The seventh via 77 in this embodiment is an example of the second connection via in the technology.

[0050] (Example 4) A semiconductor device 310 of Example 4 will be described with reference to Figure 6. In the semiconductor device 310 of this example, the fifth conductor pattern 65 of the third circuit layer L3 is electrically connected to the fourth conductor pattern 64, and the sixth conductor pattern 66 of the fourth circuit layer L4 is electrically connected to the seventh conductor pattern 67. In these respects, the semiconductor device 310 of this example differs from the semiconductor devices 10, 110, and 210 of Examples 1-3 of this example. Below, differences from Examples 1-3 will be mainly described, and components common to Examples 1-3 will be denoted by the same reference numerals and will not be described again.

[0051] In the semiconductor device 310 of this embodiment, the fifth conductor pattern 65 is connected to the fourth conductor pattern 64 through the fourth via 74. Meanwhile, the sixth conductor pattern 66 is connected to the seventh conductor pattern 67 through at least one eighth via 78. The fifth conductor pattern 65 and the sixth conductor pattern 66 are located in the same depth range as the semiconductor elements 21, 22 and the heat sink plates 31, 32, and are close to each other.

[0052] According to the configuration of the present embodiment, the fifth conductor pattern 65 functions as the same current path as the fourth conductor pattern 64, and the sixth conductor pattern 66 functions as the same current path as the seventh conductor pattern 67. The fifth conductor pattern 65, which functions as a current path, is located close to the sixth conductor pattern 66, which functions as a current path running in the opposite direction, so that the impedance in the semiconductor device 310 is further reduced.

[0053] The semiconductor device 110 according to the fourth embodiment is an example of the technology disclosed in the present specification, and does not particularly limit the content of the technology. The fifth conductor pattern 65 in this embodiment is an example of the third inner conductor pattern in the technology. The sixth conductor pattern 66 in this embodiment is an example of the fourth inner conductor pattern in the technology. The fourth via 74 in this embodiment is an example of the first connecting via in the technology. The eighth via 78 in this embodiment is an example of the third connecting via in the technology.

[0054] Fifth Embodiment A semiconductor device 410 of the fifth embodiment will be described with reference to Fig. 7. In the semiconductor device 410 of the fifth embodiment, the thickness TH of the seventh conductor pattern 67 is greater than the thicknesses of the other conductor patterns 61-66, 68, and 69, and in this respect, it differs from the semiconductor device 210 of the third embodiment. Below, differences from the third embodiment will be mainly described, and components common to the third embodiment will be denoted by the same reference numerals and will not be described again.

[0055] Increasing the thickness TH of the seventh conductor pattern 67 increases the cross-sectional area of ​​the current path of the seventh conductor pattern 67. This is expected to have an effect of reducing inductance. Furthermore, increasing the thickness of the seventh conductor pattern 67 improves the thermal conductivity of the seventh conductor pattern 67, which can be expected to have an effect of cooling the semiconductor elements 21, 22 and the heat sink plates 31, 32.

[0056] The semiconductor device 410 according to the fifth embodiment is one example of the technology disclosed in the present specification, and does not particularly limit the content of the technology. The thickness of the fourth conductor pattern 64 may be increased instead of or in addition to the seventh conductor pattern 67. The configuration according to this embodiment can also be similarly adopted in other embodiments disclosed in the present specification.

[0057] Sixth Embodiment A semiconductor device 510 of a sixth embodiment will be described with reference to Fig. 8. In the semiconductor device 510 of the sixth embodiment, an opening 67a is provided in the seventh conductor pattern 67, and in this respect, the semiconductor device 510 differs from the semiconductor device 210 of the third embodiment. Below, differences from the third embodiment will be mainly described, and components common to the third embodiment will be denoted by the same reference numerals and will not be described again.

[0058] The openings 67a of the seventh conductor pattern 67 are provided in a range facing the second heat sink plate 32. In a range where the second heat sink plate 32 is interposed between the fourth conductor pattern 64 and the seventh conductor pattern 67, which function as a current path, the effect of running the fourth conductor pattern 64 and the seventh conductor pattern 67 in parallel is reduced. For this reason, by removing parts of the seventh conductor pattern 67 in the range facing the second heat sink plate 32, more current may be concentrated in other portions where the effect of running them in parallel is expected.

[0059] The semiconductor device 510 according to the sixth embodiment is one example of the technology disclosed in the present specification, and does not particularly limit the content of the technology. Instead of or in addition to the seventh conductor pattern 67, a similar opening may be provided in the fourth conductor pattern 64. Furthermore, the configuration according to this embodiment can be similarly adopted in other embodiments disclosed in the present specification.

[0060] Although specific examples of the technology disclosed in this specification have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or in the drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. The technology exemplified in this specification or in the drawings can achieve multiple objectives simultaneously, and achieving one of these objectives itself has technical utility. [Explanation of symbols]

[0061] 10, 110, 210, 310, 410, 510: Semiconductor device 12: Board body 12a:Top surface 12b: Bottom surface 21, 22: Semiconductor elements 31, 32: Heat sink plate 40, 42, 44: Terminals 50: Control circuit 52: Surface electrical components 61-69: Conductor pattern 71-78:Beer L1-L6:Circuit layer

Claims

1. A semiconductor device (10) having an electrical component built into a circuit board, a substrate body (12) having a first surface (12a) and a second surface (12b); Electrical components (21, 22, 31, 32) disposed within the substrate body; a first terminal (42) and a second terminal (40) provided on the first surface or the second surface; a first internal conductor pattern (64) provided on a circuit layer (L2) located between the electrical component and the first surface, the first internal conductor pattern (64) being electrically connected to the first terminal and the electrical component; a second internal conductor pattern (67) provided on a circuit layer (L5) located between the electrical component and the second surface, the second internal conductor pattern (67) being electrically connected to the second terminal and the electrical component; Equipped with the first internal conductor pattern and the second internal conductor pattern have sections that run parallel to and face each other in the thickness direction of the substrate body, During at least a part of a period during which a current flows through the electrical component, currents flow simultaneously in the first internal conductor pattern and the second internal conductor pattern in the parallel sections in opposite directions to each other. Semiconductor device.

2. a third internal conductor pattern (65:66) provided on a circuit layer located in the same depth range as the electrical component; a first connection via (74; 78) electrically connecting one of the first internal conductor pattern and the second internal conductor pattern to the third internal conductor pattern, 2. The semiconductor device according to claim 1, wherein the third internal conductor pattern and the other of the first internal conductor pattern and the second internal conductor pattern have sections that run parallel to and face each other in the thickness direction of the substrate body.

3. a fourth internal conductor pattern (66; 65) located in the same depth range as the electrical component and at a different depth from the third internal conductor pattern; a second connection via (77) electrically connecting the third internal conductor pattern and the fourth internal conductor pattern; 3. The semiconductor device according to claim 2, wherein the fourth internal conductor pattern and the other of the first internal conductor pattern and the second internal conductor pattern have sections that run parallel to and face each other in the thickness direction of the substrate body.

4. a fourth internal conductor pattern (66) located in the same depth range as the electrical component and at a different depth from the third internal conductor pattern (65); a third connection via (78) electrically connecting the other of the first internal conductor pattern and the second internal conductor pattern to the fourth internal conductor pattern, 3. The semiconductor device according to claim 2, wherein the third internal conductor pattern and the fourth internal conductor pattern have sections that run parallel to and face each other in the thickness direction of the substrate body.

5. 5. The semiconductor device according to claim 1, wherein at least one of the thickness of the first internal conductor pattern and the thickness (TH) of the second internal conductor pattern is greater than the thickness of other internal conductor patterns within the substrate body.

6. 6. The semiconductor device according to claim 1, wherein at least one of said first internal conductor pattern and said second internal conductor pattern has an opening (67a) in a range facing said electrical component.

7. The semiconductor device according to claim 1 , further comprising a surface electrical component (52) provided on the first surface and controlling the operation of the electrical component.

8. The semiconductor device according to claim 1 , wherein the electrical components include a power semiconductor element (21, 22) and a heat sink plate (31, 32) to which the power semiconductor element is joined.

Images