Level Shift Circuit

Abstract

To provide a level shift circuit in which an operation voltage range is improved.SOLUTION: A first output part 21 includes: transistors M1 and M2; and a transistor M11 connected to a diode. A second output part 22 includes: transistors M3 and M4; and a transistor M12 connected to the diode. A third output part 23 includes transistors M5 and M6. A gate of the transistor M6 is connected to a connection node A between the transistor M11 and the transistor M1. A connection node C between the transistor M5 and the transistor M6 is input into an output buffer part 3.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a level shift circuit. [Background technology]

[0002] Global warming is believed to be caused by an intensification of the greenhouse effect in the atmosphere due to rising concentrations of greenhouse gases such as CO2, and with the rapid development of a communications and information society, reducing the power consumption of electronic devices has become a major issue. Many semiconductor integrated circuits are used in electronic devices, and the present invention aims to contribute to the prevention of global warming by enabling low-voltage operation of level shift circuits, which are widely used in semiconductor integrated circuits.

[0003] A circuit as shown in FIG. 5 is known as a level shift circuit used in semiconductor integrated circuits (see, for example, Patent Document 1). The level shift circuit 100 shown in FIG. 5 includes a first output section 101, a second output section 102, and an output buffer section 103. The first output section 101 includes transistors M1 and M2 connected in series between a positive power supply voltage VDD and a negative power supply voltage VSS. An input signal VIN is supplied to the gate of the transistor M1. The second output section 102 includes transistors M3 and M4 connected in series between the positive power supply voltage VDD and the negative power supply voltage VSS. An inverted signal obtained by inverting the input signal is supplied to the gate of the transistor M3.

[0004] The gate of the transistor M4 is connected to the connection node A, and the gate of the transistor M2 is connected to the connection node B. The connection node B is input to the output buffer unit 103.

[0005] In addition, a diode-connected transistor M11 is connected between the transistor M1 and the transistor M2. In addition, a diode-connected transistor M12 is connected between the transistor M3 and the transistor M4. This allows the potentials of the connection nodes A and B to drop more quickly, thereby increasing the response speed. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 4-284021 Summary of the Invention [Problem to be solved by the invention]

[0007] As described above, providing transistors M11 and M12 increases the response speed, but it also reduces the potential of connection node B in the High state. This causes a problem in that when the power supply voltage drops, it becomes difficult to stably drive output buffer unit 103 at the subsequent stage, narrowing the operating voltage range.

[0008] The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a level shift circuit that has an improved operating voltage range and can operate stably even when the power supply voltage drops. [Means for solving the problem]

[0009] In order to achieve the above-mentioned object, the level shift circuit according to the present invention has the following features [1] to [5]. [1] a first output section including a first transistor and a second transistor connected in series between a first power supply terminal to which a first power supply voltage is supplied and a second power supply terminal to which a second power supply voltage is supplied, and a first voltage clamp element connected between the first transistor and the second transistor, wherein an input signal is input to a gate or a base of the first transistor; a second output section including a third transistor and a fourth transistor connected in series between the first power supply terminal and the second power supply terminal, and a second voltage clamp element connected in series between the third transistor and the fourth transistor, wherein an inverted signal of an input signal is input to a gate or a base of the third transistor; a third output section including a fifth transistor and a sixth transistor connected in series between the first power supply terminal and the second power supply terminal, wherein either the input signal or the inverted signal is input to a gate or a base of the fifth transistor; a gate or a base of the fourth transistor is connected to a first connection node between the first transistor and the first voltage clamp element; a second connection node between the third transistor and the second voltage clamp element is connected to a gate or a base of the second transistor; When the inverted signal is input to the gate or base of the fifth transistor, the first connection node is connected to the gate or base of the sixth transistor, and when the input signal is input to the gate or base of the fifth transistor, the second connection node is connected to the gate or base of the fifth transistor. R, An output buffer unit is provided, The output buffer unit an inverter circuit having a third connection node between the fifth transistor and the sixth transistor connected to an input thereof; a seventh transistor connected between one of the first power supply terminal and the second power supply terminal that is closer to the sixth transistor and an output of the inverter circuit; When the inverted signal is input to the gate or base of the fifth transistor, the second connection node is connected to the gate or base of the seventh transistor, and when the input signal is input to the gate or base of the fifth transistor, the first connection node is connected to the gate or base of the fifth transistor. It is a level shift circuit. [2] a first output section including a first transistor and a second transistor connected in series between a first power supply terminal to which a first power supply voltage is supplied and a second power supply terminal to which a second power supply voltage is supplied, and a first voltage clamp element connected between the first transistor and the second transistor, wherein an input signal is input to a gate or a base of the first transistor; a second output section including a third transistor and a fourth transistor connected in series between the first power supply terminal and the second power supply terminal, and a second voltage clamp element connected in series between the third transistor and the fourth transistor, wherein an inverted signal of an input signal is input to a gate or a base of the third transistor; a third output section including a fifth transistor and a sixth transistor connected in series between the first power supply terminal and the second power supply terminal, wherein either the input signal or the inverted signal is input to a gate or a base of the fifth transistor; a gate or a base of the fourth transistor is connected to a first connection node between the first transistor and the first voltage clamp element; a second connection node between the third transistor and the second voltage clamp element is connected to a gate or a base of the second transistor; When the inverted signal is input to the gate or base of the fifth transistor, the first connection node is connected to the gate or base of the sixth transistor, and when the input signal is input to the gate or base of the fifth transistor, the second connection node is connected to the gate or base of the fifth transistor; An output buffer unit is provided, The output buffer unit a NAND circuit having one of two inputs connected to a third connection node between the fifth transistor and the sixth transistor; the other of the two inputs of the NAND circuit is connected to the second connection node when the inverted signal is input to the gate or base of the fifth transistor, and is connected to the first connection node when the input signal is input to the gate or base of the fifth transistor; It is a level shift circuit. [3] [ 1 ] or [ 2 In the level shift circuit according to the first voltage clamp element and the second voltage clamp element are constituted by diode-connected transistors; It is a level shift circuit. [4] [1]~[ 3 In the level shift circuit according to any one of the above items, At least one of the transistors is a field effect transistor. It is a level shift circuit. [5] [1]~[ 4] In the level shift circuit according to any one of the above items, At least one of the transistors is a bipolar transistor. It is a level shift circuit. [Effects of the Invention]

[0010] According to the present invention, it is possible to provide a level shift circuit with an improved operating voltage range.

[0011] The present invention has been briefly described above. The details of the present invention will become clearer by reading the following detailed description of the invention (hereinafter referred to as "embodiments") with reference to the accompanying drawings. [Brief explanation of the drawings]

[0012] [Figure 1]FIG. 1 is a circuit diagram showing a level shift circuit according to the first embodiment. [Figure 2] FIG. 2 is a circuit diagram showing a level shift circuit according to the second embodiment. [Figure 3] FIG. 3 is a circuit diagram showing a level shift circuit according to the third embodiment. [Figure 4] FIG. 4 is a circuit diagram showing a level shift circuit according to a modified example of the first embodiment. [Figure 5] FIG. 5 is a circuit diagram showing an example of a conventional level shift circuit. DETAILED DESCRIPTION OF THE INVENTION

[0013] Specific embodiments of the present invention will be described below with reference to the accompanying drawings.

[0014] (First embodiment) First, a level shift circuit 1 of the first embodiment will be described with reference to Fig. 1. As shown in the figure, the level shift circuit 1 is a circuit that outputs an output signal VOUT from an output terminal T3, which is obtained by level-shifting an input signal VIN input to an input terminal T1. Specifically, the level shift circuit 1 level-shifts an input signal VIN that is a negative power supply voltage VSS (low state) or a negative power supply voltage VSS plus a threshold voltage of a transistor M1 or higher (high state) to an output signal VOUT that is a negative power supply voltage VSS (low state) or a positive power supply voltage VDD (high state).

[0015] The level shift circuit 1 includes a level shift section 2 and an output buffer section 3. The level shift section 2 includes an output section 21 (first output section), an output section 22 (second output section), an output section 23 (third output section), and an inverter circuit 24. The output section 21 includes a transistor M1 (first transistor) and a transistor M2 (second transistor) connected in series between a positive power supply terminal T21 (first power supply terminal) to which a positive power supply voltage VDD (first power supply voltage) is supplied and a negative power supply terminal T22 (second power supply terminal) to which a negative power supply voltage VSS (second power supply voltage) is supplied, and a transistor M11 (first voltage clamp element) connected between the transistors M1 and M2. The transistor M1 is configured as an N-channel field effect transistor. The transistors M2 and M11 are configured as P-channel field effect transistors.

[0016] The transistor M1 has a gate to which an input signal VIN is input and a source connected to the negative power supply terminal T22. The transistor M2 has a source connected to the positive power supply terminal T21 and a drain connected to the source of a transistor M11 (described later). The transistor M11 is diode-connected with its gate and drain connected, and its drain connected to the drain of the transistor M1.

[0017] The output section 22 has a transistor M3 (third transistor) and a transistor M4 (fourth transistor) connected in series between a positive power supply terminal T21 and a negative power supply terminal T22, and a transistor M12 (second voltage clamp element) connected between the transistors M3 and M4. The transistor M3 is an N-channel field effect transistor. The transistors M4 and M12 are P-channel field effect transistors.

[0018] The gate of the transistor M3 is connected to the output of an inverter circuit 24 (described later), and an inverted signal obtained by inverting the input signal VIN is input to the gate. The source of the transistor M3 is connected to the negative power supply terminal T22. The source of the transistor M4 is connected to the positive power supply terminal T21, and the drain is connected to the source of the transistor M12 (described later). The transistor M12 is diode-connected, with its gate and drain connected, and its drain is connected to the drain of the transistor M3.

[0019] The gate of the transistor M4 is connected to a connection node A (first connection node) between the transistor M1 and the transistor M11, and the gate of the transistor M2 is connected to a connection node B (second connection node) between the transistor M3 and the transistor M12.

[0020] The output section 23 has a transistor M5 (fifth transistor) and a transistor M6 (sixth transistor) connected in series between a positive power supply terminal T21 and a negative power supply terminal T22. The source of the transistor M5 is connected to the negative power supply terminal T22, and the drain is connected to the drain of the transistor M6. The source of the transistor M6 is connected to the positive power supply terminal T21. The gate of the transistor M5 is connected to the output of an inverter circuit 24 (described later), and an inverted signal obtained by inverting an input signal VIN is input to the gate. The gate of the transistor M6 is connected to a connection node A.

[0021] The inverter circuit 24 receives the input signal VIN and outputs an inverted signal obtained by inverting the input signal VIN.

[0022] The output buffer unit 3 has inverter circuits 31 and 32. The input of the inverter circuit 31 is connected to a connection node C (third connection node) between the transistors M6 and M5. The input of the inverter circuit 32 is connected to the output of the inverter circuit 31, and the output is connected to the output terminal T3.

[0023] Next, we will explain the operation of the above-mentioned level shift circuit 1. First, we will explain the operation when the input signal VIN inverts from a high state to a low state. When the input signal VIN is in a high state, transistors M1, M4, and M6 are on, and transistors M2, M3, and M5 are off. Connection nodes B and C are in a high state, and connection node A is in a low state. At this time, a voltage drop equivalent to the gate-source voltage occurs in transistor M12, and the potential of connection node B is clamped to a value lower by the gate-source voltage of transistor M12. In other words, transistor M12 prevents connection node B from rising close to the positive power supply voltage VDD.

[0024] Next, when the input signal VIN inverts from a high state to a low state, transistor M1 turns off and transistors M3 and M5 turn on. When transistor M3 turns on, the potential at connection node B drops. When the voltage at connection node B drops enough that the gate-source voltage of transistor M2 exceeds the threshold voltage, transistor M2 turns on. When transistor M2 turns on, connection node A goes high. When connection node A goes high, transistors M4 and M6 turn off, and connection node C goes low.

[0025] Since the connection node C, which is the input of the output buffer unit 3, is in a low state, the output signal VOUT of the output terminal T3 is in a low state.

[0026] As described above, transistor M2 turns on when the connection node B drops and the voltage between the gate and source exceeds the threshold voltage. In this embodiment, due to the action of diode-connected transistor M12, connection node B starts to drop from a value lower than near the positive power supply voltage VDD. This makes it possible to accelerate the timing at which transistor M2 switches from off to on compared to when transistor M12 is not present, i.e., when the node B starts to drop near the positive power supply voltage VDD. This makes it possible to speed up the response speed from when the input signal VIN changes from high to low to when the output signal VOUT changes from high to low.

[0027] Next, we will explain the operation when the input signal VIN inverts from low to high. When the input signal VIN is low, transistors M1, M4, and M6 are off, and transistors M2, M3, and M5 are on. Connection nodes B and C are low, and connection node A is high. At this time, a voltage drop equal to the gate-source voltage occurs in transistor M11, and the potential at connection node A is clamped to a value lower by the gate-source voltage of transistor M11. In other words, transistor M11 prevents connection node A from rising close to the positive power supply voltage VDD.

[0028] Next, when the input signal VIN switches from low to high, transistor M1 turns on and transistors M3 and M5 turn off. When transistor M1 turns on, the potential at connection node A drops. When the voltage at connection node A drops enough that the gate-source voltage of transistors M4 and M6 exceeds the threshold voltage, transistors M4 and M6 turn on. When transistor M4 turns on, connection node B goes high. When connection node B goes high, transistor M2 turns off, so connection node A goes low. Furthermore, when transistor M6 turns on, connection node C goes high.

[0029] Since the connection node C, which is the input of the output buffer unit 3, is in a High state, the output signal VOUT of the output terminal T3 is in a High state.

[0030] As described above, transistors M4 and M6 turn on when the voltage at connection node A drops to a level where the voltage between the gate and source exceeds the threshold voltage. In this embodiment, due to the action of diode-connected transistor M11, connection node A starts to drop from a value lower than near the positive power supply voltage VDD. This allows the timing at which transistors M4 and M6 switch from the off state to the on state to be faster than when transistor M11 is not present, i.e., when the voltage at connection node A starts to drop from near the positive power supply voltage VDD. This allows for a faster response time from when the input signal inverts from a low state to a high state until the output signal VOUT inverts from a low state to a high state.

[0031] Furthermore, in this embodiment, the connection node C between the transistors M6 and M5 is input to the output buffer unit 3. As a result, the potential of the connection node C in the High state becomes close to the positive power supply voltage VDD. Therefore, even if the positive power supply voltage VDD drops, a stable voltage can be supplied to the input of the output buffer unit 3, and the level shift circuit 1 of this embodiment can achieve stable operation even if the positive power supply voltage VDD drops.

[0032] Therefore, the level shift circuit 1 in the first embodiment can achieve stable operation and improve the operating voltage range without causing a decrease in response speed or malfunction even when the positive power supply voltage VDD drops.

[0033] (Second embodiment) Next, a level shift circuit 1B according to a second embodiment will be described with reference to Fig. 2. In Fig. 2, the same components as those in the circuit shown in Fig. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0034] As shown in the figure, the level shift circuit 1B includes a level shift unit 2 and an output buffer unit 3B. The level shift unit 2 has already been described in the first embodiment, so a detailed description thereof will be omitted here.

[0035] The output buffer unit 3 includes inverter circuits 31 and 32 and a transistor M7. The inverter circuits 31 and 32 have already been described in the first embodiment, so detailed description thereof will be omitted here. The transistor M7 is configured as a P-channel field effect transistor. The transistor M7 has a gate connected to the connection node B, a source connected to the positive power supply terminal T21, and a drain connected to the output of the inverter circuit 31 and the input of the inverter circuit 32.

[0036] The operation of the above-described level shift circuit 1B will be described below. First, the operation when the input signal VIN inverts from a high state to a low state will be described. When the input signal VIN inverts from a high state to a low state, transistor M1 turns off and transistors M3 and M5 turn on. When transistor M3 turns on, the potential at connection node B drops. When the potential at connection node B drops to the point where the gate-source voltages of transistors M2 and M7 exceed the threshold voltage, transistors M2 and M7 turn on. When transistor M7 turns on, the input of inverter circuit 32 goes high, and a low-state output signal VOUT is output from output terminal T3.

[0037] Furthermore, the operation after transistor M2 turns on is the same as in the first embodiment described above, and ultimately, connection node A turns to a high state, transistors M4 and M6 turn to an off state, and connection node C turns to a low state.

[0038] According to the above-described embodiment, when the input signal VIN is inverted from a high state to a low state, the response speed of the connection node B in switching from a high state to a low state is faster than that of the connection node C. Therefore, by providing the transistor M7, the timing at which the input of the inverter circuit 32 changes from a low state to a high state can be made faster than in the first embodiment, and the response speed can be further increased.

[0039] When the input signal VIN is inverted from a low state to a high state, the connection nodes B and C are switched from a low state to a high state at the same time.

[0040] Therefore, the level shift circuit 1B in the second embodiment also achieves stable operation and improves the operating voltage range without causing a decrease in response speed or malfunction even when the positive power supply voltage VDD drops.

[0041] (Third embodiment) Next, a level shift circuit 1C according to a third embodiment will be described with reference to Fig. 3. In Fig. 3, the same components as those in the circuit shown in Fig. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0042] As shown in the figure, the level shift circuit 1C includes a level shift unit 2 and an output buffer unit 3C. The level shift unit 2 has already been described in the first embodiment, so a detailed description thereof will be omitted here.

[0043] The difference between the first and third embodiments is the configuration of the output buffer unit 3C. In the third embodiment, the output buffer unit 3C has a NAND circuit 33 and an inverter circuit 32. The NAND circuit 33 has two inputs connected to connection nodes B and C, and an output connected to the input of the inverter circuit 32. As in the first embodiment, the output of the inverter circuit 32 is connected to the output terminal T3.

[0044] The operation of the above-described level shift circuit 1C will now be described. As in the first embodiment, when the input signal VIN switches from a high state to a low state, the transistor M1 is turned off and the transistors M3 and M5 are turned on. When the transistor M3 is turned on, the potential of the connection node B drops. As explained in the first and second embodiments, the connection node B drops, the transistor M2 turns on in response, the connection node A rises, and the transistors M4 and M6 turn off in response, and the connection node C drops at the same time. In other words, the potential of the connection node B drops before the potential of the connection node C, so the response speed of switching from a high state to a low state is faster.

[0045] As a result, the voltage at connection node B falls below the threshold voltage of the NAND circuit 33 (the midpoint between the positive power supply voltage VDD and the negative power supply voltage VSS) before the voltage at connection node C does, and the output of the NAND circuit 33 inverts from low to high. When the output of the NAND circuit 33 switches from low to high, an output signal VOUT in low state is output. After that, even if the voltage at connection node C falls below the threshold voltage of the NAND circuit 33, the NAND circuit 33 maintains its output in high state, and the output signal VOUT in low state is maintained.

[0046] When the input signal VIN is inverted from a low state to a high state, the connection nodes B and C are switched from a low state to a high state at the same time.

[0047] According to the above-described embodiment, when the input signal VIN is inverted from a high state to a low state, the response speed of the connection node B switching from a high state to a low state is faster than that of the connection node C. Therefore, by providing the NAND circuit 33 to which the connection node B is input, the timing at which the input of the inverter circuit 32 changes from a high state to a low state can be made faster than in the first embodiment, thereby further increasing the response speed. Moreover, the through current of the output buffer unit 3C can be made smaller than in the second embodiment.

[0048] Therefore, the level shift circuit 1C in the third embodiment also achieves stable operation and improves the operating voltage range without causing a decrease in response speed or malfunction even when the positive power supply voltage VDD drops.

[0049] (Fourth embodiment) Next, a level shift circuit 1D according to a fourth embodiment will be described with reference to Fig. 4. In Fig. 4, the same components as those in the circuit shown in Fig. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0050] As shown in the figure, the level shift circuit 1D includes a level shift section 2D and an output buffer section 3, similar to the first embodiment.

[0051] The first embodiment differs from the fourth embodiment in that the conductivity types of transistors M1D, M2D, M3D, M4D, M5D, M6D, M11D, and M12D, which correspond to transistors M1, M2, M3, M4, M5, M6, M11, and M12, are reversed. Also, the first embodiment differs from the fourth embodiment in that the relationship between the positive power supply terminal T21 and the negative power supply terminal T22 is reversed.

[0052] Similarly, in the second and third embodiments, the conductivity types of the transistors M1, M2, M3, M4, M5, M6, M7, M11, and M12 may be reversed, and the relationship between the positive power supply terminal T21 and the negative power supply terminal T22 may be reversed.

[0053] The present invention is not limited to the above-described embodiments, and can be appropriately modified, improved, etc. Furthermore, the material, shape, size, number, location, etc. of each component in the above-described embodiments are arbitrary and not limited as long as they can achieve the present invention.

[0054] In the first to fourth embodiments described above, an inverted signal is input to the gate of the transistor M5(D) and the gate of the transistor M6(D) is connected to the connection node A, but this is not limiting. An input signal VIN may be input to the gate of the transistor M5(D) and the gate of the transistor M6(D) may be connected to the connection node B. In this case, if a transistor M7 is provided as in the second embodiment, the gate of the transistor M7 is connected to the connection node A. In this case, if a NAND circuit 33 is provided as in the third embodiment, the connection node A is connected to the input of the NAND circuit instead of the connection node B.

[0055] In the first to fourth embodiments described above, the transistors M1(D) to M7, M11(D), and M12(D) are configured as field-effect transistors, but this is not limitative. At least one of the transistors M1(D) to M7, M11(D), and M12(D) may be replaced with a bipolar transistor. In this case, the gates of the transistors M1(D) to M7(D), M11(D), and M12(D) can be interpreted as bases, sources as emitters, and drains as collectors.

[0056] In the first to fourth embodiments described above, diode-connected transistors M11, M12, M11D, and M12D are used as the first and second voltage clamp elements, but the present invention is not limited to this. The first and second voltage clamp elements may be any elements that generate a voltage drop, and may be configured as diodes. [Explanation of symbols]

[0057] 1, 1B~1D level shift circuit 3, 3B, 3C Output buffer section 21, 21D Output section (first output section) 22, 22D Output section (second output section) 23, 23D Output section (third output section) 24 Inverter circuit 33 NAND circuit A Connection Node (First Connection Node) B Connection node (second connection node) C. Connection node (third connection node) M1, M1D transistors (first transistors) M2, M2D transistor (second transistor) M3, M3D transistors (third transistors) M4, M4D transistor (fourth transistor) M5, M5D transistor (fifth transistor) M6, M6D transistor (sixth transistor) M7 transistor (seventh transistor) M11, M11D transistors (first voltage clamp element) M12, M12D transistors (second voltage clamp element) T21 Positive power supply terminal (first power supply terminal) T22 Negative power supply terminal (second power supply terminal) VDD Positive power supply voltage (first power supply voltage) VSS Negative power supply voltage (second power supply voltage) VIN Input signal VOUT output signal

Claims

1. a first output section including a first transistor and a second transistor connected in series between a first power supply terminal to which a first power supply voltage is supplied and a second power supply terminal to which a second power supply voltage is supplied, and a first voltage clamp element connected between the first transistor and the second transistor, wherein an input signal is input to a gate or a base of the first transistor; a second output section including a third transistor and a fourth transistor connected in series between the first power supply terminal and the second power supply terminal, and a second voltage clamp element connected in series between the third transistor and the fourth transistor, wherein an inverted signal of an input signal is input to a gate or a base of the third transistor; a third output section including a fifth transistor and a sixth transistor connected in series between the first power supply terminal and the second power supply terminal, wherein either the input signal or the inverted signal is input to a gate or a base of the fifth transistor; a gate or a base of the fourth transistor is connected to a first connection node between the first transistor and the first voltage clamp element; a second connection node between the third transistor and the second voltage clamp element is connected to a gate or a base of the second transistor; the gate or base of the sixth transistor is connected to the first connection node when the inverted signal is input to the gate or base of the fifth transistor, and is connected to the second connection node when the input signal is input to the gate or base of the fifth transistor; An output buffer unit is provided, The output buffer unit an inverter circuit having a third connection node between the fifth transistor and the sixth transistor connected to an input thereof; a seventh transistor connected between one of the first power supply terminal and the second power supply terminal that is closer to the sixth transistor and an output of the inverter circuit; When the inverted signal is input to the gate or base of the fifth transistor, the second connection node is connected to the gate or base of the seventh transistor, and when the input signal is input to the gate or base of the fifth transistor, the first connection node is connected to the gate or base of the fifth transistor. Level shift circuit.

2. A first output section having a first transistor and a second transistor connected in series between a first power supply terminal to which a first power supply voltage is supplied and a second power supply terminal to which a second power supply voltage is supplied, and a first voltage clamp element connected between the first transistor and the second transistor, wherein an input signal is input to the gate or base of the first transistor; a second output section including a third transistor and a fourth transistor connected in series between the first power supply terminal and the second power supply terminal, and a second voltage clamp element connected in series between the third transistor and the fourth transistor, wherein an inverted signal of an input signal is input to a gate or a base of the third transistor; a third output section including a fifth transistor and a sixth transistor connected in series between the first power supply terminal and the second power supply terminal, wherein either the input signal or the inverted signal is input to a gate or a base of the fifth transistor; a gate or a base of the fourth transistor is connected to a first connection node between the first transistor and the first voltage clamp element; a second connection node between the third transistor and the second voltage clamp element is connected to a gate or a base of the second transistor; the gate or base of the sixth transistor is connected to the first connection node when the inverted signal is input to the gate or base of the fifth transistor, and is connected to the second connection node when the input signal is input to the gate or base of the fifth transistor; An output buffer unit is provided, The output buffer unit a NAND circuit having one of two inputs connected to a third connection node between the fifth transistor and the sixth transistor; the other of the two inputs of the NAND circuit is connected to the second connection node when the inverted signal is input to the gate or base of the fifth transistor, and is connected to the first connection node when the input signal is input to the gate or base of the fifth transistor; Level shift circuit.

3. 3. The level shift circuit according to claim 1, the first voltage clamp element and the second voltage clamp element are constituted by diode-connected transistors; Level shift circuit.

4. 4. The level shift circuit according to claim 1, At least one of the transistors is a field effect transistor. Level shift circuit.

5. The level shift circuit according to any one of claims 1 to 4, At least one of the transistors is a bipolar transistor. Level shift circuit.

Images