Semiconductor device having a deeply depleted channel and method of manufacturing the same - Patents.com

Abstract

To provide a semiconductor device with a deeply depleted channel, and a manufacturing method thereof.SOLUTION: A semiconductor device includes a substrate, a gate structure, a source region, a drain region, a doped region and a channel region. The gate structure is disposed in the substrate, and the source region and the drain region being a first conductivity type are respectively disposed at two sides of the gate structure. The doped region being a second conductivity type different from the first conductivity type is disposed below and separated from the gate structure, the source region and the drain region. The channel region is disposed between the doped region and the gate structure and in contact with the doped region, and a dopant concentration of the channel region is less than a dopant concentration of the doped region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates generally to semiconductor devices, and more particularly to semiconductor devices having deeply depleted channels. [Background technology]

[0002] Generally, semiconductor devices with deep depleted channels are devices fabricated on bulk silicon substrates. In operation, such devices can create a depletion region beneath the gate structure at a predetermined distance, which exhibits electrical characteristics similar to those exhibited by the buried oxide of silicon-on-insulator (SOI) substrates. Because bulk silicon substrates are less expensive than SOI substrates, semiconductor devices with deep depleted channels are becoming increasingly popular in certain applications, such as IoT device applications, where low power consumption is required.

[0003] Deeply depleted channel semiconductor devices typically include a planar gate structure and a heavily doped region (also called a screen region or SCR region). The SCR region is disposed below the planar gate structure at a predetermined distance. However, current leakage often occurs between each source / drain region and the SCR region, which adversely affects the electrical performance of the semiconductor device. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-184655 [Patent Document 2] Japanese Patent Application Publication No. 63-114174 [Patent Document 3] Japanese Patent Application Publication No. 1-204472 [Patent Document 4] Japanese Patent Application Publication No. 2-112284 [Patent Document 5] Japanese Patent Application Publication No. 4-68540 [Patent Document 6] Japanese Patent Application Laid-Open No. 2006-253706 [Patent Document 7] Japanese Patent Application Laid-Open No. 2013-206945 [Patent Document 8] Japanese Patent Application Laid-Open No. 2006-190821 [Patent Document 9] Japanese Patent Application Laid-Open No. 2001-250950 [Patent Document 10] Japanese Patent Application Laid-Open No. 2009-194392 [Patent Document 11] Japanese Patent Application Laid-Open No. 2010-177318 [Patent Document 12] Japanese Patent Publication No. 2020-77712 [Patent Document 13] JP 2003-179223 A Summary of the Invention [Problem to be solved by the invention]

[0005] In this regard, there remains a need to provide improved semiconductor devices having deeply depleted channels and methods for fabricating the same. [Means for solving the problem]

[0006] According to some embodiments of the present disclosure, a semiconductor device is provided, the semiconductor device including a substrate, a gate structure, a source region, a drain region, a doped region, and a channel region. The gate structure is disposed in the substrate, and the source region and the drain region are of a first conductivity type disposed on two sides of the gate structure, respectively. Doped regions of a second conductivity type different from the first conductivity type are disposed below the gate structure, the source region, and the drain region and spaced apart from the gate structure, the source region, and the drain region. The channel region is disposed between the doped region and the gate structure and in contact with the doped region, and the dopant concentration of the channel region is lower than the dopant concentration of the doped region.

[0007] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device is provided, including: providing a substrate and forming a doped region on the substrate; then forming a channel layer on the doped region and forming a trench in the channel layer; then forming a gate structure in the trench, where the gate is disposed on the doped region and spaced apart from the doped region; then forming source and drain regions on two sides of the gate structure, where the source and drain regions are disposed on the doped region and spaced apart from the doped region; and the dopant concentration of the channel layer is lower than the dopant concentration of the doped region.

[0008] These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

[0009] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. [Figure 2] FIG. 2 is a schematic enlarged cross-sectional view illustrating the concentration profile in region A of FIG. 1 according to some embodiments of the present disclosure. [Figure 3] 1A-1C are schematic cross-sectional views illustrating semiconductor devices according to some alternative embodiments of the present disclosure. [Figure 4] 1A-1C are schematic cross-sectional views illustrating semiconductor devices according to some alternative embodiments of the present disclosure. [Figure 5] 1 is a schematic top view illustrating a semiconductor device according to some embodiments of the present disclosure. [Figure 6]1A-1D are schematic cross-sectional views illustrating process steps for manufacturing a semiconductor device according to some embodiments of the present disclosure. [Figure 7] 1A-1D are schematic cross-sectional views illustrating process steps for manufacturing a semiconductor device according to some embodiments of the present disclosure. [Figure 8] 1A-1D are schematic cross-sectional views illustrating process steps for manufacturing a semiconductor device according to some embodiments of the present disclosure. [Figure 9] 1A-1D are schematic cross-sectional views illustrating process steps for manufacturing a semiconductor device according to some embodiments of the present disclosure. [Figure 10] 10A-10C are schematic cross-sectional views illustrating process steps for manufacturing a semiconductor device according to some alternative embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0011] The present technology is described with reference to the accompanying drawings, in which like reference numerals are used throughout the drawings to denote similar or equivalent elements. The drawings are not to scale and are provided solely for illustrating the present technology. Several aspects of the present technology are described below with reference to exemplary applications for purposes of explanation. It should be understood that numerous specific details, relationships, and methods are described to provide a thorough understanding of the present technology. However, one skilled in the art will readily recognize that the present technology can be practiced without one or more of the specific details, or in other ways. In other instances, well-known structures or operations are not shown in detail to avoid obscuring the present technology. The present technology is not limited by the illustrated order of acts or events, as some acts may occur in different orders and / or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology in accordance with the present technology.

[0012] 1 is a schematic cross-sectional view illustrating a semiconductor device 100-1 according to some embodiments of the present disclosure. Referring to FIG. 1, the semiconductor device 100-1 may be a transistor having a deeply depleted channel, and may include at least a substrate 102, a doped region 104, a channel region 110, a gate structure 116, a source region 122, and a drain region 124.

[0013] The substrate 102 may be a semiconductor substrate of any required conductivity type, such as n-type or p-type. In the present disclosure, the substrate 102 may be any type of substrate used to form semiconductor devices thereon, including single crystal substrates, semiconductor-on-insulator (SOI) substrates, and epitaxial-on-semiconductor (EPI) substrates, to name a few. Furthermore, although various embodiments will be described primarily with respect to materials and processes compatible with silicon-based semiconductor materials (e.g., silicon and alloys of silicon with germanium and / or carbon), the present technology is not limited in this regard. Rather, various embodiments may be implemented using any type of semiconductor material.

[0014] The doped region 104 may be disposed on the substrate 102, and the doped region 104 may be disposed below and spaced apart from the gate structure 116. The doped region 104 may have a concentration profile such that the dopant concentration gradually increases from the bottom of the doped region 104 to a predetermined region adjacent the top of the doped region 104, and then gradually decreases from the predetermined region to the top of the doped region 104. In the doped region 104 having a concentration profile, the peak concentration of the concentration profile may be greater than 5×10 18 atoms / cm 3 is equal to 5 x 10 18 atoms / cm 3 Higher 1×10 20 atoms / cm 3 Lower, or 1×10 20 atoms / cm 3 is equal to, for example, 5 x 1018 From 1×10 20 atoms / cm 3 The peak concentration of the doped region 104 may extend laterally to the horizontal region below the source region 122, the drain region 124, and the gate structure 116. In an n-type semiconductor device, such as a silicon-based NMOS, the doped region 104 may include a p-type dopant, such as boron (B) or indium (I). In contrast, in a p-type semiconductor device, such as a silicon-based PMOS, the doped region 104 may include an n-type dopant, such as arsenic (As), antimony (Sb), or phosphorus (P). Note that if the doped region 104 is formed by performing an implantation process on the substrate 102, the doped region 104 may be considered a doped region disposed on the top of the substrate 102. In contrast, if the doped region 104 is formed by performing an epitaxial growth process on the substrate 102, the doped region 104 may be considered a doped region disposed on the top surface of the substrate 102.

[0015] Channel region 110 is disposed on doped region 104 in such a way that source region 122 and drain region 124 can be spaced apart from doped region 104 by channel region 110. Moreover, a portion of channel region 110 can be disposed between doped region 104 and gate structure 116. Thus, gate structure 116 is also spaced apart from doped region 104 by channel region 110. Channel region 110 can be an undoped or lightly doped region, such as undoped or lightly doped silicon, such that the average dopant concentration of channel region 110 is lower than the average dopant concentration of doped region 104.

[0016] According to some embodiments of the present disclosure, the channel region 110 may have a single layer structure or a double layer structure. In a double layer channel region 110, the channel region 110 may include a first channel layer 106 and a second channel layer 108 in contact with the underlying doped region 104. The first channel layer 106 may be an undoped or lightly doped layer that extends laterally over the doped region 104. A trench 140 may be formed in the first channel layer 106 and extend to the top of the doped region. Furthermore, the second channel layer 108 may be an undoped or lightly doped layer that conforms to the surface of the trench 140. Because the second channel layer 108 is disposed in the trench 140, a portion of the second channel layer 108 can be considered to be embedded in or surrounded by the doped region 104. According to different requirements, the trench 140 can be designed to have a surface that includes a curved surface or a flat bottom and sloped sidewalls. In either case, the second channel layer 108 can be conformal to the surface of the trench 140. According to some embodiments of the present disclosure, the thickness of the first channel layer 106 can be thicker than the thickness of the second channel layer 108. For example, the first channel layer 106 can have a thickness of approximately 100 to 150 nm, and the second channel layer 108 can have a thickness of approximately 10 to 40 nm.

[0017] It should be noted that although FIG. 1 illustrates a curved interface between the first channel layer 106 and the second channel layer 108, the interface may be difficult to detect or observe if both the first channel layer 106 and the second channel layer 108 are made of the same material, such as undoped silicon.

[0018] The gate structure 116 may be a trench gate including a gate dielectric 112 and a gate electrode 114, and the gate structure 116 may be disposed in a gate trench 150 defined by an inner surface of the second channel layer 108. Due to the presence of the second channel layer 108, the gate structure 116 may be spaced apart from the first channel layer 106 and the underlying doped region 104. According to different requirements, the gate electrode 114 may be, but is not limited to, a polysilicon gate or a metal gate.

[0019] The source region 122 and the drain region 124 may be disposed on two sides of the gate structure 116, respectively. Specifically, the conductivity type of each of the source region 122 and the drain region 124 is different from the conductivity type of the doped region 104. For example, if the source region 122 and the drain region 124 are n-type regions (or p-type regions), the doped region 104 is a p-type region (or n-type region).

[0020] Moreover, to further reduce contact resistance, conductive regions made of silicide or other conductive material can be formed on or on the gate electrode 114, the source region 122, and the drain region 124, respectively. For example, silicide regions 132, 134 can be disposed on and electrically coupled to the source region 122 and the drain region 124, respectively. A silicide region 136 can be disposed on the gate structure 116 so as to be disposed on and electrically coupled to the gate electrode 114 of the gate structure 116. The silicide region 136 on the gate structure 116 can be laterally spaced apart (i.e., along the x-direction) from the silicide regions 132, 134 disposed on the source region 122 and the drain region 124, respectively. In this manner, current does not transfer directly between two adjacent silicide regions, thereby preventing potential leakage current in the semiconductor device 100-1.

[0021] Additionally, isolation structures 130, such as shallow trench isolation (STI), may be used to surround the active area of ​​semiconductor device 100-1 to prevent current (eg, leakage) from flowing between adjacent devices.

[0022] During operation of the semiconductor device 100-1, the gate electrode 114 can be positively or negatively biased to allow carriers (e.g., holes or electrons) to transmit between the source region 122 and the drain region 124 along the bottom surface of the gate dielectric 112. A depletion region can be induced by the voltage bias from the gate electrode 114 and generated near the interface of the doped region 104 and the channel region 110. Moreover, because both the source region 122 and the drain region 124 are disposed above and spaced apart from the doped region 104, the source region 122 and the drain region 124 do not directly contact the underlying doped region 104. Therefore, current leakage between the source region 122 / drain region 124 and the underlying doped region 104 can be reduced or effectively avoided. Furthermore, since the carriers traveling under the gate structure 116 mainly flow within the second channel layer 108, the electrical performance of the semiconductor device 100-1 can be well controlled by adjusting the thickness of the second channel layer 108 to a predetermined value.

[0023] FIG. 2 is a schematic enlarged cross-sectional view illustrating a concentration profile in region A of FIG. 1 according to some embodiments of the present disclosure. Referring to FIG. 2, the doped region 104 may have a gradually changing dopant concentration from the bottom of the doped region 104 to a predetermined depth of the doped region 104. Moreover, the dopant concentration of the doped region 104 may remain substantially the same along the lateral direction at each depth level. As illustrated in (a) and (b) on the right-hand side of FIG. 2, the dopant concentration profile of the doped region 104 may have at least one peak. The peak may have a maximum concentration at a predetermined depth (as illustrated in (a)) or may have a maximum concentration distributed over a range along the depth direction (as illustrated in (b)). According to some embodiments of the present disclosure, to control the dopant concentration profile of the doped region 104, dopants may be implanted into the doped region 104 by performing one or more ion implantation processes with different implantation energies and doses. Preferably, the dopant concentration of the doped region 104 may be substantially within a range of ±30% of the average along the depth direction, including the maximum concentration, as a flat concentration profile. More preferably, the dopant concentration of the doped region 104 may be within a range of ±20% of the average along the depth direction, including the maximum concentration, as a flat concentration profile. Even more preferably, the dopant concentration of the doped region 104 may be within a range of ±10% of the average along the depth direction, including the maximum concentration, as a flat concentration profile. A substantially flat concentration profile can be obtained by performing ion implantation several times separately according to a selected accuracy of such a range under suitable conditions. Note that the dopant concentration of the doped region 104 at a depth lower than the lowest point of the second channel layer 108 may have the maximum dopant concentration. In other words, the bottom surface of the second channel layer 108 under the gate structure 116 may be shallower than the depth of the maximum dopant concentration.

[0024] FIG. 3 is a schematic cross-sectional view illustrating a semiconductor device according to some alternative embodiments of the present disclosure. Referring to FIG. 3, the semiconductor device 100-2 illustrated in FIG. 3 is similar to the semiconductor device 100-1 illustrated in FIG. 1, with the main difference being that the channel region 110 has a single-layer structure rather than a double-layer structure. Therefore, a trench 150 formed in the channel region 110 cannot be covered with a thin layer of a semiconductor, such as undoped silicon. Moreover, the trench 150 can be considered a gate trench 150 used to accommodate a gate structure 116. According to the semiconductor device 100-2 illustrated in FIG. 3, the doped region 104 is also spaced apart from the gate structure 116, the source region 122, and the drain region 124. Because both the source region 122 and the drain region 124 are disposed above and spaced apart from the doped region 104, the source region 122 and the drain region 124 do not directly contact the underlying doped region 104. Therefore, current leakage between the source region 122 / drain region 124 and the underlying doped region 104 can be reduced or effectively avoided.

[0025] 4 is a schematic cross-sectional view illustrating a semiconductor device according to some alternative embodiments of the present disclosure. Referring to FIG. 4, the semiconductor device 100-3 illustrated in FIG. 4 is similar to the semiconductor device 100-1 illustrated in FIG. 1, with the main difference being that the top surface of the gate electrode is adjacent to the source region 122 and the drain region 123. 124 The gate electrode 114 has a width of, for example, 20 to 200 nm and protrudes from the gate trench 150 so as to be higher than the upper surface of the gate trench 150. In addition, spacers 118 having a width of, for example, 10 to 50 nm may be disposed on two sides of the gate structure 116. . The port structure 116 is Second channel layer 108The silicide region 136 disposed on the gate structure 116 can be laterally spaced apart from the source region 122 and the drain region 124 by the spacers 118. The silicide region 136 disposed on the gate structure 116 can be laterally (i.e., along the x-direction) and vertically (i.e., along the z-direction) spaced apart from the silicide regions 132, 134 disposed on the source region 122 and the drain region 124, respectively. In this manner, current does not directly transfer between two adjacent silicide regions, thereby further preventing possible leakage current in the semiconductor device 100-3 than in the semiconductor device 100-1 illustrated in FIG. 1. Furthermore, due to the presence of the spacers 118 disposed on two sidewalls of the gate electrode 114, the silicide regions 132, 134 can each be disposed further away from the sidewalls of the gate electrode 114, compared to the semiconductor device 100-1 illustrated in FIG. 1, which does not have spacers.

[0026] FIG. 5 is a schematic top view illustrating a semiconductor device 100-4 according to some embodiments of the present disclosure. Referring to FIG. 5, the cross-sectional views illustrated in FIGS. 1, 3, and 4 can be considered to be taken along line A-A′ in FIG. 5. An active region (not shown) including at least a source region 122 and a drain region 124 can be surrounded by an isolation structure 130. The source region 122 and the drain region 124 can extend along a first direction, such as the x-direction, and the gate structure 116 can extend along a second direction, such as the y-direction. It should be noted that the direction in which the source region 122 and the drain region 124 extend is not limited to being perpendicular to the direction in which the gate structure 116 extends.

[0027] To enable those skilled in the art to practice the present disclosure, methods for manufacturing the semiconductor devices of the present disclosure are further described below.

[0028] 6 through 9 are schematic cross-sectional views illustrating process steps of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. Referring to FIG. 6, a substrate 102, such as a semiconductor substrate, is provided. Doped wells (not shown) of a certain conductivity type can be formed in the substrate 102. According to some embodiments of the present disclosure, the doped wells can be formed by performing at least one ion implantation process. For example, for a p-type doped well, a p-type dopant, such as boron, is implanted at a concentration of 1×10 12 ~1×10 14 cm -2 The substrate 102 may be implanted with, but not limited to, an n-type dopant, such as phosphorus, at a dose of 1×10 12 ~1×10 14 cm -2 The doped regions 104 can be implanted into the substrate 102 at a dose of, but not limited to, 100 keV and an energy of 200-400 keV. The doped regions 104 can be formed on the substrate 102 by an ion implantation process or an epitaxial growth process. The conductivity type of the dopant in the doped regions 104 is the same as the conductivity type of the dopant in the doped well. According to some embodiments of the present disclosure, the doped regions 104 can be p-type regions containing p-type dopants, such as boron or indium. According to some alternative embodiments of the present disclosure, the doped regions 104 can be n-type regions containing n-type dopants, such as arsenic (As), antimony (Sb), or phosphorus (P). To control the dopant concentration profile, various types of dopants can be implanted at different energies and doses during one or more ion implantation processes. Additionally, the doped regions 104 can also contain other dopants, such as carbon, germanium, or boron fluoride, which can be used to adjust the concentration profile of the p-type or n-type dopants. According to some embodiments of the present disclosure, when the doped region 104 is p-type, the p-type doped region 104 is formed by doping 1×10 germanium into a p-type doped well. 13 ~1×10 15 cm-2 The carbon is implanted into the p-doped well at a dose of 1×10 13 ~1×10 15 cm -2 Implant 1×10 boron into a p-doped well at a dose of 1×10 12 ~1×10 14 cm -2 Implant 1×10 boron fluoride into the p-doped well at an energy of 10-30 keV with a dose of 12 ~1×10 14 cm -2 The doped region 104 may be formed by sequentially performing several ion implantation processes, such as implanting 1×10 antimony into an n-type doped well at a dose of 1×10 ions at an energy of 200-400 keV. According to some alternative embodiments of the present disclosure, if the doped region 104 is n-type, the n-type doped region 104 may be formed by implanting 1×10 antimony into an n-type doped well at a dose of 1×10 ions at an energy of 200-400 keV. 12 ~1×10 14 cm -2 Implant 1×10 antimony into the n-doped well at a dose of 1×10 12 ~1×10 14 cm -2 The doped region 104 may also be formed by performing several ion implantation processes in sequence, such as implanting at a dose of 100 kJ / cm2 at an energy of 10-30 keV. After the process for forming the doped region 104, the dopants in the doped region 104 may be activated by performing a heat treatment at a suitable temperature, such as in the range of 500-700°C.

[0029] According to some embodiments of the present disclosure, the conditions and / or number of ion implantations for forming the doped region 104 can be adjusted to obtain a desired concentration profile, such as the concentration profile shown in FIG. 2. To obtain the concentration profile shown in FIG. 2(b), a dopant having a certain conductivity can be implanted into the substrate 102 by performing several ion implantation processes rather than a single ion implantation process. For example, in the p-type doped region 104, a p-type dopant such as boron fluoride (BF) can be implanted at 1×10 ions at an energy of 5-15 keV. 12 ~1×10 14 cm -2 The first implantation process has a dose of 1×10 at an energy of 7–17 keV. 12 ~1×10 14 cm -2 a second implantation process with a dose of 1×10 at an energy of 10-20 keV; 12 ~1×10 14 cm -2 and a third implantation process with a dose of 1 × 10 at an energy of 15–25 keV. 12 ~1×10 14 cm -2 Similarly, in the n-type doped region 104, an n-type dopant, such as antimony (Sb), can be implanted into the substrate 102 by sequentially performing four ion implantation processes, such as, but not limited to, a fourth implantation process having a dose of 1×10 at an energy of 10-30 keV. 12 ~1×10 14 cm -2 The first implantation process has a dose of 1×10 at an energy of 15-35 keV. 12 ~1×10 14 cm -2 a second implantation process with a dose of 1 × 10 at an energy of 20–40 keV; 12 ~1×10 14 cm -2 and a third implantation process with a dose of 1 × 10 at an energy of 25–45 keV. 12 ~1×10 14 cm -2The dopant concentration may be implanted into the substrate 102 by, but not limited to, performing four ion implantation processes in sequence, such as a fourth implantation process having a dose of 100 . To obtain a precise range (i.e., smaller variation) of dopant concentration along the depth direction as a flat concentration profile, several alternate ion implantations may be performed to obtain the desired precise concentration range, but not limited to. Also, fewer ion implantations may be employed if it is sufficient to obtain a precise range of dopant concentration along the depth direction as a flat concentration profile.

[0030] 6, a first channel layer 106 having a thickness of 300-500 nm can be formed on the doped region 104 by an epitaxial growth process. The first channel layer 106 can be an undoped layer or a lightly doped layer, and the dopant concentration of the first channel layer 106 is at least 1 / 10 to 1 / 10 times lower than the dopant concentration of the doped region 104. 3 About twice as low.

[0031] 7 , the isolation structure 130 can be formed in a predetermined area, and then a trench 140 having a width (along the x-direction) of 50 to 150 nm and a depth (along the z-direction) of 250 to 550 nm can be formed in the first channel layer 106 downward to the top of the doped region 104. In this manner, a portion of the doped region 104 can be exposed from the bottom surface of the trench 140. It should be noted that, according to some alternative embodiments of the present disclosure, the trench 140 may not reach the doped region 104 such that none of the doped region 104 can be exposed from the bottom surface of the trench 140. Furthermore, even if none of the doped region 104 is exposed from the bottom surface of the trench 140 after the main process for forming the trench 140, additional post-processing, such as a wet etching process, can be performed on the bottom surface of the trench 140 until the doped region 104 is exposed from the bottom surface of the trench 140. Moreover, to protect the top surface of the first channel layer 106 from being damaged during the process of forming the isolation structure 130 and the trench 140, the top surface of the first channel layer 106 can be covered with a thin protective layer such as SiO2.

[0032] 8, a second channel layer 108 having a thickness of 10 to 40 nm may be formed on the surface of the trench 140 to define the gate trench 150. However, if the first channel layer 106 remains on the bottom surface of the trench 140, the second channel layer 108 may be omitted and therefore not formed in the trench 140 according to some alternative embodiments of the present disclosure, such as the structure illustrated in FIG. 3. The bottom of the second channel layer 108 may be in direct contact with the doped region 104. Moreover, the second channel layer 108 may be an undoped layer or a lightly doped layer, and the dopant concentration of the second channel layer 108 may be at least 1 / 10 to 1 / 10 times lower than the dopant concentration of the doped region 104. 3The gate dielectric layer 142 can then be conformally formed on the exposed surfaces of the first channel layer 106 and the second channel layer 108. According to some embodiments of the present disclosure, the gate dielectric layer 142 having a thickness of 1 to 3 nm can be formed by thermal oxidation at a processing temperature of 800 to 1000°C. According to some alternative embodiments of the present disclosure, the gate dielectric layer 142 made of silicon oxynitride, hafnium oxide, or the like can be formed by a deposition process. Thereafter, a gate electrode layer 144, which can be polysilicon or metal, is formed on the gate dielectric layer 142 and fills the gate trench 150. To completely fill the trench 150, the thickness of the gate electrode layer 144 can be in the range of 500 to 700 nm.

[0033] 9, the gate electrode layer 144 may be planarized to stop on the gate dielectric layer 142 to form the gate electrode 114 in the gate trench 150. The source region 122 and the drain region 124 may then be formed on the sides of the gate electrode 114 by implanting dopants into the first channel layer 106 and the second channel layer 108. According to some embodiments of the present disclosure, when the source region 122 and the drain region 124 are both n-type, the source region 122 and the drain region 124 may have a dopant concentration of 1×10 15 ~1×10 17 cm -2 Alternatively, the source region 122 and the drain region 124 may be formed by performing at least one ion implantation process, such as implanting phosphorus at a dose of 1×10 and an energy of 5-15 keV. According to some alternative embodiments of the present disclosure, when the source region 122 and the drain region 124 are both p-type, the source region 122 and the drain region 124 may be formed by implanting phosphorus at a dose of 1×10 and an energy of 5-15 keV. 12 ~1×10 14 cm -2 The implantation of boron at an energy of 5 to 15 keV with a dose of 1×10 14 ~1×10 16 cm -2 Ge is implanted at an energy of 10-30 keV with a dose of 1×10 14 ~1×1016 cm -2 The source and drain regions 122 and 124 may also be formed by sequentially performing several ion implantation processes, such as implanting boron at a dose of 1000 kJ / cm2 and an energy of 3-10 keV. After the process for forming the source and drain regions 122 and 124, the dopants in the source and drain regions 122 and 124 may be activated by performing a heat treatment, such as a spike anneal, at a suitable temperature, such as in the range of 1000-1100°C. A silicidation process may then be performed to form metal silicides in the source and drain regions 122, 124, and gate electrode 114, respectively. Other processes may then be performed to obtain the structure shown in FIG. 1.

[0034] FIG. 10 is a schematic cross-sectional view illustrating a process of a method for fabricating a semiconductor device according to some alternative embodiments of the present disclosure. Referring to FIG. 10, the process illustrated in FIG. 10 is an alternative process following FIG. 8. According to some alternative embodiments of the present disclosure, following the step of FIG. 8, the gate electrode layer 144 may be patterned by a photolithography process to form the gate electrode 114 illustrated in FIG. 10 to fabricate the gate structure 116 as illustrated in FIG. 4. Two opposing protruding sidewalls 118 (not shown) of the gate electrode 114 may be further formed with a width (along the x-direction) of 50 to 150 nm after forming the gate electrode 114, as illustrated in FIG. 4. The source region 122 and the drain region 124 (not shown) may be further formed after forming the two opposing protruding sidewalls 118, as illustrated in FIG. 4. The silicide regions 132, 134, and 136 (not shown) may be further formed after forming the source region 122 and the drain region 124, as illustrated in FIG. 4. In this manner, both the patterned gate electrode 114 and the two opposing sidewalls 118 may be spaced apart laterally (i.e., along the x-direction) or vertically (i.e., along the z-direction) between the silicide region 136 disposed on the gate structure 116 and the silicide regions 132, 134 disposed on the source region 122 and the drain region 124, respectively, to be further spaced apart by the spacers 118, which can further prevent leakage current that may occur in the semiconductor device 100-3 as shown in FIG. 4 (not shown in FIG. 10) than in the semiconductor device 100-1 as shown in FIG. 1. Furthermore, it should be noted that the thickness and width of the gate electrode 114 can be adjusted according to various requirements and should not be construed in a limiting sense.

[0035] Thereafter, a source region 122 and a drain region 124 may be formed on the sides of the gate electrode 114 by implanting dopants into the first channel layer 106 and the second channel layer 108. Thus, the top surface of the gate electrode 114 may be higher than the top surfaces of the source region 122 and the drain region 124. A silicidation process may then be performed to form a metal silicide in the source region 122, the drain region 124, and the gate electrode 114, respectively. Other processes may then be performed to obtain the structure illustrated in FIG. 4. With reference to FIG. 10, it should be noted that although the sidewalls of the protrusions of the gate electrode 114 are substantially aligned with the outer edges of the second channel layer 108, the sidewalls of the protrusions of the gate electrode 114 may be laterally misaligned with the outer edges of the second channel layer 108. According to some embodiments of the present disclosure, the sidewalls of the protrusion of the gate electrode 114 may extend outward beyond the outer edge of the second channel layer 108 so that the gate electrode 114 can cover portions of the first channel layer 106, thereby preventing doped regions (i.e., S / D regions) from forming in portions of the first channel layer 106 covered by the gate electrode 114. According to some alternative embodiments of the present disclosure, the sidewalls of the protrusion of the gate electrode 114 may be undercut inward relative to the outer edge of the second channel layer 108 so that portions of the doped regions (i.e., S / D regions) can form in portions of the second channel layer 108 not covered by the gate electrode 114.

[0036] While various embodiments of the present technology have been described above, it should be understood that they have been presented by way of example only, and not limitation. Many modifications can be made to the disclosed embodiments in accordance with the disclosure herein without departing from the spirit or scope of the present technology. Thus, the breadth and scope of the present technology should not be limited to any of the above-described embodiments. Rather, the scope of the present technology should be defined according to the following claims and their equivalents.

[0037] While the present technology has been shown and described with respect to one or more implementations, equivalent alternatives and modifications will occur to those skilled in the art upon reading and understanding this specification and the accompanying drawings. Additionally, while a particular feature of the present technology may be disclosed with respect to only one of several implementations, such feature can be combined with one or more other features of other implementations, as may be desired or advantageous in any given or particular application.

[0038] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the present technology. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context dictates otherwise. Furthermore, to the extent that "including," "including," "having," "having," "comprising," or variations thereof are used in either the detailed description and / or claims, these terms are intended to be inclusive in a similar manner to the term "comprising."

[0039] Unless otherwise specified, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this technology belongs. Furthermore, terms such as "about," "substantially," and "approximately," used herein in connection with a stated value or characteristic, are intended to indicate within 20% of the stated value or characteristic, unless otherwise specified. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted to have a meaning consistent with their meaning in the context of the relevant field, and will not be interpreted in an idealized or overly conventional sense unless expressly defined herein.

[0040] Those skilled in the art will readily appreciate that numerous modifications and alternatives to the present devices and methods may be made while retaining the teachings of the present invention. Accordingly, the above disclosure should be considered limited only by the metes and bounds of the appended claims. [Explanation of symbols]

[0041] 100-1 Semiconductor Devices 100-2 Semiconductor Devices 100-3 Semiconductor Devices 100-4 Semiconductor Devices 102 Circuit Board 104 doped region 106 First channel layer 108 Second Channel Layer 110 channel region 112 Gate Dielectric 114 gate electrode 116 Gate Structure 118 Spacer, sidewall 122 Source Region 124 Drain Region 130 Separation structure 132 Silicide region 134 Silicide region 136 Silicide Region 140 Trench 142 Gate dielectric layer 144 gate electrode layer 150 trenches, gate trenches

Claims

1. A substrate; a gate structure disposed on the substrate; a source region and a drain region disposed on two sides of the gate structure, respectively, the source region and the drain region being of a first conductivity type; a doped region disposed below the gate structure, the source region, and the drain region and spaced apart from the gate structure, the source region, and the drain region, the doped region being of a second conductivity type different from the first conductivity type; a first channel layer disposed between the doped region and the source and drain regions and in contact with the doped region, the first channel layer having a dopant concentration lower than a dopant concentration of the doped region; a trench surrounded by the first channel layer, the gate structure disposed in the trench, and a bottom surface of the trench being lower than a top surface of the doped region.

2. The semiconductor device of claim 1 , further comprising a second channel layer disposed within the trench, the second channel layer conforming to a surface of the trench.

3. The semiconductor device of claim 1 , wherein a top surface of the gate structure is higher than top surfaces of the source and drain regions.

4. The semiconductor device of claim 2 , wherein the source and drain regions are spaced from the gate structure by the second channel layer.

5. a first silicide region disposed on the source region and the drain region; 2. The semiconductor device of claim 1, further comprising: second silicide regions disposed on said gate structures, each of said first silicide regions being laterally spaced from said second silicide regions.

6. The semiconductor device of claim 2 , wherein a portion of the second channel layer is buried within the doped region.

7. The semiconductor device of claim 1 , wherein the first channel layer is disposed between the doped region and the source / drain region.

8. The doped region has a first depth of 5×10 １８ atoms / cm ３ is equal to 5 x 10 １８ atoms / cm ３ Higher 1x10 ２０ atoms / cm ３ Lower, or 1 x 10 ２０ atoms / cm ３ 10. The semiconductor device of claim 1, having a dopant concentration equal to

9. 3. The semiconductor device of claim 2, wherein the doped region has a maximum value of the dopant concentration at a first depth along a depth direction, and a bottom surface of the second channel layer under the gate structure is shallower than the first depth.

10. 5 x 10 １８ atoms / cm ３ is equal to 5 x 10 １８ atoms / cm ３ Higher 1x10 ２０ atoms / cm ３ Lower, or 1 x 10 ２０ atoms / cm ３ 2. The semiconductor device of claim 1, wherein the doped region having a dopant concentration equal to is disposed below the source region and the drain region.

11. providing a substrate; forming a doped region on the substrate; forming a first channel layer over the doped region; forming a trench in the first channel layer; forming a gate structure in the trench, the gate being disposed above and spaced apart from the doped region; forming source and drain regions on two sides of the gate structure, the source and drain regions being disposed above and spaced apart from the doped region; a dopant concentration of the first channel layer is lower than a dopant concentration of the doped region; A method for manufacturing a semiconductor device, wherein when the trench is formed in the first channel layer, the doped region is exposed from the trench.

12. The method of claim 11 , wherein the trench extends into the doped region.

13. The method of claim 11 , further comprising forming a second channel layer in the trench before forming the gate structure in the trench.

14. The method of claim 13 , wherein the second channel layer is conformal to a surface of the trench.

15. The method of claim 11 , wherein the doped region is disposed below and spaced apart from the gate structure, the source region, and the drain region.

16. 14. The method of claim 13, wherein the source and drain regions are spaced from the gate structure by the second channel layer.

17. providing a substrate; forming a doped region on the substrate; forming a first channel layer over the doped region; forming a trench in the first channel layer; forming a gate structure in the trench, the gate being disposed above and spaced apart from the doped region; forming source and drain regions on two sides of the gate structure, the source and drain regions being disposed above and spaced apart from the doped region; forming first silicide regions disposed on the source region and the drain region, respectively; forming a second silicide region disposed on the gate structure; a dopant concentration of the first channel layer is lower than a dopant concentration of the doped region; A method for manufacturing a semiconductor device, wherein each of the first silicide regions is laterally spaced from the second silicide region.

18. 12. The method of claim 11, wherein the source and drain regions are of a first conductivity type and the doped region is of a second conductivity type different from the first conductivity type.

19. The doped region has a first depth of 5×10 １８ atoms / cm ３ is equal to 5 x 10 １８ atoms / cm ３ Higher 1x10 ２０ atoms / cm ３ Lower, or 1 x 10 ２０ atoms / cm ３ 12. The method of claim 11, wherein the dopant concentration is equal to

20. 14. The method of claim 13, wherein the doped region has a maximum dopant concentration at a first depth along a depth direction, and a bottom surface of the second channel layer below the gate structure is shallower than the first depth.

21. 5 x 10 １８ atoms / cm ３ is equal to 5 x 10 １８ atoms / cm ３ Higher 1x10 ２０ atoms / cm ３ Lower, or 1 x 10 ２０ atoms / cm ３ 12. The method of claim 11, wherein the doped region having a dopant concentration equal to is disposed below the source region and the drain region.

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