Semiconductor Devices

Abstract

To improve power consumption efficiency.SOLUTION: A semiconductor device (1) comprises: a hardware accelerator including a plurality of multiply-accumulate circuits (11) and used for processing that uses a neural network; a target table (51) in which a target value indicating a ratio of the multiply-accumulate circuits to be activated is set for each neural network model; a power supply control unit (50) which refers to the target table and controls supplying power to the multiply-accumulate circuits or stopping the power supplied to the circuits separately, in accordance with the target value set for the model of the neural network to be executed; a monitoring unit (30) which observes, when the semiconductor device executes the processing, an actual utilization ratio of the multiply-accumulate circuits; and a table update unit (54) which sets, when update of the target value is required during the processing executed on the semiconductor device, a new target value based on the actual utilization ratio, and updates the target table with the new target value.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 describes a technology for reducing the power consumption of a semiconductor integrated circuit. The technology described in Patent Document 1 calculates the leakage current corresponding to the temperature of the semiconductor integrated circuit, and reduces power consumption by employing a power gating method or a DVFS (Dynamic Voltage Frequency Scaling) method depending on the magnitude of the leakage current.

[0003] Furthermore, with the widespread use of deep learning, semiconductor integrated circuits now exist that are specialized for executing processing using neural networks. In semiconductor integrated circuits for neural networks, in order to speed up processing, some or all of the processing may be executed by dedicated hardware (hereinafter, dedicated hardware will be referred to as a "hardware accelerator"). In neural networks, the main operation is multiply-accumulate. For this reason, the hardware accelerator provided in semiconductor integrated circuits for neural networks includes multiple multiply-accumulate circuits. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2009 / 078081 Summary of the Invention [Problem to be solved by the invention]

[0005] Depending on the model of the neural network being executed, only a portion of the multiple multiply-accumulate circuits included in the hardware accelerator may be used. Even in such cases, if power is supplied to all of the multiply-accumulate circuits, power will be consumed unnecessarily. Therefore, there is a need to improve power consumption efficiency. [Means for solving the problem]

[0006] According to one embodiment of the present disclosure, there is provided a semiconductor device (1), comprising: a hardware accelerator including a plurality of product-sum calculation circuits (11) and used for processing using a neural network; a target table (51) in which target values ​​indicating a proportion of the plurality of product-sum calculation circuits to be active are set for each neural network model; a power supply control unit (50) that refers to the target table and individually controls the supply or stop of power to the plurality of product-sum calculation circuits according to the target values ​​set for the neural network model to be executed in the semiconductor device; a monitor unit (30) that observes actual usage rates of the plurality of product-sum calculation circuits while processing is being executed in the semiconductor device; and a table update unit (54) that, when the target values ​​need to be updated while processing is being executed in the semiconductor device, sets new target values ​​based on the actual usage rates and updates the target table with the new target values.

[0007] According to this embodiment, the supply or stop of power to the multiple product-sum calculation circuits is individually controlled according to a target value set for each model of the neural network to be executed, so power is not consumed unnecessarily compared to an embodiment in which power and clock signals are supplied to all product-sum calculation circuits. Furthermore, because the target value is set according to the model of the neural network to be executed, the power supply to the product-sum calculation circuits can be controlled without degrading the performance of processing using the neural network. In this way, power consumption efficiency can be improved. Furthermore, since the target value is updated based on the actual usage rate while processing is being performed in the semiconductor device, the target value can be updated according to the actual usage status of the product-sum operation circuit, thereby improving power consumption efficiency. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram illustrating a configuration of a semiconductor device. [Figure 2] FIG. 10 is a diagram illustrating a target table. [Figure 3] 10 is a flowchart of a power gating process. [Figure 4] 10 is a flowchart of a target value update process. [Figure 5] FIG. 10 is a diagram illustrating a target value identification table. DETAILED DESCRIPTION OF THE INVENTION

[0009] A. Embodiment As shown in FIG. 1, a semiconductor device 1 according to an embodiment performs processing using a neural network. For example, the semiconductor device 1 is provided in a control unit mounted on an automobile. This control unit also includes an ECU (Electrical Control Unit) for an ADAS (Advanced Driving Assistant System). When the ADAS ECU performs processing to grasp the situation around the automobile, the semiconductor device 1 performs processing related to image recognition based on image data captured by a camera mounted on the automobile. The semiconductor device 1 includes an NPU (Neural Processing Unit / Neural network Processing Unit) 10, an NPU monitor 30, a power supply control unit 50, and a bus 90.

[0010] The NPU 10 executes processing using a neural network. In this specification, the neural network includes not only a three-layer neural network but also a deep neural network (DNN) with four or more layers, a convolutional neural network (CNN) with a convolutional layer and a pooling layer, etc. The NPU 10 includes N (N is an integer equal to or greater than 1) NN accelerators 11, a processor 12, a memory 13, and a direct memory access controller (DMAC) 14.

[0011] The N NN accelerators 11 (111 to 11N) function as hardware accelerators used for processing using neural networks in the NPU 10. The use of dedicated hardware to increase the execution speed of a specific process is called hardware acceleration. A hardware accelerator is dedicated hardware for hardware acceleration.

[0012] The NN accelerator 11 includes a MAC (Multiply Accumulation) unit 110, a switching unit 120, a processor 130, a DMAC 140, and a memory 150. The NN accelerators 111 to 11N have the same configuration. The NN accelerator 11 is also called a multiply-accumulate circuit.

[0013] The MAC unit 110 includes a plurality of multiply-accumulate units and performs multiply-accumulate operations. For example, the MAC unit 110 includes 1K (1024) multiply-accumulate units. The switching unit 120 includes a switch provided on a power supply line of the NN accelerator 11 and a clock gating circuit. When the switch is turned on by a control signal supplied from the power supply control unit 50, power is supplied to the NN accelerator 11. When the switch is turned off by a control signal supplied from the power supply control unit 50, power supply to the NN accelerator 11 is stopped. When an enable signal is supplied from the power supply control unit 50 to the clock gating circuit, a clock signal is supplied to the NN accelerator 11. When a disable signal is supplied from the power supply control unit 50 to the clock gating circuit, the supply of the clock signal to the NN accelerator 11 is stopped.

[0014] The processor 130 is a processor that controls the NN accelerator 11. The DMAC 140 transfers data from the memory 150 in response to a read request for data from the memory 150 from the processor 12 or another NN accelerator 11. The memory 150 is a local memory of the NN accelerator 11.

[0015] The processor 12 is a processor that performs overall control of the NPU 10. The processor 12 also executes arithmetic processing other than multiply-accumulate operations. The memory 13 is a shared memory. The memory 13 is used, for example, for transmitting and receiving image data, DNN models, and weight data between the ADAS CPU and the NPU 10. The DMAC 14 transfers data from the memory 13 in response to a read request for data from the memory 13 from the NN accelerators 111 to 11N of the NPU 10.

[0016] The NPU monitor 30 monitors the utilization rate of each NN accelerator 11 at a predetermined time interval while the NPU 10 is performing processing. The utilization rate of an NN accelerator 11 is the ratio of the number of NN accelerators 11 in use to the total number. The utilization rate is also called the actual utilization rate. The predetermined time interval is, for example, one second. The NPU monitor 30 is also called a monitor unit.

[0017] The NPU monitor 30 transmits the observation results to the determination unit 52 of the power supply control unit 50 via the bus 90. The NPU monitor 30 starts observing the usage rate when power supply to the semiconductor device 1 starts. For example, when the vehicle engine is started, power supply to the semiconductor device 1 starts. Also, when the vehicle engine is stopped, power supply to the semiconductor device 1 is stopped.

[0018] The power supply control unit 50 individually controls the supply or stop of power to the N NN accelerators 11. The power supply control unit 50 includes a target table 51, a determination unit 52, a switching unit 53, and a table update unit .

[0019] 2, the number of NN accelerators 11 to be activated among N NN accelerators 11 is set as a target value for each neural network model in the target table 51. The initial target value in the target table 51 is a value calculated in advance by, for example, simulation or the like.

[0020] 1 outputs a signal to the switching unit 53 indicating an instruction to activate, among the N NN accelerators 11, the number of NN accelerators 11 indicated by the target value set in the target table 51, and to deactivate the remaining NN accelerators 11. Here, activating the NN accelerator 11 means supplying power and a clock signal to the NN accelerator 11 so that the NN accelerator 11 becomes operable.

[0021] Furthermore, if the target value needs to be updated, the determining unit 52 outputs a signal representing an instruction to update the target table 51 to the table updating unit 54 .

[0022] The switching unit 53 switches the supply of power and clock signals to the N NN accelerators 11 individually in response to an instruction from the determining unit 52.

[0023] When the NPU 10 is executing processing and the table update unit 54 receives a signal from the determination unit 52 indicating an instruction to update the target table 51, the table update unit 54 sets a new target value based on the observed usage rate and updates the target table 51 with the new target value. How to determine the new target value will be described later.

[0024] The power supply control unit 50 executes the power gating process at the timing when the NPU 10 executes the process, more specifically, before the start of the image recognition process by the NPU 10. The NPU 10 executes the image recognition process every time an execution instruction is transmitted to the processor 12 by the ADAS CPU.

[0025] 3, in step S101, the discrimination unit 52 of the power supply control unit 50 reads out the target value set for the neural network model to be executed from the target table 51. It is assumed that the discrimination unit 52 has information on the neural network model to be executed in advance.

[0026] In step S103, the discrimination unit 52 notifies the switching unit 53 of a switching instruction based on the target value. Specifically, the discrimination unit 52 outputs a switching signal to the switching unit 53 indicating an instruction to activate, among the N NN accelerators 11, the number of NN accelerators 11 indicated by the target value, and to deactivate the remaining NN accelerators 11.

[0027] In step S105, upon receiving the switching signal from the determining unit 52, the switching unit 53 switches the supply of power and clock signals to the N NN accelerators 11 individually.

[0028] The supply of power and clock signals to the NN accelerator 11 is switched, for example, as follows: The switching unit 53 outputs a control signal that turns on the switching included in the switching unit 120 of the NN accelerator 11 to be activated. This starts the supply of power to the NN accelerator 11. At the same time, the switching unit 53 outputs an enable signal to the clock gating circuit included in the switching unit 120 of the NN accelerator 11 to be activated. This starts the supply of clock signals to the NN accelerator 11.

[0029] Furthermore, the switching unit 53 outputs a control signal to turn off the switch included in the switching unit 120 of the NN accelerator 11 to be deactivated. This stops the supply of power to the NN accelerator 11. Additionally, the switching unit 53 outputs a disable signal to the clock gating circuit included in the switching unit 120 of the NN accelerator 11 to be deactivated. This stops the supply of the clock signal to the NN accelerator 11.

[0030] For example, the switching unit 53 activates a specified number of NN accelerators 11 among the N NN accelerators 11, starting with the NN accelerator 111 with the smallest number. If an instruction is given to activate five NN accelerators 11, the NN accelerators 111 to 115 are activated. This completes the flow of the power gating process.

[0031] In this way, by supplying power only to the number of NN accelerators 11 indicated by the target value, it is possible to improve the efficiency of power consumption.

[0032] Furthermore, when the supply of power to the semiconductor device 1 is started, the power supply control unit 50 starts a process of updating the target value. Furthermore, the NPU 10 starts executing a program for image recognition processing in which a neural network model is implemented, for example, in response to an instruction from the ADAS CPU. The process of updating the target value is executed in parallel with the power gating process described above. To facilitate understanding of the technology, the embodiment assumes that the NPU 10 does not execute multiple neural network models simultaneously. For example, when multiple neural network models need to be executed in parallel, the NPU 10 executes the multiple neural models in a time-sharing manner in response to an instruction from the ADAS CPU.

[0033] 4, in step S301, the determination unit 52 determines whether or not an observation result has been received from the NPU monitor 30. If the determination unit 52 has received an observation result from the NPU monitor 30 (step S301; YES), the determination unit 52 executes the process of step S303. If the determination unit 52 has not received an observation result from the NPU monitor 30 (step S301; NO), the determination unit 52 waits.

[0034] In step S303, the discrimination unit 52 determines whether or not the target value needs to be updated. The target value needs to be updated when the difference between the ratio of the currently active NN accelerators 11 to the whole and the usage rate is equal to or greater than a preset value. If the target value needs to be updated in step S303 (step S303; YES), the discrimination unit 52 outputs a signal representing an instruction to update the target table 51 to the table update unit 54. Thereafter, the process of step S305 is executed. On the other hand, if the target value does not need to be updated in step S303 (step S303; YES), the process of step S307 is executed.

[0035] In step S305, the table update unit 54 updates the target value. First, the table update unit 54 multiplies the maximum usage rate observed during a predetermined period by a predetermined coefficient. The predetermined coefficient is preferably greater than 1 and less than 1.5. For example, the predetermined coefficient is 1.2. The obtained value is also referred to as a first value. The table update unit 54 multiplies the obtained first value by N, which is the total number of NN accelerators 11. The table update unit 54 rounds up the obtained value to an integer value. This integer value is the new target value. The table update unit 54 updates the target value for the target neural network model in the target table 51 with the new target value. Note that the table update unit 54 is assumed to have information about the neural network model being executed in advance. Thereafter, the table update unit 54 outputs a signal indicating that the target value has been updated to the discrimination unit 52.

[0036] In step S307, the determination unit 52 determines whether or not the update process can be terminated. The termination condition for the update process is that the execution of the program for image recognition processing has ended. The NPU 10 terminates the execution of the program for image recognition processing in response to an instruction from the ADAS CPU. If the termination condition for the update process is met (step S307; YES), the update process is terminated. If the termination condition for the update process is not met (step S307; NO), the process of step S301 is executed again.

[0037] In the embodiment, the target value is set so that the proportion of the NN accelerators 11 to which power is supplied, among the N NN accelerators 11, approaches a value obtained by multiplying the maximum value of the utilization rate observed in a predetermined period by a predetermined coefficient. In this way, by setting the target value based on the value obtained by multiplying the maximum value of the utilization rate observed in a predetermined period by a predetermined coefficient, it is possible to set a target value adapted to the actual utilization status of the NN accelerator 11.

[0038] Furthermore, when processing is being executed in the NPU 10, if the difference between the percentage of NN accelerators 11 to which power is being supplied among the N NN accelerators 11 and the utilization rate is equal to or greater than a preset value, the target value is updated. Thus, the target value can be updated according to the actual utilization status of the NN accelerators 11. This makes it possible to improve power consumption efficiency.

[0039] For example, suppose that the processing capacity of one NN accelerator 11 is 10 TOPS (Tera Operations Per Second). Furthermore, suppose that the NPU 10 is equipped with ten NN accelerators 11. In this case, the processing capacity of the ten NN accelerators 11 is 100 TOPS. For example, if the processing capacity required for the image recognition processing to be executed is 8 TOPS, it can be said that there is no problem if only one NN accelerator 11 is operating. In such a case, in the configuration according to the embodiment, the supply of power and clock signals to the remaining nine NN accelerators is stopped. This prevents unnecessary power consumption compared to an embodiment in which power and clock signals are supplied to all of the NN accelerators 11.

[0040] The target value is set according to the model of the neural network to be executed. Some neural network models use a large number of NN accelerators 11 in parallel, while others do not. The supply or stop of power supply to the N NN accelerators 11 is individually controlled according to the target value set for each neural network model to be executed. Therefore, compared to a mode in which power and clock signals are supplied to all NN accelerators 11, unnecessary power consumption is prevented. Furthermore, power consumption efficiency can be improved without degrading the performance of processing using the neural network.

[0041] In particular, many DNN models have a lower utilization rate of the N NN accelerators 11 during execution compared to, for example, a three-layer neural network. For this reason, the configuration according to the embodiment can be said to be particularly effective in improving the power consumption efficiency during execution of processing using DNN.

[0042] B1. Other embodiment 1 In the embodiment, the table update unit 54 calculates the new target value by multiplying the maximum value of the usage rate observed in a predetermined period by a predetermined coefficient. However, the method for calculating the new target value is not limited to this.

[0043] When it is necessary to update the target value, that is, when the table update unit 54 receives a signal from the discrimination unit 52 indicating an instruction to update the target table 51, the table update unit 54 calculates the average value of the usage rates observed over a predetermined period. The table update unit 54 multiplies the average value by N, which is the total number of NN accelerators 11. The table update unit 54 rounds up the obtained value to an integer value. This integer value is the new target value. The table update unit 54 updates the target value for the target neural network model in the target table 51 with the new target value.

[0044] In this way, the target value is set so that the proportion of the NN accelerators 11 to which power is supplied, among the N NN accelerators 11, approaches the average value of the utilization rates observed over a predetermined period. In this way, by setting the target value based on the average value of the utilization rates observed over a predetermined period, it is possible to set a target value that is adapted to the actual usage status of the NN accelerators 11.

[0045] Also in the first alternative embodiment, the target value is updated when the difference between the usage rate and the proportion of the NN accelerators 11 to which power is being supplied among the N NN accelerators 11 is equal to or greater than a preset value. Thus, the target value can be updated at a timing according to the actual usage status of the NN accelerators 11.

[0046] B2. Other embodiment 2 Alternatively, the table update unit 54 may update the target value using a machine learning model generated by machine learning. The table update unit 54 is assumed to have a machine learning model that has been machine-learned. This machine learning model is, for example, data on usage rates observed for each neural network model when that model was previously executed, and is generated by machine learning using usage rate data from 10,000 runs as training data. When usage rate data observed over a predetermined period when the target neural network model was executed is input, this machine learning model outputs a predicted value of usage rate, for example, one second later. The table update unit 54 multiplies the predicted value of usage rate by N, which is the total number of NN accelerators 11. The table update unit 54 rounds up the obtained value to an integer value. This integer value is the new target value. The table update unit 54 updates the target value for the target neural network model in the target table 51 with the new target value.

[0047] In this way, the target value is updated using a machine learning model generated by machine learning, so it is possible to set a target value adapted to the actual usage status of the NN accelerator 11. Furthermore, the target value is updated when the difference between the percentage of NN accelerators 11 to which power is being supplied among the N NN accelerators 11 and the usage rate is equal to or greater than a preset value. Thus, the target value can be updated at a timing according to the actual usage status of the NN accelerator 11.

[0048] Furthermore, the processor 130 may perform control to distribute the load on the NN accelerator 11 based on the predicted value of the utilization rate output by the machine learning model.

[0049] B3. Other embodiment 3 Alternatively, the table update unit 54 may update the target value using the following method. As shown in FIG. 5, the table update unit 54 includes a target value identification table 541 that associates utilization rates with target values ​​for each neural network model. The target values ​​in the target value identification table are values ​​determined by simulation. When it is necessary to update the target value, that is, when the table update unit 54 receives a signal from the discrimination unit 52 indicating an instruction to update the target table 51, the table update unit 54 refers to the target value identification table 541 and sets a target value corresponding to the maximum utilization rate observed during a predetermined period. Alternatively, when it is necessary to update the target value, the table update unit 54 refers to the target value identification table 541 and sets a target value corresponding to the average utilization rate observed during a predetermined period.

[0050] In this way, the target value is set using the target value identification table 541 that associates the usage rate with the target value, so that it is possible to set a target value that is adapted to the actual usage status of the NN accelerator 11. Also in the third alternative embodiment, the target value is updated when the difference between the usage rate and the proportion of NN accelerators 11 to which power is being supplied among the N NN accelerators 11 is equal to or greater than a preset value. Thus, the target value can be updated at a timing that corresponds to the actual usage status of the NN accelerator 11.

[0051] B4. Other embodiment 4 In the embodiment, an example has been described in which the target value indicates the number of NN accelerators 11 to which power is supplied among the N NN accelerators 11. However, the target value may also be the ratio of the number of NN accelerators 11 to which power is supplied to the total number of NN accelerators 11.

[0052] B5. Other Embodiment 5 In the embodiment, an example has been described in which the time interval at which the NPU monitor 30 observes the utilization rate of each NN accelerator 11 is fixed. However, the time interval at which the NPU monitor 30 performs observation may be changed as follows.

[0053] For example, assume that the NPU monitor 30 observes the actual utilization rate at one-second intervals. The determination unit 52 first determines whether or not the target value needs to be updated based on the observation results received from the NPU monitor 30. If the determination unit 52 determines that the target value needs to be updated, the table update unit 54 updates the target value.

[0054] Thereafter, if the period change condition is satisfied, the determination unit 52 determines that it is necessary to change the time interval for observing the actual utilization rate by the NPU monitor 30. The period change condition is satisfied if a second value indicating the difference between the proportion of the NN accelerator 11 that is the target of the current power supply to the whole and the current actual utilization rate is greater than a third value indicating the difference between the proportion of the NN accelerator 11 that is the target of the previous power supply to the whole and the previous actual utilization rate.

[0055] Here, the ratio of the NN accelerator 11 to which power is currently being supplied to the entire system is calculated based on the updated target value updated by the table update unit 54. The current actual utilization rate is the actual utilization rate indicated by the observation result currently received from the NPU monitor 30. The ratio of the NN accelerator 11 to which power was previously supplied to the entire system is calculated based on the target value before the update. The current actual utilization rate is the actual utilization rate indicated by the observation result currently received from the NPU monitor 30.

[0056] If the period change condition is satisfied, it is considered that the effect of the power supply control resulting from the previous target value update was not fully realized. Therefore, if the period change condition is satisfied, the determination unit 52 notifies the NPU monitor 30 to shorten the time interval for observing the actual utilization rate. Therefore, the NPU monitor 30 changes the time interval for observing the actual utilization rate from 1 second to 0.5 seconds, for example.

[0057] In this way, when the effect of power supply control resulting from the previous target value update is not fully apparent, the time interval for observing the actual usage rate is shortened and the frequency of target value updates is increased, thereby enabling more precise power supply control to be achieved.

[0058] The period change condition may further include a condition that the second value is greater than the third value by a predetermined value or more. The period change condition may further include a condition that the time difference between the current time and the previous time is equal to or less than a predetermined value.

[0059] B6. Other Embodiment 6 In the embodiment, an example has been described assuming that multiple neural network models are not executed simultaneously in the NPU 10. However, multiple neural network models may be executed simultaneously in the NPU 10. In this case, in the power gating process, the power supply control unit 50 reads target values ​​set for each of the multiple neural network models to be executed, and individually switches the supply of power and clock signals to the NN accelerator 11 based on the sum of the multiple target values.

[0060] B7. Other Embodiments 7 In the embodiment, an example has been described in which the discrimination unit 52 determines that the target value needs to be updated when the difference between the ratio of power-supplied NN accelerators 11 out of the N NN accelerators 11 and the usage rate is equal to or greater than a preset value. Alternatively, the discrimination unit 52 may determine that the target value needs to be updated when the difference between the number of power-supplied NN accelerators 11 out of the N NN accelerators 11 and the number of used NN accelerators 11 is equal to or greater than a preset value based on the observation results of the NPU monitor 30. The NPU monitor 30 is assumed to have a function of observing which of the N NN accelerators 11 are being used.

[0061] Furthermore, in the embodiment, an example has been described in which the N NN accelerators 11 have the same configuration, but the N NN accelerators 11 may have different configurations.

[0062] The present disclosure is not limited to the above-described embodiments and can be realized in various configurations without departing from the spirit thereof. For example, the technical features in the embodiments corresponding to the technical features in each aspect described in the Summary of the Invention section can be appropriately replaced or combined to solve some or all of the above-described problems or achieve some or all of the above-described effects. Furthermore, if a technical feature is not described as essential in this specification, it can be appropriately deleted. [Explanation of symbols]

[0063] 1... semiconductor device, 11... NN accelerator, 12... processor, 13... memory, 14... DMAC, 30... NPU monitor, 50... power supply control unit, 51... target table, 52... discrimination unit, 53... switching unit, 54... table update unit, 90... bus, 110... MAC unit, 120... switching unit, 130... processor, 140... DMAC, 150... memory

Claims

1. A semiconductor device (1), a hardware accelerator including a plurality of product-sum calculation circuits (11) and used for processing using a neural network; a target table (51) in which a target value indicating a ratio of the product-sum calculation circuits to be activated among the plurality of product-sum calculation circuits is set for each neural network model; a power supply control unit (50) that refers to the target table and individually controls the supply or stop of power to the plurality of product-sum calculation circuits in accordance with the target value set for a neural network model to be executed in the semiconductor device; a monitor unit (30) for observing an actual usage rate of the plurality of product-sum operation circuits when processing is being executed in the semiconductor device; a table update unit (54) that, when a process is being executed in the semiconductor device and the target value needs to be updated, sets a new target value based on the actual usage rate and updates the target table with the new target value; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, the plurality of product-sum calculation circuits have the same configuration, the target value indicates the number of product-sum operation circuits to which power is to be supplied among the plurality of product-sum operation circuits; the power supply control unit supplies power to the number of product-sum arithmetic circuits indicated by the target value among the plurality of product-sum arithmetic circuits, and does not supply power to the remaining product-sum arithmetic circuits. Semiconductor device.

3. 3. The semiconductor device according to claim 2, The table update unit determining that the target value needs to be updated when a difference between a ratio of the product-sum operation circuits to which power is supplied among the plurality of product-sum operation circuits and the actual usage rate is equal to or greater than a preset value; setting the target value based on a first value obtained by multiplying a maximum value of the actual utilization rate observed in a predetermined period by a predetermined coefficient; Semiconductor device.

4. 3. The semiconductor device according to claim 2, The table update unit determining that the target value needs to be updated when a difference between a ratio of the product-sum operation circuits to which power is supplied among the plurality of product-sum operation circuits and the actual usage rate is equal to or greater than a preset value; setting the target value based on an average value of the actual usage rate observed during a predetermined period; Semiconductor device.

5. 3. The semiconductor device according to claim 2, The table update unit determining that the target value needs to be updated when a difference between a ratio of the product-sum operation circuits to which power is supplied among the plurality of product-sum operation circuits and the actual usage rate is equal to or greater than a preset value; updating the target value based on a predicted value of the actual utilization rate predicted using a machine learning model that is generated by machine learning and that predicts the actual utilization rate; Semiconductor device.

6. 3. The semiconductor device according to claim 2, a target value specification table that associates the actual usage rate with the target value; The table update unit determining that the target value needs to be updated when a difference between a ratio of the product-sum operation circuits to which power is supplied among the plurality of product-sum operation circuits and the actual usage rate is equal to or greater than a preset value; referencing the target value identification table, and setting the target value according to the maximum value of the actual utilization rate observed in a predetermined period or the average value of the actual utilization rate observed in a predetermined period; Semiconductor device.

7. 7. The semiconductor device according to claim 3, the monitor unit observes the actual usage rate at predetermined time intervals, the table update unit receives the observation result from the monitor unit, and updates the target value if it is necessary to update the target value; When a predetermined period change condition is satisfied, including the current difference being larger than the previous difference, the monitor unit shortens the time interval for observing the actual utilization rate. Semiconductor device.

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