Power semiconductor device and method for manufacturing a power semiconductor device - Patents.com

Abstract

The semiconductor device comprises a first main electrode (3), a second main electrode (4), a gate electrode layer (5) between the first main electrode (3) and the second main electrode (4), and a semiconductor layer stack (2) between the first main electrode (3) and the second main electrode (4) and in electrical contact with the first main electrode (3) and the second main electrode (4), the semiconductor layer stack (2) comprising differently doped semiconductor layers, at least two of which differ in at least one of conductivity type and doping concentration, and a plurality of pillar-like or fin-like regions (20) extending through the gate electrode layer (5), each of the plurality of pillar-like or fin-like regions (20) being disposed on the first main electrode (3). A power semiconductor device (1) is described, comprising contact layers (21) having a first doping concentration and a first conductivity type, each contact layer (21) extending to a surface (5A) of the gate electrode layer (5) facing a first main electrode (3), and the contact layers (21) of adjacent pillar-shaped or fin-shaped regions (20, 930) meeting at a surface facing the first main electrode (3, 921) of the gate electrode layer (5, 94) such that the contact layers (21) of adjacent pillar-shaped or fin-shaped regions (20, 930) are arranged contiguously on the surface facing the first main electrode (3, 921) of the gate electrode layer (5, 94).

Description

[Technical Field]

[0001] A power semiconductor device is provided. A manufacturing method for such a power semiconductor device is also provided. The power semiconductor device may be a silicon carbide device. [Background technology]

[0002] Compared to typical silicon (Si)-based devices, silicon carbide (SiC)-based devices have much higher breakdown field strength and thermal conductivity, allowing them to reach efficiency levels that would otherwise be unattainable. 4H-SiC is the polytype of choice for power electronics, such as metal-oxide-semiconductor field-effect transistors (MOSFETs) or accumulation-mode MOSFETs (ACCUFETs), due to advances in the field of 4H-SiC growth technology and its attractive electronic properties, such as a larger bandgap, compared to other available wafer-scale polytypes, such as 6H SiC or 3C-SiC. 4H-SiC power MOSFETs and power ACCUFETs are already commercially available, but their on-resistance, R on There is a large room for improvement in the inversion channel mobility of power MOSFETs to further reduce

[0003] Most commercially available power field-effect transistors based on silicon carbide (SiC) are realized with a planar design, where the channel is formed on the surface of the wafer, such as in vertical double-diffused metal-oxide-semiconductor field-effect transistors (VDMOS). However, increasing current density in these devices is difficult because the p-type implant in n-channel VDMOS forms a parasitic junction field-effect transistor (JFET) gate that tends to reduce the width of the current flow.

[0004] Trench metal-oxide-semiconductor field-effect transistors (MOSFETs) have a low on-resistance R due to the absence of a parasitic JFET. onFurthermore, in the case of SiC, the trench MOSFET configuration allows for carrier mobility optimization by engineering the channel for various crystal planes. SiC trench MOSFETs are known, for example, from U.S. Patent Application Publication No. 2018 / 0350977. Known methods for fabricating SiC-based trench MOSFETs require etching deep trenches in SiC to form trench gate electrodes. Etching SiC is difficult and costly compared to etching other semiconductor materials, such as silicon (Si).

[0005] For high voltage classes above 3 kV, the drift layer resistance R drift is the on-resistance R on While R is dominant over R, reducing the latter is essential to significantly reduce on-state power losses and switching losses in the commercially more important lower voltage classes (e.g., voltage classes below 1.7 kV) used in electric and hybrid electric vehicles (EV / HEV). Here, as shown in Figure 1, R on is still significantly higher than ideal. In this regard, low inversion channel mobility presents one of the major challenges that can significantly impact the cost of the device and therefore the widespread adoption of SiC power MOSFETs. Although the enhancement of inversion channel mobility using improved gate stacks and SiC / oxide interfaces has not been very successful, it is known as one of the most important events in the development and commercialization of SiC power MOSFETs. The introduction of nitrogen monoxide (NO) after oxidation of 6H-SiC in the late 90s and its application to 4H-SiC MOSFETs in 2001 led to the reduction of the interface defect density D due to the introduction of nitrogen (N) near the interface by NO annealing. it This allows for a significant improvement in inversion layer electron mobility (see Figure 2). However, there is a strong demand for devices with higher mobility than state-of-the-art NO-annealed SiC MOSFETs, especially to expand SiC MOSFETs into the low-voltage class market.

[0006] Additionally, higher channel mobility allows for ideal / lower R on In addition to reaching this, the following problems can also be avoided:

[0007] a) The gate can be driven at a lower voltage, resulting in a smaller electric field in the gate oxide layer, improving threshold stability and long-term oxide reliability.

[0008] b) There is no need to aggressively change the transistor channel length to reduce the channel resistance, thus avoiding short channel effects.

[0009] Alternative strategies beyond NO treatment to reduce interface defects are the introduction of interfacial layers with trace impurities, surface counterdoping, high-temperature oxidation, and alternative non-polar crystal faces (instead of the conventional polar Si faces) due to their inherently higher mobility.

[0010] Inversion channel mobility and drift layer resistance R drift Besides the source resistance R, which represents all resistances between the source terminal of the device and the channel of the device, including, for example, the resistances of the wire bonds, source metallization, and source layer S On-resistance R on There are other parameters that affect the performance and are therefore worth improving.

[0011] US 2019 / 0371889, EP 3264470, DE 10227831 and US 2017 / 0077304 refer to semiconductor devices. Summary of the Invention [Problem to be solved by the invention]

[0012] The problem to be solved is to provide a power semiconductor device with high efficiency. [Means for solving the problem]

[0013] Exemplary embodiments of the present disclosure address the above-mentioned drawbacks, inter alia, by means of a power semiconductor device and a manufacturing method as defined in the independent claims. Exemplary further developments form the subject matter of the dependent claims.

[0014] According to at least one embodiment, a power semiconductor device includes a first main electrode, a second main electrode, and a gate electrode layer between the first and second main electrodes. Optionally, the power semiconductor device further includes a first insulating layer including at least one of a plurality of first insulating layer portions across the gate electrode layer and at least one second insulating layer portion disposed on a surface of the gate electrode layer facing the second main electrode. The second insulating layer portion may be a continuous layer or a discontinuous layer including a plurality of second insulating layer portions. For example, "across" means "passing by."

[0015] The power semiconductor device also includes a semiconductor layer stack located between and in electrical contact with the first and second main electrodes. The semiconductor layer stack being "located between" the first and second main electrodes means that the first and second main electrodes define a space in which the semiconductor layer stack is disposed. The semiconductor layer stack includes silicon carbide.

[0016] The semiconductor layer stack further includes differentially doped semiconductor layers, with at least two semiconductor layers differing in at least one of conductivity type and doping concentration. The semiconductor layer stack further includes a plurality of pillar- or fin-shaped regions across the gate electrode layer, each of the plurality of pillar- or fin-shaped regions including a contact layer having a first doping concentration and a first conductivity type disposed on the first main electrode. Each contact layer extends to a surface of the gate electrode layer facing the first main electrode. The contact layer can be grown horizontally above the gate electrode layer such that the surface of the gate electrode layer facing the first main electrode is at least partially covered by the contact layer.

[0017] In operation of the power semiconductor device, when the power semiconductor device is in an on-state, i.e., when a positive gate bias is applied, for example, a current flows through the semiconductor layer stack between the first and second main electrodes. When the power semiconductor device is in an off-state, i.e., when the gate bias is zero, for example, the current flow between the first and second main electrodes is blocked. For example, the first main electrode is a source electrode of the power semiconductor device, and the second main electrode is a drain electrode. Furthermore, each pillar-shaped or fin-shaped region can have a source layer on the first main electrode, which can include or consist of a contact layer.

[0018] The contact layer may include or consist of a wide bandgap material, such as at least one of silicon carbide, e.g., 3C-SiC, or GaN. Additionally, the contact layer may be a highly doped layer. For example, the first doping concentration may be 10 19~ 10 20 cm -3 may be in the range of

[0019] The gate electrode layer may be a highly doped Si layer or a metal layer such as a layer of Al.

[0020] In the context of the present application, a "pillar-like region" may be a region whose main direction of extension extends obliquely or perpendicularly to the device plane, which is the plane of main extension of the device. Furthermore, a "fin-like region" may be a region whose main direction of extension is along the device plane. For example, a pillar-like region may in each case have the shape of a truncated cone, a truncated pyramid, a prism, or a cylinder. A fin-like region may in each case have the shape of a prism.

[0021] The pillar-like or fin-like regions are sometimes referred to as nanowires or microwires. For example, US Patent Application Publication No. 2016 / 0351391 refers to the fabrication of semiconductor nanowires.

[0022] According to at least one embodiment, each pillar-like or fin-like region has a first horizontal extension along the device plane of less than 2 μm or less than 1 μm, the first horizontal extension being the shorter of two horizontal extensions that extend obliquely relative to each other.

[0023] The contact layer extending to the surface of the gate electrode layer facing the first main electrode has the advantage that each pillar-shaped or fin-shaped region has a larger contact area on the surface facing the first main electrode, illustratively by at least a factor of two.

[0024] Increasing the contact area has the positive effect of reducing the contact resistance at the transition between the first main electrode and the contact layer, and therefore the source resistance R S can be reduced.

[0025] According to at least one embodiment of the power semiconductor device, the contact layers of adjacent pillar-shaped or fin-shaped regions meet on a surface of the gate electrode layer facing the first main electrode, i.e., the contact layers of adjacent pillar-shaped or fin-shaped regions are arranged continuously on a surface of the gate electrode layer facing the first main electrode.

[0026] According to at least one embodiment of the power semiconductor device, the semiconductor layer stack includes a plurality of channel layers, each assigned to one of the pillar-shaped or fin-shaped regions and arranged on a surface of the contact layer facing away from the first main electrode. The channel layers have a second doping concentration and a second conductivity type, and the second doping concentration is different from the first doping concentration and / or the second conductivity type is different from the first conductivity type. The channel layers include or consist of silicon carbide, such as 3C-SiC.

[0027] For example, the first conductivity type is n-type, while the second conductivity type is p-type. However, it is also possible for the first conductivity type to be p-type and the second conductivity type to be n-type. Furthermore, the first conductivity type and the second conductivity type may be the same, for example, n-type or p-type. When the first conductivity type and the second conductivity type are the same, for example, n-type, the first doping concentration may illustratively be at least 10 times greater than the second doping concentration. For example, the first doping concentration may be 10 times greater than the second doping concentration. 19 ~10 20 cm -3 and the second doping concentration may be in the range of 10 16 ~10 17 cm -3 may be in the range of

[0028] According to at least one embodiment of the power semiconductor device, a first insulating layer is disposed between the gate electrode layer and the channel layer such that the gate electrode layer is electrically isolated from each of the channel layers. The first insulating layer may include at least one of silicon dioxide and silicon nitride, or may be composed of at least one of silicon dioxide and silicon nitride. The thickness of the first insulating layer is illustratively in the range of 5 to 500 nm, and the thickness refers to the maximum extent of the first insulating layer in a direction parallel to the surface normal.

[0029] The shape of the first insulating layer portions can correspond to the shape of the side surfaces of the pillar-shaped or fin-shaped regions, each of which may have the shape of a truncated cone, a truncated pyramid, a prism, or a cylinder, as described above. The first insulating layer portions can extend directly onto the side surfaces of the plurality of pillar-shaped or fin-shaped regions, respectively, such that the plurality of first insulating layer portions cover at least a portion of the contact layer of each pillar-shaped or fin-shaped region.

[0030] According to at least one embodiment of the power semiconductor device, the channel layer is at least partially disposed in a common plane with the gate electrode layer, and the first insulating layer includes a first insulating layer portion extending to a side of the pillar-shaped or fin-shaped region. This embodiment enables the design of a MOSFET or ACCUFET power semiconductor device.

[0031] The primary difference between an accumulation-channel ACCUFET and an inversion-channel METASFET is the presence of a channel layer, or accumulation layer, below and / or adjacent to the first insulating layer. The thickness, length, and doping concentration of this accumulation layer can be carefully selected so that it is completely depleted during operation.

[0032] According to at least one embodiment, for example when the power semiconductor device has an ACCUFET design, the first and second conductivity types are the same, e.g., n-type, and the first doping concentration illustratively exceeds the second doping concentration by at least a factor of 10. For example, the first doping concentration may be at least 10. 19 ~10 20 cm -3 and the second doping concentration may be in the range of 10 16 ~10 17 cm -3 may be in the range of

[0033] According to at least one embodiment, when the power semiconductor device has a MOSFET design, the first conductivity type and the second conductivity type are different, and each pillar-shaped or fin-shaped region can include a drain layer of the first conductivity type disposed on a surface of the channel layer facing away from the contact layer. Illustratively, the drain layer comprises 4H—SiC or 6H—SiC.

[0034] The first insulating layer portion can partially or completely surround each corresponding pillar-shaped or fin-shaped region in the horizontal direction to form a plurality of vertical gate-all-around field-effect transistor cells. The gate-all-around field-effect transistor cells enable the most efficient gate control. In the context of this application, "horizontal direction" means parallel to the device plane. Here, the first insulating layer may be composed of the first insulating layer portion.

[0035] The power semiconductor device may include a second insulating layer disposed on a surface of the gate electrode layer facing away from the first main electrode. Exemplarily, the second insulating layer includes SiO2. The second insulating layer may also be a spin-on-glass (SOG) layer. The second insulating layer reduces parasitic capacitance of the gate electrode layer.

[0036] According to at least one embodiment of the power semiconductor device, for example, when the power semiconductor device has a planar MOSFET design, such as a VDMOS design, the channel layer is arranged in a plane different from that of the gate electrode layer, and the first insulating layer includes a second insulating layer portion arranged on a surface of the gate electrode layer facing the second main electrode. Furthermore, the first insulating layer may be composed of the second insulating layer portion. For example, the second insulating layer portion has a planar configuration. Here, the first and second conductivity types may be different, and a drain layer of the first conductivity type may be arranged on a surface of the channel layer facing away from the contact layer. Exemplarily, the drain layer includes 4H-SiC or 6H-SiC. Furthermore, the power semiconductor device may include only a fin region.

[0037] According to at least one embodiment, the power semiconductor device includes an intermediate insulating layer disposed between the gate electrode layer and the contact layer of each pillar-shaped or fin-shaped region, at least on a surface of the gate electrode layer facing the first main electrode. Illustratively, the intermediate insulating layer includes SiO2. The second insulating layer may be a spin-on-glass (SOG) layer.

[0038] As mentioned above, the channel layer may contain 3C-SiC, and the drain layer may contain 4H-SiC or 6H-SiC. The idea here is to combine the advantages of two SiC polytypes, i.e., 3C-SiC and 4H-SiC or 3C-SiC and 6H-SiC, to enable high-performance SiC power devices. While 4H-SiC or 6H-SiC, used for the drain layer, ensures good blocking capability due to its large bandgap, 3C-SiC is used as the channel material because channel mobility exceeding 160 cm2 / vs has been measured for 3C-SiC. In the case of SiC, near-interface traps (NITs) are an important type of interface defect that can be found inside the oxide very close to the interface in Si and SiC MOS structures. In the latter case, they are responsible for a high concentration of neutral defect states near the conduction band edge (EC-ET < 0.2 eV), as shown in Figure 2. However, the distribution and density of NITs strongly depend on the SiC polytype. The density of NITs increases nearly exponentially toward the conduction band edge for 4H-SiC or 6H-SiC, but remains relatively low for 3C-SiC. In addition, defect states in the lower half of the bandgap (near the valence band, see Figure 2) are donor-like and do not directly affect n-type carrier mobility. However, defect states near the conduction band are acceptor-like and can become negatively charged, for example, when a gate voltage is applied. As a result, electrons in the inversion channel become trapped and nearly immobile, acting as cooling scattering centers, which significantly limit n-channel mobility. Therefore, the 3C-SiC / oxide interface in power MOSFET devices exhibits a lower interface defect density (DIT) and therefore higher channel mobility compared to its 4H-SiC / oxide or 6H-SiC / oxide counterparts.

[0039] In an exemplary embodiment, the power semiconductor device comprises a carrier on which the semiconductor layer stack is disposed, which may be a substrate or substrate layer on which the semiconductor layer stack is epitaxially grown.

[0040] According to at least one embodiment, the power semiconductor device is a power device. For example, the power semiconductor device is configured to have a maximum current through the channel layer of at least 10 A or at least 50 A. Optionally, the maximum current is up to 500 A. Alternatively, or in addition, the power semiconductor device is configured to have a maximum voltage of at least 0.65 kV or at least 1.2 kV. Optionally, the maximum voltage can be up to 6.5 kV.

[0041] The power semiconductor device is for a vehicle power module that converts direct current from a battery into alternating current for an electric motor, for example in a hybrid or plug-in electric vehicle.

[0042] In one embodiment, the power semiconductor device comprises a plurality of nanowires or microwires (also called pillars) made of semiconductor material, with the accumulation channel configured within the wire such that the wire is composed only of material of the same conductivity type, such as n-type SiC.

[0043] In at least one embodiment, the power semiconductor device comprises: a first main electrode, for example a continuous metal layer; a second main electrode, for example another continuous metal layer, a semiconductor layer stack located between the first and second main electrodes, optionally in direct contact with the first and second main electrodes; a gate electrode layer located between the first main electrode and the second main electrode but electrically isolated from the first main electrode and the second main electrode; Equipped with the semiconductor layer stack comprises a plurality of pillars in contact with a first main electrode, the pillars also being referred to as nanowires or microwires; - the pillar penetrates the gate electrode layer, for example, completely penetrates the gate electrode layer, also called crossing the gate electrode layer, the entire semiconductor layer stack is of the same conductivity type, for example n-type, entirely or in the location from the first main electrode to the second main electrode along a direction perpendicular to the common plane; - each of the pillars comprises an upper region having a first doping concentration located in the first main electrode, the upper region may be in direct contact with the first main electrode; - in a surface of the upper region facing away from the first main electrode, in a common plane with the gate electrode layer, each of the pillars comprises a channel region having a second doping concentration; The first doping concentration exceeds the second doping concentration by at least 5 times, or at least 10 times, or at least 50 times, or at least 200 times.

[0044] For example, each of the pillars includes a lower region on a surface of the respective channel region facing the second main electrode, and the third doping concentration of the lower region is the first doping concentration within a tolerance of up to two times.

[0045] Thus, in the power semiconductor device described herein, for example, to realize a SiC AccuFET, i.e., an accumulation channel field effect transistor, the semiconductor layer stack grown from the first main electrode to the second main electrode along a direction perpendicular to the common plane is composed exclusively of n-type SiC, for example. The key difference between an AccuFET using an accumulation channel and a conventional metal-oxide-semiconductor FET using an inversion channel is the presence of a thin n-channel region, i.e., an accumulation layer, below and / or adjacent to the gate insulator. The thickness, length, and n-doping concentration of this accumulation layer can be carefully selected to ensure that it is fully depleted during operation.

[0046] This is the case, for example, for more highly doped n +This creates a potential barrier between the doped source and the more lightly doped n-doped drift region, resulting in a normally-off device where the entire drain voltage is supported by the n-doped drift region. Therefore, the power semiconductor device can block high forward voltages at zero gate bias with low leakage current. When a positive gate bias is applied, an electron accumulation channel is formed at the insulator-SiC interface, thus providing a low-resistance path for electron current from source to drain. This structure eliminates the effect of poor interface quality on the accumulation channel mobility by offering the possibility of moving the accumulation channel away from the insulator interface.

[0047] For example, a so-called "gate-first" integration is proposed, i.e. the gate insulator, the gate itself, which may consist of highly doped Si or at least one metal, and the gate passivation are deposited before the selective growth step using standard layer deposition and thermal oxidation techniques, for example to ensure the best possible layer quality of the gate insulator.

[0048] Thus, the power semiconductor devices described herein may be based on selectively grown SiC pillars in a semiconductor layer stack including, for example, 3C SiC and 4H SiC on a substrate made of doped or undoped Si, or a wide bandgap material such as SiC, sapphire, or GaN, and the power semiconductor devices may be of AccuFET design and may be fabricated by a self-aligned gate-first process.

[0049] According to at least one embodiment, the gate electrode layer is a continuous layer. Thus, in a top view, there may be exactly one gate electrode layer with holes in which the pillars are located. The gate electrode may therefore be limited to the space horizontally adjacent to the pillars and may not extend beyond the pillars in the direction of their growth and / or main extent, where "horizontal" refers to a direction parallel to the common plane in which the gate electrode layer is located. This does not exclude the gate electrode layer being in electrical contact with at least one gate electrode line that is not located between the pillars and may have a larger extent perpendicular to the common plane than the pillars.

[0050] According to at least one embodiment, the pillars are in contact with the first main electrode, which can therefore be fabricated directly on the pillars.

[0051] According to at least one embodiment, the common plane is perpendicular to the growth direction and / or the direction of the main extent of the pillar. Thus, the common plane may be parallel to the first main electrode and the second electrode. The common plane may be located at the center of the gate electrode layer when viewed along the height and / or the direction of the main extent of the pillar.

[0052] According to at least one embodiment, each of the channel regions of the pillars is in direct contact with a respective top region, or there may be at least one intermediate region between the assigned top region and the channel region.

[0053] According to at least one embodiment, the pillars comprise or consist of SiC, or may alternatively comprise or consist of another high bandgap compound semiconductor material such as Ga2O3 or GaN.

[0054] According to at least one embodiment, the first doping concentration is at least 5×10 15 cm -3 , or at least 1 × 10 16 cm -3, or at least 2 × 10 16 cm -3 Alternatively or additionally, the first doping concentration is at most 5×10 17 cm -3 , or up to 2×10 17 cm -3 , or up to 1×10 17 cm -3 is.

[0055] According to at least one embodiment, the second doping concentration is at least 1×10 18 cm -3 , or at least 5 × 10 18 cm -3 , or at least 1 × 10 19 cm -3 Alternatively or additionally, the second doping concentration is at most 5×10 20 cm -3 , or up to 2×10 20 cm -3 , or up to 1×10 20 cm -3 is.

[0056] According to at least one embodiment, the width of the pillars, as viewed in a cross section through and parallel to the common plane, is at least 0.05 μm, or at least 0.1 μm, or at least 0.2 μm, Alternatively or additionally, the width is at most 2 μm, or at most 1.0 μm, or at most 0.6 μm.

[0057] According to at least one embodiment, the height of the pillars, when viewed in a cross section through the common plane and perpendicular to the common plane, is at least two or at least five times the width of the pillars. Alternatively, or in addition, the height is at most 50, or at most 20, or at most 10 times the width of the pillars.

[0058] According to at least one embodiment, the density of the pillars, as viewed in a common plane top view, is at least 2×10 5 cm -2 , or at least 1 × 106 cm -2 , or at least 1 × 10 7 cm -2 Alternatively or additionally, this density can be up to 1×10 8 cm -2 , or up to 4×10 7 cm -2 , or up to 2×10 7 cm -2 is.

[0059] According to at least one embodiment, a gate insulator wall is present on the sidewall of the pillar. For example, the gate insulator wall extends all the way around the pillar. For each pillar, there may be one gate insulator wall, e.g., tubular or frustoconical. For example, the gate insulator wall is thermal silicon dioxide.

[0060] According to at least one embodiment, an upper gate insulator layer is present on the side of the gate electrode facing the first main electrode. Alternatively or additionally, a lower gate insulator layer is present on the side of the gate electrode facing the second main electrode. The upper and lower gate insulator layers can be in direct contact with the first and second main electrodes, respectively. For example, the upper and / or lower gate insulator layers can be made of silicon dioxide.

[0061] According to at least one embodiment, the upper gate insulator layer ends flush with the upper region of the pillar, e.g., with a tolerance of at most 0.3 μm or at most 0.1 μm, i.e., the faces of the upper region facing away from the first main electrode and the face of the upper gate insulator layer may be in the same or approximately the same plane parallel to a common plane.

[0062] According to at least one embodiment, each of the pillars comprises a lower region on a side of the respective channel region facing the second main electrode. The lower region may be in direct contact with the assigned channel region. Alternatively or additionally, the lower region may be in direct contact with the second main electrode.

[0063] According to at least one embodiment, the third doping concentration of the lower region is, for example, at most 5 times, or at most 2 times, or at most 1.5 times the first doping concentration, and thus the upper and lower regions can have the same or approximately the same conductivity.

[0064] According to at least one embodiment, the lower gate insulator layer ends flush with the lower region of the pillar, e.g., with a tolerance of at most 0.3 μm or at most 0.1 μm, i.e., the surface of the lower region facing the first main electrode and the surface of the lower gate insulator layer may be in the same or approximately the same plane parallel to a common plane.

[0065] According to at least one embodiment, the pillars each have the shape of a truncated cone, a truncated pyramid, a prism, or a cylinder. When the pillars are shaped like truncated cones or pyramids, the opening angle of the truncated cones or pyramids is, for example, at least 10° or at least 20° and / or at most 70°, at most 35°, or at most 25°. This opening angle is determined, for example, in a plane perpendicular to the common plane and passing through the central axis of each pillar. The truncated cones or pyramids are truncated cones or pyramids. The truncated cones or pyramids do not necessarily have to be cut perpendicular to the axis of the cone or pyramid; oblique cuts are also possible. Furthermore, the base of each cone or pyramid does not necessarily have to be in a plane perpendicular to the axis of the cone or pyramid, but may be arranged in an oblique manner.

[0066] According to at least one embodiment, the pillar also contacts the second main electrode, thus extending from the first main electrode to the second main electrode, thereby allowing the semiconductor layer stack to be comprised of multiple pillars.

[0067] According to at least one embodiment, the semiconductor layer stack further comprises one or more base layers. For example, at least one base layer is a continuous layer. The at least one base layer is located on a surface of the pillar facing away from the first main electrode. The at least one base layer can be disposed parallel to the common plane.

[0068] According to at least one embodiment, all pillars are in contact with at least a base layer. For example, at least one base layer is a growth base for the pillars. The at least one base layer can comprise a substrate or can be a substrate of a semiconductor layer stack.

[0069] According to at least one embodiment, the pillars and the at least one base layer comprise different semiconductor materials and / or different crystal structures, for example, the base layer is made of 4H n-type SiC and the pillars are made of 3C n-type SiC.

[0070] According to at least one embodiment, the base layer comprises a superjunction structure. That is, adjacent columns of n-type and p-type semiconductor material can be present in the base layer. These columns can be separated from each other by tubes of insulating material, such as oxide or nitride, e.g., silicon dioxide. The tubes can have very thin walls, e.g., with a wall thickness of up to 50 nm, up to 20 nm, or up to 10 nm. However, pillars that cross or penetrate the gate electrode layer still have a single conductivity type. If a superjunction structure is not present, the entire semiconductor layer stack consists of only one conductivity type.

[0071] The footprint of the tube may be, for example, square or circular or polygonal or elliptical. According to at least one embodiment, the power semiconductor device is or is included in a field effect transistor (FET for short), or may be part of an insulated gate bipolar transistor (IGBT), which may further comprise an additional semiconductor layer stack as a collector region.

[0072] For example, a gate insulator wall is present on the sidewall of the pillar around the entire periphery of the pillar, an upper gate insulator layer is present on the surface of the gate electrode facing the first main electrode, and a lower gate insulator layer is present on the surface of the gate electrode facing the second main electrode, and the gate insulator wall is made of thermal oxide.

[0073] For example, the lower gate insulator layer ends flush with the lower region of the pillar. For example, the pillar contacts the second main electrode such that the pillar extends from the first main electrode to the second main electrode.

[0074] For example, the semiconductor layer stack (3) further comprises a base layer that is a continuous layer, the base layer being located parallel to a common plane on the surfaces of the pillars facing away from the first main electrode, all of the pillars being in contact with the base layer, and the pillars and the base layer comprising at least one of different semiconductor materials and different crystal structures.

[0075] For example, the base layer comprises a superjunction structure and / or the power semiconductor device is a field effect transistor.

[0076] There is also provided a method for manufacturing a power semiconductor device, by which, for example, a power semiconductor device is manufactured as set forth in relation to at least one of the above-described embodiments, and therefore, features of the power semiconductor device are also disclosed for the method, and vice versa.

[0077] In at least one embodiment, a method for manufacturing a power semiconductor device includes: A) Preparing a substrate; B) providing a semiconductor mask for a pillar or fin of a semiconductor layer stack on a substrate; C) forming a tube or forming plate of insulating material on the sidewall of the semiconductor mask; D) growing a semiconductor layer stack including SiC in or around the tube or forming plate; Including, The tube or forming plate remains within the completed power semiconductor device.

[0078] In at least one embodiment, a method for manufacturing a power semiconductor device comprises the following steps: A) providing a semiconductor substrate; B) providing a semiconductor mask for the pillars of the semiconductor layer stack on the semiconductor substrate; C) forming a tube of insulating material on the sidewall of the semiconductor mask; D) growing pillars, for example comprising SiC, in or around the tube; for example, in the order listed above, The tube remains in the completed power semiconductor device.

[0079] Instead of a semiconductor mask, an oxide mask or a nitride mask may be used. One challenge of power semiconductor devices described herein, such as the low-voltage class of power SiC MOSFETs, is low inversion channel mobility and therefore low on-resistance. Improving channel mobility is key to improving switching and conduction losses, especially for devices that can be used in electric and hybrid electric vehicles.

[0080] In the power semiconductor device described herein, for example, a vertical SiC power MOSFET design is proposed using a selectively grown SiC tube. + 4H SiC substrate and epitaxial n -While n-type 4H SiC can be used as the drift layer, selectively grown n-type 3C SiC, which exhibits high carrier mobility, will be used for the channel and source regions. This concept therefore combines the advantages of the two SiC polytypes, i.e., 3C SiC and 4H SiC, to enable power semiconductor devices such as high-performance SiC power MOSFETs for low-voltage applications.

[0081] This method allows for the fabrication of improved superjunction structures (abbreviated as SJ structures). While in conventional superjunction structures, n-type and p-type doped semiconductor regions are in direct contact, in the method described herein, the superjunction structure can instead be formed by a thin insulator layer, such as an oxide, between the doped semiconductors, where "thin" means, for example, at least 1 nm and / or at most 10 nm thick.

[0082] An additional advantage is the two-step selective epitaxial growth of in-situ doped superjunctions with layer thicknesses exceeding 10 μm, since this insulator layer can be used as a growth mask material for selective epitaxy. Furthermore, when patterned stripes, hexagons, squares, or other growth masks are used, the density of defects due to lattice mismatch or the substrate itself can be significantly reduced by defect trapping along the semiconductor / insulator interface, also known as aspect ratio trapping. Therefore, crystal defects do not propagate into the superjunction structure itself, and high channel carrier mobility can be achieved.

[0083] According to at least one embodiment, method step B) comprises the following substeps: B1) growing a continuous or already structured starting layer; B2) optionally structuring the successive starting layers so as to provide a positive semiconductor mask of pillars; Includes:

[0084] According to at least one embodiment, the semiconductor mask is completely removed after step C) and before step D), i.e., the mask is not present when growing the pillars and therefore is not present in the finished device.

[0085] According to at least one embodiment, in step D), pillars are selectively grown within the tubes, with the spaces between adjacent tubes being free of solid material. Thus, pillars can be grown at all locations on the substrate where tube material is not present. Thus, pillar growth is limited to and follows the tubes.

[0086] According to at least one embodiment, the method comprises: E) Fabricating a gate electrode layer between the pillars Step E) can be performed after step D) or before step D).

[0087] According to at least one embodiment, in method step B), the semiconductor mask is provided as a negative of the pillars, After step C), the spaces between adjacent tubes are filled with at least one filler material or at least one further semiconductor material in step C1). For example, the semiconductor mask can be removed between step C1) and step D). In this case, the semiconductor mask can be completely removed after step C) and before step D).

[0088] According to at least one embodiment, the semiconductor substrate is a Si substrate, or alternatively, the semiconductor substrate is made of SiC, GaN, or sapphire.

[0089] According to at least one embodiment, the semiconductor substrate is removed after step D). Thus, the semiconductor substrate is not present in the finished power semiconductor device. Alternatively, the semiconductor substrate may be part of the semiconductor layer stack and thus an integral part of the finished power semiconductor device.

[0090] In at least one embodiment, a method for manufacturing a power semiconductor device according to any one of the preceding embodiments comprises the steps of: - providing a substrate; - forming a sacrificial layer on a first major surface of a substrate; - structuring the sacrificial layer to form a plurality of sacrificial structures protruding from the first main surface and having the shape of pillars or fins; - forming an insulating material layer over at least one, illustratively each, of the plurality of sacrificial structures and the first major surface, at least a portion of which forms a first insulating layer within the power semiconductor device; - removing at least one, illustratively each, sacrificial structure to form at least one cavity, illustratively a plurality of cavities, in the insulating material layer; - forming a gate electrode layer over one or more second portions of the layer of insulating material that form at least one second insulating layer portion in the power semiconductor device; - selectively forming a semiconductor layer of a first conductivity type on the first major surface and forming a contact layer in at least one, illustratively each, cavity extending to a surface of the gate electrode layer facing away from the substrate; - forming a first main electrode on a surface of the semiconductor layer stack facing away from the substrate; - forming a second main electrode on a surface of the semiconductor layer stack facing away from the first main electrode; Includes:

[0091] For example, US Patent Application Publication No. 2011 / 0124169 refers to a method for selectively depositing an epitaxial layer.

[0092] Compared with the manufacturing method of SiC-based trench power MOSFET, the above-mentioned method does not require the step of etching deep trenches in SiC, which facilitates manufacturing in view of the difficulty of forming deep trenches in SiC by etching.

[0093] In an exemplary embodiment, the sacrificial layer comprises amorphous silicon. Each sacrificial structure may have a vertical extension in a vertical direction perpendicular to the first major surface in the range of 50 nm to 10 μm, illustratively in the range of 5 to 10 μm.

[0094] In an exemplary embodiment, the insulating material layer is formed by thermal oxidation of a sacrificial structure, which provides good properties for the gate insulating layer and allows the insulating material layer to be formed of a very stable oxide material with good mechanical properties, which favors its use as a gate dielectric.

[0095] The process of removing portions of the insulating material layer may include masking and etching techniques.

[0096] According to at least one embodiment, the method includes forming a semiconductor layer of a first conductivity type that is provided to form a contact layer after the fabrication of a gate electrode layer. This refers to so-called "gate-first" integration, in which the gate electrode layer and further layers, such as a second insulating layer and an intermediate insulating layer, are deposited before the selective formation / growth of the pillar- or fin-shaped region. However, it is also possible to selectively grow the pillar- or fin-shaped region before the fabrication of the gate electrode layer and possibly the second insulating layer and the intermediate insulating layer.

[0097] According to at least one embodiment, the method includes selectively forming a semiconductor layer of a second conductivity type between the contact layer and the substrate on the first major surface in each cavity to form a channel layer, which embodiment is suitable for implementing a MOSFET or ACCUFET design for a power semiconductor device.

[0098] According to at least one embodiment, the method includes selectively forming a semiconductor layer of a first conductivity type between the channel layer and the substrate on the first major surface within each cavity to form a drain layer, which embodiment is suitable for implementing a MOSFET design for a power semiconductor device.

[0099] In an exemplary embodiment, the formation of the first conductivity type semiconductor layers for forming the contact layer is each performed at a temperature less than 1400°C. Temperatures above 1400°C can damage insulating material layers used as gate dielectrics in power semiconductor devices. For example, silicon oxide materials are damaged at temperatures above 1400°C. The formation of other semiconductor layers of the semiconductor layer stack may also each be performed at temperatures less than 1400°C.

[0100] In an exemplary embodiment, the method includes forming a second insulating layer on the insulating material layer before forming the gate electrode layer, such that after forming the gate electrode layer, the second insulating layer is sandwiched between the insulating material layer and the gate electrode layer in a vertical direction perpendicular to the first major surface. Illustratively, the second insulating layer is a spin-on-glass (SOG) layer.

[0101] The above-described method is suitable for manufacturing the power semiconductor devices described herein, and therefore features described in relation to the power semiconductor devices also apply to the method, and vice versa.

[0102] The power semiconductor devices and methods described herein will be explained in more detail below by way of exemplary embodiments with reference to the drawings. Identical elements in different figures are designated by the same reference numerals. However, the relationships between elements are not shown to scale, and rather individual elements may be exaggerated to aid understanding.

[0103] In the drawings [Brief explanation of the drawings]

[0104] [Figure 1] Demonstrates the performance of state-of-the-art 4H-SiC power MOSFETs. [Figure 2] The distribution of interface states within the band gap of various SiC polytypes is shown. [Figure 3A] 1 shows a schematic perspective view of a first exemplary embodiment of a power semiconductor device; [Figure 3B] 1 shows a schematic cross-sectional view of a first exemplary embodiment of a power semiconductor device; [Figure 3C] 1 shows a schematic perspective view of a first exemplary embodiment of a power semiconductor device; [Figure 3D] 1 shows a schematic perspective view of a first exemplary embodiment of a power semiconductor device; [Figure 3E] 1 shows a top view of a first exemplary embodiment of a power semiconductor device; [Figure 3F] 1 shows a schematic cross-sectional view of a first exemplary embodiment of a power semiconductor device; [Figure 4A] 1 shows a schematic perspective view of a second exemplary embodiment of a power semiconductor device; [Figure 4B] 3 shows a schematic cross-sectional view of a second exemplary embodiment of a power semiconductor device. [Figure 4C] 1 shows a schematic perspective view of a second exemplary embodiment of a power semiconductor device; [Figure 4D] 1 shows a schematic perspective view of a second exemplary embodiment of a power semiconductor device; [Figure 5] 4 shows a schematic cross-sectional view of a third exemplary embodiment of a power semiconductor device. [Figure 6A] 10 shows a schematic cross-sectional view of a fourth exemplary embodiment of a power semiconductor device. [Figure 6B] 10 shows a schematic cross-sectional view of a fourth exemplary embodiment of a power semiconductor device. [Figure 7A]1 illustrates a method for manufacturing a semiconductor power device according to one of the first to third exemplary embodiments. [Figure 7B] 1 illustrates a method for manufacturing a semiconductor power device according to one of the first to third exemplary embodiments. [Figure 7C] 1 illustrates a method for manufacturing a semiconductor power device according to one of the first to third exemplary embodiments. [Figure 7D] 1 illustrates a method for manufacturing a semiconductor power device according to one of the first to third exemplary embodiments. [Figure 7E] 1 illustrates a method for manufacturing a semiconductor power device according to one of the first to third exemplary embodiments. [Figure 7F] 1 illustrates a method for manufacturing a semiconductor power device according to one of the first to third exemplary embodiments. [Figure 8A] 10 illustrates a method for manufacturing a semiconductor power device according to a fourth exemplary embodiment. [Figure 8B] 10 illustrates a method for manufacturing a semiconductor power device according to a fourth exemplary embodiment. [Figure 8C] 10 illustrates a method for manufacturing a semiconductor power device according to a fourth exemplary embodiment. [Figure 8D] 10 illustrates a method for manufacturing a semiconductor power device according to a fourth exemplary embodiment. [Figure 8E] 10 illustrates a method for manufacturing a semiconductor power device according to a fourth exemplary embodiment. [Figure 9] 1 is a schematic perspective view of an exemplary embodiment of a power semiconductor device described herein; [Figure 10] FIG. 10 is a schematic cross-sectional view of the power semiconductor device of FIG. [Figure 11] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device described herein. [Figure 12]1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device described herein. [Figure 13] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device described herein. [Figure 14] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device described herein. [Figure 15] 1A-1C are schematic cross-sectional views of method steps of an exemplary embodiment of a method for manufacturing a power semiconductor device as described herein. [Figure 16] 1A-1C are schematic cross-sectional views of method steps of an exemplary embodiment of a method for manufacturing a power semiconductor device as described herein. [Figure 17] 1A-1C are schematic cross-sectional views of method steps of an exemplary embodiment of a method for manufacturing a power semiconductor device as described herein. [Figure 18] 1A-1D are schematic cross-sectional views of method steps of an exemplary embodiment of a method for manufacturing a power semiconductor device as described herein. [Figure 19] 1A-1D are schematic cross-sectional views of method steps of an exemplary embodiment of a method for manufacturing a power semiconductor device as described herein. [Figure 20] 1A-1C are schematic cross-sectional views of method steps of an exemplary embodiment of a method for manufacturing a power semiconductor device as described herein. [Figure 21] 1A-1D are schematic cross-sectional views of method steps of an exemplary embodiment of a method for manufacturing a power semiconductor device as described herein. [Figure 22] 1A-1D are schematic cross-sectional views of method steps of an exemplary embodiment of a method for manufacturing a power semiconductor device as described herein. [Figure 23] 1A-1D are schematic cross-sectional views of method steps of an exemplary embodiment of a method for manufacturing a power semiconductor device as described herein. [Figure 24] 1A-1D are schematic cross-sectional views of method steps of an exemplary embodiment of a method for manufacturing a power semiconductor device as described herein. [Figure 25]1A-1D are schematic cross-sectional views of method steps of an exemplary embodiment of a method for manufacturing a power semiconductor device as described herein. [Figure 26] 1A-1D are schematic cross-sectional views of method steps of an exemplary embodiment of a method for manufacturing a power semiconductor device as described herein. [Figure 27] 1A-1D are schematic cross-sectional views of method steps of an exemplary embodiment of a method for manufacturing a power semiconductor device as described herein. [Figure 28] 1 is a schematic perspective view of an exemplary embodiment of a power semiconductor device described herein; [Figure 29] FIG. 29 is a schematic top view of the power semiconductor device of FIG. 28. [Figure 30] FIG. 29 is a schematic top view of another exemplary embodiment of the power semiconductor device of FIG. 28. [Figure 31] 1 is a schematic perspective view of an exemplary embodiment of a power semiconductor device described herein; [Figure 32] FIG. 32 is a schematic top view of the power semiconductor device of FIG. 31. DETAILED DESCRIPTION OF THE INVENTION

[0105] 3A to 3F show various schematic views of a first exemplary embodiment of the power semiconductor device 1, where FIG. 3B is a cross-sectional view taken along the plane A-A' shown in FIG. 3C and FIG. 3F is a cross-sectional view taken along the plane B-B' shown in FIG. 3D.

[0106] The power semiconductor device 1 according to the first exemplary embodiment has a rectangular parallelepiped shape defined by a first horizontal extension w along a first horizontal extension direction L1, a second horizontal extension l along a second horizontal extension direction L2 perpendicular to the first horizontal extension direction L1, and a vertical extension h in a vertical direction V perpendicular to the device plane D in which the first horizontal extension direction L1 and the second horizontal extension direction L2 extend (see FIG. 3A).

[0107] The power semiconductor device 1 comprises a first main electrode 3, a second main electrode 4, and a semiconductor layer stack 2 located between and in electrical contact with the first and second main electrodes 3, 4 (see FIGS. 3A and 3B). The semiconductor layer stack 2 is sandwiched between the first and second main electrodes 3, 4 in a vertical direction V. "In electrical contact" means that during operation, e.g., in the on-state of the power semiconductor device 1, a current flows through the semiconductor layer stack 2 between the first and second main electrodes 3, 4. The first and second main electrodes 3, 4 are, for example, metal electrodes. The first main electrode 3 may be a source electrode, and the second main electrode 4 may be a drain electrode. The power semiconductor device 1 has a MOSFET design.

[0108] As becomes apparent from Figure 3B, the semiconductor layer stack 2 comprises differently doped semiconductor layers 13, 14, 15 stacked in a vertical direction V, where semiconductor layer 15 is highly n-doped and has a first doping concentration, semiconductor layer 14 is highly p-doped and has a second doping concentration, and semiconductor layer 13 is n-doped and has a third doping concentration that is lower than the doping concentration of semiconductor layer 15. For example, the first doping concentration may exemplarily be at least 10 times greater than the third doping concentration. For example, the first doping concentration may be 10 19 ~10 20 cm -3 and the third doping concentration may be in the range of 10 16 ~10 17 cm -3 Furthermore, the second doping concentration may be in the range of 10 16 ~10 18 cm -3 may be in the range of

[0109] Each of the semiconductor layers 13, 14, and 15 is a discontinuous layer. Semiconductor layer stack 2 is silicon carbide-based, i.e., at least one of semiconductor layers 13, 14, 15 of semiconductor layer stack 2 comprises or consists of SiC. Semiconductor layers 13, 14, 15 may be of any SiC polytype. Layers 13, 14, 15 may be of different SiC polytypes or the same SiC polytype. In an exemplary embodiment, layer 15 and layer 14 may each comprise 3C—SiC, while layer 13 may comprise 4H—SiC or 6H—SiC.

[0110] The power semiconductor device 1 comprises a gate electrode layer 5 between a first main electrode 3 and a second main electrode 4, where "between" means sandwiched in the vertical direction V (see FIG. 3B). The gate electrode layer 5 may be a highly doped Si layer or a metal layer, for example a layer of Al.

[0111] The power semiconductor device 1 includes a first insulating layer 6 having a plurality of first insulating layer portions 6A that cross the gate electrode layer 5. The first insulating layer 6 includes at least one of silicon dioxide and silicon nitride, or is made of at least one of silicon dioxide and silicon nitride. Illustratively, the first insulating layer 6 is a thermal oxide layer. Illustratively, the layer thickness d of the first insulating layer 6 is in the range of 5 to 500 nm, and the layer thickness d refers to the maximum extent of the first insulating layer 6 in a direction parallel to the surface normal.

[0112] 3C and 3D , the semiconductor layer stack 2 includes a plurality of pillar-shaped regions 20 that cross the gate electrode layer 5. Each of the pillar-shaped regions 20 includes a contact layer 21 that has a first doping concentration and a first conductivity type and is disposed on the first main electrode 3. Each of the contact layers 21 is part of the semiconductor layer 15 and therefore has the same qualities as those described in relation to the semiconductor layer 15. For example, the contact layer 21 functions as a source layer of the power semiconductor device 1. Furthermore, each of the plurality of pillar-shaped regions 20 includes a portion of the semiconductor layer 14 and a portion of the semiconductor layer 13. The portion of the semiconductor layer 14 is a channel layer 22 of the power semiconductor device 1, and the portion of the semiconductor layer 13 is a drain layer 23. The channel layer 22 is disposed in a common plane with the gate electrode layer 5.

[0113] The pillar-like regions 20 may have a vertical extension h that is greater than a horizontal extension w. Illustratively, the vertical extension h may be at least two or three times greater than the horizontal extension w.

[0114] 3D, multiple pillar-shaped regions 20 may be arranged in a matrix. The number of pillar-shaped regions 20 is not limited to the number shown in the figure and may be more or less than this number.

[0115] Each contact layer 21 extends to a surface 5A of the gate electrode layer 5 facing the first main electrode 3. As becomes clear from Figure 3B, the contact layers 21 of adjacent pillar-shaped regions 20 are arranged continuously on the surface of the gate electrode layer 5 facing the first main electrode 3. The continuously arranged contact layers 21 enable a substantially flat surface of the semiconductor layer stack 2 facing the first main electrode 3, facilitating the application of the first main electrode 3.

[0116] The overlap region 18 where the contact layers 21 of adjacent pillar-shaped regions 20 meet on the surface 5A of the gate electrode layer 5 facing the first main electrode 3 may contain defects in the semiconductor material that can be detected, for example, by TEM ("transmission electron microscopy").

[0117] 3F, the contact layer 21 comprises a first portion 21A extending to the surface 5A of the gate electrode layer 5 facing the first main electrode 3, and a second portion 21B arranged in the cavity 16 of the first insulating layer portion 6A, which may be tubular. If the contact layer 21 does not extend horizontally beyond the cavity 16, the contact area of ​​the contact layer 21 is defined by the horizontal extension w of the cavity 16, which is less than 2 μm, illustratively less than 1 μm. However, by extending the contact layer 21 horizontally to the surface 5A of the gate electrode layer 5 facing the first main electrode 3, the contact area 21C is defined by the horizontal dimension w of the second portion 21B, resulting in an increase of the contact area 21C by at least a factor of two and therefore in a decrease in the source resistance R S The contact area 21C is 10 mm 2 ~20mm 2 The layer thickness d of the first portion 21A of the contact layer 21 may be several hundred nanometers, for example, 100 nm to 500 nm.

[0118] The first insulating layer portions 6A extend in direct contact with the side surfaces 20A of the pillar-shaped regions 20. The first insulating layer portions 6A horizontally cover and surround the drain layer 23, the channel layer 22, and the first portions 21A of the contact layer 21. The gate electrode layer 5 is a continuous layer that horizontally surrounds each pillar-shaped region 20.

[0119] A second insulating layer 19 is sandwiched between the second main electrode 4 and the gate electrode layer 5 in the vertical direction V. The second insulating layer 19 separates the gate electrode layer 5 from the second main electrode 4 and minimizes the parasitic capacitance of the gate electrode layer 5. The second insulating layer 19 may be any electrically insulating material. For example, it may be a spin-on-glass (SOG) layer.

[0120] In the first exemplary embodiment, each transistor cell 24 comprises one of the plurality of pillar-shaped regions 20, one of the plurality of first insulating layer portions 6A, and a portion of the gate electrode layer 5, as described above, to form a vertical gate-all-around field effect transistor cell.

[0121] 3B and 3F, the power semiconductor device 1 includes an intermediate insulating layer 25 disposed on the gate electrode layer 5, and the first main electrode 3 is disposed on the intermediate insulating layer 25. The first main electrode 3 is separated and electrically insulated from the gate electrode layer 5 by the intermediate insulating layer 25.

[0122] 3E, the upper part of the first main electrode 3 is a source contact pad 3A, which functions as a source terminal of the power semiconductor device 1. Alternatively, the source contact pad 3A may be realized as a separate element electrically connected to the first main electrode 3. The gate electrode layer 5 extending below the first main electrode 3 is electrically connected to a control contact pad 5B, which functions as a gate terminal of the power semiconductor device 1. In the first exemplary embodiment, the control contact pad 5B is arranged laterally of the source contact pad 3A. This means that the contact layer 21 is connected to the source contact pad 3A from above, while the gate electrode layer 5 is connected to the control contact pad 5B from the side of the power semiconductor device 1. That is, in the orthogonal projection onto the device plane D, the source contact pad 3A overlaps the plurality of transistor cells 24, while the control contact pad 5B is arranged laterally of the plurality of transistor cells 24.

[0123] The power semiconductor device 1 according to the first exemplary embodiment does not have a carrier. A second exemplary embodiment of the power semiconductor device 1 is shown in FIGS. 4A-4D, with FIG. 4B being a cross-sectional view taken along the plane A-A' shown in FIG. 4C.

[0124] The second exemplary embodiment is similar to the first exemplary embodiment described in relation to FIGS. 3A to 3F. Therefore, the above description also applies to the second exemplary embodiment. A difference exists in that the power semiconductor device 1 according to the second exemplary embodiment comprises a first substrate layer 9 between the pillar-shaped region 20 and the second main electrode 4. The first substrate layer 9 may be formed of the same material as the semiconductor layer 13. The first substrate layer 9 may play a role in growing the semiconductor layer stack 2 in the manufacturing process. The first substrate layer 9 may also function as a drift layer of the power semiconductor device 1.

[0125] Figure 5 shows a cross-sectional view of a third exemplary embodiment of the power semiconductor device 1. The second exemplary embodiment has similarities with the first exemplary embodiment described in relation to Figures 3A to 3F. Therefore, the above description also applies to the third exemplary embodiment.

[0126] The difference is that each pillar-shaped region 20 of the power semiconductor device 1 according to the third exemplary embodiment comprises a channel layer 22 having a second conductivity type that is the same as the first conductivity type, for example, n-type. Thus, the pillar-shaped region 20 and the semiconductor layer stack 2 are of only one conductivity type. For example, the semiconductor layer stack 2 consists of n-doped 3C SiC. The power semiconductor device 1 is designed as an ACCUFET device.

[0127] The contact layer 21 is, for example, 10 19 ~10 20 cm -3 In comparison, the channel layer 22 is heavily n-doped with a first doping concentration of, for example, 10 16 ~10 17 cm -3 is weakly doped with a lower second doping concentration of .

[0128] 6A and 6B show various schematic views of a transistor cell 24 of a fourth exemplary embodiment of a power semiconductor device, with FIG. 6A being a cross-sectional view taken along the plane A-A' shown in FIG. 6B.

[0129] The power semiconductor device includes a first main electrode 3, a second main electrode 4, and a semiconductor layer stack 2 located between the first main electrode 3 and the second main electrode 4 and electrically contacting the first main electrode 3 and the second main electrode 4. The first main electrode 3 includes a first portion 3B arranged parallel to the second main electrode 3 and a second portion 3C arranged diagonally, e.g., perpendicularly, to the first portion 3B. When manufacturing the power semiconductor device, an insulating material layer 17 used to form the first insulating layer 6 can be formed by a first portion 17A and a second portion 17B (see FIG. 8B). The first portion 17A can be removed, and the second portion 3C of the first main electrode 3 can be generated in the void of the removed first portion 17A (see FIG. 8E).

[0130] The power semiconductor device further comprises a gate electrode layer 5 sandwiched in the vertical direction V between the first portion 3B of the first main electrode 3 and the second main electrode 4.

[0131] The power semiconductor device also includes a first insulating layer 6 made up of a plurality of second insulating layer portions 6B arranged on a surface of the gate electrode layer 5 facing the second main electrode 4. The second insulating layer portions 6B have a planar configuration.

[0132] The power semiconductor device is a planar MOSFET and has a vertical double-diffused metal-oxide-semiconductor (VDMOS) design.

[0133] The semiconductor layer stack 2 comprises differently doped semiconductor layers 15A, 15B, 14A, 14B, and 13, where layers 15A, 15B, and 13 are of the same first conductivity type, e.g., n-type, and the doping concentration of layer 15A is higher than the doping concentration of layer 15B. Furthermore, layers 14A and 14B are of the same second conductivity type, e.g., p-type, and the doping concentration of layer 14A is lower than the doping concentration of layer 14B. Layers 14B and 15B are arranged adjacent to each other in a plane parallel to the device plane D. For example, semiconductor layer 15A is n ++ -SiC layer, and the semiconductor layer 15B is n+ -SiC layer, and the semiconductor layer 14B is p + The semiconductor layer 14A is a p-SiC layer, and the semiconductor layer 13 is an n-SiC layer.

[0134] The power semiconductor device comprises a plurality of fin-like regions 20 across the gate electrode layer 5, each of which comprises a contact layer 21 disposed on the first main electrode 3, and each of which contact layer 21 extends to a surface 5A of the gate electrode layer 5 facing the first main electrode 3. The fin-like region 20 may be composed of the contact layer 21.

[0135] Each contact layer 21 is part of semiconductor layer 15A and therefore has the same qualities as those described in relation to semiconductor layer 15A. Each contact layer 21 is disposed on a portion of semiconductor layer 15B, which together with contact layer 21 forms a source layer.

[0136] Furthermore, a channel layer 22 is assigned to one fin-shaped region 20 and is disposed on the surface of the contact layer 21 facing away from the first main electrode 3. The channel layer 22 includes a portion of the semiconductor layer 14A and a portion of the semiconductor layer 14B, with the portion of the semiconductor layer 14B being disposed between the second portion 3C of the first main electrode 3 and the portion of the semiconductor layer 14A. Two adjacent channel layers 22 are separated in the horizontal direction by a ridge region 13A of the semiconductor layer 13, which forms a common drain layer for all transistor cells 24. The channel layer 22 is disposed in a plane different from the plane of the gate electrode layer 5. The drain layer 13 is disposed on the surface of the channel layer 22 facing away from the contact layer 21. Exemplarily, the drain layer includes 4H—SiC or 6H—SiC. A first insulating layer 6 is disposed between the gate electrode layer 5 and the channel layer 22 so that the gate electrode layer 5 is electrically isolated from each of the channel layers 22.

[0137] A method for manufacturing the power semiconductor device 1 according to any one of the first to third exemplary embodiments will be described with reference to FIGS. 7A to 7F.

[0138] The method includes providing a substrate 8 comprising a first substrate layer 9 and a second substrate layer 10. The first substrate layer 9 can be deposited on the second substrate layer 10, for example, by a chemical vapor deposition (CVD) process. Alternatively, a two-layer structure of the substrate 8 can be formed by implanting an n-type preliminary substrate with n-type dopants to form the first substrate layer 9 and the second substrate layer 10 with different doping concentrations. For example, the second substrate layer 10 can be formed from n-type 4H—SiC. + The first substrate layer 10 may be an n-layer of 4H—SiC.

[0139] The method further includes forming a sacrificial layer 11 on the first main surface 8A of the substrate 8 and structuring the sacrificial layer 11 to form a plurality of sacrificial structures 12 protruding from the first main surface 8A and having the shape of pillars or fins (see FIG. 7B). The sacrificial layer 11 may be a polysilicon (poly-Si) layer or an amorphous silicon layer. Illustratively, each sacrificial structure 12 has a vertical extension h in a vertical direction V perpendicular to the first main surface 8A in the range of 50 nm to 10 μm, illustratively in the range of 5 μm to 10 μm (see FIG. 7B).

[0140] The method further includes forming an insulating material layer 17 on the plurality of sacrificial structures 12 and the first major surface 8A, the insulating material layer 17 including a first portion 17A for forming a first insulating layer portion 6A in the power semiconductor device and a second portion 17B for forming a second insulating layer portion 6B in the power semiconductor device (see FIG. 7C ). The insulating material layer 17 may be a thermal oxide layer formed by thermal oxidation of the sacrificial structures 12 and exposed portions of the first substrate layer 9. Alternatively, the insulating material layer 17 may be formed by a deposition process such as plasma-enhanced CVD (PE-CVD) or other suitable deposition process. Illustratively, the insulating material layer 17 is a silicon oxide or silicon nitride layer.

[0141] The method further includes removing the sacrificial structure 12 to form a plurality of cavities 16 in the insulating material layer 17 (see FIG. 7D). The sacrificial structure 12 may be removed by selective etching.

[0142] The method further includes forming a gate electrode layer 5 on a second portion 17B of the insulating material layer 17, which forms the second insulating layer portion 6B of the insulating layer 6 in the power semiconductor device. Prior to forming the gate electrode layer 5, a second insulating layer 19 may be formed on the portion of the insulating material layer 17 that forms the at least one second insulating layer portion 6B of the insulating layer 6. Furthermore, an intermediate insulating layer 25 may be formed on a surface of the gate electrode layer 5 facing away from the substrate 8 (see FIG. 7E).

[0143] Furthermore, a semiconductor layer stack 2 is formed, which includes selectively forming a semiconductor layer 15 of a first conductivity type on the first main surface 8A and forming a contact layer 21 in each cavity 16 so as to extend to a surface of the gate electrode layer 5 facing away from the substrate 8 (see FIG. 7F). In a "gate-first" integration scheme, the formation of the semiconductor layer stack 2 is performed after the formation of the gate electrode layer 5.

[0144] Forming the semiconductor layer stack 2 further includes selectively forming a semiconductor layer 14 of a second conductivity type between the contact layer 21 and the substrate 8 on the first major surface 8A within each cavity 16 to form a channel layer 22.

[0145] Forming the semiconductor layer stack 2 for manufacturing the semiconductor power device according to the first and second exemplary embodiments further includes selectively forming a semiconductor layer 13 of the first conductivity type between the channel layer 22 and the substrate 8 on the first major surface 8A within each cavity 16 to form a drain layer 23.

[0146] Furthermore, a first main electrode 3 can be formed on a surface of the semiconductor layer stack 2 facing away from the substrate 8. Also, a second main electrode 4 can be formed (not shown) on a surface of the semiconductor layer stack 2 facing away from the first main electrode 3. Before forming the second main electrode 4, the substrate 8 and at least one second portion 17B of the insulating material layer 17, as well as a portion of the semiconductor layer stack 2 horizontally surrounded by the second portion 17B, can be removed.

[0147] A second exemplary embodiment of a method for manufacturing a power semiconductor device 1 will be described in relation to Figures 8A to 8E, but the method is also suitable for manufacturing a power semiconductor device according to a fourth exemplary embodiment.

[0148] 8A, the method includes providing a substrate 8, which comprises a first substrate layer 9 and a second substrate layer 10, where the first substrate layer 9 comprises semiconductor layers 15B, 14A, 14B, and 13 of the semiconductor layer stack 2.

[0149] The method further includes forming a sacrificial layer on the first main surface 8A of the substrate 8 and structuring the sacrificial layer to form a plurality of sacrificial structures (e.g., as shown in FIG. 7B ) protruding from the first main surface 8A and having the shape of fins. Further, an insulating material layer (e.g., as shown in FIG. 7C ) is formed on the plurality of sacrificial structures and on the first main surface 8A, at least a portion of which forms a first insulating layer of the power semiconductor device 1. Then, each sacrificial structure is removed to form a plurality of cavities 16 in the insulating material layer (see FIG. 8B ).

[0150] The method further includes forming a gate electrode layer 5 on a second portion 17B of the insulating material layer 17, which forms a second insulating layer portion 6B of the insulating layer 6 in the power semiconductor device (see FIG. 8E). An intermediate insulating layer 25 is formed over the gate electrode layer 5, covering a surface of the gate electrode layer 5 facing away from the substrate 8 and a side surface of the gate electrode layer 5. Before forming the intermediate insulating layer 25, the first portion 17A of the insulating material layer 17 adjacent to the second portion 17B of the insulating material layer 17 may be removed.

[0151] The method further includes selectively forming a semiconductor layer 15A of a first conductivity type on the first major surface 8A and forming a contact layer 21 in each cavity 16 to extend to the surface 5A of the gate electrode layer 5 facing away from the substrate 8 (see Figure 8D).

[0152] The method further includes forming a first portion 3B of the first main electrode 3 on the surface of the semiconductor layer stack 2 facing away from the substrate 8 (see FIG. 8E). Then, a second portion 3C of the first main electrode 3 is formed in the void space formed by removing the first portion 17A of the insulating material layer 17 adjacent to the contact layer 21.

[0153] The method further includes forming a second main electrode 4 on the side of the semiconductor layer stack 2 facing away from the first main electrode 3 (see FIG. 8E). Before forming the second main electrode 4, the second substrate layer 10 may be removed.

[0154] 9 and 10 show another exemplary embodiment of the power semiconductor device 1. The power semiconductor device 1 comprises a first main electrode 921 on a first main surface 911 and a second main electrode 922 on a second main surface 912. The first and second main electrodes 921, 922 are, for example, metal electrodes.

[0155] Between the first and second main electrodes 921, 922 is a semiconductor layer stack 93 consisting of a plurality of pillars 930. Thus, the pillars 930 extend from the first main electrode 921 to the second main electrode 922. Additionally, between the first and second main electrodes 921, 922 is a gate electrode layer 94 embedded between an upper gate insulator layer 942 and a lower gate insulator layer 943. Gate insulator walls 941 are present on the sidewalls of the pillars 930. Note that in FIG. 10 , two pillars 930 are shown with a portion of the gate electrode layer 94 located between them. For example, the gate electrode layer 94 is highly doped silicon.

[0156] The gate electrode layer 94 defines a common plane P that is perpendicular to the main extension direction of the pillars 930 and therefore perpendicular to the growth direction of the pillars 930. The common plane P may extend parallel to the first and second main electrodes 921, 922 and may be located in the center of the gate electrode layer 94. Gate insulators 941, 942, 943 electrically insulate the gate electrode layer 94 from the first and second main electrodes 921, 922 and the semiconductor layer stack 93. A gate electrode line (not shown) may be present that provides external electrical contact to the gate electrode layer 94.

[0157] The pillars 930, and therefore the semiconductor layer stack 93, are of only one conductivity type. For example, the semiconductor layer stack 93 is made of n-type doped 3C SiC. The power semiconductor device 1 may therefore be a so-called AccuFET device.

[0158] Each pillar 930 includes an upper region 931 in the first main electrode 921 and a channel region 932 between the upper region 931 and the second main electrode 922. The upper region 931 has a size of, for example, 3×10 19 cm -3 At the first doping concentration of n + In comparison, the channel region 932 is doped with, for example, 5×10 16 cm -3 is weakly doped with a lower second doping concentration of .

[0159] In a direction perpendicular to the common plane P, the upper region 931 can end up flush with the upper gate insulator layer 942. For example, the thickness of the upper region 931 and / or the upper gate insulator layer 942 and / or the lower gate insulator layer 943 is at least 0.1 μm and / or at most 1 μm, e.g., 0.3 μm. The thickness of the channel region 932 exceeds the thickness of the upper region 931 in a direction perpendicular to the common plane P by, for example, at least two times and / or at most 20 times.

[0160] However, in contrast to what is shown in Figures 9 and 10, pillars 930 may optionally merge above and / or below gate electrode layer 94, similar to, for example, contact layer 21 in Figure 3B. Therefore, the same content as in Figures 1-8 is also applicable to Figures 9 and 10, except for what has been said with respect to Figures 9 and 10. Although different reference numerals may be used in Figures 9 and 10 compared to Figures 1-8, corresponding components may be considered equivalent. The same is true for Figures 11-32 below.

[0161] In the exemplary embodiment of FIG. 11, the semiconductor layer stack 93 further comprises a base layer 95. For simplicity of illustration, only one base layer 95 is shown in FIG. 11. However, there may be multiple such layers. At least one base layer 95 is a continuous layer from which all of the pillars 930 begin. The base layer 95 may be in direct contact with the second main electrode 922. The base layer 95 is of the same conductivity type as the pillars 930, such that the entire semiconductor layer stack 93 is either n-doped or p-doped.

[0162] For example, the base layer 95 may comprise a SiC substrate of 4H SiC and may include an epitaxially grown drift region and / or at least one buffer layer (not shown). The thickness of the base layer 95 may be, for example, at least 0.01 μm and / or at most 10 μm if the base layer is epitaxially grown alone, or at least 5 μm and / or at most 0.5 mm if the base layer is a growth substrate. The common plane P may be parallel to the surface of the base layer 95 facing the first main electrode 921.

[0163] Otherwise, the same content as in FIGS. 9 and 10 is applicable to FIG. 12, each pillar 930 includes a lower region 933 on a side of the channel region 932 remote from the upper region 931. The lower region 933 is, for example, n-type doped 3C SiC. For example, the third doping concentration of the lower region 933 is the same as the first doping concentration of the upper region 931. The lower region 933 may be in direct contact with the base layer 95 or, if no such base layer is present as in FIGS. 9 and 10, may be in direct contact with the second main electrode 922.

[0164] In a direction perpendicular to the common plane P, the lower region 933 can end up flush with the lower gate insulator layer 943. For example, the thickness of the lower region 933 is at least 0.1 μm and / or at most 1 μm, e.g., 0.3 μm. The thickness of the channel region 932 exceeds the thickness of the lower region 931 in a direction perpendicular to the common plane P by, for example, at least two times and / or at most 920 times.

[0165] Other than that, the same contents as those in FIGS. 9 to 11 can also be applied to FIG. According to Fig. 13, the pillars 930 taper along the direction away from the second main electrode 922, and thus towards the first main electrode 921. The pillars 930 may have the shape of a truncated cone. The opening angle of the truncated cone is, for example, 30°. Such conical pillars 930 can also be used in the exemplary embodiments of Figs. 9 and 10 and 12.

[0166] Other than that, the same contents as those in FIGS. 9 to 12 can also be applied to FIG. 14, the pillars 930 also converge in a direction towards the first main electrode 921. In contrast to FIG. 13, the gate insulator wall 941 and the lower gate insulator layer 943 are made in one piece. Also, the conical pillars 930 can have an opening angle of, for example, only 15° or less.

[0167] The width w of the pillars 930 measured on a surface of the pillars 930 facing the second main electrode 922 is, for example, at least 0.3 μm and / or at most 1 μm. The height h of the pillars 930 in a direction perpendicular to the common plane P is, for example, not less than 2 μm and / or not more than 10 μm. The pitch of the pillars 930, i.e., the distance between the center lines of adjacent pillars 930 measured parallel to the common plane P, is, for example, not less than 2 μm and / or not more than 10 μm. The density of the pillars 930 on the second main electrode 922 is, for example, 2×10 6 cm -2 or greater and / or 5×10 7 cm -2 These values ​​are also applicable to all other exemplary embodiments individually or collectively.

[0168] Other than that, the same contents as those in FIGS. 9 to 13 can also be applied to FIG. 15 to 21 show a method for manufacturing a power semiconductor device. According to Fig. 15, a base layer 95 is provided. The base layer 95 may be, for example, n + The semiconductor substrate 951 may include a relatively thick semiconductor substrate such as 4H SiC with a doping type of 4H.

[0169] Optionally, on top of the semiconductor substrate 951, e.g., n - There is a drift region 952, such as 4H SiC, with a doping of at least 1×10 15 cm -3 and / or up to 3 x 10 16 cm -3 , e.g. 4×1015 cm -3 The doping concentration is

[0170] The thickness of the semiconductor substrate 951 is, for example, 0.1 mm or more and / or 1 mm or less. The thickness of the optional drift region 952 may be at least 0.1 μm and / or at most 1 μm. The same applies to all other exemplary embodiments.

[0171] Furthermore, on the base layer 95 there is a starting layer 962 for a subsequent semiconductor mask 963. For example, the starting layer 962 is made of amorphous silicon.

[0172] 16, the starting layer 962 is structured by etching into a semiconductor mask 963. The semiconductor mask 963 is a positive version of the future pillars 930, and the individual columns of the semiconductor mask 963 can have a height h of 2 μm to 5 μm and a width w of 0.3 μm to 1 μm.

[0173] 17, the columns of the semiconductor mask 963 are oxidized to create tubes 964 for the subsequent gate insulator walls 941. The tubes 964 are therefore made of, for example, thermal SiO2. Furthermore, the tops of these columns of the semiconductor mask 963 can be etched, for example, using reactive ion etching, to expose the tops of the columns. The wall thickness of the tubes 964 is, for example, 5 nm to 0.2 μm.

[0174] 18, the amorphous Si columns of the semiconductor mask 963 are completely removed by etching, for example using tetramethylammonium hydroxide (abbreviated as TMAH), leaving hollow tubes 964 of SiO2 on the surface of the base layer 95. The tubes 964 thus surround the cavities 66.

[0175] 19, pillars 930 are grown within tube 964, starting on base layer 95. Because the semiconductor material of pillar 930 does not grow on the material used for tube 964, the shape of pillar 930 is well defined and the interface between tube 964 and pillar 930 is of high quality, i.e., growth is prevented in all areas and surfaces above base layer 95, which is covered with SiO2. Only inside hollow tube 964 are pillars 930 of 3C SiC grown, which can be doped in situ if desired.

[0176] 20, optionally planarization is then performed using, for example, spin-on glass (SOG for short), thus creating a lower gate insulator layer 943.

[0177] 21, a self-aligned gate process enables a gate-all-around device design to produce a gate electrode layer 94. As is possible in all other exemplary embodiments, the gate electrode layer 94 may be split into two parts between adjacent pillars 930, in contrast to what is shown in FIGS.

[0178] The final steps of fabricating the top gate insulator layer and the first main electrode are not shown in the method of FIGS.

[0179] Other than that, the same contents as those in FIGS. 9 to 14 are also applicable to FIGS. 15 to 21. 22 to 24 show another method for manufacturing the power semiconductor devices 1, 1*. The manufactured power semiconductor devices 1, 1* may be, for example, AccuFETs as shown in FIGS. 9 to 14, but may also be IGBTs, diodes, or vertical FETs. For example, the structure manufactured by the method of FIGS. 22 to 24 is a superjunction structure housed in the base layer 95 of the power semiconductor device 1 of FIGS. 11 to 14.

[0180] According to Figure 23, n +A semiconductor substrate 951, which may be doped SiC, is provided, and a semiconductor mask 963, for example made of silicon, is applied to the semiconductor substrate 951.

[0181] In a first variant, the semiconductor mask 963 may be a positive version of the pillars to be subsequently fabricated and may therefore consist of a plurality of columns. Alternatively, in a second variant, the semiconductor mask 963 may be a negative version of the subsequent pillars and may therefore be a continuous layer with holes for the subsequent pillars. Figures 22 to 24 and 25 to 27 show the first variant, but the same naturally applies equally to the second variant, although this is not explicitly and fully described.

[0182] Thus, according to a first variant, and referring also to Figure 22, the columns of the semiconductor mask 963 are oxidized to result in tubes 964. If, for example, a superjunction is to be produced, the thickness of the tubes 964 is, for example, between 1 nm and 10 nm. If, instead, a gate insulator wall 941 is to be produced, the thickness can be greater, for example between 5 nm and 0.2 µm.

[0183] 23, a filler material 965 is grown between the columns of semiconductor mask 963 that are still present. The filler material 965 may be, for example, n + Doped SiC or n - The filler material 965 is doped SiC. Thus, according to the first variant, the filler material 965 is a continuous layer surrounding the columns of the semiconductor mask 963. Otherwise, in the second variant, the filler material 965 is shaped as multiple columns. However, the tubes 964 are present in both variants, the only difference being whether the filler material 965 is located outside or inside the tubes 964.

[0184] Of course, if fins are produced instead of pillars, the tubes 964 may be formed plates, so that plane-parallel walls are formed instead of cylindrical walls of the tubes 964. The same applies to all other exemplary embodiments of the method and power semiconductor devices 1, 1*.

[0185] Optionally, a cap layer 967 can be grown on the fill material 965. The thickness of the cap layer 967 is, for example, 10% or less of the thickness of the fill material 965. The cap layer 967 can be, for example, n - It is doped SiC.

[0186] 23, in a first variant, the columns of semiconductor mask 963 are removed to result in cylindrical cavities 966. However, tubes 964 remain. Thus, in a second variant, not shown, the cylindrical cavities are absent and there is empty space around pillars of fill material 965.

[0187] Optionally, cap layer 967 may be provided with an oxide layer, which may be similar to that of tube 964 .

[0188] 24, according to a first variant, the cavity 966 is filled with a further semiconductor material 968 which may constitute, for example, pillars 930 as described in FIGS. 9 to 14. For example, the further semiconductor material 968 may be p + Alternatively, for example in the case of an AccuFET, the further semiconductor material 968 may be n-doped SiC for the channel region. - doped SiC, and n for the upper region + According to a second variant, the further semiconductor material 968 is considered to be a continuous layer formed around the pillar-shaped filling material 965, although in both cases there is the insulating material of the tube 964 between the filling material 965 and the further semiconductor material 968.

[0189] In a subsequent optional step (not shown), a planarization layer may be provided if necessary and the method steps of Figures 15-21 may be performed on the planarization layer to further create an AccuFET structure on top of the superjunction structure 97 that may be formed by the method steps of Figures 22-24.

[0190] The same concept shown in Figures 22-24 works using an oxide or nitride mask (not shown) instead of the semiconductor mask 963. Next, in this variation, a fill material 965 is applied, followed by oxidation or oxide deposition (not shown). Although not shown, in this variation, prior to the growth step of further semiconductor material as shown in Figure 24, an anisotropic oxide removal is performed at the bottom of the cavity so that further semiconductor material 968 can be applied onto the substrate 951.

[0191] As an alternative to the semiconductor fill material 965, a gate electrode layer and upper and lower gate insulator layers as shown in Figures 9-14 may be applied instead.

[0192] The method of Figures 25 to 27 is essentially the same as that of Figures 22 to 24, but instead of the SiC semiconductor substrate 951 that may be present in the completed power semiconductor device 1, 1*, a temporary Si semiconductor substrate 961 is used (see Figure 25).

[0193] Therefore, a defect buffer region 969 can be provided in the vicinity of the Si semiconductor substrate 961 (see FIG. 26).

[0194] This defect buffer region 969 may extend into further semiconductor material 968 grown in cavity 966. Optionally, defect buffer region 969 can be removed along with semiconductor substrate 961 (not shown).

[0195] Otherwise, the same content as in Figures 22 to 24 can also be applied to Figures 25 to 27. For example, both the first and second variants described in relation to Figures 22 to 24 can also be applied to the methods of Figures 25 to 27.

[0196] An exemplary embodiment of the power semiconductor device 1, which is an AccuFET, and an exemplary embodiment of the power semiconductor device 1*, which is a Superjunction FET, are shown in Figures 28 and 29. These power semiconductor devices 1, 1* can be manufactured using, for example, the methods of Figures 22 to 24 or Figures 25 to 27.

[0197] In the case of a power semiconductor device 1 that is an AccuFET, the base layer 95 includes a superjunction structure 97 fabricated, for example, by the method of Figures 22-24. The pillar 930 thus includes an n-doped upper region 931, an n-doped channel region 932, and an optional n-doped lower region 933. Between the gate electrode layer 94 and the second main electrode layer 922 is a further semiconductor material 968, which may be p-doped, separated from the n-doped region by a tube 964. The semiconductor substrate 951 is also n-doped.

[0198] In the case of a power semiconductor device 1* that is a superjunction MOSFET or a superjunction MISFET, there is an n-doped upper region 931, a p-doped channel region 932*, and an n-doped lower region 933 within the pillar 930, and an n-doped semiconductor substrate 51 within an optional base layer 95.

[0199] As seen in Figure 29, the pillars 930 may be arranged in a hexagonal pattern and can have a square footprint. Alternatively, a square or rectangular pattern can be used. Additionally, circular, oval, or polygonal footprints are also possible for the pillars 930. The same applies to all other exemplary embodiments.

[0200] Other than that, the same contents as those in FIGS. 9 to 27 are also applicable to FIGS. In Figure 30 another exemplary embodiment of a power semiconductor device 1* is shown in a top view and in the same cross section as in Figure 28. In this embodiment, the gate electrode layer 94 and thus the further p-doped semiconductor material 968 is structured, for example, as stripes running parallel to one another.

[0201] The filling material 965 consists of a plurality of pillars 930 arranged adjacent to one another along the stripes of the gate electrode layer 94. Between adjacent pillars 930 there are in each case walls of the tubes 964 and therefore walls of the insulating material that make up the tubes 964. For example, the footprint of the pillars 930 is 1 μm×1 μm and the thickness of the walls of the pillars 930 is 10 nm.

[0202] Other than that, the same contents as in FIGS. 28 and 29 are applicable to FIG. 30 as well. Another exemplary embodiment of the power semiconductor device 1* is shown in Figures 31 and 32. The power semiconductor device 1* is a superjunction Schottky diode comprising an upper region 931, which may be n-doped, in a superjunction structure 97, a filler material 965, which may also be n-doped, and a further semiconductor material 968, which may be p-doped. Optionally, a common semiconductor substrate 951 can be present. An electrical insulator material 942 is disposed on top of the further semiconductor material 968 and extends closer to the second main electrode 922 than the upper region 931.

[0203] When viewed from the top, the additional semiconductor material 968 as well as the filler material 965 may be arranged in stripes. In either case, the stripes are made up of a plurality of respective columns 930. Between adjacent columns are walls of the tubes 964. Such an arrangement of the additional semiconductor material 968 may also be present in FIG. 29 or FIG. 30.

[0204] Other than that, the same contents as those in FIGS. 9 to 30 are also applicable to FIGS. 31 and 32. Thus, the designs shown in Figures 28-32 are possible for diodes and MOSFETs, for example. This can be applied to pillar and stripe layouts with or without oxide bridges along the stripes for further defect capture. The dimensions can be relatively small so that, in addition to the superjunction effect, volume inversion can also occur to further improve current conduction. The advantage of this concept is that, for example, the gate refill can be fully self-aligned within the pillar, resulting in a low pitch of less than 1 μm, without the need for advanced lithography tools.

[0205] Such a superjunction structure 97 can provide excellent current blocking with low leakage. The low leakage is due to the low electric field at the metal / semiconductor interface. For example, in the case of a MOSFET, this effect means that the electric field at the gate insulator during blocking is reduced compared to conventional trench designs, resulting in better reliability and the possibility of thinner gate insulators, further improving the performance of the power semiconductor device 1, 1*.

[0206] Therefore, having a superjunction structure allows the use of alternative substrate materials other than SiC, such as Si, and low-temperature epitaxy reactors, since defect growth, stress, and relaxation defects are confined to the thin defect buffer region and do not extend toward the bulk region of the superjunction structure itself, allowing the use of standard Si CVD. Therefore, smooth and crystalline layers can be grown at growth temperatures below 1250°C, which are suitable for selective epitaxy. Therefore, high-performance wide-bandgap superjunction devices with excellent conduction performance can be obtained at relatively low cost.

[0207] The term "and / or" expresses only a relational relationship for describing related objects and indicates that three relationships may exist. For example, A and / or B can represent three cases: only A is present, both A and B are present, and only B is present. Correspondingly, the phrase "at least one of A, B, and C" can represent seven cases: only A is present, only B is present, only C is present, both A and B are present, both A and B are present, both A and C are present, both B and C are present, and all three of A, B, and C are present. The same applies whether the phrase "at least one of..." lists only two entities or more than three. Thus, "at least one of A and B" is equivalent to "A and / or B."

[0208] The exemplary embodiments described in this disclosure are not limited by the description provided with reference to the exemplary embodiments, but rather, the present disclosure is believed to encompass any novel feature and any combination of features, including in particular any combination of features in the claims, even if the feature or combination itself is not explicitly set forth in the claims or exemplary embodiments.

[0209] This patent application claims priority to European Patent Applications Nos. 20216094.1 and 20216022.2, the disclosures of which are incorporated herein by reference.

[0210] List of Reference Numbers [Explanation of symbols]

[0211] 1,1* Semiconductor power devices 2,93 Semiconductor layer stack 3,921 First main electrode 3A source contact pad 3B First portion of first main electrode 3C Second part of the first main electrode 4,922 Second main electrode 5,94 Gate electrode layer 5A: Surface of gate electrode layer facing first main electrode 5B control contact pad 6 First insulating layer 6A First insulating layer portion 6B Second insulating layer portion 7. Career 8 PCB 8A First main surface of substrate 9 First substrate layer 10 Second substrate layer 11 Sacrificial Layer 12 Sacrificial Structure 13, 14A, 14B, 15A, 15B Semiconductor layers 13A Ridge region 16 cavities 17 insulating material layer 17A first portion of insulating material layer 17B second portion of insulating material layer 18 Overlapping area 19 Second insulating layer 20,930 Pillar-like or fin-like regions 20A Side of pillar-like or fin-like region 21 Contact layer 21A first portion of contact layer 21B second portion of contact layer 21C Contact Area 22 Channel Layer 23 Drain layer 24 transistor cells 25 Intermediate insulating layer 911 First main surface 912 Second main surface 930 Pillar 931 Upper area 932 Channel region, same conductivity type as upper region 932* Conductivity type other than the channel region and upper region 933 Lower area 941 Gate Insulator Wall 942 Top gate insulator layer 943 Lower gate insulator layer 95 Base layer of semiconductor layer stack 951 Semiconductor substrate, permanently present 952 Drift Region 961 Semiconductor substrate, temporary presence 962 Starting layer for semiconductor mask 963 Semiconductor Mask 964 Pipes of insulating material 965 Filling materials 966 Cavity 967 Cap Layer 968 Further Semiconductor Materials 969 Defective Buffer Area 97 Superjunction Structure d layer thickness w first horizontal extension, width of pillar or fin l Second horizontal extension h Vertical extension, height of pillar or fin D Device plane L1 First horizontal extension direction L2 Second horizontal extension direction P common plane V vertical direction

Claims

1. A method for manufacturing a semiconductor device (1), comprising: - providing a substrate (8); - forming a sacrificial layer (11) on the first main surface (8A) of said substrate (8); - structuring said sacrificial layer (11) to form a plurality of sacrificial structures (12) protruding from said first main face (8A) and having the shape of pillars or fins; forming, on at least one of said plurality of sacrificial structures (12) and on said first main surface (8A), a layer of insulating material (17), at least a portion of which will form a first insulating layer (6) in said semiconductor device (1); - removing at least one sacrificial structure (12) to form at least one cavity (16) in said layer of insulating material (17); - forming a gate electrode layer (5) on one or more second portions (17B) of said insulating material layer (17) forming at least one second insulating layer portion (6B) in said semiconductor device (1); - selectively forming a first semiconductor layer (15, 15A) of a first conductivity type on said first main surface (8A) to form a contact layer (21) in said at least one cavity (16) extending to a surface (5A) of said gate electrode layer (5) facing away from said substrate (8); - forming a first main electrode (3) on the face of the semiconductor layer stack (2) facing away from said substrate (8); - forming a second main electrode (4) on the face of said semiconductor layer stack (2) facing away from said first main electrode (3); Including, said gate electrode layer (5, 94) is located between said first main electrode (3, 921) and said second main electrode (4, 922); said semiconductor layer stack (2, 93) is located between said first main electrode (3, 921) and said second main electrode (4, 922) and is in electrical contact with said first main electrode (3, 921) and said second main electrode (4, 922), said semiconductor layer stack (2, 93) comprising: - the first semiconductor layer (15, 15A) of the first conductivity type and the second semiconductor layer (14) of the second conductivity type, the first semiconductor layer (15, 15A) and the second semiconductor layer (14) being different in at least conductivity type; a plurality of pillar- or fin-like regions (20, 930) extending through said gate electrode layer (5, 94), each of said pillar- or fin-like regions (20, 930) comprising said contact layer (21) having a first doping concentration and said first conductivity type arranged on said first main electrode (3, 921); Equipped with each contact layer (21) extends to the surface (5A) of said gate electrode layer (5, 94) facing said first main electrode (3, 921); the contact layers (21) of adjacent pillar-shaped or fin-shaped regions (20, 930) meet at the face of the gate electrode layer (5, 94) facing the first main electrode (3, 921); method.

2. 2. The method of claim 1, wherein the method comprises forming the first semiconductor layer (15, 15A) of the first conductivity type, which is provided for forming the contact layer (21) after fabrication of the gate electrode layer (5).

3. The method comprises: - selectively forming the second semiconductor layer (14) of the second conductivity type between the contact layer (21) and the substrate (8) on the first main surface (8A) in each cavity (16) to form a channel layer (22); - selectively forming a semiconductor layer (13) of the first conductivity type between the channel layer (22) and the substrate (8) on the first main surface (8A) in each cavity (16) to form a drain layer (23); 3. The method of claim 1 or 2, comprising:

4. a first main electrode (3,921), a second main electrode (4, 922), a gate electrode layer (5, 94) between said first main electrode (3, 921) and said second main electrode (4, 922); a single semiconductor layer stack (2, 93) comprising silicon carbide, i.e. SiC, between said first main electrode (3, 921) and said second main electrode (4, 922) and in electrical contact with said first main electrode (3, 921) and said second main electrode (4, 922); wherein the single semiconductor layer stack (2, 93) comprises: differently doped semiconductor layers (13, 14A, 14B, 15A, 15B, 95, 931, 932, 933), at least two of which differ in at least their conductivity type; a plurality of pillar-shaped regions (20, 930) extending through said gate electrode layer (5, 94), each comprising a contact layer (21) having a first doping concentration and a first conductivity type arranged on said first main electrode (3, 921), said pillar-shaped regions (20, 930) having a square, polygonal, circular or elliptical footprint; exactly one first insulating layer (6) comprising a plurality of first insulating layer portions (6A) extending through the gate electrode layer (5) and at least one second insulating layer portion (6B) arranged on a surface of the gate electrode layer (5) facing the second main electrode (4); Equipped with each contact layer (21) extends to the surface (5A) of said gate electrode layer (5, 94) facing said first main electrode (3, 921); the contact layers (21) of adjacent pillar-shaped regions (20, 930) meet at the face of the gate electrode layer (5, 94) facing the first main electrode (3, 921); the first insulating layer portion (6A) is in each case filled with the single semiconductor layer stack (2, 93) directly covering the inner surface of the first insulating layer portion (6A) so that the first insulating layer portion (6A) defines the pillar-shaped region (20, 930), the first insulating layer portion (6A) completely surrounds a corresponding pillar-shaped region in the horizontal direction so as to form a plurality of vertical gate all-around field effect transistor cells; Semiconductor device (1).

5. The single semiconductor layer stack (2, 93) comprises silicon carbide, i.e., SiC; the gate electrode layer (5, 94) is a continuous layer; the footprint of the pillar-like region (20, 930) is square or circular; A semiconductor device (1) according to claim 4.

6. The following, i.e., the single semiconductor layer stack (2) comprises a plurality of channel layers (22), each of which is assigned to one pillar-shaped region (20) and which is arranged on a face of the contact layer (21) facing away from the first main electrode (3); and the plurality of pillar-shaped regions (20, 930) are pillar-shaped so as to form a plurality of pillars (930), each of the pillars (930) comprising an upper region (931) with a first doping concentration located in the first main electrode (921), and on the face of the upper region (931) facing away from the first main electrode (921), in a common plane (P) with the gate electrode layer (94), each of the pillars (930) comprises a channel region (932) with a second doping concentration; 6. The semiconductor device (1) according to claim 5, wherein at least one of the following applies:

7. the channel layer (22) has a second doping concentration and a second conductivity type; - said second doping concentration is different from said first doping concentration; and the second conductivity type is different from the first conductivity type; 7. The semiconductor device (1) according to claim 6, wherein at least one of

8. 8. The semiconductor device (1) according to claim 6 or 7, wherein the first insulating layer (6) is disposed between the gate electrode layer (5) and the channel layer (22) such that the gate electrode layer (5) is electrically isolated from each of the channel layers (22).

9. The semiconductor device (1) according to claim 6, wherein the channel layer (22) is at least partially arranged in a common plane with the gate electrode layer (5).

10. The plurality of pillar-shaped regions (20, 930) are pillar-shaped such that a plurality of pillars (930) are formed; The following, i.e., - said pillars (930) extend perpendicular to said common plane (P); said first doping concentration is 1×10 １６ cm －３ 2x10 or more １７ cm －３ and the second doping concentration is 5×10 or less. １８ cm －３ 2 x 10 or more ２０ cm －３ Below is the the width (w) of said pillars (930), seen in a cross section through and parallel to said common plane (P), is at least 0.05 μm and at most 1 μm; - the height (h) of said pillars (930), as seen in said cross section through and perpendicular to said common plane (P), is at least twice the width (w) and at most 20 times the width (w); and - the density of the pillars (930), seen in a top view of the common plane (P), is 1 x 10 ６ cm －２ 4 x 10 or more ７ cm －２ Below is the The semiconductor device (1) according to any one of claims 6 to 9, wherein the semiconductor device (1) corresponds to at least one of the following:

11. each pillar-like region (20) has a first horizontal extension (w) that is less than 2 μm or less than 1 μm; 11. The semiconductor device (1) of claim 6, wherein each pillar-shaped region (20) comprises a lower region (33) on a surface of the respective channel region (32) facing the second main electrode (4), and a third doping concentration of the lower region (33) is the first doping concentration within a tolerance of up to two times.

12. A semiconductor device (1) described in any one of claims 4 to 11, wherein the plurality of pillar-shaped regions (20, 930) are pillar-shaped so as to form a plurality of pillars (930), and the pillars (930) in each case have the shape of a truncated cone, and the opening angle of the truncated cone is greater than or equal to 10° and less than or equal to 35°.

13. a plurality of said pillar-like regions (20, 930) are pillar-like, so that a plurality of pillars (930) are formed; - the single semiconductor layer stack (93) further comprises a continuous base layer (95) which lies parallel to the common plane (P) on the face of the pillar (930) facing away from the first main electrode (921); - all said pillars (930) are in contact with said base layer (95), said pillars (930) and said base layer (95) comprising different semiconductor materials and / or different crystalline structures; A semiconductor device (1) according to any one of claims 6 to 9.

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