Field-effect transistors and switching elements

Abstract

This field effect transistor has: a substrate having a (111) plane, the substrate comprising a group IV semiconductor doped with a first electroconductivity type; a core-shell nanowire including a core nanowire connected to the (111) plane of the substrate, the core nanowire comprising a group III-V compound semiconductor doped with a second electroconductivity type different from the first electroconductivity type, and a shell layer disposed so as to cover the core nanowire, the shell layer comprising a group III-V compound semiconductor doped with the first electroconductivity type; a first electrode electrically connected to the shell layer; a second electrode electrically connected to the substrate; and a gate electrode for inducing a field at the joining interface between the substrate and the core nanowire and at the shell layer.

Description

[Technical Field]

[0001] The present invention relates to a field effect transistor and a switching element. [Background technology]

[0002] Semiconductor microprocessors and highly integrated circuits are manufactured by integrating elements such as metal-oxide-semiconductor (hereinafter referred to as "MOS") field-effect transistors (hereinafter referred to as "FETs") on a semiconductor substrate. Generally, complementary metal-oxide-semiconductor field-effect transistors (hereinafter referred to as "CMOS") are the basic elements (switching elements) of integrated circuits. Silicon, a group IV semiconductor, is primarily used as the material for the semiconductor substrate. By miniaturizing the transistors that make up CMOS, the integration density and performance of semiconductor microprocessors and highly integrated circuits can be improved. One of the challenges in miniaturizing CMOS is the increase in power consumption. The two main causes of this increase in power consumption are the increase in the number of CMOS that can be mounted on a single microchip and the increase in leakage current due to the short channel effect.

[0003] Tunnel FETs (hereinafter also referred to as "TFETs") are known as switching elements that operate at a subthreshold coefficient smaller than that of general MOSFETs. TFETs are considered to be promising candidates for next-generation switching elements because they are free from short-channel effects and can achieve a high ON / OFF ratio at low voltages. In recent years, TFETs using III-V compound semiconductor nanowires have been reported (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2011 / 040012 Summary of the Invention [Problem to be solved by the invention]

[0005] In conventional FETs, it was necessary to fabricate different device structures to achieve different switching characteristics. For example, in a CMOS composed of Si-MOSFETs, it was necessary to fabricate npn and pnp structures separately.

[0006] An object of the present invention is to provide a field effect transistor that exhibits a plurality of switching characteristics with a single device structure, and a switch device including the field effect transistor. [Means for solving the problem]

[0007] The field-effect transistor of the present invention comprises a core-shell nanowire including a substrate having a (111) surface and made of a group IV semiconductor doped to a first conductivity type, a core nanowire connected to the (111) surface of the substrate and made of a group III-V compound semiconductor doped to a second conductivity type different from the first conductivity type, and a shell layer arranged to cover the core nanowire and made of a group III-V compound semiconductor doped to the first conductivity type, a first electrode electrically connected to the shell layer, a second electrode electrically connected to the substrate, and a gate electrode that applies an electric field to the junction interface between the substrate and the core nanowire and to the shell layer.

[0008] A switching element according to the present invention includes the above-described field effect transistor. [Effects of the Invention]

[0009] According to the present invention, it is possible to provide a field effect transistor that exhibits a plurality of switching characteristics with one element structure, and a switch element including the field effect transistor. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a cross-sectional view showing a configuration of a FET according to a first embodiment of the present invention. [Figure 2]2A to 2C are diagrams showing how the FET according to the first embodiment operates as an nTFET. [Figure 3] 3A to 3C are diagrams showing how the FET according to the first embodiment operates as a pFET. [Figure 4] FIG. 4 is a cross-sectional view showing a configuration of an FET according to a second embodiment of the present invention. [Figure 5] Figure 5 is a scanning electron microscope image of a silicon substrate on which core-shell nanowires are periodically arranged. [Figure 6] 6A and 6B are graphs showing the relationship between gate voltage and drain current when the TFET of the example operates as an nTFET, respectively. [Figure 7] 7A and 7B are graphs showing the relationship between the gate voltage and the drain current when the TFET of the example operates as a pFET, respectively. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0012] [Embodiment 1] (Field-effect transistor structure) Fig. 1 is a cross-sectional view showing a structure of a field-effect transistor (FET) 100 according to a first embodiment of the present invention. As shown in Fig. 1, the FET 100 according to this embodiment has a substrate 110, an insulating film 120, a core-shell nanowire 130, a first electrode 140, a second electrode 150, a gate dielectric film 160, a gate electrode 170, and an insulating protection film 180. Each component will be described below.

[0013] The substrate 110 is made of a group IV semiconductor such as silicon or germanium and has a (111) surface. The substrate 110 is doped to a first conductivity type (n-type or p-type). For example, the substrate is an n-type silicon (111) substrate or a p-type silicon (111) substrate.

[0014] The insulating film 120 covers the (111) surface of the substrate 110 and has one or more openings. The insulating film 120 functions as a mask pattern when growing the core nanowires 131 from the (111) surface of the substrate 110. The material of the insulating film 120 is not particularly limited as long as it can inhibit the growth of the core nanowires and is an insulator. Examples of materials for the insulating film 120 include silicon oxide (SiO2), silicon nitride (SiN), and aluminum oxide (Al2O3). The insulating film 120 may be a single layer or may consist of two or more layers. The thickness of the insulating film 120 is not particularly limited as long as it can properly exhibit its insulating properties. For example, the insulating film 120 is a silicon oxide film with a thickness of 10 to 100 nm.

[0015] The openings in the insulating film 120 penetrate all the way to the (111) plane of the substrate 110, and the (111) plane of the substrate 110 is exposed in the openings. The openings determine the growth position, thickness, and shape of the core nanowire 131 when manufacturing the FET 100 according to this embodiment. The shape of the openings is not particularly limited and can be determined arbitrarily. Examples of the shape of the openings include a triangle, a square, a hexagon, and a circle. The diameter of the circumscribing circle of the openings may be approximately 2 to 500 nm. When the number of openings is two or more, the center-to-center distance between the openings may be approximately several tens of nm to several μm.

[0016] The core-shell nanowire 130 is a core-shell structure made of a III-V compound semiconductor and having a diameter of approximately 7.6 nm to 1 μm and a length of approximately 100 nm to 100 μm. The core-shell nanowire 130 is arranged on the (111) surface of the substrate 110 exposed in the opening of the insulating film 120 and on the insulating film 120 around it, with its long axis perpendicular to the (111) surface of the substrate. More specifically, the core nanowire 131 of the core-shell nanowire 130 is arranged on the (111) surface of the substrate 110 exposed in the opening of the insulating film 120, and the shell layer 134 covering the surface of the core nanowire 131 is arranged on the insulating film 120 around the opening. By forming the core nanowire 131 on the (111) surface of the substrate 110 in this way, the core nanowire 131 can be arranged perpendicular to the (111) surface.

[0017] 1, core-shell nanowire 130 has core nanowire 131 and shell layer 134 covering the surface of core nanowire 131. Shell layer 134 covers the side surface of core nanowire 131 and the end face on the first electrode 140 side, but does not cover the end face of core nanowire 131 on the substrate 110 side. Here, "side surface of core nanowire 131" refers to the surface along the central axis (long axis) of core nanowire 131, and "end face of core nanowire 131" refers to the surface intersecting with the central axis of core nanowire 131.

[0018] The core nanowire 131 is made of a III-V compound semiconductor doped with a second conductivity type (p-type or n-type) different from the conductivity type (first conductivity type) of the substrate 110, and extends upward from the (111) surface of the substrate 110 through the opening in the insulating film 120. The III-V compound semiconductor constituting the core nanowire 131 may be a binary compound semiconductor, a ternary compound semiconductor, a quaternary compound semiconductor, or a semiconductor composed of more elements. Examples of binary compound semiconductors include InAs, InP, GaAs, GaN, InSb, GaSb, and AlSb. Examples of ternary compound semiconductors include AlGaAs, InGaAs, InGaN, AlGaN, GaNAs, InAsSb, GaAsSb, InGaSb, and AlInSb. Examples of quaternary compound semiconductors include InGaAlN, AlInGaP, InGaAsP, GaInAsN, InGaAlSb, InGaAsSb, and AlInGaPSb. The thickness of the core nanowire 131 (the diameter of the circumscribed circle of the cross section perpendicular to the axial direction) may be about 2 to 500 nm. The length of the core nanowire 131 may be about 100 nm to 100 μm. For example, the core nanowire 131 may be an In nanowire with a thickness of 80 nm. 0.7 Ga 0.3 As nanowires.

[0019] The core nanowire 131 may or may not be divided into a first region 132 connected to the (111) plane of the substrate 110 and a second region 133 not connected to the (111) plane. In this embodiment, the core nanowire 131 includes the first region 132 and the second region 133. Both the first region 132 and the second region 133 are doped to a second conductivity type (p-type or n-type), but the impurity density of the first region 132 is different from the impurity density of the second region 133. For example, when the substrate 110 is a p-type silicon (111) substrate, the first region 132 is made of a lightly n-type doped InGaAs nanowire, and the second region 133 is made of a heavily n-type doped InGaAs nanowire. When the substrate 110 is an n-type silicon (111) substrate, the first region 132 is made of lightly p-type doped InGaAs nanowires, and the second region 133 is made of heavily p-type doped InGaAs nanowires. The impurity density of the first region 132 is not particularly limited as long as the first region 132 is of the second conductivity type, and may be, for example, 10 15 ~10 20 cm -3 The impurity density of the second region 133 is not particularly limited as long as the second region 133 has the second conductivity type. 16 ~10 20 cm -3 The impurity density of the core nanowire 131 when not divided into the first region 132 and the second region 133 is not particularly limited as long as the core nanowire 131 has the second conductivity type, and is within the range of, for example, 10 15 ~10 20 cm -3 The second region 133 is electrically connected to the first electrode 140 via the shell layer 134. The first region 132 of the core nanowire 131 and the (111) plane of the substrate 110 form a junction interface that is essentially dislocation- and defect-free.

[0020] In the FET 100 according to this embodiment, the junction interface between the (111) plane of the substrate 110 made of a group IV semiconductor and the core nanowire 131 made of a group III-V compound semiconductor is preferably dislocation- and defect-free, but may contain a small number of dislocations or defects. Specifically, the period of misfit dislocations at the junction interface should be larger than the period of misfit dislocations calculated from the lattice mismatch between the group IV semiconductor constituting the substrate 110 and the group III-V compound semiconductor constituting the core nanowire 131. In addition, the density of threading dislocations at the junction interface should be in the range of 0 to 10. 10 pieces / cm 2 By forming the core nanowire 131 by the manufacturing method described later, the FET 100 of this embodiment having a junction interface that is essentially free of dislocations and defects can be manufactured.

[0021] The shell layer 134 covers the surface of the core nanowire 131. The shell layer 134 is in contact with the insulating film 120 but not with the substrate 110. The shell layer 134 is made of a III-V compound semiconductor doped to a first conductivity type (n-type or p-type) different from the conductivity type (second conductivity type) of the core nanowire 131. The III-V compound semiconductor constituting the shell layer 134 is not particularly limited as long as it satisfies these conditions. Examples of III-V compound semiconductors constituting the shell layer 134 are the same as the examples of the III-V compound semiconductor constituting the core nanowire 131 described above. The impurity density of the shell layer 134 is not particularly limited as long as the shell layer 134 is of the first conductivity type, and may be, for example, 10 15 ~10 20 cm -3The thickness of the shell layer 134 is within the range of 1 to 200 nm. There are no particular limitations on the thickness of the shell layer 134, and it may be, for example, approximately 1 to 200 nm. From the viewpoint of increasing the drain current when the FET 100 operates as a first conductivity type FET, it is preferable that the thickness of the shell layer 134 is large. On the other hand, from the viewpoint of increasing the effective gate electric field strength when the FET 100 operates as a second conductivity type TFET, it is preferable that the thickness of the shell layer 134 is small. For example, when the core nanowire 131 is an n-type doped InGaAs nanowire, the shell layer 134 is a 45 nm-thick highly p-type doped GaSb layer.

[0022] The first electrode 140 is electrically connected to the core-shell nanowire 130. More specifically, the first electrode 140 is electrically connected to the shell layer 134 of the core-shell nanowire 130. The second electrode 150 is electrically connected to the substrate 110. The first electrode 140 functions as one of a source electrode and a drain electrode, and the second electrode 150 functions as the other of the source electrode and drain electrode. For example, the first electrode 140 may function as a drain electrode, and the second electrode 150 may function as a source electrode. In this case, the second electrode 150 may be grounded. Alternatively, the first electrode 140 may function as a source electrode, and the second electrode 150 may function as a drain electrode. In this case, the first electrode 140 may be grounded.

[0023] The type of the first electrode 140 is not particularly limited, but is preferably a metal film, alloy film, or metal multilayer film that can make ohmic contact with the shell layer 134. An example of a metal film that can make ohmic contact with the shell layer 134 includes Mo. Examples of metal multilayer films that can make ohmic contact with the shell layer 134 include a Ti / Au multilayer film, a Ni / Ge / Au multilayer film, a Ge / Au / Ni / Au multilayer film, a Ti / Pt / Au multilayer film, and a Ti / Pd / Au multilayer film. The type of the second electrode 150 is not particularly limited, but is preferably a metal film, alloy film, metal multilayer film, or silicide metal film that can make ohmic contact with the substrate 110. Examples of metal multilayer films that can make ohmic contact with the substrate 110 include a Ti / Au multilayer film and a Ni / Au multilayer film. Examples of silicide metal films that can make ohmic contact with the substrate 110 include a NiSi film and a TiSi film. In this embodiment, the first electrode 140 is a Ti / Au multilayer film or a Ge / Au / Ni / Au multilayer film arranged on the core-shell nanowire 130 and the insulating protective film 180, and the second electrode 150 is a Ti / Au multilayer film formed on the substrate 110.

[0024] The gate dielectric film 160 covers at least a portion of the side surface of the core-shell nanowire 130. In this embodiment, the gate dielectric film 160 covers a portion of the side surface of the core-shell nanowire 130 facing the substrate 110 and the insulating film 120. The material of the gate dielectric film 160 is not particularly limited, but is preferably a high dielectric constant film. Examples of materials for the gate dielectric film 160 include hafnium aluminate (HfAlO x ), zirconium oxide (ZrO2), and lanthanum oxide (La2O3). For example, the gate dielectric film 160 is a hafnium aluminate film with a thickness of 10 nm.

[0025] The gate electrode 170 is disposed on the gate dielectric film 160 so as to surround at least a portion of the core-shell nanowire 130. More specifically, the gate electrode 170 is disposed on the gate dielectric film 160 so as to apply an electric field to the junction interface between the substrate 110 and the core nanowire 131 and to the portion of the shell layer 134 directly below the gate electrode 170. In this embodiment, the gate electrode 170 is disposed so as to surround the end of the core-shell nanowire 130 on the substrate 110 side. That is, the FET 100 according to this embodiment is a gate-all-around (GAA) FET.

[0026] The type of gate electrode 170 is not particularly limited as long as it is conductive, and may be, for example, a metal film, a metal multilayer film, a metal compound film, or other conductive film. Examples of metals constituting the metal film include W, Ti, Pt, Au, and Mo. Examples of metal multilayer films include a Ti / Au multilayer film. Examples of metal compound films include a tantalum nitride (TaN) film and a tungsten nitride (WN) film. In this embodiment, the gate electrode 170 is a Ti / Au multilayer film formed on the gate dielectric film 160.

[0027] The insulating protective film 180 is a film made of insulating resin that covers the core-shell nanowires 130, the gate dielectric film 160, and the gate electrode 170. The type of insulating resin is not particularly limited, but may be, for example, BCB resin.

[0028] (Field-effect transistor operation) When the polarity of the gate voltage is either positive or negative, the FET 100 according to this embodiment operates as a tunneling field-effect transistor (TFET) of a second conductivity type, in which the gate electrode 170 applies an electric field to modulate the tunneling current at the junction interface between the substrate 110 and the core nanowire 131. When the polarity of the gate voltage is the other of positive and negative, the FET 100 according to this embodiment operates as a field-effect transistor (FET) of a first conductivity type, in which the gate electrode 170 applies an electric field to modulate the thermal diffusion current in the shell layer 134.

[0029] More specifically, when the substrate 110 and the shell layer 134 are p-type (first conductivity type) and the core nanowire 131 is n-type (second conductivity type), the FET 100 operates by changing the polarity of the gate voltage to positive (V G >0), it operates as an n-type TFET (nTFET), and the polarity of the gate voltage is negative (V G <0), it operates as a p-type FET (pFET).

[0030] Also, when the substrate 110 and the shell layer 134 are n-type (first conductivity type) and the core nanowire 131 is p-type (second conductivity type), the FET 100 can be configured such that the polarity of the gate voltage is negative (V G <0), it operates as a p-type TFET (pTFET), and the polarity of the gate voltage is positive (V G >0), it operates as an n-type FET (nFET).

[0031] 2A-C are diagrams illustrating how FET 100 operates as an n-type TFET when substrate 110 and shell layer 134 are p-type (first conductivity type) and core nanowire 131 is n-type (second conductivity type). FIG. 2A is a cross-sectional schematic diagram of FET 100 showing the current flow, FIG. 2B is a band diagram in a thermal equilibrium state, and FIG. 2C is a diagram illustrating how FET 100 operates when the polarity of the drain-source voltage is positive (V DS >0), and the polarity of the gate voltage is positive (V G >0). Note that the aspect ratio in Figure 2A has been changed from that in Figure 1 to make the current flow easier to see.

[0032] As shown in Figures 2A-C, the polarity of the drain-source voltage is changed to positive (V DS >0), and the polarity of the gate voltage is positive (V G >0) and applying a sufficient gate voltage, band-to-band tunneling occurs at the junction interface between the substrate 110 and the core nanowire 131, causing a current to flow from the first electrode 140 to the second electrode 150. In other words, the FET 100 operates as an nTFET.

[0033] 3A-3C are diagrams showing how the FET 100 operates as a p-type FET (MOSFET) when the substrate 110 and the shell layer 134 are p-type (first conductivity type) and the core nanowire 131 is n-type (second conductivity type). FIG. 3A is a cross-sectional schematic diagram of the FET 100 showing the current flow, FIG. 3B is a band diagram in a thermal equilibrium state, and FIG. 3C is a diagram showing the operation of the FET 100 when the polarity of the drain-source voltage is negative (V DS <0), and the polarity of the gate voltage is negative (V G <0). Note that the aspect ratio in Figure 3A has been changed from that in Figure 1 to make it easier to see the current flow.

[0034] As shown in Figures 3A-C, the polarity of the drain-source voltage is changed to negative (V DS <0), and the polarity of the gate voltage is negative (V G <0), the valence band barrier becomes small in the shell layer 134 in contact with the core nanowire 131, and current flows from the second electrode 150 to the first electrode 140. In other words, the FET 100 operates as a pFET (pMOSFET).

[0035] As described above, the FET 100 according to this embodiment can be operated as both an n-type field effect transistor (nFET) and a p-type field effect transistor (pFET) by switching the polarity of the gate voltage. Therefore, since the nFET and the pFET have the same configuration, the nFET and the pFET can be easily manufactured simultaneously.

[0036] By using the FET 100 according to this embodiment as a switching element, it is possible to reduce the power consumption of a semiconductor device, thereby achieving energy savings and reducing the environmental load.

[0037] (Field Effect Transistor Manufacturing Method) There are no particular limitations on the method for manufacturing FET 100 according to this embodiment. Many of the components of FET 100 (components other than shell layer 134) can be manufactured using the method described in Patent Document 1 (WO 2011 / 040012), for example.

[0038] For example, a FET 100 in which the substrate 110 and the shell layer 134 are p-type (first conductivity type) and the core nanowire 131 is n-type (second conductivity type) can be manufactured by the following procedure.

[0039] First, a highly p-type doped group IV semiconductor substrate 110 is prepared. An insulating film 120 is formed on the (111) surface of this substrate 110 by thermal oxidation or the like. Next, an opening of a predetermined size (e.g., 80 nm in diameter) is formed in the insulating film 120 on the substrate 110 by photolithography or the like.

[0040] Next, a core nanowire 131 made of a III-V compound semiconductor is grown on the (111) surface of the substrate 110 exposed through the opening by metalorganic chemical vapor phase epitaxy (hereinafter also referred to as "MOVPE") or molecular beam epitaxy (hereinafter also referred to as "MBE"), etc. At this time, before growing the core nanowire 131, it is preferable to form a thin film of a III-V compound semiconductor on the (111) surface of the substrate 110 by an alternate source supply modulation method (see Patent Document 1).

[0041] The core nanowire 131 is doped n-type. For example, the core nanowire 131 can be doped with an n-type dopant by supplying a doping gas or a doping organic metal while forming the core nanowire 131 by MOVPE. At this time, the concentration of the doping gas or doping organic metal may be changed midway to form the first region 132 that is lightly doped n-type and the second region 133 that is heavily doped n-type. Alternatively, the first region 132 that is lightly doped n-type and the second region 133 that is heavily doped n-type may be formed by implanting ions of group IV atoms into the portions of the core nanowire 131 that will become the first region 132 and the second region 133, respectively, by ion implantation.

[0042] Next, shell layer 134 is formed on the surface of core nanowire 131. Shell layer 134 is formed by, for example, MOVPE or MBE. From the viewpoint of reducing the number of work steps, the method for forming shell layer 134 is preferably the same as the method for manufacturing core nanowire 131. For example, to form shell layer 134 made of GaSb on the surface of core nanowire 131 made of InGaAs, a source gas containing gallium and a source gas containing antimony may be supplied and GaSb (shell layer 134) may be grown at 580°C.

[0043] The shell layer 134 is doped to the same first conductivity type (p-type or n-type) as the substrate 110. For example, a p-type shell layer 134 can be formed by simultaneously supplying a gas or organometallic material containing group VI atoms and the material for the shell layer 134 using an MOVPE method. Similarly, an n-type shell layer 134 can be formed by simultaneously supplying a gas or organometallic material containing group IV atoms and the material for the shell layer 134 using an MOVPE method. The types of doping gas and doping organometallic are not particularly limited as long as they contain C, Zn, or Te when doping to p-type, and are not particularly limited as long as they contain C, Si, Ge, Sn, O, S, Se, or Te when doping to n-type.

[0044] By the above procedure, the FET 100 according to this embodiment can be manufactured.

[0045] (effect) As described above, the field-effect transistor 100 according to the first embodiment can be operated as both an n-type field-effect transistor (nFET) and a p-type field-effect transistor (pFET) by switching the polarity of the gate voltage and the polarity of the drain voltage. Therefore, according to the present invention, it is possible to simultaneously and easily manufacture nFETs and pFETs.

[0046] [Embodiment 2] (Field-effect transistor structure) 4 is a cross-sectional view showing a structure of a field-effect transistor (FET) 200 according to a second embodiment of the present invention. As shown in FIG. 4, the FET 200 according to this embodiment includes a substrate 110, an insulating film 120, a core-shell nanowire 130, a first electrode 140, a second electrode 150, a third electrode 210, a gate dielectric film 220, a gate electrode 230, and an insulating protection film 180.

[0047] The FET 200 according to the present embodiment differs from the field-effect transistor 100 according to the first embodiment in that it has a third electrode 210. Hereinafter, the same components as those in the field-effect transistor 100 according to the first embodiment will be denoted by the same reference numerals and will not be described.

[0048] The third electrode 210 is electrically connected to the shell layer 134 of the core-shell nanowire 130. In this embodiment, the third electrode 210 is disposed on the insulating film 120. The third electrode 210 functions as one of a source electrode and a drain electrode for a first conductivity type FET, in which the gate electrode 230 applies an electric field to modulate the thermal diffusion current in the shell layer 134. In this embodiment, the second electrode 150 functions as one of a source electrode and a drain electrode for a second conductivity type TFET, in which the gate electrode 230 applies an electric field to modulate the tunneling current at the junction interface. The first electrode 140 functions as the other of the source electrode and the drain electrode for both the second conductivity type TFET and the first conductivity type FET.

[0049] For example, the first electrode 140 may function as a drain electrode for both the second conductivity type TFET and the first conductivity type FET, the second electrode 150 may function as a source electrode for the second conductivity type TFET, and the third electrode 210 may function as a source electrode for the first conductivity type FET. In this case, the second electrode 150 and the third electrode 210 may be grounded. Alternatively, the first electrode 140 may function as a source electrode for both the second conductivity type TFET and the first conductivity type FET, the second electrode 150 may function as a drain electrode for the second conductivity type TFET, and the third electrode 210 may function as a drain electrode for the first conductivity type FET. In this case, the first electrode 140 may be grounded.

[0050] The type of the third electrode 210 is not particularly limited, but is preferably a metal film, an alloy film, or a metal multilayer film that can make ohmic contact with the shell layer 134. Examples of the third electrode 210 are the same as the examples of the first electrode 140.

[0051] The gate dielectric film 220 covers at least a part of the side surface of the core-shell nanowire 130. In this embodiment, the gate dielectric film 220 covers the lower half of the side surface of the core-shell nanowire 130 and the third electrode 210. Other aspects of the gate dielectric film 220 are the same as those of the gate dielectric film 160 of the FET 100 in the first embodiment.

[0052] The gate electrode 230 is disposed on the gate dielectric film 220 so as to cover at least a portion of the core-shell nanowire 130. More specifically, the gate electrode 230 is disposed on the gate dielectric film 220 so as to apply an electric field to the junction interface between the substrate 110 and the core nanowire 131 and to a region between the connection portion of the shell layer 134 with the first electrode 140 and the connection portion of the shell layer 134 with the third electrode 210. Other aspects of the gate electrode 230 are the same as those of the gate electrode 170 of the FET 100 in the first embodiment.

[0053] (Field-effect transistor operation) Like the FET 100 according to the first embodiment, the FET 200 according to the second embodiment operates as a tunneling field-effect transistor (TFET) of a second conductivity type in which, when the gate voltage has either a positive or negative polarity, the gate electrode 230 applies an electric field to modulate a tunneling current at the junction interface between the substrate 110 and the core nanowire 131. Furthermore, when the gate voltage has the other of a positive and negative polarity, the FET 200 according to the second embodiment operates as a field-effect transistor (FET) of a first conductivity type in which the gate electrode 230 applies an electric field to modulate a thermal diffusion current in the shell layer 134.

[0054] More specifically, when the substrate 110 and the shell layer 134 are p-type (first conductivity type) and the core nanowire 131 is n-type (second conductivity type), the FET 200 operates by changing the polarity of the gate voltage to positive (V G >0), it operates as an n-type TFET (nTFET), and the polarity of the gate voltage is negative (V G<0), it operates as a p-type FET (pFET). When FET 200 operates as an nTFET, a current flows between first electrode 140 and second electrode 150. On the other hand, when FET 200 operates as a pFET, a current flows between first electrode 140 and third electrode 210.

[0055] Also, when the substrate 110 and the shell layer 134 are n-type (first conductivity type) and the core nanowire 131 is p-type (second conductivity type), the FET 200 can be configured such that the polarity of the gate voltage is negative (V G <0), it operates as a p-type TFET (pTFET), and the polarity of the gate voltage is positive (V G >0), it operates as an n-type FET (nFET). When FET 200 operates as a pTFET, a current flows between first electrode 140 and second electrode 150. On the other hand, when FET 200 operates as an nFET, a current flows between first electrode 140 and third electrode 210.

[0056] (effect) As described above, in the FET 200 according to the second embodiment, when operated as a first conductivity type FET, the current flowing between the first electrode 140 (e.g., functioning as a drain electrode) and the third electrode 210 (e.g., functioning as a source electrode) passes only through the shell layer 134, without passing through the heterointerface between the substrate 110 and the core nanowire 131 or the heterointerface between the core nanowire 131 and the shell layer 134. Therefore, in addition to the same effects as the FET 100 according to the first embodiment, the FET 200 according to the second embodiment can increase the drain current when operated as a first conductivity type FET. [Example]

[0057] The present invention will be described in detail below with reference to examples, but the present invention is not limited to these examples.

[0058] 1. Field-effect Transistor Fabrication p-type silicon (111) substrate (carrier concentration: 7 × 10 18 cm-3 ) was thermally oxidized to form a 20 nm thick silicon oxide film on the surface. Electron beam lithography and wet chemical etching were used to form periodic openings in the silicon oxide film, exposing the surface of the silicon substrate. The openings were hexagonal in shape, with a diameter of the circumscribed circle of 80 nm.

[0059] The substrate with the opening formed was placed in a low-pressure horizontal MOVPE reactor (HR2339; Taiyo Nippon Sanso Corporation). The temperature of the silicon substrate was raised to 925°C and maintained for 5 minutes to remove the native oxide film formed on the surface of the opening. The temperature of the silicon substrate was then lowered from 925°C to 400°C. Arsenic hydride was supplied together with hydrogen gas (carrier gas). The partial pressure of arsenic hydride was 1.3 × 10 -4 It was ATM.

[0060] Next, an InGaAs thin film was formed in the opening of the silicon substrate using the alternating source supply modulation method. Specifically, one cycle consisted of a 1-second supply of trimethylindium and trimethylgallium, a 2-second interval of hydrogen gas, a 1-second supply of arsenic hydride, and a 2-second interval of hydrogen gas. This cycle was repeated 20 times over a 2-minute period. The partial pressure of trimethylindium was 4.7 x 10 -7 atm, and the partial pressure of trimethylgallium is 5.7 × 10 -7 atm, and the partial pressure of arsenic hydride is 1.3 × 10 -4 It was ATM.

[0061] Next, after increasing the temperature of the silicon substrate, n-type In was grown by MOVPE with a diameter of 80 nm and a length of 1.2 μm. 0.7 Ga 0.3 As nanowires (core nanowires) were grown. Specifically, the temperature of the silicon substrate was raised from 400 to 670°C, and then trimethylindium, trimethylgallium, arsenic hydride, and monosilane were supplied together with hydrogen gas to grow n-type In nanowires with a length of 100 nm. 0.7 Ga 0.3As nanowires (first region) were grown under a partial pressure of 5.0 × 10 trimethylindium. -7 atm, and the partial pressure of trimethylgallium is 1.0 × 10 -6 atm, and the partial pressure of arsenic hydride is 2.5 × 10 -4 atm, and the partial pressure of monosilane was 1.3 × 10 -7 The dopant (Si) concentration in the first region was 5×10 18 cm -3 Subsequently, trimethylindium, trimethylgallium, arsenic hydride, and monosilane were supplied together with hydrogen gas to form n-type In layers with a length of 1.1 μm. 0.7 Ga 0.3 As nanowires (second region) were grown under a partial pressure of 4.9 × 10 trimethylindium. -7 atm, and the partial pressure of trimethylgallium is 5.7 × 10 -7 atm, and the partial pressure of arsenic hydride is 1.3 × 10 -4 atm, and the partial pressure of monosilane was 7.0 × 10 -8 The dopant (Si) concentration in the second region was 5 × 10 18 cm -3 It was.

[0062] Next, In 0.7 Ga 0.3 A p-type GaSb layer (shell layer) was formed around the As nanowire (core nanowire). Specifically, the temperature of the silicon substrate was set to 580°C, and trimethylgallium, tridimethylaminoantimony, and dimethylzinc were supplied together with hydrogen gas to form the In nanowire. 0.7 Ga 0.3 A GaSb layer (shell layer) with a thickness of 45 nm was formed on the side of the As nanowire (core nanowire). The partial pressure of trimethylgallium was 1.0 × 10 -6 atm, and the partial pressure of tridimethylaminoantimony is 5.0 × 10 -5 atm, and the partial pressure of dimethylzinc is 4.0 × 10 -7 The dopant (Zn) concentration in the GaSb layer (shell layer) was 1×10 19 cm -3 It was.

[0063] Through these steps, core-shell nanowires with a thickness (diameter of the circumscribed circle) of 170 nm and a length of 1.2 μm were formed on the surface of the silicon substrate. Figure 5 is a scanning electron microscope photograph (oblique view) of a silicon substrate on which core-shell nanowires were periodically arranged. As shown in Figure 5, the long axes of the core-shell nanowires were perpendicular to the surface of the silicon substrate.

[0064] A gate dielectric film was formed on the side of the core-shell nanowire, and then a gate electrode was formed on top of it. Specifically, a 10-nm-thick Hf 0.8 Al 0.2 An O film (gate dielectric film) was then formed. A 100-nm-thick W film (gate electrode) was then formed on the silicon substrate side of the core-shell nanowire by radio-frequency sputtering. The length of the gate electrode along the longitudinal axis of the core-shell nanowire was 200 nm.

[0065] Next, an insulating resin (BCB resin) film was formed on the silicon substrate, and the core-shell nanowires on the silicon substrate were embedded in the insulating resin. Next, a portion of the upper surface of the insulating resin was removed by reactive ion etching to expose the tips of the core-shell nanowires.

[0066] Next, a 120-nm-thick Ti (20 nm) / Pd (20 nm) / Au (100 nm) multilayer film was formed on the exposed surface of the core-shell nanowire as the first electrode (drain electrode), and a 50-nm-thick Ti (20 nm) / Au (30 nm) multilayer film was formed on the silicon substrate as the second electrode (source electrode).

[0067] By the above procedure, the FET according to the first embodiment of the present invention was fabricated (see FIG. 1).

[0068] 2.Evaluation of electrical characteristics The electrical characteristics of the FET fabricated by the above process were measured.

[0069] Figure 6A shows the gate voltage (VG ) and drain current (I DS ) is a graph showing the relationship (transfer characteristics) between DS = 0.01V, 0.05V, 0.10V, 0.25V, 0.50V, 0.75V, 1.00V). Figure 6B shows the drain voltage (V DS ) and drain current (I DS ) (output characteristics) G = 0V to 1.0V, in 0.10V increments).

[0070] As shown in Figures 6A and 6B, the polarity of the drain-source voltage is changed to positive (V DS >0), and the polarity of the gate voltage is positive (V G >0), the drain current is modulated by the gate bias. This shows that the FET operates as an nFET. The ON / OFF ratio is about 10 3 The minimum subthreshold coefficient was 105 mV / decade.

[0071] Figure 7A shows the gate voltage (V G ) and drain current (I DS ) is a graph showing the relationship (transfer characteristics) between DS = -1.50V, -1.25V, -1.00V, -0.75V, -0.50V). Figure 7B shows the drain voltage (V DS ) and drain current (I DS ) (output characteristics) G =-1.0V to 0V, in 0.10V increments).

[0072] As shown in Figures 7A and 7B, the polarity of the drain-source voltage is changed to negative (V DS <0), and the polarity of the gate voltage is negative (V G <0), the drain current is modulated by the gate bias. This shows that the FET operates as a pFET. The ON / OFF ratio is about 10 2The minimum subthreshold coefficient was 115 mV / decade.

[0073] This application claims priority from Japanese Patent Application No. 2022-048567, filed March 24, 2022. The contents of the specification and drawings of that application are incorporated herein by reference in their entirety. [Industrial Applicability]

[0074] The FET according to the present invention is useful, for example, as a switching element formed in semiconductor microprocessors and highly integrated circuits. [Explanation of symbols]

[0075] 100, 200 Field-effect transistor 110 Substrate 120 insulating film 130 Core-shell nanowires 131 Core Nanowire 132 First area 133 Second area 134 Shell Layer 140 1st electrode 150 2nd electrode 160, 220 Gate dielectric film 170, 230 gate electrode 180 Insulating protective film 210 3rd electrode

Claims

1. a substrate having a (111) surface and made of a group IV semiconductor doped to a first conductivity type; an insulating film having an opening and covering the (111) plane of the substrate; a core-shell nanowire including: a core nanowire connected to the (111) plane of the substrate exposed in the opening and made of a III-V compound semiconductor doped with a second conductivity type different from the first conductivity type; and a shell layer disposed on the insulating film around the opening so as to cover the core nanowire and made of a III-V compound semiconductor doped with the first conductivity type; a first electrode electrically connected to the shell layer; a second electrode electrically connected to the substrate; a gate electrode for applying an electric field to the junction interface between the substrate and the core nanowire and to the shell layer; and the shell layer covers the side surface of the core nanowire and the end surface on the first electrode side; Field effect transistor.

2. the core nanowire includes a first region connected to the (111) plane and a second region; The impurity density of the first region is different from the impurity density of the second region.

2. The field effect transistor of claim 1.

3. Further comprising a gate dielectric film disposed on a side surface of the core-shell nanowire; the gate electrode is disposed on the gate dielectric film; 2. The field effect transistor of claim 1.

4. a third electrode electrically connected to the shell layer; the gate electrode is disposed so as to apply an electric field to a bonding interface between the substrate and the core nanowire and to a region of the shell layer between a connection portion with the first electrode and a connection portion with the third electrode.

2. The field effect transistor of claim 1.

5. The field effect transistor is When the polarity of the gate voltage is set to either positive or negative, the gate electrode acts on the transistor to modulate a tunnel current at the junction interface, thereby operating as the tunnel field effect transistor of the second conductivity type; When the polarity of the gate voltage is the other of positive and negative, the gate electrode acts on the semiconductor substrate to modulate the current in the shell layer, thereby operating as a field effect transistor of the first conductivity type.

2. The field effect transistor of claim 1.

6. A switching element comprising the field effect transistor according to any one of claims 1 to 5.

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