On-chip antenna

Abstract

To increase a signal radiation amount of an on-chip antenna.SOLUTION: An on-chip antenna includes a handle layer 1, a first insulating layer 2 provided on the handle layer 1, a device layer 3 provided on the first insulating layer 2, a second insulating layer 4 provided on the device layer 3, and an antenna 5 provided on the second insulating layer 4. The handle layer 1, the first insulating layer 2, and the device layer 3 are constructed using an SOI substrate. Of the handle layer 1 and the device layer 3, the device layer 3 is connected to ground and the handle layer 1 is floated.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an on-chip antenna in which a semiconductor integrated circuit chip and an antenna are integrated together. [Background technology]

[0002] 2. Description of the Related Art On-chip antennas are known in which an antenna is provided on a chip of a semiconductor integrated circuit in order to reduce size and cost.

[0003] Non-Patent Document 1 describes an on-chip antenna in which a meander dipole antenna is formed on a Si substrate.

[0004] Patent Document 1 describes forming an insulating layer in a grid pattern directly below the on-chip coil, thereby suppressing the generation of eddy currents and improving the amount of magnetic field radiation.

[0005] Patent Document 2 describes forming a depletion layer directly below the on-chip coil, thereby suppressing the generation of eddy currents, as in Patent Document 1. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 10-321802 [Patent Document 2] Japanese Patent Application Laid-Open No. 2009-252965 [Non-patent literature]

[0007] [Non-Patent Document 1] H.Kikkawa, et al., “Gaussian Monocycle Pulse Transmitter Using 0.18um CMOS Technology With On-Chip integrated Antennas for Inter-Chip UWB Communication”, JSSC, 2008 Summary of the Invention [Problem to be solved by the invention]

[0008] As described in Non-Patent Document 1, in a typical Si substrate, the Si substrate is connected to the ground for the operation of the circuit mounted together with the on-chip antenna, which causes the bottom surface of the on-chip antenna to become the ground surface, resulting in a problem of reduced signal radiation from the on-chip antenna.

[0009] Furthermore, although the methods of Patent Documents 1 and 2 are effective for magnetic field radiation antennas, they are less effective for electric field radiation antennas.

[0010] SUMMARY OF THE INVENTION An object of the present invention is to increase the amount of signal radiation from an on-chip antenna. [Means for solving the problem]

[0011] The present invention provides a semiconductor device having a handle layer made of Si, a first insulating layer made of an insulator and provided on the handle layer, a device layer made of Si and provided on the first insulating layer, a second insulating layer made of an insulator and provided on the device layer, and an antenna made of a conductor with a predetermined planar pattern and provided on the second insulating layer, The handle layer is connected to ground, and the device layer is a floating on-chip antenna. The present invention also provides an on-chip antenna comprising: a handle layer made of Si; a first insulating layer made of an insulator and provided on the handle layer; a device layer made of Si and provided on the first insulating layer; a second insulating layer made of an insulator and provided on the device layer; and an antenna made of a conductor with a predetermined planar pattern and provided on the second insulating layer, wherein at least one of the handle layer and the device layer is floating, and the resistivity of the handle layer and the device layer is 10 Ω cm or less. The present invention also provides an on-chip antenna comprising: a handle layer made of Si; a first insulating layer made of an insulator and provided on the handle layer; a device layer made of Si and provided on the first insulating layer; a second insulating layer made of an insulator and provided on the device layer; and an antenna made of a conductor with a predetermined planar pattern and provided on the second insulating layer, wherein the handle layer and the device layer are floating.

[0012] In the present invention, it is preferable that the thinner of the handle layer and the device layer is connected to ground.

[0013] In the present invention, the handle layer may be connected to ground.

[0014] In the present invention, the resistivity of the handle layer and the device layer is preferably 10 Ω·cm or less.

[0015] In the present invention, the antenna may be of the field emission type.

[0016] In the present invention, the antenna may be a meander antenna, and the device layer may include a Si oscillator circuit. [Effects of the Invention]

[0017] According to the present invention, the amount of signal radiation from the on-chip antenna can be increased. [Brief explanation of the drawings]

[0018] [Figure 1] FIG. 2 is a diagram showing the configuration of an on-chip antenna according to the first embodiment. [Figure 2] FIG. 4 is a diagram showing a modified example of the on-chip antenna of the first embodiment. [Figure 3] FIG. 1 is a diagram showing the planar pattern of a meander antenna. [Figure 4] 10 is a graph showing frequency characteristics of signal propagation amount. [Figure 5] 10 is a graph showing frequency characteristics of signal propagation amount. [Figure 6] 10 is a graph showing frequency characteristics of signal propagation amount. DETAILED DESCRIPTION OF THE INVENTION

[0019] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0020] (First embodiment) Fig. 1 is a diagram showing the configuration of an on-chip antenna according to the first embodiment. As shown in Fig. 1, the on-chip antenna according to the first embodiment has a handle layer 1, a first insulating layer 2 provided on the handle layer 1, a device layer 3 provided on the first insulating layer 2, a second insulating layer 4 provided on the device layer 3, and an antenna 5 provided on the second insulating layer 4. The handle layer 1, the first insulating layer 2, and the device layer 3 are formed using an SOI substrate.

[0021] The handle layer 1 is a layer made of Si. The thickness of the handle layer 1 is, for example, 100 to 1000 μm. The handle layer 1 may be doped with impurities to control its conductivity type, and may be any of n-type, intrinsic, or p-type.

[0022] The first insulating layer 2 is a layer made of an insulator and provided on the handle layer 1. The material of the first insulating layer 2 may be any material that can sufficiently insulate the handle layer 1 from the device layer 3, such as SiO2. The thickness of the first insulating layer 2 may also be within a range that can sufficiently insulate the handle layer 1 from the device layer 3, such as 0.1 to 10 μm.

[0023] The device layer 3 is a layer made of Si provided on the first insulating layer 2. The device layer 3 includes an integrated circuit (not shown) configured with semiconductor elements made of Si. The integrated circuit includes, for example, a Si oscillator circuit. The thickness of the device layer 3 is, for example, 1 to 100 μm. In an SOI substrate, the device layer 3 is usually thinner than the handle layer 1. The device layer 3 may be doped with impurities to control its conductivity type, and may be any of n-type, intrinsic, or p-type.

[0024] The resistivity of the handle layer 1 and the device layer 3 is preferably 10 Ω·cm or less. If the resistivity of the handle layer 1 and the device layer 3 is 10 Ω·cm or less, the presence of a Si layer directly below the antenna 5 significantly reduces the amount of signal radiation from the antenna 5, but according to the first embodiment, this reduction in signal radiation can be effectively suppressed. The resistivity is more preferably 5 Ω·cm or less, and even more preferably 1 Ω·cm or less.

[0025] Of the handle layer 1 and device layer 3, the device layer 3 is connected to the ground and the handle layer 1 is left floating. Conversely, the handle layer 1 may be connected to the ground and the device layer 3 may be left floating (Fig. 2). Also, both the handle layer 1 and the device layer 3 may be left floating.

[0026] The connection to ground is, for example, as follows: A ground pattern is formed on the mounting substrate on which the on-chip antenna of the first embodiment is mounted, and wiring is formed to connect to the ground pattern. When connecting the handle layer 1 to ground, the on-chip antenna of the first embodiment is mounted on the mounting substrate so that the wiring on the mounting substrate contacts the handle layer 1. When connecting the device layer 3 to ground, part of the second insulating layer 4 is removed to expose the device layer 3, and after mounting the on-chip antenna of the first embodiment on the mounting substrate, the exposed device layer 3 is connected to the wiring on the mounting substrate by wire bonding, thereby connecting to ground.

[0027] The second insulating layer 4 is a layer made of an insulator and provided on the device layer 3. The material of the second insulating layer 4 may be any material that can sufficiently insulate the device layer 3 from the antenna 5, such as SiO2. The first insulating layer 2 and the second insulating layer 4 may be made of the same material. The thickness of the second insulating layer 4 may also be within a range that can sufficiently insulate the device layer 3 from the antenna 5, such as 1 to 500 μm.

[0028] The antenna 5 is provided on the second insulating layer 4 and is a conductive film formed in a predetermined planar pattern. The conductive material is Al, Cu, Au, or the like. The antenna 5 is connected to the integrated circuit in the device layer 3. The antenna 5 may be located above the integrated circuit.

[0029] The planar pattern of the antenna 5 may be any pattern capable of transmitting and receiving electromagnetic waves. For example, it may be a meander antenna with a line folded in a zigzag pattern (see Figure 3). Using a meander antenna allows the antenna's bandwidth to be widened. A meander antenna is suitable when the device layer 3 includes a Si oscillator circuit. Si oscillator circuits have frequency variations due to variations in transistor characteristics and temperature characteristics, but a wideband meander antenna can be used to operate even with frequency variations. The line width and number of folds of the meander antenna are set according to the coaxial frequency and bandwidth. In addition to meander antennas, square, rectangular, or circular patch antennas may also be used.

[0030] Furthermore, it is preferable that the antenna 5 be of a field emission type. With conventional on-chip antennas, it has been difficult to increase the amount of signal radiation of field emission antennas, but with the on-chip antenna of the first embodiment, it is possible to increase the amount of signal radiation even for field emission antennas.

[0031] The resonant frequency of the antenna 5 is not particularly limited, but is preferably higher than the operating frequency of the circuit in the device layer 3. For example, if the operating frequency of the circuit is 1 to 2 GHz, the resonant frequency of the antenna 5 is preferably 2 to 3 GHz.

[0032] In addition to the antenna 5, wiring (not shown) is provided on the second insulating layer 4 to connect the elements of the integrated circuit in the device layer 3. The elements in the device layer 3 are connected to the wiring on the second insulating layer 4 through holes formed in the second insulating layer 4. Multilayer wiring may be used in which the second insulating layer 4 and the wiring are alternately layered.

[0033] The on-chip antenna of the first embodiment can increase the amount of signal radiation compared to conventional on-chip antennas for the following reasons.

[0034] Since Si is conductive, the Si layer connected to the ground below the antenna 5 functions as the ground plane of the antenna 5. Generally, the presence of a ground plane below the antenna 5 reduces the amount of signal radiation. Therefore, in the on-chip antenna of the first embodiment, only one of the handle layer 1 and the device layer 3 is connected to the ground, and the other is left floating. This reduces the total thickness of the Si layer connected to the ground, weakening the function of the Si layer as the ground plane of the antenna 5. As a result, the on-chip antenna of the first embodiment can increase the amount of signal radiation from the antenna 5.

[0035] As can be seen from the above reasons, it is preferable to connect the thinner of the handle layer 1 and the device layer 3 to ground. Usually, in an SOI substrate, the device layer 3 is thinner than the handle layer 1, so it is preferable to connect the device layer 3 to ground.

[0036] As described above, in the on-chip antenna of the first embodiment, the amount of signal radiation from the antenna 5 can be improved.

[0037] Next, the simulation results for the first embodiment will be described.

[0038] Two on-chip antennas of the first embodiment were prepared, each with a meandering antenna 5 having a resonant frequency of 3 GHz. The two on-chip antennas were arranged so that the antennas 5 were 5 mm apart. The handle layer 1 and the device layer 3 were changed to a total of four states: connected to ground and floating. The resistivities of the handle layer 1 and the device layer 3 were set to three values: 40 Ω·cm, 10 Ω·cm, and 1 Ω·cm. Hereinafter, Example 1 will be referred to as Example 1, where the handle layer 1 was connected to ground and the device layer 3 was floating; Example 2, where the device layer 3 was connected to ground and the handle layer 1 was floating; Example 3, where both were floating; and Comparative Example 1, where both were connected to ground. The antenna 5 was evaluated alone, without being connected to the circuit of the device layer 3.

[0039] 4 to 6 are graphs showing the frequency characteristics of the signal propagation amount between the antennas 5. FIG. 4 shows the case where the resistivity of the handle layer 1 and the device layer 3 is 40 Ω·cm, FIG. 5 shows the case where it is 10 Ω·cm, and FIG. 6 shows the case where it is 1 Ω·cm. Looking at the graphs in FIGS. 5 and 6, it was found that the signal propagation amount increases in the following order: Example 3, Example 1, Example 2, and Comparative Example 1. As a result, it was found that the fewer the number of layers connected to ground, the greater the signal propagation amount. Furthermore, since the signal propagation amount was greater when the device layer 3 was connected to ground than when the handle layer 1 was connected to ground, it was found that the thinner the total thickness of the Si layers connected to ground (the handle layer 1 and the device layer 3) was, the greater the signal propagation amount. Furthermore, it was found that the lower the resistivity of the Si layer, the more the connection state with ground affects the signal propagation amount, and this effect was found to be significant when the resistivity was 10 Ω·cm or less. [Industrial Applicability]

[0040] The present invention can be used for various types of communication. [Explanation of symbols]

[0041] 1: Handle layer 2: First insulating layer 3: Device layer 4: Second insulating layer 5: Antenna

Claims

1. a handle layer made of Si; a first insulating layer formed on the handle layer and made of an insulator; a device layer made of Si and provided on the first insulating layer; a second insulating layer formed on the device layer and made of an insulator; an antenna provided on the second insulating layer and made of a conductor having a predetermined planar pattern; and the handle layer is connected to ground; the device layer is floating; An on-chip antenna characterized by:

2. a handle layer made of Si; a first insulating layer formed on the handle layer and made of an insulator; a device layer made of Si and provided on the first insulating layer; a second insulating layer formed on the device layer and made of an insulator; an antenna provided on the second insulating layer and made of a conductor having a predetermined planar pattern; and At least one of the handle layer and the device layer is floating; The on-chip antenna is characterized in that the resistivity of the handle layer and the device layer is 10 Ω·cm or less.

3. a handle layer made of Si; a first insulating layer formed on the handle layer and made of an insulator; a device layer made of Si and provided on the first insulating layer; a second insulating layer formed on the device layer and made of an insulator; an antenna provided on the second insulating layer and made of a conductor having a predetermined planar pattern; and the handle layer and the device layer are floating; An on-chip antenna characterized by:

4. The on-chip antenna according to claim 2 , wherein the thinner of the handle layer and the device layer is connected to ground.

5. The on-chip antenna according to claim 2 , wherein the handle layer is connected to ground.

6. 4. The on-chip antenna according to claim 1, wherein the handle layer and the device layer have resistivities of 10 Ω·cm or less.

7. 7. The on-chip antenna according to claim 1, wherein the antenna is a field emission type.

8. 8. The on-chip antenna according to claim 1, wherein the antenna is a meander antenna, and the device layer includes a Si oscillator circuit.

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