Semiconductor Devices

Abstract

To provide a semiconductor device capable of reducing power consumption.SOLUTION: A semiconductor device according to an embodiment includes: a first electrode, an n-type first semiconductor region, a p-type second semiconductor region, an n-type third semiconductor region, a gate electrode, and a second electrode. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on the first semiconductor region and includes a first contact region. The third semiconductor region is provided on a portion of the second semiconductor region. The third semiconductor region includes a second contact region. A concentration of a first element in the second contact region is less than a concentration of the first element in the first contact region. The first element is at least one selected from the group consisting of platinum group elements and gold. The gate electrode faces the second semiconductor region via a gate insulating layer. The second electrode is provided on the second and third semiconductor regions and is in contact with the first and second contact regions.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] Semiconductor devices such as metal oxide semiconductor field effect transistors (MOSFETs) are used for applications such as power conversion, etc. It is desirable for semiconductor devices to consume small amounts of power. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-27229 Summary of the Invention [Problem to be solved by the invention]

[0004] An embodiment of the present invention provides a semiconductor device capable of reducing power consumption. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first electrode, an n-type first semiconductor region, a p-type second semiconductor region, an n-type third semiconductor region, a gate electrode, and a second electrode. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on the first semiconductor region and includes a first contact region. The third semiconductor region is provided on a portion of the second semiconductor region. The third semiconductor region includes a second contact region. The concentration of a first element in the second contact region is lower than the concentration of the first element in the first contact region. The first element is at least one selected from the group consisting of gold and platinum-group elements. The gate electrode faces the second semiconductor region via a gate insulating layer. The second electrode is provided on the second semiconductor region and the third semiconductor region and contacts the first contact region and the second contact region. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a perspective cross-sectional view showing a semiconductor device according to a first embodiment. [Figure 2] 2(a) and 2(b) are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 3] 3(a) and 3(b) are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 4] 4(a) and 4(b) are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 5] FIG. 5 is a perspective cross-sectional view showing a semiconductor device according to a first modification of the first embodiment. [Figure 6] FIG. 6 is a perspective cross-sectional view showing a semiconductor device according to a first modification of the first embodiment. [Figure 7] 7(a) and 7(b) are cross-sectional views showing a method for manufacturing a semiconductor device according to a first modification of the first embodiment. [Figure 8] FIG. 8 is a perspective cross-sectional view showing a semiconductor device according to a second modification of the first embodiment. [Figure 9] FIG. 9 is a perspective cross-sectional view showing a semiconductor device according to a third modification of the first embodiment. [Figure 10] FIG. 10 is a perspective cross-sectional view showing a semiconductor device according to the second embodiment. [Figure 11] FIG. 11 is a cross-sectional view showing a semiconductor device according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In the present specification and the drawings, elements similar to those already explained are given the same reference numerals and detailed explanations will be omitted as appropriate. In the following description and drawings, n + , n, n - and p + , p, p - The notation indicates the relative level of each impurity concentration. That is, a notation with a "+" indicates a relatively higher impurity concentration than a notation with neither a "+" nor a "-" and a notation with a "-" indicates a relatively lower impurity concentration than a notation with neither a "+" nor a "-". When both p-type and n-type impurities are contained in each region, these notations indicate the relative level of the net impurity concentration after the impurities compensate for each other.

[0008] (First embodiment) FIG. 1 is a perspective cross-sectional view showing a semiconductor device according to a first embodiment. The semiconductor device according to the first embodiment is a MOSFET. As shown in FIG. - a p-type drift region 1 (first semiconductor region), a p-type base region 2 (second semiconductor region), and +A source region 3 (third semiconductor region) of the n type + The semiconductor device includes a drain region 4, a gate electrode 10, a drain electrode 21 (first electrode), and a source electrode 22 (second electrode). In Fig. 1, the source electrode 22 is indicated by a dashed line.

[0009] An XYZ Cartesian coordinate system is used to explain the embodiments. The direction from the drain electrode 21 toward the drift region 1 is defined as the Z direction (first direction). A direction perpendicular to the Z direction is defined as the X direction (second direction). A direction perpendicular to the X and Z directions is defined as the Y direction. Here, the direction from the drain electrode 21 toward the drift region 1 is referred to as "up," and the opposite direction is referred to as "down." These directions are based on the relative positional relationship between the drain electrode 21 and the drift region 1 and are unrelated to the direction of gravity.

[0010] The drain electrode 21 is provided on the bottom surface of the semiconductor device 100. The drain region 4 is an n + The drift region 1 is formed on the drain electrode 21 and is electrically connected to the drain electrode 21. The drift region 1 is formed on the drain region 4.

[0011] The drift region 1 is electrically connected to the drain electrode 21 via the drain region 4. The base region 2 is provided on the drift region 1. The source region 3 is provided on a part of the base region 2.

[0012] The gate electrode 10 faces the base region 2 via a gate insulating layer 11. In the semiconductor device 100, the gate electrode 10 faces a part of the drift region 1, the base region 2, and the source region 3 via the gate insulating layer 11 in the X direction.

[0013] The source electrode 22 is provided on the base region 2 and the source region 3 and is electrically connected to the base region 2 and the source region 3. A gate insulating layer 11 is provided between the gate electrode 10 and the source electrode 22, and the source electrode 22 is electrically isolated from the gate electrode 10.

[0014] The base region 2 includes a contact region 2a (first contact region) in contact with the source electrode 22. The source region 3 includes a contact region 3a (second contact region) in contact with the source electrode 22.

[0015] The contact region 2a contains a first element, which is at least one selected from the group consisting of gold and platinum-group elements. The platinum-group element is at least one selected from the group consisting of ruthenium, rhodium, palladium, osmium, iridium, and platinum. The concentration of the first element in the contact region 2a is higher than the concentration of the first element in the contact region 3a. The contact region 3a may not contain the first element. In other words, the concentration of the first element in the contact region 3a may be zero.

[0016] In addition to the contact region 2a, the drift region 1 may also contain the first element. For example, the drift region 1 includes a first region 1a aligned with the gate electrode 10 in the X direction and a second region 1b provided below the first region 1a. The second region 1b is located between the drain electrode 21 and the gate electrode 10 in the Z direction. The first region 1a contains the first element. The concentration of the first element in the first region 1a is higher than the concentration of the first element in the second region 1b. The second region 1b may not contain the first element. That is, the concentration of the first element in the second region 1b may be zero.

[0017] The contact region 2a may contain a silicide of the first element. Alternatively, the contact region 3a may contain a silicide of a metal element contained in the source electrode 22. The contact region 3a does not contain a silicide of the first element.

[0018] The base region 2, the contact region 2a, the source region 3, the contact region 3a, and the gate electrode 10 each extend in the Y direction, and a plurality of them are provided in the X direction. The source electrode 22 is provided on the plurality of base regions 2 and the plurality of source regions 3, and is electrically connected to the plurality of base regions 2 and the plurality of source regions 3.

[0019] The operation of the semiconductor device 100 will now be described. With a positive voltage applied to the drain electrode 21 relative to the source electrode 22, a voltage equal to or greater than the threshold is applied to the gate electrode 10. This forms a channel (inversion layer) in the base region 2, turning the semiconductor device 100 on. Electrons flow through the channel from the source electrode 22 to the drain electrode 21. When the voltage applied to the gate electrode 10 becomes lower than the threshold, the channel in the base region 2 disappears, turning the semiconductor device 100 off.

[0020] An example of the material of each component of the semiconductor device 100 will be described. The drift region 1, the base region 2, the source region 3, and the drain region 4 include semiconductor materials. The semiconductor material may be silicon, silicon carbide, gallium nitride, or gallium arsenide. Among these materials, silicon is preferred. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony may be used as the n-type impurity. Boron may be used as the p-type impurity.

[0021] The gate electrode 10 includes polysilicon. The gate insulating layer 11 includes an insulating material. For example, the gate insulating layer 11 includes silicon oxide, silicon nitride, or silicon oxynitride. The drain electrode 21 and the source electrode 22 include a metal such as titanium, aluminum, or copper.

[0022] 2(a) to 4(b) are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment. First, n + A semiconductor substrate including a semiconductor layer 4x is provided. + On the semiconductor layer 4x, a semiconductor material is epitaxially grown to form n - As shown in FIG. 2(a), a n-type semiconductor layer 1x is formed by reactive ion etching (RIE). - A part of the semiconductor layer 1x is removed, and n - An opening OP1 is formed in the semiconductor layer 1x. The opening OP1 extends in the Y direction, and a plurality of openings OP1 are formed in the X direction.

[0023] The inner surface of the opening OP1 and - An insulating layer 11x is formed along the upper surface of the semiconductor layer 1x by thermal oxidation. A conductive layer is formed on the insulating layer 11x by chemical vapor deposition (CVD). The upper surface of the conductive layer is recessed by chemical dry etching (CDE) or wet etching. As a result, a gate electrode 10 is formed inside the opening OP1, as shown in FIG. 2(b).

[0024] n - p-type impurities and n-type impurities are ion-implanted sequentially into the upper surface of the p-type semiconductor layer 1x, forming p-type semiconductor regions 2x and n-type semiconductor regions 2x. + The p-type semiconductor region 3x is formed by CVD. + An insulating layer 11y is formed on the p-type semiconductor region 3x. As shown in FIG. 3(a), a part of the insulating layer 11y is removed by RIE to form an opening OP2 in the insulating layer 11y. + A part of the semiconductor region 3x is exposed through the opening OP2.

[0025] As shown in FIG. 3(b), a mask M is formed on the insulating layer 11y. For example, the mask M is a photoresist, and is processed into a predetermined shape by photolithography. The mask M may be a hard mask containing a metal material or an insulating material. The mask M is formed on the surface of the insulating layer 11y and the n - It may be formed along the top surface of the semiconductor layer 1x. + The p-type semiconductor region 3x is covered by the mask M. At least a part of the p-type semiconductor region 2x is not covered by the mask M.

[0026] Mask M by n + With the p-type semiconductor region 3x covered, a first element is supplied to the p-type semiconductor region 2x. The first element is supplied to the p-type semiconductor region 2x by ion implantation or sputtering. By supplying the first element, a silicide layer 2y is formed on the upper surface of the p-type semiconductor region 2x. The silicide layer 2y contains a silicide of the first element. Furthermore, by heat treatment, n - The first element diffuses into the semiconductor layer 1x.

[0027] As an example, epitaxially grown n - The thickness of the p-type semiconductor layer 1x is 13 μm. The depth of the opening OP1 is 2 μm. The thickness of the p-type semiconductor region 2x is 1.5 μm. After diffusion by heat treatment, the concentration of the first element at a depth of about 3 μm from the top surface of the p-type semiconductor region 2x is 1.0×10 17 / cm -3 At a depth of 6 μm from the top surface of the p-type semiconductor region 2x, the concentration of the first element is 1.0 × 10 16 / cm -3 is.

[0028] The mask M is removed. As shown in FIG. 4(a), the p-type semiconductor region 2x, the silicide layer 2y, and the n + Metal layers 22x to 22z are sequentially formed on the shaped semiconductor region 3x by sputtering. The metal layer 22x contains titanium. The metal layer 22y is provided on the metal layer 22x and contains nitrogen and titanium. The metal layer 22z is provided on the metal layer 22y and contains aluminum. The metal layer 22z may further contain copper. The titanium and n of the metal layer 22x + The silicide layer 3y is formed by reacting with the silicon-containing semiconductor region 3x. + The semiconductor layer 4x is then grown to a predetermined thickness. + The bottom surface of the semiconductor layer 4x is ground. By sputtering aluminum, the n-type semiconductor layer 4x is formed as shown in FIG. 4(b). + A metal layer 21x is formed on the lower surface of the semiconductor layer 4x. In this way, the semiconductor device 100 is manufactured.

[0029] n shown in Figure 4(b) - The p-type semiconductor layer 1x corresponds to the drift region 1 of the semiconductor device 100 shown in FIG. 1. The p-type semiconductor region 2x corresponds to the base region 2. The silicide layer 2y corresponds to the contact region 2a. + The semiconductor region 3x corresponds to the source region 3. The silicide layer 3y corresponds to the contact region 3a. +The shaped semiconductor layer 4x corresponds to the drain region 4. The insulating layers 11x and 11y correspond to the gate insulating layer 11. The metal layer 21x corresponds to the drain electrode 21. The metal layers 22x to 22z correspond to the source electrode 22.

[0030] The advantages of the embodiment will be described. In order to reduce the switching loss of the semiconductor device 100, it is preferable that the semiconductor region contains the first element. When the semiconductor region contains the first element, the carrier lifetime, which is the period from when carriers are generated until when they disappear, becomes shorter. For example, when the semiconductor device 100 is turned off, the carriers accumulated in the semiconductor region disappear more quickly, thereby shortening the switching time of the semiconductor device 100. This reduces the switching loss of the semiconductor device 100 and the power consumption of the semiconductor device 100.

[0031] In particular, when the contact region 2a contains platinum as the first element, the Schottky barrier against holes between the base region 2 and the source electrode 22 is reduced. This reduces the electrical resistance between the base region 2 and the source electrode 22, further reducing the power consumption of the semiconductor device 100.

[0032] On the other hand, if the contact region 3a contains the first element, the characteristics of the semiconductor device 100 may be degraded. For example, the first element inhibits the reaction between the semiconductor contained in the source region 3 and the metal contained in the source electrode 22, increasing the electrical resistance between the source region 3 and the source electrode 22. In particular, if the first element is platinum, the semiconductor material and platinum react with each other and agglomerate. The silicide formed by the agglomeration inhibits the formation of a silicide between the semiconductor contained in the source region 3 and the metal contained in the source electrode 22, increasing the Schottky barrier against electrons.

[0033] To address this issue, in the semiconductor device 100 according to the embodiment, the concentration of the first element in the contact region 3a is lower than the concentration of the first element in the contact region 2a. The relatively low concentration of the first element in the contact region 3a can suppress deterioration in the characteristics of the semiconductor device 100. For example, silicide of the first element is not formed, and an increase in electrical resistance between the source region 3 and the source electrode 22 is suppressed. Furthermore, the relatively high concentration of the first element in the contact region 2a can shorten the carrier lifetime and reduce switching loss of the semiconductor device 100.

[0034] According to the first embodiment, it is possible to reduce the switching loss of the semiconductor device 100 while suppressing deterioration in the characteristics of the semiconductor device 100.

[0035] The contact region 2a preferably contains a silicide of the first element. When the contact region 2a contains a silicide of the first element, the electrical resistance to holes between the base region 2 and the source electrode 22 is further reduced. This allows the power consumption of the semiconductor device 100 to be reduced.

[0036] The contact region 3a preferably contains a silicide of the metal contained in the source electrode 22. When the contact region 3a contains a silicide, the electrical resistance to electrons between the source region 3 and the source electrode 22 is further reduced, thereby reducing the power consumption of the semiconductor device 100.

[0037] In addition to the base region 2, the drift region 1 also preferably contains the first element. When the drift region 1 contains the first element, carriers can be eliminated more quickly in a wider region of the semiconductor device 100. This further reduces the switching loss of the semiconductor device 100. For example, the concentration of the first element in the first region 1a is higher than the concentration of the first element in the second region 1b. The first region 1a is located between the gate electrodes 10 in the X direction.

[0038] (First Modification) 5 and 6 are perspective cross-sectional views showing a semiconductor device according to a first modification of the first embodiment. 5 and 6 further includes a conductive portion 15. The conductive portion 15 is provided in the drift region 1 via an insulating layer 16. At least a portion of the conductive portion 15 is located below the gate electrode 10.

[0039] The conductive portion 15 extends in the Y direction, and a plurality of conductive portions 15 are provided in the X direction. For example, the end portion of the conductive portion 15 in the Y direction is pulled upward and contacts the source electrode 22. The conductive portion 15 is electrically isolated from the gate electrode 10.

[0040] Alternatively, the conductive portion 15 may be in contact with the gate electrode 10 and electrically connected to the gate electrode 10. In this case, the conductive portion 15 is electrically isolated from the source electrode 22.

[0041] Furthermore, in the semiconductor device 110, a portion of the source electrode 22 extends toward the base region 2. The portion of the source electrode 22 is located within the base region 2 and is aligned with a portion of the base region 2 and a portion of the source region 3 in the X direction.

[0042] The contact region 2a is located lower than the contact region 3a. For example, as shown in FIG. 5, the contact region 2a extends in the X direction along the boundary between the base region 2 and the source electrode 22. As shown in FIG. 6, the contact region 2a may be provided over a wider range. Specifically, a portion of the contact region 2a may be provided along the X direction, and another portion of the contact region 2a may be provided along a direction inclined toward the X direction.

[0043] In the drift region 1, the first region 1a is aligned with the gate electrode 10 and the conductive portion 15 in the X direction. The second region 1b is provided below the first region 1a and is located between the drain electrode 21 and the conductive portion 15 in the Z direction. The concentration of the first element in the first region 1a is higher than the concentration of the first element in the second region 1b.

[0044] Figs. 7(a) and 7(b) are cross-sectional views showing a method of manufacturing a semiconductor device according to a first modification of the first embodiment. Perform the same process as the process shown in Fig. 2(a), and form an opening OP1 in the n - type semiconductor layer 1x. At this time, form an opening OP1 deeper than the example shown in Fig. 2(a). In the opening OP1, form an insulating layer 16x, a conductive portion 15, an insulating layer 11x, and a gate electrode 10. Perform the same process as the process shown in Fig. 3(a), and form a p-type semiconductor region 2x, n + type semiconductor region 3x, an insulating layer 11y, etc. Then, when forming the opening OP2, in addition to a part of the insulating layer 11y, remove a part of the n + type semiconductor region 3x and a part of the p-type semiconductor region 2x. Thereby, as shown in Fig. 7(a), an opening OP2 reaching the p-type semiconductor region 2x is formed.

[0045] As shown in Fig. 7(b), form a mask M on the insulating layer 11y. The n + type semiconductor region 3x is covered by the mask M. At least a part of the p-type semiconductor region 2x is not covered by the mask M.

[0046] Supply a first element to the p-type semiconductor region 2x by ion implantation or sputtering. For example, a silicide layer 2y can be formed on a part of the p-type semiconductor region 2x at the bottom of the opening OP2 by ion implantation from a direction parallel to the Z direction, or by long-throw sputtering with high particle straightness.

[0047] Oblique rotation ion implantation from a direction inclined with respect to the Z direction, or normal sputtering with lower particle straightness than long-throw sputtering may be performed. In this case, the first element is also supplied to the lower part of the side surface of the opening OP2. As a result, as shown in Fig. 6, a contact region 2a (silicide layer) is formed along a direction inclined in the X direction.

[0048] The processes after Fig. 7(b) are the same as those in Figs. 4(a) and 4(b). Through the above processes, a semiconductor device 110 according to the first modification is manufactured.

[0049] When the semiconductor device 110 is switched to the off state, the positive voltage applied to the drain electrode 21 with respect to the source electrode 22 increases. When the conductive portion 15 is provided, a depletion layer spreads from the interface between the drift region 1 and the insulating layer 16 toward the drift region 1 due to the potential difference between the conductive portion 15 and the drain electrode 21. This spread of the depletion layer can increase the breakdown voltage of the semiconductor device 110. Alternatively, the n-type impurity concentration in the drift region 1 can be increased while maintaining the breakdown voltage of the semiconductor device 110, thereby reducing the on-resistance of the semiconductor device 110.

[0050] (Second Modification) FIG. 8 is a perspective cross-sectional view showing a semiconductor device according to a second modification of the first embodiment. The semiconductor device 120 according to the second modification has a different structure of the base region 2 compared to the semiconductor device 110.

[0051] In the semiconductor device 120, the base region 2 includes a high-concentration region 2b in addition to a contact region 2a. The p-type impurity concentration of the high-concentration region 2b is higher than the p-type impurity concentration of other regions. For example, the silicide of the contact region 2a is located between the high-concentration region 2b and the source electrode 22.

[0052] The provision of the high concentration region 2b can further reduce the electrical resistance between the base region 2 and the source electrode 22. This allows the power consumption of the semiconductor device 120 to be further reduced.

[0053] (Third Modification) FIG. 9 is a perspective cross-sectional view showing a semiconductor device according to a third modification of the first embodiment. In the semiconductor devices 100 to 120, the gate electrode 10 is provided in the semiconductor region, and the base region 2 faces the gate electrode 10 in the X direction via the gate insulating layer 11. In the semiconductor device 130 according to the third modification shown in Fig. 9, the gate electrode 10 is provided on the semiconductor region, and the base region 2 faces the gate electrode 10 in the Z direction via the gate insulating layer 11. In the illustrated example, the gate electrode 10 also faces a part of the drift region 1 and a part of the source region 3 in the Z direction via the gate insulating layer 11.

[0054] Except for the positional relationship between each semiconductor region and the gate electrode 10, the structure and operation of the semiconductor device 130 are similar to those of the semiconductor device 100. For example, the base region 2 and the source region 3 each include a contact region 2a and a contact region 3a that are in contact with the source electrode 22. The concentration of the first element in the contact region 3a is lower than the concentration of the first element in the contact region 2a.

[0055] In the semiconductor device 130, similarly to the semiconductor device 100, the switching loss of the semiconductor device 130 can be reduced while suppressing deterioration in the characteristics of the semiconductor device 130.

[0056] (Second embodiment) FIG. 10 is a perspective cross-sectional view showing a semiconductor device according to the second embodiment. 10, the conductivity type of each semiconductor region is reversed compared to the semiconductor device 100. Specifically, the semiconductor device 200 has p - n-type drift region 1 (first semiconductor region), n-type base region 2 (second semiconductor region), p + A source region 3 (third semiconductor region) of p + The semiconductor device includes a drain region 4, a gate electrode 10, a drain electrode 21 (first electrode), and a source electrode 22 (second electrode).

[0057] In the semiconductor devices 100 to 130 according to the first embodiment, when in the on state, electrons flow from the source electrode 22 to the drain electrode 21. In contrast, in the semiconductor device 200, when in the on state, holes flow from the source electrode 22 to the drain electrode 21. That is, the semiconductor devices 100 to 130 are N-type MOS (NMOS), while the semiconductor device 200 is a P-type MOS (PMOS).

[0058] The base region 2 and the source region 3 include contact regions 2a and 3a, respectively. However, in the semiconductor device 200, the concentration of the first element in the contact region 3a is higher than the concentration of the first element in the contact region 2a. The concentration of the first element in the contact region 2a may be zero.

[0059] The relatively high concentration of the first element in the contact region 3a of the p-type source region 3 can shorten the lifetime and reduce the switching loss of the semiconductor device 200. When the first element is platinum, the Schottky barrier against holes between the source region 3 and the source electrode 22 is lowered, further reducing the power consumption of the semiconductor device 200.

[0060] Furthermore, the relatively low concentration of the first element in the contact region 2a can suppress deterioration in the characteristics of the semiconductor device 200. For example, an increase in the electrical resistance between the base region 2 and the source electrode 22 can be suppressed.

[0061] According to the second embodiment, as in the first embodiment, it is possible to reduce the switching loss of the semiconductor device 200 while suppressing the deterioration of the characteristics of the semiconductor device 200.

[0062] The structures according to the modifications of the first embodiment can also be applied to the semiconductor device according to the second embodiment. For example, the semiconductor device 200 may include a conductive portion 15, similar to the semiconductor device 110. Similar to the semiconductor device 120, the base region 2 may include a high-concentration region having a higher n-type impurity concentration. Similar to the semiconductor device 130, a gate electrode 10 may be provided on the semiconductor region, and the base region 2 may face the gate electrode 10 in the Z direction via a gate insulating layer 11.

[0063] (Third embodiment) FIG. 11 is a cross-sectional view showing a semiconductor device according to the third embodiment. 11, the semiconductor device 300 according to the third embodiment includes an NMOS region 310, wirings 322 to 324, a PMOS region 330, wirings 342 to 344, an insulating portion 350, and an insulating layer 352. The semiconductor device 300 includes a complementary MOS (CMOS) structure.

[0064] The NMOS region 310 is p - Semiconductor area 311, n + Semiconductor region 312, n + The semiconductor region 313 and the gate electrode 314 are included. + The semiconductor regions 312 and 313 are p - The semiconductor region 311 is provided on the n + The semiconductor region 313 is an n + The semiconductor region 312 is spaced apart from the - A part of the semiconductor region 311 is n + The gate electrode 314 is located between the p-type semiconductor regions 312 and 313 through the gate insulating layer 315. - The portion of the semiconductor region 311, n + A part of the semiconductor region 312 and + The semiconductor region 313 faces a part of the semiconductor region 313 .

[0065] For example, p - The direction from the semiconductor region 311 toward the gate electrode 314 is parallel to the Z direction. + Shape semiconductor region 312 to n +The direction toward the semiconductor region 313 is parallel to the X direction.

[0066] The wiring 322 is + 312, and + The wiring 323 is electrically connected to the n-type semiconductor region 312. + 313, and + The wiring 322 is electrically connected to the semiconductor region 313. The wiring 324 is provided on the gate electrode 314 and is electrically connected to the gate electrode 314. The wirings 322 to 324 are electrically isolated from each other.

[0067] n + The potential of the semiconductor region 312 and n + A voltage equal to or higher than the threshold is applied to the gate electrode 314 while the potential of the semiconductor region 313 is different from that of the gate electrode 314. - A channel is formed in the part of the NMOS semiconductor region 311, and the NMOS region 310 is turned on. Electrons pass through the channel and + Semiconductor region 312 and n + The current flows from one side of the semiconductor region 313 to the other.

[0068] The PMOS region 330 is - Semiconductor region 331, p + Semiconductor region 332, p + The semiconductor region 333 includes a gate electrode 334. + The semiconductor regions 332 and 333 are n - The semiconductor region 331 is provided on the substrate. + The semiconductor region 333 is p + The semiconductor region 332 is spaced apart from the - A part of the semiconductor region 331 is p + The gate electrode 334 is located between the n-type semiconductor regions 332 and 333 via the gate insulating layer 335. - The portion of the semiconductor region 331, p + A part of the semiconductor region 332 and p + The semiconductor region 333 faces a part of the semiconductor region 333 .

[0069] The wiring 342 is p + 332, and + The wiring 343 is electrically connected to the p-type semiconductor region 332. + 333, and + The wiring 342 is electrically connected to the semiconductor region 333. The wiring 344 is provided on the gate electrode 334 and is electrically connected to the gate electrode 334. The wirings 342 to 344 are electrically isolated from each other.

[0070] p + The potential and p of the semiconductor region 332 + A voltage equal to or higher than the threshold is applied to the gate electrode 334 while the potential of the n-type semiconductor region 333 is different from that of the n-type semiconductor region 333. - A channel is formed in the part of the semiconductor region 331, and the PMOS region 330 is turned on. Holes pass through the channel and + Semiconductor region 332 and p + The current flows from one side of the semiconductor region 333 to the other.

[0071] The insulating portion 350 is provided between at least a part of the NMOS region 310 and at least a part of the PMOS region 330. + Semiconductor region 313 and p + The insulating portion 350 is formed of local oxidation of silicon (LOCOS) or the like, and electrically separates the NMOS region 310 and the PMOS region 330.

[0072] The insulating layer 352 is provided on the NMOS region 310, the PMOS region 330, and the insulating portion 350. The wirings 322 to 324 and the wirings 342 to 344 extend in the insulating layer 352 in the Z direction.

[0073] Each semiconductor region of the NMOS region 310 and the PMOS region 330 contains a semiconductor material. Silicon is preferable as the semiconductor material. The gate electrodes 314 and 334 contain polysilicon. The gate insulating layer 315, the gate insulating layer 335, the insulating portion 350, and the insulating layer 352 contain an insulating material such as silicon oxide. The wirings 322 to 324 and the wirings 342 to 344 contain metal. For example, each wiring has a stacked structure of a titanium layer, a titanium nitride layer, and a tungsten layer.

[0074] n + The semiconductor region 312 includes a contact region 312a that contacts the wiring 322. + The semiconductor region 313 includes a contact region 313a that contacts the wiring 323. + The semiconductor region 332 includes a contact region 332a that contacts the wiring 342. + The semiconductor region 333 includes a contact region 333 a that contacts the wiring 343 .

[0075] The contact regions 332a and 333a include a first element. The concentration of the first element in each of the contact regions 332a and 333a is higher than the concentration of the first element in each of the contact regions 312a and 313a. The concentration of the first element in each of the contact regions 312a and 313a may be zero.

[0076] For example, the contact region 312a includes a silicide of a metal contained in the interconnect 322. The contact region 313a includes a silicide of a metal contained in the interconnect 323. The contact regions 332a and 333a each include a silicide of a first element.

[0077] The relatively high concentration of the first element in each of the contact regions 332a and 333a results in p + The electrical resistance and p between the semiconductor region 332 and the wiring 342 + This reduces the electrical resistance between the semiconductor region 333 and the wiring 343. This reduces the power consumption of the semiconductor device 300.

[0078] Furthermore, since the concentrations of the first element in each of the contact regions 312a and 313a are relatively low, it is possible to suppress deterioration in the characteristics of the semiconductor device 300. For example, + The electrical resistance and n between the semiconductor region 312 and the wiring 322 + An increase in electrical resistance between the semiconductor region 313 and the wiring 323 is suppressed.

[0079] According to the third embodiment, the power consumption of the semiconductor device 300 can be reduced while suppressing deterioration in the characteristics of the semiconductor device 300.

[0080] The impurity concentration and the concentration of the first element in each semiconductor region in each of the embodiments described above can be measured by, for example, secondary ion mass spectrometry (SIMS). The concentrations of the first element in multiple regions can also be compared using energy dispersive X-ray spectrometry (EDX).

[0081] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0082] 1: drift region, 1a: first region, 1b: second region, 1x: n - p-type semiconductor layer, 2: base region, 2a: contact region, 2b: high concentration region, 2x: p-type semiconductor region, 2y: silicide layer, 3: source region, 3a: contact region, 3x: n + shaped semiconductor region, 3y: silicide layer, 4: drain region, 4x: n +Semiconductor layer, 10: gate electrode, 11: gate insulating layer, 11x, 11y: insulating layer, 15: conductive portion, 16, 16x: insulating layer, 21: drain electrode, 21x: metal layer, 22: source electrode, 22x to 22z: metal layer, 100 to 130, 200, 300: semiconductor device, 310: NMOS region, 311: p - Semiconductor area, 312,313:n + Semiconductor region, 312a, 313a: contact region, 314: gate electrode, 315: gate insulating layer, 322 to 324: wiring, 330: PMOS region, 331: n - Semiconductor area, 332,333:p + Semiconductor region, 332a, 333a: contact region, 334: gate electrode, 335: gate insulating layer, 342 to 344: wiring, 350: insulating portion, 352: insulating layer, M: mask, OP1, OP2: openings

Claims

1. A first electrode; an n-type first semiconductor region provided on the first electrode; a p-type second semiconductor region provided on the first semiconductor region and including a first contact region containing a first element that is at least one selected from the group consisting of ruthenium, rhodium, palladium, osmium, iridium, and platinum; an n-type third semiconductor region provided on a portion of the second semiconductor region, including a second contact region containing the first element, wherein the concentration of the first element in the second contact region is lower than the concentration of the first element in the first contact region; a gate electrode facing the second semiconductor region via a gate insulating layer; a second electrode containing a metal, the second electrode being provided on the second semiconductor region and the third semiconductor region, in contact with the first contact region and the second contact region, the second electrode containing a silicide of the metal; A semiconductor device comprising:

2. The semiconductor device according to claim 1 , wherein said first contact region includes a silicide of said first element.

3. 2. The semiconductor device according to claim 1, wherein said gate electrode faces said second semiconductor region via said gate insulating layer in a second direction perpendicular to a first direction from said first electrode toward said first semiconductor region.

4. 4. The semiconductor device according to claim 3, further comprising a conductive portion provided in said first semiconductor region via an insulating layer.

5. The first semiconductor region is a first region facing the gate electrode with the gate insulating layer interposed therebetween in the second direction; a second region located below the first region; Including, 4. The semiconductor device according to claim 3, wherein the concentration of said first element in said first region is higher than the concentration of said first element in said second region.

6. 2. The semiconductor device according to claim 1, wherein said gate electrode faces said second semiconductor region via said gate insulating layer in a first direction from said first electrode toward said first semiconductor region.

7. 7. The semiconductor device according to claim 1, wherein the first element is platinum.

8. A first electrode; a p-type first semiconductor region provided on the first electrode; an n-type second semiconductor region provided on the first semiconductor region and including a first contact region; a p-type third semiconductor region including a second contact region provided on a portion of the second semiconductor region and having a higher concentration of a first element, the first element being at least one selected from the group consisting of ruthenium, rhodium, palladium, osmium, iridium, and platinum, than the first contact region; a gate electrode facing the second semiconductor region via a gate insulating layer; a second electrode provided on the second semiconductor region and the third semiconductor region and in contact with the first contact region and the second contact region; A semiconductor device comprising:

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