Semiconductor device manufacturing method

Abstract

To improve the reliability of a method for manufacturing a semiconductor device in which wiring is formed on a semiconductor substrate by a plating method, followed by grinding of the back surface of the semiconductor substrate.SOLUTION: A method of manufacturing a semiconductor device includes steps of: forming a silicon oxide film covering a first main surface SF1 and a second main surface SF2 of the semiconductor substrate SB; forming a redistribution wiring RM on the first main surface SF1 side of the semiconductor substrate SB; and grinding the second main surface SF2 of the semiconductor substrate SB. The grinding step is performed with the thickness of the silicon oxide film located on the second main surface SF2 being 10 nm or more and 30 nm or less.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique that is effective when applied to a method for manufacturing a semiconductor device in which rewiring is formed on a semiconductor substrate by plating and then the back surface of the semiconductor substrate is ground. [Background technology]

[0002] In some cases, after a wiring layer is formed on a semiconductor wafer, rewiring is formed on the wiring layer by plating. Patent Document 1 (JP 2018-113307 A) describes a method for thinning a semiconductor wafer, in which the back surface of the semiconductor wafer is ground while leaving the outer periphery of the semiconductor wafer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-113307 Summary of the Invention [Problem to be solved by the invention]

[0004] For semiconductor wafers with a diameter greater than 8 inches, the back surface of the semiconductor substrate is mirror-finished to ensure the flatness of the semiconductor wafer. Even if the back surface is oxidized during the semiconductor device manufacturing process, the back surface remains mirror-finished (smooth). If the back surface grinding process is performed in this state, the grinding teeth (grinding wheel) may stop rotating immediately, resulting in improper polishing. If the rotation speed of the grinding teeth is increased to ensure proper polishing, an overcurrent may be generated, causing the grinding device to stop. This has led to a problem of a deterioration in the reliability of semiconductor device manufacturing methods.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] A brief summary of a representative embodiment of the present invention will be given below.

[0007] A method for manufacturing a semiconductor device according to one embodiment includes the steps of: preparing a semiconductor substrate having a first main surface and a second main surface opposite the first main surface; forming silicon oxide films covering the first and second main surfaces; forming interconnects on the first main surface; forming rewirings on the interconnects by plating; and grinding the silicon oxide film located on the second main surface and the second main surface. The grinding of the silicon oxide film and the second main surface is performed while the silicon oxide film located on the second main surface has a thickness of 10 nm to 30 nm.

[0008] A method for manufacturing a semiconductor device according to one embodiment includes the steps of preparing a semiconductor substrate having a first main surface and a second main surface opposite the first main surface, forming a silicon oxide film covering each of the first main surface and the second main surface, forming wiring on the first main surface, forming rewiring on the wiring using a plating method, removing the silicon oxide film located on the second main surface to expose the second main surface, covering the first main surface with a protective tape, grinding the second main surface, and peeling off the protective tape. [Effects of the Invention]

[0009] According to one embodiment, the reliability of the method for manufacturing a semiconductor device can be improved. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a cross-sectional view of the semiconductor device according to the first embodiment during the manufacturing process. [Figure 2] 2 is a cross-sectional view of the semiconductor device during the manufacturing process, continuing from FIG. 1. [Figure 3] 3 is a cross-sectional view of the semiconductor device during the manufacturing process, continuing from FIG. 2. [Figure 4] 4 is a cross-sectional view of the semiconductor device during the manufacturing process, continuing from FIG. 3. [Figure 5]5 is a cross-sectional view of the semiconductor device during the manufacturing process, continuing from FIG. 4. [Figure 6] 6 is a cross-sectional view of the semiconductor device during the manufacturing process, continuing from FIG. 5. [Figure 7] FIG. 7 is a cross-sectional view of the semiconductor device during the manufacturing process, continuing from FIG. 6. [Figure 8] 8 is a cross-sectional view of the semiconductor device during the manufacturing process, continuing from FIG. 7. [Figure 9] 9 is a cross-sectional view of the semiconductor device during the manufacturing process following FIG. 8. [Figure 10] FIG. 10 is a perspective view of the semiconductor device during the manufacturing process, subsequent to FIG. [Figure 11] FIG. 11 is a perspective view of the semiconductor device during the manufacturing process following FIG. [Figure 12] 12 is a cross-sectional view of the semiconductor device during the manufacturing process following FIG. 11. [Figure 13] 13 is a cross-sectional view of the semiconductor device during the manufacturing process following FIG. 12. [Figure 14] FIG. 14 is a perspective view of the semiconductor device during the manufacturing process following FIG. [Figure 15] 10A and 10B are cross-sectional views of a semiconductor device according to a second embodiment during a manufacturing process. [Figure 16] FIG. 16 is a cross-sectional view of the semiconductor device during the manufacturing process following FIG. [Figure 17] FIG. 17 is a cross-sectional view of the semiconductor device during the manufacturing process following FIG. [Figure 18] FIG. 18 is a cross-sectional view of the semiconductor device during the manufacturing process following FIG. [Figure 19] FIG. 19 is a cross-sectional view of the semiconductor device during the manufacturing process following FIG. 18. DETAILED DESCRIPTION OF THE INVENTION

[0011] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one is a partial or complete modification, detail, supplementary explanation, etc. of the other. Furthermore, in the following embodiments, when the number of elements, etc. (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to the mentioned number, and may be more or less than the mentioned number, unless otherwise specified or when it is clearly limited in principle to a specific number.

[0012] Furthermore, in the following embodiments, the components (including element steps, etc.) are not necessarily essential unless otherwise specified or considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., it is intended to include those that are substantially similar or similar to the shape, etc., unless otherwise specified or considered to be clearly not essential in principle. The same applies to the above numerical values ​​and ranges.

[0013] Hereinafter, embodiments will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. In the following embodiments, explanations of the same or similar parts will not be repeated unless particularly necessary.

[0014] (Embodiment 1) <Method of manufacturing a semiconductor device> A method for manufacturing a semiconductor device according to this embodiment will be described below with reference to Figures 1 to 14. Figures 1 to 8, 12, and 13 show an element formation region 1A and an element isolation formation region 1B. Below, a case where an IGBT (Insulated Gate Bipolar Transistor) element is formed in the element formation region 1A will be described.

[0015] First, as shown in Figure 1, a semiconductor substrate SB is prepared, which has a first main surface (upper surface, front surface) SF1 and a second main surface (lower surface, back surface) SF2 opposite the first main surface SF1. The semiconductor substrate SB is made of n-type conductivity single-crystal silicon (Si). The semiconductor substrate SB is a disk-shaped semiconductor wafer. Hereinafter, the semiconductor substrate SB and the structure formed thereon may be collectively referred to as a semiconductor wafer.

[0016] Next, insulating films IF1 and IF2 are formed in this order on the semiconductor substrate SB. First, insulating film IF1 is formed on the semiconductor substrate SB. The insulating film IF1 is made of a silicon oxide (SiO2) film formed by, for example, thermal oxidation. Next, insulating film IF2 is formed on insulating film IF1. The insulating film IF2 is made of a silicon nitride (Si3N4) film deposited by, for example, CVD (Chemical Vapor Deposition). The film thickness of insulating film IF1 is, for example, 30 nm. The film thickness of insulating film IF2 is, for example, 150 nm.

[0017] Next, a trench D1 is formed on the semiconductor substrate SB. The trench D1 is formed in the semiconductor substrate SB by using photolithography and dry etching, penetrating the insulating films IF2 and IF1 in the element isolation formation region 1B. The trench D1 has a predetermined depth in the direction from the first main surface SF1 toward the second main surface. Next, although not shown, the insulating films IF1 and IF2 covering the outer peripheral surface (side surface) of the semiconductor substrate wafer are removed by etching.

[0018] Next, as shown in FIG. 2, an insulating film IF3 is formed by thermal oxidation on the first main surface SF1 of the semiconductor substrate SB exposed from the insulating films IF1 and IF2 in the element isolation formation region 1B. That is, the insulating film IF3 is formed in the trench D1. Here, the insulating film IF3 covering the outer peripheral surface (side surface) of the semiconductor substrate wafer is also formed. The insulating film IF3 is made of a silicon oxide film. The thickness of the insulating film IF3 is, for example, 300 nm or more. The insulating film IF3 formed in the element isolation formation region 1B is a LOCOS (LOCal Oxidation of Silicon) oxide film that constitutes the element isolation region EI. Note that in the element isolation formation region 1B, the element isolation region EI may be STI (Shallow Trench Isolation) or PN junction isolation.

[0019] 3, the insulating films IF1 and IF2 are removed by wet etching or the like. Subsequently, an n-type impurity (e.g., phosphorus (P)) is introduced into the first main surface SF1 of the semiconductor substrate SB in the element formation region 1A by ion implantation. Subsequently, a p-type impurity (e.g., boron (B)) is introduced into the first main surface SF1 of the semiconductor substrate SB by ion implantation.

[0020] Next, using photolithography and dry etching, a plurality of grooves D2 are formed in the first main surface SF1 of the semiconductor substrate SB in the element formation region 1A. The grooves D2 have a predetermined depth from the first main surface SF1. The semiconductor substrate SB is then subjected to a heat treatment to diffuse the impurities introduced into the semiconductor substrate SB. This forms n-type semiconductor regions HB and p-type semiconductor regions FR. The semiconductor regions HB and FR each have a predetermined depth from the first main surface SF1. The grooves D2 are formed between the semiconductor regions HB and FR.

[0021] Next, as shown in FIG. 4, an insulating film IF4a covering the first main surface SF1 of the semiconductor substrate SB is formed on the first main surface SF1, and an insulating film IF4b covering the second main surface SF2 of the semiconductor substrate SB is formed on the second main surface SF2. Each of the insulating films IF4a and IF4b is made of, for example, a silicon oxide film and has a film thickness of, for example, 100 nm. The insulating films IF4a and IF4b are formed by, for example, thermal oxidation. The insulating film IF4a is formed on the side surface and bottom surface of the trench D2. That is, the insulating film IF4a is formed on the inner surface of the trench D2 and on the first main surface SF1. The insulating film IF4b is formed on the second main surface SF2.

[0022] Next, a semiconductor layer SL1 made of polysilicon is formed on the insulating film IF4a on the first main surface SF1 of the semiconductor substrate SB. The semiconductor layer SL1 is embedded in the trench D2 via the insulating film IF4a. At this time, although not shown, a polysilicon film is also formed to cover the second main surface SF2 of the semiconductor substrate SB via the insulating film IF4b.

[0023] Subsequently, the polysilicon film covering the second main surface SF2 of the semiconductor substrate SB is removed by wet etching using, for example, fluoronitric acid. This exposes the insulating film IF4b. By over-etching the polysilicon film formed on the second main surface SF2, a portion of the insulating film IF4b formed on the second main surface SF2 is removed. As a result, the film thickness of the insulating film IF4b formed on the second main surface SF2 becomes, for example, approximately 60 nm or more and 70 nm or less.

[0024] Next, as shown in FIG. 5, the semiconductor layer SL1 is etched to remove the semiconductor layer SL1 formed outside the trench D2. As a result, the semiconductor layer SL1 remains only in the trench D2. The semiconductor layer SL1 in the trench D2 constitutes the gate electrode GE. Subsequently, the insulating film IF4a is etched to remove the insulating film IF4a formed outside the trench D2. As a result, the insulating film IF4a remains only in the trench D2. The insulating film IF4a in the trench D2 constitutes the gate insulating film.

[0025] Next, although not shown, a silicon oxide film covering the first main surface SF1 and the second main surface SF2 of the semiconductor substrate SB is formed by, for example, a CVD method. As a result, the film thickness of the insulating film IF4b covering the second main surface SF2 of the semiconductor substrate SB is, for example, 70 nm or more and 80 nm or less. Next, p-type impurities (e.g., boron (B)) are introduced into the first main surface SF1 of the semiconductor substrate SB in the element formation region 1A by an ion implantation method. Next, a heat treatment is performed on the semiconductor substrate SB to form a p-type semiconductor region CHR. The semiconductor region CHR has a predetermined depth from the first main surface SF1 of the semiconductor substrate SB. The depth of the semiconductor region CHR is shallower than the depth of the groove D2.

[0026] Subsequently, the silicon oxide film (not shown) covering the first main surface SF1 and the second main surface SF2 of the semiconductor substrate SB is removed by wet etching, so that the thickness of the insulating film IF4b covering the second main surface SF2 of the semiconductor substrate SB becomes, for example, about 50 nm or more and 60 nm or less.

[0027] Next, as shown in FIG. 6, n-type impurities (e.g., arsenic (As)) are introduced into the first main surface SF1 of the semiconductor substrate SB between adjacent trenches D2 in the element formation region 1A by ion implantation. This forms n-type semiconductor regions ER in the first main surface SF1 of the semiconductor substrate SB. The semiconductor regions ER have a predetermined depth from the first main surface SF1. The depth of the semiconductor regions ER is shallower than the depth of the semiconductor regions CHR. The semiconductor regions ER constitute the diffusion layer of the emitter region. The n-type impurity concentration of the semiconductor regions ER is higher than the n-type impurity concentration of the semiconductor regions HR.

[0028] Next, an interlayer insulating film IL is formed on the first main surface SF1 of the semiconductor substrate SB. The interlayer insulating film IL is made of, for example, mainly a silicon oxide film and is formed by, for example, a CVD method. Next, using photolithography and dry etching, a plurality of contact holes (connection holes) CH are formed that penetrate the interlayer insulating film IL and expose a portion of each of the gate electrode GE and the first main surface SF1 of the semiconductor substrate SB. Note that FIG. 6 does not show the contact holes CH directly above the gate electrode GE. In the element formation region 1A, the contact holes CH penetrate the semiconductor region ER and reach the semiconductor region CHR. Similarly, in the element isolation formation region 1B, the contact holes CH reach the semiconductor region CHR.

[0029] 7, using the interlayer insulating film IL as an ion implantation blocking mask, p-type impurities (e.g., boron (B)) are introduced into the first main surface SF1 of the semiconductor substrate SB by ion implantation. As a result, p-type semiconductor regions BC are formed in the exposed semiconductor substrate SB at the bottoms of the contact holes CH in the element formation region 1A and the element isolation formation region 1B. The depth of the semiconductor regions BC is shallower than the depth of the semiconductor regions CHR, for example. The p-type impurity concentration of the semiconductor regions BC is higher than the p-type impurity concentration of the semiconductor regions CHR.

[0030] Subsequently, contact plugs (conductive connecting portions) CP are formed in each contact hole CH. Specifically, a tungsten (W) film is deposited on the first main surface SF1 of the semiconductor substrate SB by a sputtering method or the like so as to fill the contact holes CH. Thereafter, the tungsten film formed outside the contact holes CH is removed by a CMP (Chemical Mechanical Polishing) method or the like to form contact plugs CP made of the tungsten film remaining in the contact holes CH. The contact plugs CP shown in the element formation region 1A in FIG. 7 are electrically connected to the semiconductor regions ER. Furthermore, the contact plugs CP are electrically connected to the semiconductor regions (channel formation regions) CHR via the semiconductor regions BC. The contact plugs CP formed in the element isolation formation region 1B are electrically connected to the semiconductor regions (channel formation regions) CHR via the semiconductor regions BC.

[0031] Next, a wiring (wiring layer) M1 is formed on the interlayer insulating film IL and the contact plugs CP. Specifically, a barrier conductor film made of, for example, Ti (titanium), TiN (titanium nitride) or TiW (titanium tungsten), and a main conductor film made of, for example, AlCu (aluminum copper) are deposited in this order by sputtering or the like. This forms a wiring M1 made of the barrier conductor film and the main conductor film. The wiring M1 is connected to each of the multiple contact plugs CP. In this process, a metal film (not shown) covering the outer peripheral surface of the semiconductor wafer is formed. Next, the metal film covering the outer peripheral surface of the semiconductor wafer is removed by wet etching. In this process, a portion of the surface of the insulating film IF4b covering the second main surface SF2 of the semiconductor substrate SB is also removed, thereby reducing the thickness of the insulating film IF4b. As a result, the thickness of the insulating film IF4b covering the second main surface SF2 of the semiconductor substrate SB is, for example, 10 nm or more and 30 nm or less. Here, the thickness of the insulating film IF4b is, for example, 30 nm.

[0032] Next, as shown in FIG. 8, photolithography and dry etching are used to remove a portion of the wiring M1, exposing the interlayer insulating film IL. That is, the wiring M1 is patterned. Subsequently, a passivation film PF made of, for example, polyimide is formed on the first main surface SF1 of the semiconductor substrate SB. Subsequently, the passivation film PF is patterned by exposure and development. The passivation film PF has an opening that exposes a portion of the wiring M1.

[0033] Next, as shown in FIG. 9, a rewiring process is performed. That is, a rewiring RM is formed on a part of the wiring M1 exposed from the passivation film PF. FIG. 9 shows a cross-sectional view including the edge of the semiconductor wafer. The film thickness of the rewiring RM is smaller than that of the passivation film PF. Here, a metal film MF is also formed on the surface of the end of the wiring M1, that is, on the upper surface and side surface of the wiring M1 exposed from the passivation film PF. In this rewiring process, for example, a nickel (Ni) film and a gold (Au) film are formed in sequence by plating to form the rewiring RM having a stacked structure made of the nickel film and the gold film. At this time, the film thickness of the insulating film IF4b covering the second main surface SF2 of the semiconductor substrate SB is 10 nm or more and 30 nm or less.

[0034] 10, after a protective tape TP is attached to cover the first main surface SF1 of the semiconductor wafer WF, the semiconductor wafer WF is turned upside down. That is, the semiconductor wafer WF is turned upside down so that the first main surface SF1 covered with the protective tape TP faces downward.

[0035] Next, as shown in FIG. 11, the second main surface SF2 of the semiconductor wafer WF and the silicon oxide film formed on the second main surface are ground. The grinding process is performed when the thickness of the silicon oxide film formed on the second main surface SF2 is 10 nm or more and 30 nm or less. Grinding is performed from the second main surface SF2 side of the semiconductor wafer WF to thin the thickness of the semiconductor substrate SB. As a result, the thickness of the semiconductor substrate becomes, for example, approximately 40 μm or more and 60 μm or less. Because protective tape TP is attached to the front side of the semiconductor wafer WF, semiconductor elements and the like formed on the semiconductor substrate SB are not destroyed.

[0036] Here, the outermost edge portion EG of the semiconductor wafer WF (reinforcement portion, ring-shaped reinforcing portion, annular reinforcing protrusion) is left, and only the second main surface SF2 of the semiconductor substrate SB inside it is ground to thin it. The width of the edge portion EG that is not ground is, for example, approximately 2.5 mm or more and 3 mm or less. Here, grinding is performed by rotating the semiconductor wafer WF and bringing the grinding teeth of a rotating grinding wheel GR into contact with the second main surface SF2 of the semiconductor wafer WF.

[0037] Thereafter, although not shown, spin etching is performed on the second main surface SF2 of the semiconductor substrate SB. First, the semiconductor wafer WF is vacuum-sucked or mechanically fixed to, for example, a spin head equipped with a rotation mechanism. Then, while the semiconductor wafer WF is being rotated, an etching solution is poured onto the second main surface SF2 of the semiconductor wafer WF from a nozzle provided above the semiconductor wafer WF, thereby cleaning the second main surface SF2 of the semiconductor wafer WF.

[0038] Next, as shown in FIG. 12, an n-type impurity (e.g., arsenic (As)) is introduced into the second main surface SF2 of the semiconductor substrate SB by ion implantation. As a result, an n-type semiconductor region CR is formed in the second main surface SF2 of the semiconductor substrate SB. As a result, a trench-type IGBT is formed in the element formation region 1A. The semiconductor region CR constitutes the collector region of the IGBT. That is, the IGBT has at least a gate electrode GE, a semiconductor region ER which is an emitter region, a semiconductor region CR which is a collector region, and a semiconductor region CHR which is a channel formation region.

[0039] 13, a back electrode (collector electrode) BE is formed to cover the second main surface SF2 of the semiconductor substrate SB. Specifically, a laminated metal film made of Al, Ti, Ni, Au, etc. is formed on the second main surface SF2 of the semiconductor substrate SB. This forms the back electrode BE made of the laminated metal film.

[0040] Next, as shown in FIG. 14, the protective tape TP is peeled off from the semiconductor wafer WF.

[0041] Although subsequent steps are not shown in the drawings, the semiconductor wafer WF is diced to separate the semiconductor wafer WF into individual pieces. This results in a plurality of semiconductor chips being obtained from the semiconductor wafer. With the above steps, the semiconductor device of this embodiment is substantially completed.

[0042] <Effects of this embodiment> In the method for manufacturing a semiconductor device according to the present embodiment, the back surface of the semiconductor substrate is ground to thin the semiconductor substrate. Here, a rewiring process is performed before the grinding process. However, if silicon on the second main surface (back surface) of the semiconductor substrate is exposed in the rewiring process, the second main surface is conductive, and therefore foreign matter is generated (precipitated) on the second main surface due to a reaction in the plating process.

[0043] One way to prevent the generation of foreign matter is to perform the rewiring process while the second main surface is covered with protective tape. However, adding a step of forming the protective tape on the second main surface (especially if a new device for applying the protective tape is introduced) increases the manufacturing cost of the semiconductor device. Furthermore, after the rewiring process, a step of removing the protective tape is also required to perform the grinding step of the second main surface, the ion implantation into the second main surface, and the back surface electrode formation step, as described with reference to FIGS. 11 to 13.

[0044] Therefore, in this embodiment, the rewiring process is performed with the second main surface SF2 of the semiconductor substrate SB covered with the insulating film IF4b. That is, because the second main surface SF2 is protected by the insulating film IF4b, which is a nonconductor, it is possible to prevent foreign matter from being generated on the second main surface SF2 during the plating process. In this case, if the thickness of the insulating film IF4b is less than 10 nm, there is a risk that the generation of the foreign matter cannot be prevented, so the thickness of the insulating film IF4b needs to be 10 nm or more. Here, the insulating film IF4b is used, which is formed by also oxidizing the back surface in the oxidation process after forming the groove D2 of the IGBT.

[0045] Here, in a semiconductor wafer having a diameter larger than 8 inches (e.g., 300 mm), in order to ensure flatness, the second main surface SF2 of the semiconductor wafer is a mirror (smooth) surface, and the surface of the insulating film IF4b covering the second main surface SF2 is also a mirror (smooth) surface. For such a semiconductor wafer, if the grinding step is performed when the insulating film IF4b is relatively thick, the rotation of the grinding teeth (grinding wheel) may stop immediately, preventing grinding from progressing. In other words, after a small amount of the insulating film IF4b is removed, the grinding teeth may begin to slide on the surface of the insulating film IF4b, preventing grinding from progressing. Increasing the rotation speed of the grinding teeth to proceed with grinding may result in an overcurrent causing the grinding device to stop. Thus, the fact that the second main surface SF2 of the semiconductor wafer has a mirror (smooth) surface and is covered with a relatively thick insulating film IF4b may cause a deterioration in the reliability of the semiconductor device manufacturing method.

[0046] Therefore, in this embodiment, the grinding step is performed when the thickness of the insulating film IF4b is 10 nm or more and 30 nm or less. In this way, if the thickness of the insulating film IF4b is 30 nm or less, the insulating film IF4b is thin, so that the insulating film IF4b can be easily removed by grinding, and the semiconductor substrate SB can be thinned by grinding.

[0047] This prevents the generation of foreign matter during the rewiring process and allows the semiconductor substrate to be thinned by backside grinding. Therefore, it is not necessary to form and peel off a protective tape on the backside of the semiconductor wafer in order to prevent the generation of foreign matter. This improves the reliability of the semiconductor device manufacturing method.

[0048] In this embodiment, it is essential that the grinding step of the back surface of the semiconductor substrate SB is performed in a state in which the film thickness of the insulating film IF4b is 10 nm or more and 30 nm or less. In this embodiment, the film thickness of the insulating film IF4b is thinned in multiple steps, but this is not limited to this. The film thickness of the insulating film IF4b may be thinned in a single step. In addition, the film thickness of the insulating film IF4b removed in each step of thinning the film thickness of the insulating film IF4b is also not particularly limited.

[0049] (Embodiment 2) As explained in the semiconductor device manufacturing method of the first embodiment, the thickness of the insulating film covering the back surface of the semiconductor wafer gradually decreases due to the process of removing the semiconductor layer formed on the back surface of the semiconductor wafer, the process of removing the metal film formed on the outer peripheral surface of the semiconductor wafer, etc. Therefore, a method for preventing the thickness of the insulating film from becoming 10 nm or less immediately before the rewiring process will be explained below with reference to Figures 15 to 19. Figures 15 to 19 are cross-sectional views showing a semiconductor device during the manufacturing process, similar to the process explained with reference to Figures 1 to 6, and show a portion including the peripheral edge of the semiconductor wafer.

[0050] First, as shown in FIG. 15, the process of preparing the semiconductor substrate SB and the process of forming the insulating films IF1 and IF2 described in FIG. 1 are performed. However, the formation of the groove D1 described in FIG. 1 is not yet performed. At this time, the peripheral portion of the semiconductor wafer WF and the second main surface SF2 of the semiconductor substrate SB are also covered with the insulating films IF1 and IF2. Note that, although the second main surface SF2 of the semiconductor substrate SB is also covered with the insulating films IF1 and IF2 in the first embodiment, this is not shown. In the first embodiment, the insulating films IF1 and IF2 are removed before the formation of the insulating films IF4a and IF4b. The thickness of the insulating film IF1 is, for example, 30 nm. The thickness of the insulating film IF2 is, for example, 150 nm.

[0051] Next, as shown in Fig. 16, the groove D1 is formed by carrying out the process described with reference to Fig. 1. Subsequently, the insulating films IF1 and IF2 covering the outer peripheral surface of the semiconductor wafer WF are removed.

[0052] Next, as shown in FIG. 17, the insulating film IF3 described with reference to FIG. 2 is formed. At this time, the insulating film IF3 is also formed on the exposed outer peripheral surface of the semiconductor wafer WF. Although not shown in FIG. 2, in the oxidation step of forming the insulating film IF3, an insulating film IF3a is also formed on the insulating film IF2 made of a silicon nitride film. This applies to both the first main surface SF1 side and the second main surface SF2 side of the semiconductor substrate SB. By forming the insulating film IF3 on the outer peripheral surface of the semiconductor wafer WF, it is possible to prevent foreign matter from being generated on the outer peripheral surface of the semiconductor wafer WF in a subsequent rewiring step.

[0053] 18, wet etching is performed using hydrofluoric acid (HF) to remove the insulating film IF3a covering the insulating film IF2 on the first main surface SF1 side of the semiconductor substrate SB. Here, wet etching is performed only on the first main surface SF1 side of the semiconductor substrate SB using single-wafer equipment. By removing the insulating film IF3a on the first main surface SF1 while leaving the insulating film IF3a covering the second main surface SF2, the insulating film IF2 is exposed.

[0054] Next, as shown in FIG. 19 , wet etching using hot phosphoric acid is performed to remove the exposed insulating film IF2, thereby exposing the insulating film IF1 on the first main surface SF1 of the semiconductor substrate SB. That is, the insulating film IF2 on the first main surface SF1 is removed while leaving the insulating film IF2 on the second main surface SF2, thereby exposing the insulating film IF1 on the first main surface SF1. This step corresponds to the step of removing the insulating film IF2 described with reference to FIG. 3. In this step, silicon nitride is selectively removed, so the silicon oxide film remains without being removed. Therefore, the insulating film IF2 on the second main surface SF2 side of the semiconductor substrate SB, which is covered with the insulating film IF3a made of a silicon oxide film, remains without being removed. Note that the insulating film IF3, which is a LOCOS oxide film formed on the first main surface SF1 side of the semiconductor substrate SB, also remains without being removed. One of the main features of this embodiment is that leaving the insulating film IF2 on the second main surface SF2 side of the semiconductor substrate SB prevents the insulating film IF1 between the insulating film IF2 and the second main surface SF2 of the semiconductor substrate SB from becoming thin or being completely removed in a subsequent step.

[0055] Next, although not shown, the insulating film IF1 is removed and the process of forming the semiconductor regions FR, HB, and trenches D2 is performed as described with reference to Fig. 3. The subsequent processes are performed in the same manner as those described with reference to Figs. 4 to 6. Then, the process of forming the contact plugs CP is performed as described with reference to Fig. 7. However, since the second main surface SF2 of the semiconductor substrate SB is covered with the insulating films IF1 and IF2, it is possible that the insulating film IF4b shown in Fig. 4 will not be formed on the second main surface SF2 side.

[0056] 19, and immediately before the step of forming the interlayer insulating film IL shown in Fig. 6, the exposed insulating film IF2 is removed by wet etching using hot phosphoric acid. Until this removal step, the insulating film IF1 on the second main surface SF2 side of the semiconductor substrate SB is covered with the insulating film IF2, and therefore, the insulating film IF1 is not removed in the step of removing the semiconductor layer or the like.

[0057] Thereafter, the semiconductor device of this embodiment is substantially completed by performing steps similar to those described with reference to FIGS. 6 to 14. In the description of the manufacturing process using FIG. 7, the step of removing the metal film (not shown) formed to cover the outer peripheral surface of the semiconductor wafer WF in the wiring M1 formation step was described. This removal step is a step that can remove the insulating film IF1 when it is exposed on the second main surface SF2 side of the semiconductor substrate SB. If the insulating film IF1 on the second main surface SF2 side is removed and the second main surface SF2 is exposed, there is a risk of foreign matter being generated on the second main surface SF2 in the rewiring formation step. However, in this embodiment, the insulating film IF2 protects the insulating film IF1 until just before the passivation film PF is formed, preventing the thickness of the insulating film IF1 from decreasing and exposing the second main surface SF2. This more reliably leaves the insulating film IF1 on the second main surface SF2 with a thickness of 10 nm or more and 30 nm or less. Therefore, in the grinding step described with reference to FIG. 11, grinding of the second main surface SF2 of the semiconductor substrate SB can be easily performed.

[0058] That is, in the present embodiment, the insulating film IF2 covering the second main surface SF2 of the semiconductor substrate SB is intentionally left in the step described with reference to Fig. 18, thereby preventing the insulating film IF1 covering the second main surface SF2 from being removed during the manufacturing steps of the semiconductor device. In this way, by leaving the insulating film IF1 until the grinding step described with reference to Fig. 11, the same effect as in the first embodiment can be obtained.

[0059] (Embodiment 3) In this embodiment, the manufacturing process of the semiconductor device described with reference to FIGS. 1 to 9 is performed in the same manner as in the first embodiment. In this embodiment, after the rewiring process described with reference to FIG. 9, the insulating film (e.g., insulating film IF4b) covering the second main surface SF2 of the semiconductor substrate SB is entirely removed. This exposes the second main surface SF2 of the semiconductor substrate SB. The insulating film can be removed by wet etching or dry etching.

[0060] Next, the protective tape TP is attached as described with reference to FIG. 10. Then, the process described with reference to FIG. 11 is performed. Here, the exposed second main surface SF2 of the semiconductor substrate SB is directly ground. If the second main surface SF2 is a silicon surface, even if the second main surface SF2 is a mirror finish, grinding can be performed more easily than if the second main surface SF2 is a smooth surface made of a thick silicon oxide film. This improves the reliability of the semiconductor device manufacturing method.

[0061] In this embodiment, the insulating film covering the second main surface SF2 of the semiconductor substrate SB is removed before the formation of the protective tape TP described using Figure 10, so the film thickness of the insulating film before this removal process may be greater than 30 nm.

[0062] The invention made by the present inventors has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the spirit of the invention.

[0063] For example, the conductivity types of the constituent parts of the IGBTs described in the first to third embodiments may be interchanged. Furthermore, the elements formed in the element formation region 1A may not be IGBTs, but may be any elements such as power semiconductors other than IGBTs, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), or diodes. The elements are not limited to vertical semiconductor elements, but may also be planar elements having constituent parts only on the first main surface side of the semiconductor substrate. [Explanation of symbols]

[0064] 1A Device formation area 1B Element isolation formation area BC, CHR, CR, ER, FR, HB, HR Semiconductor area BE Back electrode CH contact hole CP Contact Plug D1, D2 groove EG edge part EI element isolation area GE gate electrode GR grinding wheel IF1 to IF5, IF3a, IF4a, IF4b insulating film IL Interlayer insulating film M1 wiring MF metal film PF passivation film RM rewiring SB semiconductor substrate SF1 First principal surface SF2 Second principal surface SL1 semiconductor layer TP Protective Tape WF Semiconductor wafer

Claims

1. (a) providing a semiconductor substrate having a first major surface and a second major surface opposite the first major surface; (b) forming a silicon oxide film covering each of the first main surface and the second main surface; (c) forming wiring on the first main surface after the step (b); (d) forming a rewiring on the wiring by plating; (e) after the step (d), grinding the silicon oxide film located on the second main surface and the second main surface; and The method for manufacturing a semiconductor device, wherein the step (e) is performed in a state where the silicon oxide film located on the second main surface has a film thickness of 10 nm or more and less than 30 nm.

2. 2. The method of manufacturing a semiconductor device according to claim 1, The step (b) comprises: (b1) forming the silicon oxide film to cover each of the first main surface and the second main surface; (b2) after the step (b1), forming a silicon nitride film covering each of the first main surface and the second main surface; (b3) forming an element isolation region on the first main surface exposed from the silicon oxide film and the silicon nitride film; (b4) after the step (b3), removing the silicon nitride film located on the first main surface while leaving the silicon nitride film located on the second main surface, thereby exposing the silicon oxide film located on the first main surface; The method for manufacturing a semiconductor device comprising the steps of:

3. 3. The method for manufacturing a semiconductor device according to claim 2, (c1) after the step (b), removing the silicon nitride film located on the second main surface; (c2) forming an interlayer insulating film on the first main surface after the step (c1) and before the step (c); and In the step (c), the wiring is formed on the interlayer insulating film; In the step (d), the rewiring is formed on a part of the wiring.

4. 2. The method of manufacturing a semiconductor device according to claim 1, The step (b) comprises: (b5) forming a groove in the first main surface; (b6) forming the silicon oxide film by oxidizing the inner surface of the trench, the first main surface, and the second main surface; (b7) forming a gate electrode in the trench; and The silicon oxide film in the trench constitutes a gate insulating film.

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