Molybdenum template for tungsten

Abstract

A low resistance metallization stack structure for logic and memory applications and related fabrication methods are provided. The method may be implemented by a method including providing a molybdenum (Mo)-containing layer 308 in a feature on a substrate and depositing a tungsten (W)-containing layer over the Mo-containing layer, thereby filling the feature. In some embodiments, the method further includes annealing the Mo-containing layer before depositing the W-containing layer. The Mo-containing layer may be a template for W grain growth.

Description

[Background technology]

[0001] [Incorporated by reference] A PCT application is being filed concurrently herewith as part of this application, and each application identified in that concurrently filed PCT application to which this application claims benefit or priority is incorporated herein by reference in its entirety for all purposes.

[0002] Tungsten (W) film deposition using chemical vapor deposition (CVD) techniques is an essential part of semiconductor fabrication. For example, tungsten films may be used as low-resistivity electrical connections in the form of horizontal interconnects, vias between adjacent metal layers, and contacts between the first metal layer on a silicon substrate and devices. Tungsten films may also be used in various memory applications, including the formation of buried wordline (bWL) architectures for dynamic random access memory (DRAM), wordlines for 3D NAND, and logic applications. However, the continued reduction in feature size and film thickness poses various challenges for thinning, including high resistivity.

[0003] The background discussion provided herein is intended to present the contents of the present disclosure generally. Work by the currently named inventors within the scope of what is described in this background section, as well as aspects of the description that may not otherwise be considered prior art at the time of filing, are not admitted, expressly or impliedly, as prior art against the present disclosure. Summary of the Invention

[0004] Provided herein is a method for forming a low-resistivity bulk conductor. The method includes forming a bulk conductive film on a thin, low-resistivity transition metal layer having a large grain size. The bulk conductive film follows the grain of the low-resistivity transition metal film, resulting in a large grain size. Also provided is a device including the template layer and the bulk film.

[0005] One aspect of the present disclosure may be practiced by a method including providing a molybdenum (Mo)-containing layer in a feature on a substrate and depositing a tungsten (W)-containing layer on the Mo-containing layer, thereby filling the feature. In some embodiments, the method further includes annealing the Mo-containing layer before depositing the W-containing layer. The Mo-containing layer may be a template for W grain growth. In some embodiments, the Mo-containing layer is elemental Mo with less than 1 atomic % impurity. The Mo-containing layer may be relatively thin, e.g., 1-10 nm, or 1-5 nm thick. The W-containing layer may be at least 5, 10, or 20 times thicker than the Mo-containing layer. In some embodiments, the Mo-containing layer overlies a dielectric layer, such as a silicon oxide layer or an aluminum oxide layer. In some embodiments, the Mo-containing layer overlies a barrier layer, such as a titanium nitride layer. In some embodiments, the Mo-containing layer does not include fluorine impurities.

[0006] In some embodiments, the Mo-containing layer has an average crystallite size of at least 20 nm. In some embodiments, the W-containing layer has an average crystallite size of at least 20 nm.

[0007] The method may further include depositing a Mo-containing layer. In some embodiments, the Mo-containing layer is deposited from one or more molybdenum chloride precursors. Examples include molybdenum pentachloride (MoCl5), molybdenum dioxide dichloride (MoOCl2), and molybdenum oxide tetrachloride (MoOCl4). In some embodiments, depositing the Mo-containing layer includes performing an atomic layer deposition process in which a molybdenum chloride precursor is reduced by hydrogen.

[0008] In some embodiments, the W-containing layer is deposited using tungsten hexafluoride. The W-containing layer may be deposited without depositing a nucleation layer. In some embodiments, the W-containing layer is deposited by atomic layer deposition (ALD). In some embodiments, the tungsten-containing film is deposited by chemical vapor deposition (CVD).

[0009] Another aspect of the present disclosure may be implemented by a method including forming a conductive template layer on a substrate, the template layer being 1 to 5 nm thick; annealing the conductive template layer to increase grain size in the conductive template layer; and forming a bulk conductive layer on the template layer, wherein the grains in the bulk conductive layer follow the grains of the conductive template layer. In some embodiments, the conductive template layer is molybdenum. The bulk conductive layer may be selected from the group consisting of one of tungsten, cobalt, ruthenium, and nickel, and an alloy containing at least one of tungsten, cobalt, ruthenium, and nickel. In some embodiments, the conductive template layer is deposited to fill features, and the bulk conductive layer is deposited to fill the features with bulk conductive material.

[0010] Another aspect of the present disclosure may be practiced by a method including providing a partially fabricated 3D NAND structure having multiple oxide layers separated by gaps and conformally depositing a molybdenum template layer in the gaps, the molybdenum template layer being approximately 1-10 nm thick. In some embodiments, the molybdenum template layer is deposited directly on the oxide surface. In some embodiments, the molybdenum template layer is 1-5 nm thick. The method may further include filling the gaps with tungsten.

[0011] Another aspect of the present disclosure may be practiced by a method of filling a 3D structure of a partially fabricated semiconductor substrate with tungsten, the 3D structure comprising a sidewall and a plurality of openings in the sidewall leading to a plurality of features having a plurality of interior regions fluidly accessible through the openings, the method including depositing a first layer of molybdenum in the 3D structure such that the first layer conformally fills the plurality of features of the 3D structure, and depositing tungsten (W) on the Mo-containing layer, thereby filling the feature with tungsten.

[0012] Another aspect of the present disclosure may be practiced by an apparatus comprising one or more chambers, each configured to accommodate a substrate, a support substrate in each of the one or more chambers, a gas inlet configured to direct a gas into each of the one or more chambers, a heater configured to heat the substrate support in each chamber, and a controller including program instructions for injecting a molybdenum precursor into the one or more chambers and, after injecting the molybdenum precursor, injecting a tungsten precursor into the one or more chambers.

[0013] Another aspect of the present disclosure may be implemented by a 3D NAND structure including multiple tungsten word lines separated by an oxide layer and a thin film of molybdenum at the tungsten-oxide interface. In some embodiments, the thin film of molybdenum is 1-5 nm thick.

[0014] These and other aspects are discussed below with reference to the figures. [Brief explanation of the drawings]

[0015] [Figure 1A] FIG. 1A is a schematic example of a material stack including a molybdenum (Mo) template and a tungsten (W) conductor according to various embodiments. [Figure 1B] FIG. 1B is a schematic example of a material stack including a molybdenum (Mo) template and a tungsten (W) conductor according to various embodiments.

[0016] [Figure 2] Figure 2 shows a schematic example of a DRAM architecture including W buried word lines (bWL) on a Mo template.

[0017] [Figure 3A] FIG. 3A is a schematic example of a W word line in a 3D NAND structure.

[0018] [Figure 3B] FIG. 3B illustrates the material stack of a W word line including a Mo template layer.

[0019] [Figure 4] FIG. 4 is a process flow diagram illustrating operations in a method for depositing a conductive material.

[0020] [Figure 5] FIG. 5 is a process flow diagram illustrating operations in a method for filling a feature with tungsten.

[0021] [Figure 6] Figure 6 shows an image of a tungsten film deposited on a molybdenum template.

[0022] [Figure 7] FIG. 7 is a graph showing the decrease in resistivity for Mo films of various thicknesses after annealing at 800° C.

[0023] [Figure 8] FIG. 8 is a block diagram of a processing system suitable for carrying out deposition processes according to embodiments described herein. DETAILED DESCRIPTION OF THE INVENTION

[0024] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail in order to not unnecessarily obscure the disclosed embodiments. It should be understood that while the disclosed embodiments will be described in conjunction with specific embodiments, they are not intended to limit the disclosed embodiments.

[0025] Provided herein are low-resistivity metallization stack structures for logic and memory applications. FIGS. 1A and 1B are schematic examples of material stacks including molybdenum (Mo) as a template for tungsten growth. FIGS. 1A and 1B illustrate the order of materials in a particular stack, which may be used in any suitable architecture and application, as further described below with respect to FIGS. 2, 3A, and 3B. In the example of FIG. 1A, a substrate 102 has a Mo layer 108 deposited thereon. The substrate 102 may be a silicon or other semiconductor wafer, e.g., a 200 mm wafer, a 300 mm wafer, or a 450 mm wafer, including wafers having one or more layers of material, such as a dielectric material, a conductive material, or a semiconductive material, deposited thereon. The method may also be applied to forming metallization stack structures on other substrates, such as glass, plastic, and the like.

[0026] In FIG. 1A, a dielectric layer 104 is located on a substrate 102. The dielectric layer 104 may be deposited directly on the semiconductor (e.g., Si) surface of the substrate 102, or any number of intervening layers may be present. Examples of dielectric layers include doped and undoped silicon oxide, silicon nitride, and aluminum oxide layers, with specific examples including doped or undoped layers of SiO2 and Al2O3. Also in FIG. 1A, a diffusion barrier layer 106 is located between the Mo layer 108 and the dielectric layer 104. Examples of diffusion barrier layers include titanium nitride (TiN), titanium / titanium nitride (Ti / TiN), tungsten nitride (WN), and tungsten carbonitride (WCN). A further example of a diffusion barrier is a multi-component Mo-containing film, as described further below. A tungsten (W) layer 110 is deposited on the Mo layer 108 and is the primary conductor of the structure. As discussed further below, the Mo layer 108 provides a template for tungsten growth. In some embodiments, the resulting W layer 110 is deposited without a tungsten nucleation layer.

[0027] FIG. 1B shows another example of a material stack. In this example, the stack includes a substrate 102 and a dielectric layer 104, with a Mo layer 108 deposited directly on the dielectric layer 104 without an intervening diffusion barrier layer. As in the example of FIG. 1A, a W layer 110 is deposited on the Mo layer 108 and is the primary conductor of the structure. By using large-grained molybdenum as a template for tungsten growth, tungsten with large grains and low resistivity can be formed. Furthermore, resistivity can be improved by eliminating the higher-resistivity tungsten nucleation layer.

[0028] 1A and 1B show an example metallization stack, the method and resulting stack are not so limited. For example, in some embodiments, Mo may be deposited directly onto a Si or other semiconductor substrate as a template for tungsten growth.

[0029] Furthermore, although W growth on a Mo template is described in the above examples, the Mo layer may serve as a template for low-resistivity growth of other metals, including molybdenum (Mo), cobalt (Co), ruthenium (Ru), nickel (Ni), and alloys containing these metals, such as MoW.

[0030] The material stacks described above and further below may be used in various embodiments. Figures 2, 3A, and 3B provide examples of structures in which the stacks may be used. Figure 2 illustrates a schematic example of a DRAM architecture including a W buried wordline (bWL) 210 in a silicon substrate 202. The W bWL 210 is formed in a trench etched into the silicon substrate 202. Filling the trench is a conformal Mo layer 208 and an insulating layer 204 disposed between a conformal barrier layer 206 and the silicon substrate 202. In the example of Figure 2, the insulating layer 204 may be a gate oxide layer formed from a high-k dielectric material such as a silicon oxide or silicon nitride material. In some embodiments, a conformal barrier layer such as TiN or a tungsten-containing layer may be inserted between the Mo layer 208 and the insulating layer 204.

[0031] FIG. 3A illustrates a schematic example of W word lines 310 in a 3D NAND structure 323. The W word lines 310 are separated by oxide layers 311. FIG. 3B shows details of the interface between the W word lines 310 and oxide layer 311, including a layer of aluminum oxide (Al2O3) 304 and a Mo layer 308. As mentioned above, the W word lines 310 may be deposited on the Mo layer 308 without a tungsten nucleation layer. In some embodiments, the Mo layer 308 may be deposited directly on the oxide layer 311 or on a TiN or other barrier layer, as described herein. The Mo layer may be, for example, about 10 Å to 100 Å, or 10 Å to 50 Å, for deposition of a W word line layer of about 10 nm to 100 nm.

[0032] FIG. 4 is a process flow diagram illustrating operations in a method for depositing a conductive material. In operation 402, a template layer is formed. As described further below, this can include vapor deposition techniques such as chemical vapor deposition (CVD) and atomic layer deposition (ALD). The template layer is a material with relatively large grain growth, such as molybdenum. In some embodiments, the layer is relatively thin, 10 nm or less, or 50 nm or less. Generally, the layer is thick enough to grow continuously on the underlying structure. Exemplary thicknesses range from 1 nm to 5 nm, or from 2 nm to 5 nm. The template layer may conform to the underlying structure, as in the examples of FIGS. 2 and 3B. For challenging structures such as 3D NAND structures, ALD may be used to form a conformal layer. Exemplary surfaces on which the template layer may be formed include the surfaces of dielectric layers and barrier layers. In certain embodiments, the template layer may be deposited from a fluorine-free precursor, which prevents fluorine from migrating into the underlying structure.

[0033] In some embodiments, the template layer is annealed in operation 402. Thermal annealing of the layer can increase grain size and lower resistivity. Example annealing temperatures for molybdenum range from 700°C to 1100°C. Typically, the annealing is performed at or near the melting temperature. The annealing may be performed in a furnace or by rapid thermal annealing. According to various embodiments, the annealing may be performed in any suitable atmosphere, including a hydrogen (H2) atmosphere, a nitrogen (N2) atmosphere, or a vacuum. In some embodiments, the film may be exposed to a reducing environment before annealing to remove any oxide formation. Oxides are particularly likely to form if the template is exposed to air before annealing. In operation 406, a bulk layer is formed on the template layer. Deposition on the template results in an increased grain size. The bulk layer is generally the primary conductor of the structure. By depositing a bulk layer on the template, cheaper and / or more readily available precursors such as tungsten hexafluoride (WF6) or molybdenum hexafluoride (MoF6) may be used. Depending on the structure, ALD or CVD methods may be used. In one example, WF6 and H2 are used to deposit tungsten. The deposition of other bulk films is further described below.

[0034] Methods for forming Mo template layers include vapor deposition techniques such as CVD deposition and ALD deposition. In ALD techniques, pulses of a reducing agent (or other co-reactant), an optional purge gas, and a Mo-containing precursor are sequentially injected into a reaction chamber and purged from the reaction chamber. Alternatively, deposition of a Mo layer can occur via a CVD process in which a reducing agent and a Mo-containing precursor are flowed into a deposition chamber and a Mo layer is deposited on the feature. An inert carrier gas may be used to deliver one or more of the reactant streams, which may or may not be premixed. Unlike ALD processes, this operation generally requires continuous reactant flow until the desired amount is deposited. In certain embodiments, the CVD operation may be performed in multiple stages, with periods of continuous and simultaneous reactant flow separated by periods of bypassing one or more reactant flows.

[0035] Mo-containing precursors include molybdenum hexafluoride (MoF6), molybdenum pentachloride (MoCl5), molybdenum dioxide dichloride (MoO2Cl2), molybdenum oxide tetrachloride (MoOCl4), and molybdenum hexacarbonyl (Mo(CO)6). Organometallic precursors such as molybdenum silylcyclopentadienyl and molybdenum silylallyl complexes may also be used. Mo-containing precursors may also be halide precursors, including MoF6 and MoCl5, as well as mixed halide precursors with two or more halogens capable of forming stable molecules. An example of a mixed halide precursor is MoCl, which may form stable molecules. x Br y where x and y are any numbers greater than 0.

[0036] In certain embodiments, the Mo layer is deposited directly on a dielectric layer or a TiN or other barrier layer. In an ALD process, pulses of a co-reactant, an optional purge gas, and a Mo-containing precursor are sequentially injected into and purged from the reaction chamber. In some embodiments, a thin Mo layer is deposited using one or more of a boron-containing reducing agent (e.g., B2H6), a silicon-containing reducing agent (e.g., SiH4), or hydrogen (H2) as the co-reactant. For example, one or more S / Mo cycles (here, S / Mo refers to a pulse of silane followed by a pulse of a Mo-containing precursor) may be used to deposit a thin Mo layer that serves as a template for tungsten deposition. In another example, one or more B / Mo cycles (here, B / Mo refers to a pulse of diborane followed by a pulse of a Mo-containing precursor) may be used to deposit a thin Mo layer on a deposited tungsten layer. Both B / Mo and S / Mo cycles may be used to deposit a Mo layer, e.g., x(B / Mo)+y(S / Mo), where x and y are integers. Still further, one or more H2 / Mo cycles may be used to deposit a thin Mo layer, with or without a B / Mo and / or S / Mo cycle.

[0037] Depending on the thickness of the Mo layer and the structure of the deposited Mo layer, the deposition of the Mo layer can include deposition of a Mo nucleation layer followed by deposition of a bulk layer, hi some embodiments, this can include ALD deposition of a nucleation layer followed by CVD deposition of a bulk layer.

[0038] In some embodiments, deposition of the Mo template layer can include forming a reducing agent layer and subsequently exposing the reducing agent layer to a Mo-containing precursor. The reducing agent layer can include elemental silicon (Si), elemental boron (B), elemental germanium (Ge), or a mixture thereof, or can consist essentially of elemental silicon (Si), elemental boron (B), elemental germanium (Ge), or a mixture thereof. For example, the reducing agent layer can include Si and B. By adjusting the amount of B, a high deposition rate of the reducing agent layer can be achieved even with low resistivity.

[0039] The substrate temperature during Mo deposition can be between 300°C and 800°C. The substrate temperature will depend on the thermal budget and the species being deposited. The thermal budget is application dependent; high deposition temperatures may not be an issue for memory applications, but may exceed the thermal budget for logic applications.

[0040] FIG. 5 illustrates an example process for feature filling. The process of FIG. 5 may be used, for example, to fill tungsten word lines. In operation 502, a Mo template is deposited by ALD using a chlorine-containing Mo precursor. The ALD process can be used to achieve conformality and step coverage for challenging 3D NAND structures. An ALD cycle may be used to deposit, for example, a Mo layer of approximately 10 Å to 50 Å on the surface of a dielectric or barrier layer. In some embodiments, the ALD cycle uses H2 as a reducing agent without incorporating boron or silicon into the film. Additionally, the ALD cycle uses a chloride-containing precursor, which prevents exposure of the underlying dielectric layer to fluorine. For chlorine-containing Mo precursors, relatively high deposition temperatures may be used, for example, between 450°C and 800°C, and in some embodiments, at least 500°C, or between 550°C and 650°C. High temperatures facilitate deposition due to the relatively strong Mo-Cl bond in these precursors.

[0041] Next, in operation 504, the Mo template is annealed. As mentioned above, a reduction step to remove oxides may be performed before the anneal. This removes molybdenum dioxide (MoO2) or molybdenum trioxide (MoO3) that may have formed as a result of exposure to air or other oxidizing agents. MoO3, in particular, has a melting point of 795°C and may melt during the anneal if not removed. Next, in operation 506, a bulk layer is deposited on the Mo template to form the word lines or other conductors. The tungsten fill may include a fluorinated precursor such as WF6, with the Mo layer providing a barrier against fluorine migration into the dielectric. For 3D NAND structures, operation 506 may include alternating pulses of WF6 and H2 in the ALD deposition. In some embodiments, the deposition may be performed without forming a tungsten nucleation layer. Exemplary thicknesses of tungsten range from 50 Å to 300 Å. According to some embodiments, the thickness ratio of W:Mo may be 1:1 to 15:1, such as 2:1 to 10:1, or 2:1 to 5:1.

[0042] As mentioned above, the method discussed with reference to Figure 4 may be used to deposit other low resistivity bulk films on the template. Such films can include cobalt (Co), ruthenium (Ru), and nickel (Ni). Examples of cobalt precursors include dicarbonylcyclopentadienyl cobalt, cobalt carbonyl, cobalt amidinate precursors, cobalt diazadienyl complexes, and cobalt amidinate / guanidinate precursors. Examples of ruthenium precursors that may be used in the oxidation reaction include (ethylbenzyl)(1-ethyl-1,4-cyclohexadienyl)Ru(0), (1-isopropyl-4-methylbenzyl)(1,3-cyclohexadienyl)Ru(0), 2,3-dimethyl-1,3-butadienyl)Ru(0) tricarbonyl, (1,3-cyclohexadienyl)Ru(0) tricarbonyl, and (cyclopentadienyl)(ethyl)Ru(II) dicarbonyl. Examples of ruthenium precursors that react with non-oxidizing reactants are bis(5-methyl-2,4-hexanediketonato)Ru(II) dicarbonyl and bis(ethylcyclopentadienyl)Ru(II). Examples of nickel precursors include cyclopentadienylallylnickel (CpAllylNi) and MeCpNi.

[0043] As discussed above, ALD may be used to deposit bulk tungsten or other bulk materials. In particular, ALD may be used to deposit tungsten or other metals with lateral grain growth. Metals deposited in this manner have much greater grain growth than can be achieved with techniques such as CVD or sputtering, including greater lateral grain growth. In some embodiments, grains at least 100 Å wide are grown. Exemplary WALD deposition conditions that can provide lateral grain growth include substrate temperatures between 300°C and 500°C, or temperatures below 500°C and chamber pressures between 10 and 50 torr.

[0044] Example applications include 3D NAND wordline filling and DRAM bWL filling. In these applications, a single template layer of molybdenum (or other template layer) may be used to fill the remainder of the feature with tungsten (or other primary conductor). Other template layers of Mo may be deposited on layers such as titanium nitride (TiN) or oxides such as silicon oxide (e.g., SiO), aluminum oxide (e.g., AlO), hafnium oxide (e.g., HfO), and zirconium oxide (e.g., ZrO).

[0045] experiment Molybdenum films were grown directly on Al2O3, followed by annealing and deposition of tungsten. Figure 6 shows an image of a W film on a Mo film. The image shows that the W grains form templates from the underlying Mo grains.

[0046] In some embodiments, a thermal anneal is performed after Mo deposition. This allows for Mo grain growth and resistivity reduction. Because the melting point of Mo is lower than that of W, grain growth and the associated resistivity reduction occur at lower temperatures for Mo films. Example annealing temperatures range from 700°C to 1100°C. The annealing may be performed in a furnace or by rapid thermal annealing. According to various embodiments, the annealing may be performed in any suitable atmosphere, including a hydrogen (H2) atmosphere, a nitrogen (N2) atmosphere, or a vacuum.

[0047] According to various embodiments, the Mo film may or may not be exposed to air between deposition and annealing. If exposed to air or other oxidizing environments, a reducing environment may be used during or before annealing to remove molybdenum dioxide (MoO2) or molybdenum trioxide (MoO3) formed as a result of the exposure. MoO3, in particular, has a melting point of 795°C and may melt during annealing if not removed.

[0048] Table 1 below compares two W films (A and B) and two Mo films (C and D). [Table 1]

[0049] Film A is a tungsten film deposited using WF6. Film B is a tungsten film deposited using WCl5 and WCl6. Film C is a molybdenum film deposited using MoCl5, and Film D is a molybdenum film deposited using MoOCl4. Film D underwent a post-deposition anneal. Notably, the resistivity is lower for Films C and D than for Films A and B. The resistivity decreases with thickness, with 25 μΩ-cm (Film C) and 17 μΩ-cm (Film D) directly comparable to 40 μΩ-cm (Film A). Film D, deposited with an O-containing precursor, exhibits low O. The stress of Films C and D is comparable to that of Films A and B.

[0050] Figure 7 is a graph showing the decrease in resistivity for Mo films of various thicknesses deposited on WCN after annealing at 800°C. For comparison, the resistivity of a W film on WCN is also shown. A significant decrease in resistivity is observed. The decrease in resistivity is due to grain growth. Table 2 below shows the phase and average grain size for Mo particles in CVD Mo films after deposition and annealing. [Table 2] Furnace annealing at 800°C for 1 hour and 5 minutes in a H2 atmosphere showed comparable results.

[0051] Device Any suitable chamber may be used to practice the disclosed embodiments. Exemplary deposition apparatus include various systems, such as the ALTUS™ and ALTUS™ Max available from Lam Research, Inc., Fremont, Calif., or any of a variety of other commercially available process systems. Processes can be performed in parallel at multiple deposition stations.

[0052] In some embodiments, the molybdenum template deposition process is performed in a first station, which is one of two, five, or even more deposition stations positioned within a single deposition chamber. In some embodiments, various steps for the process are performed in two different stations within the deposition chamber. For example, the substrate may be exposed to H in the first station using individual gas supply systems to create a local atmosphere at the substrate surface, and then the substrate may be transferred to the second station for exposure to a precursor such as MoOCl to deposit the template layer. In some embodiments, the substrate may then be returned to the first station for a second exposure to hydrogen. The substrate may then be transferred to the second station for exposure to MoOCl (or other tungsten chloride). This may be repeated as necessary to complete the Mo template deposition, and tungsten deposition may proceed in the same or a different station. Tungsten deposition may then be performed as described above using one or more stations.

[0053] FIG. 8 is a block diagram of a process system suitable for carrying out deposition processes according to embodiments described herein. System 800 includes a transfer module 803. Transfer module 803 provides a clean, pressurized environment to minimize the risk of substrate contamination as the substrate moves between various reactor modules during processing. According to embodiments described herein, transfer module 803 is fitted with a multi-station reactor 809 capable of performing nucleation layer deposition (sometimes referred to as pulsed nucleation layer (PNL) deposition), as well as ALD and CVD deposition. Chamber 809 may include multiple stations 811, 813, 815, and 817 capable of sequentially performing these operations. For example, chamber 809 may be configured such that stations 811 and 813 perform PNL or ALD deposition, and stations 813 and 815 perform CVD. Each deposition station may include a heated wafer pedestal and a showerhead, distribution plate, or other gas inlet.

[0054] The transfer module 803 may also be fitted with one or more single-station or multi-station modules 807 capable of performing plasma or chemical (non-plasma) pre-cleaning. Modules may also be used for various other processes, such as reducing agent soaks. The system 800 also includes one or more (in this case, two) wafer source modules 801 that store pre- and post-process wafers. An atmospheric robot (not shown) in the atmospheric transfer chamber 819 initially removes wafers from the source modules 801 and transfers them to the load lock 821. A wafer transfer device (typically a robot arm unit) in the transfer module 803 moves wafers from the load lock 821 to the modules attached to the transfer module 803 and between modules.

[0055] In certain embodiments, a system controller 829 is used to control process conditions during deposition. The controller will typically include one or more memory devices and one or more processors. The processor may include a CPU or computer, analog and / or digital input / output connections, stepper motor controller boards, etc.

[0056] The controller may control all of the deposition equipment's activities. The system controller executes system control software that includes a set of instructions for controlling the timing, mixture of gases, chamber pressure, chamber temperature, wafer temperature, radio frequency (RF) power levels, if used, wafer chuck or pedestal position, and other parameters of a particular process. In some embodiments, other computer programs stored on memory devices associated with the controller may be used.

[0057] Typically, there will be a user interface associated with the controller, which may include a display screen, a graphical software display of equipment and / or process conditions, and user input devices such as a pointing device, keyboard, touch screen, microphone, etc.

[0058] The system control logic may be configured in any suitable manner. In general, logic may be designed or configured in hardware and / or software. Instructions for controlling the drive circuitry may be hard-coded or provided as software. The instructions may be provided by “programming.” Such programming is understood to include all forms of logic, including hard-coded logic in digital signal processors, application-specific integrated circuits, and other devices with specific algorithms implemented as hardware. Programming is also understood to include software or firmware instructions executable on a general-purpose processor. The system control software may be coded in any suitable computer-readable programming language. Alternatively, the control logic may be hard-coded into the controller. For these purposes, application-specific integrated circuits, programmable logic devices (e.g., field-programmable gate arrays, or FPGAs), etc. may be used. In the following description, where “software” or “code” is used, functionally equivalent hard-coded logic may be utilized instead.

[0059] Computer program code for controlling deposition and other processes in a process sequence can be written in any conventional computer-readable programming language, such as assembly language, C, C++, Pascal, Fortran, etc. The compiled object code or script is executed by a processor to perform the tasks identified in the program.

[0060] The controller parameters relate to process conditions such as, for example, process gas composition and flow rates, temperature, pressure, cooling gas pressure, and chamber wall temperature, etc. These parameters are provided to the user in the form of a recipe and can be entered using a user interface.

[0061] Signals for monitoring the process may be provided by analog and / or digital input connections of the system controller, and signals for controlling the process are output at analog and digital output connections of the deposition device.

[0062] The system software may be designed or configured in many different ways. For example, various chamber component subroutines or control objects may be written to control the operation of the chamber components necessary to carry out the deposition processes described herein. Examples of programs or sections of programs for this purpose include substrate positioning code, process gas control code, pressure control code, heater control code, and plasma control code.

[0063] In some embodiments, the controller 829 is part of a system, and such a system may be part of the examples described above. Such a system may include semiconductor processing equipment, including one or more process tools, one or more chambers, one or more processing platforms, and / or specific process components (such as a wafer pedestal, gas flow system, etc.). These systems may be integrated with electronics for controlling system operation before, during, and after semiconductor wafer or substrate processing. Such electronics may be referred to as a “controller” and may control various components or subcomponents of one or more systems. The controller 829 may be programmed to control any of the processes disclosed herein, depending on the process requirements and / or type of system. Such processes may include process gas delivery, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings in some systems, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and motion settings, wafer transfer to and from the tool, and wafer transfer to and from other transfer tools and / or load locks connected or interfaced with the particular system.

[0064] Broadly, a controller may be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. Integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application-specific integrated circuits (ASICs), and / or one or more microprocessors, i.e., microcontrollers, that execute program instructions (e.g., software). Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files) that define operational parameters for performing a particular process on or for a semiconductor wafer or for a system. In some embodiments, the operational parameters are part of a recipe defined by a process engineer that may enable one or more process steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer dies.

[0065] In some embodiments, the controller 829 may be part of, coupled to, or a combination of a computer integrated with or otherwise networked to the system. For example, the controller 829 may be in the “cloud” or may be all or part of a fab host computer system. This enables remote access of wafer processing. The computer may provide remote access to the system to monitor the current progress of a fabrication operation, examine the history of past fabrication operations, examine trends or performance criteria from multiple fabrication operations, modify parameters of a current process, set process steps following a current process, or initiate a new process. In some examples, a remote computer (e.g., a server) can provide process recipes to the system over a network. Such a network may include a local network or the Internet. The remote computer may include a user interface that enables entry or programming of parameters and / or settings, which are then communicated to the system from the remote computer. In some examples, the controller receives instructions in the form of data. Such data identifies parameters for each process step performed during one or more operations. It should be understood that the parameters may be specific to the type of process being performed and the type of tool the controller is configured to interface with or control. Thus, as noted above, the controller may be distributed, for example, by including one or more individual controllers networked together and cooperating toward a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes would include one or more integrated circuits on the chamber that are located remotely (e.g., at the platform level or as part of a remote computer) and communicate with one or more integrated circuits that couple to control the process on the chamber.

[0066] Without limitation, exemplary systems may include plasma etch chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel edge etch chambers or modules, physical vapor deposition (PVD) chambers or modules, CVD chambers or modules, ALD chambers or modules, atomic layer etch (ALE) chambers or modules, ion implantation chambers or modules, tracking chambers or modules, and any other semiconductor processing systems that may be associated with or used in the fabrication and / or manufacturing of semiconductor wafers.

[0067] As described above, depending on the process step or steps being performed by the tool, the controller may communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used in material transport to and from tool locations and / or load ports in a semiconductor fabrication factory.

[0068] The controller 829 may include a variety of programs. A substrate positioning program may include program code for controlling chamber components used to load a substrate onto a pedestal or chuck and control the spacing between the substrate and other parts of the chamber, such as a gas inlet and / or target. A process gas control program may include code for controlling gas composition and flow rates to stabilize the pressure in the chamber, and optionally, code for flowing gas into the chamber before deposition. A pressure control program may include code for controlling the pressure in the chamber, for example, by adjusting a throttle valve in the chamber's exhaust system. A heater control program may include code for controlling the current to a heating unit used to heat the substrate. Alternatively, the heater control program may control the delivery of a heat transfer gas (such as helium) to the wafer chuck.

[0069] Examples of chamber sensors that can be monitored during deposition include mass flow controllers, pressure sensors such as pressure gauges, and thermocouples located in the pedestal or chuck. Appropriately programmed feedback and control algorithms may be used in conjunction with data from these sensors to maintain desired process conditions.

[0070] The implementation of embodiments of the present disclosure in single or multi-chamber semiconductor processing tools has been described above.

[0071] The implementation of the disclosed embodiments in single-chamber or multi-chamber semiconductor processing tools has been described above. The apparatus and processes described herein may be used in conjunction with lithographic patterning tools or processes, for example, for the fabrication or manufacture of semiconductor devices, displays, LEDs, solar panels, etc. Typically, although not necessarily, such tools / processes will be used or performed together in a common fabrication facility. Lithographic patterning of films typically involves some or all of the following steps, each of which is provided with numerous possible tools: (1) applying photoresist to a workpiece (i.e., substrate) using a spin-on or spray-on tool; (2) curing the photoresist using a hotplate or furnace or UV curing tool; (3) exposing the photoresist to visible or UV or X-ray light using a tool such as a wafer stepper; (4) developing the resist to selectively remove and thereby pattern the resist using a tool such as a wet bench; (5) transferring the resist pattern to the underlying film or workpiece by using a dry etching tool or a plasma-assisted etching tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper.

[0072] In the above description and claims, numerical ranges include the endpoints of the range. For example, "a thickness of 1 to 5 nm" includes 1 nm and 5 nm. Similarly, ranges expressed with a prime include the endpoints of the range.

[0073] conclusion Although the foregoing embodiments have been described in some detail for clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems, and apparatus of the present embodiments. Therefore, the present embodiments should be considered as illustrative rather than restrictive, and the present embodiments should not be limited to the details set forth herein. The present disclosure can also be realized as the following application examples. [Application example 1] depositing a molybdenum (Mo)-containing layer in a feature on a substrate; depositing tungsten (W) on the Mo-containing layer, thereby filling the feature with tungsten; A method comprising: [Application example 2] The method according to Application Example 1, The method further comprising thermally annealing the Mo-containing layer before depositing tungsten. [Application example 3] The method according to Application Example 1, The method wherein the Mo-containing layer is a template for W grain growth. [Application example 4] The method according to Application Example 1, The method wherein the Mo-containing layer is elemental Mo with less than 1 atomic % impurities. [Application example 5] The method according to Application Example 1, The Mo-containing layer has a thickness of 1 to 10 nm. [Application Example 6] The method according to Application Example 1, The method wherein the Mo-containing layer is overlying a dielectric layer. [Application Example 7] The method according to Application Example 1, The method, wherein the Mo-containing layer does not contain fluorine impurities. [Application Example 8] The method according to Application Example 1, The method further comprising depositing the Mo-containing layer. [Application Example 9] The method according to Application Example 8, The method wherein the Mo-containing layer is deposited from one or more molybdenum chloride precursors. [Application Example 10] The method according to Application Example 9, The one or more molybdenum chloride precursors may be molybdenum pentachloride (MoCl 5 ), molybdenum dioxide dichloride (MoO 2 Cl 2 ), and molybdenum oxide tetrachloride (MoOCl 4 ) a method selected from the above. [Application Example 11] The method according to Application Example 8, The method, wherein depositing the Mo-containing layer comprises performing an atomic layer deposition process in which a molybdenum chloride precursor is reduced by hydrogen. [Application Example 12] The method according to Application Example 1, The method wherein the tungsten is deposited using tungsten hexafluoride. [Application Example 13] The method according to Application Example 1, The method wherein the Mo-containing layer has an average crystallite size of at least 20 nm. [Application Example 14] The method according to Application Example 1, The method wherein the average crystallites of the tungsten are at least 20 nm. [Application Example 15] The method according to Application Example 1, The method wherein the tungsten is deposited without depositing a nucleation layer. [Application Example 16] The method according to Application Example 1, The method wherein the tungsten is deposited by atomic layer ALD. [Application Example 17] 1. A method of filling a 3D structure of a partially fabricated semiconductor substrate with tungsten, the 3D structure comprising a sidewall and a plurality of openings in the sidewall that lead to a plurality of features having a plurality of interior regions fluidly accessible through the openings, the method comprising: depositing a first layer of molybdenum within the 3D structure such that the first layer conformally fills the plurality of features of the 3D structure; depositing tungsten (W) on the Mo-containing layer, thereby filling the feature with tungsten; A method comprising: [Application Example 18] forming a conductive template layer on a substrate, the conductive template layer having a thickness of 1 to 5 nm; annealing the conductive template layer to increase grain size in the conductive template layer; forming a bulk conductive layer on the template layer, wherein particles in the bulk conductive layer follow particles of the conductive template layer; A method comprising: [Application Example 19] The method according to Application Example 18, The method wherein the conductive template layer is molybdenum. [Application Example 20] The method according to Application Example 19, The method of claim 1, wherein the bulk conductive layer is selected from the group consisting of one of tungsten, cobalt, ruthenium, nickel, and an alloy containing at least one of tungsten, cobalt, ruthenium, and nickel. [Application Example 21] providing a partially fabricated 3D NAND structure having a plurality of oxide layers separated by gaps; conformally depositing a molybdenum template layer in the gap; A method comprising: [Application Example 22] The method according to Application Example 21, The molybdenum template layer is about 1-10 nm thick. [Application Example 23] The method according to Application Example 21, The method wherein the molybdenum template layer is deposited directly on an oxide surface. [Application Example 24] The method according to Application Example 21, The molybdenum template layer is 1 to 5 nm thick. [Application Example 25] The method according to Application Example 21, The method further comprising filling the gap with tungsten. [Application Example 26] one or more chambers, each configured to accommodate a substrate; a support substrate in each of the one or more chambers; a gas inlet configured to direct a gas into each of the one or more chambers; a heater configured to heat the substrate support in each chamber; injecting a molybdenum precursor into the one or more chambers; injecting a tungsten precursor into the one or more chambers after injecting the molybdenum precursor; a controller containing program instructions for An apparatus comprising: [Application Example 27] a plurality of tungsten word lines separated by an oxide layer; Molybdenum thin films at the tungsten-oxide interface and 3D NAND structure.

Claims

1. forming a first molybdenum (Mo) layer by exposing the substrate to molybdenum oxychloride and a boron-containing reducing agent in a reaction chamber; Hydrogen (H 2 forming a bulk conductive layer on the first Mo layer using Including, The molybdenum oxychloride is molybdenum dioxide dichloride (MoO 2 Cl 2 ), and molybdenum oxide tetrachloride (MoOCl 4 ) method.

2. 10. The method of claim 1, Forming the first Mo layer includes: 2 The method of claim 1, further comprising exposing the

3. 10. The method of claim 1, The method wherein the temperature of the substrate during the formation of the first Mo layer is between 300°C and 800°C.

4. 10. The method of claim 1, The molybdenum oxychloride is molybdenum dioxide dichloride (MoO 2 Cl 2 ) a method.

5. 10. The method of claim 1, The method wherein the first Mo layer is formed by atomic layer deposition (ALD).

6. 10. The method of claim 1, The method wherein the bulk conductive layer is formed by chemical vapor deposition (CVD).

7. 10. The method of claim 1, The method wherein the bulk conductive layer is formed by ALD.

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