Semiconductor Devices

Abstract

To provide a semiconductor device capable of reducing ON resistance and reducing ON loss.SOLUTION: A semiconductor device comprises an n type drift layer. The semiconductor device comprises a p type body layer in contact with an upper surface of the drift layer. The semiconductor device comprises an n type source region arranged above the body layer. The semiconductor device comprises a trench penetrating the body layer from an upper surface of the source region to reach the drift layer. The semiconductor device comprises a gate electrode arranged in the trench with a gate insulation film interposed. The semiconductor device comprises a first p type region arranged in the drift layer and also in a region below a bottom face of the trench apart from the bottom face of the trench. The semiconductor device comprises a second p type region arranged in the drift layer and also in a region below a lower surface of the first p type region apart from the lower surface of the first p type region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a semiconductor device. [Background technology]

[0002] In trench gate semiconductor devices, increasing the concentration of the n-type drift layer is effective in achieving low on-resistance. This allows for a large current. Related technology is disclosed in Patent Document 1. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2020-141130 Summary of the Invention [Problem to be solved by the invention]

[0004] Gate-drain capacitance is formed in the n-type drift layer directly below the trench gate. When a p-n junction is formed below the trench gate, the smaller the extension of the depletion layer from the p-n junction, the smaller the electrode distance for the gate-drain capacitance, and therefore the larger the gate-drain capacitance. As the gate-drain capacitance increases, the rise time of the gate voltage on increases, resulting in greater losses during transient turn-on. In other words, increasing the concentration of the n-type drift layer increases the gate-drain capacitance and the on-loss. [Means for solving the problem]

[0005] One embodiment of a semiconductor device disclosed in this specification includes an n-type drift layer. The semiconductor device includes a p-type body layer in contact with an upper surface of the drift layer. The semiconductor device includes an n-type source region disposed on top of the body layer. The semiconductor device includes a trench extending from an upper surface of the source region through the body layer to reach the drift layer. The semiconductor device includes a gate electrode disposed in the trench with a gate insulating film interposed therebetween. The semiconductor device includes a first p-type region disposed in the drift layer below a bottom surface of the trench and spaced apart from the bottom surface of the trench. The semiconductor device includes a second p-type region disposed in the drift layer below a bottom surface of the first p-type region and spaced apart from the bottom surface of the first p-type region.

[0006] In the above configuration, a first pn junction can be formed by the upper surface of the first p-type region and the drift layer between the first p-type region and the bottom of the trench. A second pn junction can be formed by the lower surface of the first p-type region and the drift layer between the first p-type region and the second p-type region. A third pn junction can be formed by the upper surface of the second p-type region and the drift layer between the first p-type region and the second p-type region. Because the depletion layer can be expanded from each of the three pn junctions, the depletion layer can be expanded more widely than in a single pn junction. Therefore, even when the impurity concentration of the drift layer is high, the gate-drain capacitance can be reduced, thereby minimizing losses during transient turn-on. This allows for both reduced on-resistance and on-loss.

[0007] The semiconductor device may further include a third p-type region disposed in the drift layer below the lower surface of the second p-type region and in contact with the lower surface of the second p-type region. The impurity concentration of the second p-type region may be higher than the impurity concentration of the third p-type region. Details of the effects will be described in the examples.

[0008] A first n-type region may be located between the bottom of the trench and the first p-type region. A second n-type region may be located between the first p-type region and the second p-type region. A depletion layer extending from each pn junction interface may cover the entire first n-type region, the first p-type region, and the second n-type region. Details of the effects will be explained in the examples.

[0009] The second p-type region may be connected to the body layer. The impurity concentration of the second p-type region may be higher than the impurity concentration of the first p-type region. Details of the effects will be described in the examples.

[0010] The second p-type region may have a thickness in the depth direction greater than the thickness in the depth direction of the first p-type region.

[0011] When the distance from the bottom surface of the trench to the upper surface of the first p-type region is defined as a first distance and the distance from the bottom surface of the trench to the upper surface of the second p-type region is defined as a second distance, the ratio of the first distance to the second distance may be in the range of 0.2 to 0.7. Details of the effects will be described in the examples.

[0012] A first n-type region may be located between the bottom of the trench and the first p-type region. The ratio of the impurity concentration of the first p-type region to the impurity concentration of the first n-type region may be in the range of 1 to 2.5. Details of the effects will be described in the examples.

[0013] When the width of the bottom surface of the trench in a direction parallel to the surface of the semiconductor substrate is defined as the trench width and the width of the first p-type region in a direction parallel to the surface of the semiconductor substrate is defined as the first width, the ratio of the first width to the trench width may be in the range of 1 to 1.6. Details of the effects will be described in the examples.

[0014] When the width of the bottom surface of the trench in a direction parallel to the surface of the semiconductor substrate is defined as the trench width and the width of the second p-type region in a direction parallel to the surface of the semiconductor substrate is defined as the second width, the ratio of the second width to the trench width may be in the range of 1 to 1.6. Details of the effects will be described in the examples. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 2 is a cross-sectional view of the semiconductor device 1. [Figure 2] FIG. 10 is a cross-sectional view of the semiconductor device 1 in a state where the depletion layer DL1 has expanded. [Figure 3] FIG. 1 is a cross-sectional view of a semiconductor device 100 of a comparative example. [Figure 4] 10 shows the results of a simulation in which the depth of the first p-type region 41 is changed. [Figure 5] 10 shows the results of a simulation in which the width Wp of the first p-type region 41 is changed. [Figure 6] 10 shows the results of a simulation in which the width Wp2 of the second p-type region 42 is changed. DETAILED DESCRIPTION OF THE INVENTION

[0016] FIG. 1 shows a cross-sectional side view of a semiconductor device 1. FIG. 1 shows only a partial cross section of the semiconductor device 1. The unit structure shown in FIG. 1 is repeatedly formed in the semiconductor device 1. The semiconductor device 1 is a power semiconductor element known as a MOSFET. The semiconductor device 1 is a trench gate type.

[0017] In Figure 1, reference numeral 10 denotes a SiC substrate. The direction parallel to a surface 10s of the SiC substrate 10 and extending to the left and right of the paper surface is the x-direction, and the direction perpendicular to the paper surface is the y-direction. The direction perpendicular to the surface 10s is the z-direction. A source electrode 30 is formed on the surface 10s of the SiC substrate 10, and a drain electrode 31 is formed on the back surface.

[0018] The SiC substrate 10 is + a drain layer 11, an n-type drift layer 12, a p-type body layer 13, and an n + type source region 14 and p +The SiC substrate 10 includes a body contact region 15. A trench 20 is formed in the SiC substrate 10, extending from the upper surface of the source region 14, through the source region 14 and the body layer 13, and reaching the drift layer 12. A conductive trench gate electrode 23 is filled inside the trench 20 with a gate insulating film 22 interposed therebetween. The gate insulating film 22 disposed on the bottom surface 20b of the trench 20 has a thickness GT1. The gate insulating film 22 disposed on the side surface 20s of the trench 20 has a thickness GT2. The thickness GT1 is greater than the thickness GT2. An interlayer insulating film 24 is formed on the upper surface of the trench gate electrode 23. The interlayer insulating film 24 insulates the trench gate electrode 23 from the source electrode 30.

[0019] The impurity concentration of the drift layer 12 is set to a high concentration so as to reduce the on-resistance. In this embodiment, the impurity concentration is 1 to 4×10 17 (cm -3 ) In a region within the drift layer 12 below the bottom surface 20b of the trench 20, a first p-type region 41, a second p-type region 42, and a third p-type region 43 are arranged. The first p-type region 41 is arranged at a distance from the bottom surface 20b of the trench 20. The second p-type region 42 is arranged in a region below (on the −z direction side of) a lower surface 41u of the first p-type region 41 at a distance from the lower surface 41u. The third p-type region 43 is arranged in a region below a lower surface 42u of the second p-type region 42 in contact with the lower surface 42u. The impurity concentration of the second p-type region 42 is higher than the impurity concentration of the third p-type region 43. The change in impurity concentration between the second p-type region 42 and the third p-type region 43 may be gradual. As a result, the boundary between the second p-type region 42 and the third p-type region 43 may have a width in the depth direction. A first n-type region n1 is located between the bottom surface 20b of the trench 20 and the first p-type region 41. A second n-type region n2 is located between the first p-type region 41 and the second p-type region 42. The first n-type region n1 and the second n-type region n2 are part of the drift layer 12.

[0020] The first p-type region 41 has a thickness PT1 in the depth direction (-z direction). The second p-type region 42 and the third p-type region 43 have a thickness PT2 in the depth direction. The thickness PT2 is thicker than the thickness PT1. The second p-type region 42 is connected to the body layer 13 at a position in the y direction (direction perpendicular to the paper). The impurity concentration of the second p-type region 42 is higher than the impurity concentration of the first p-type region 41. This allows the second p-type region 42 to be maintained at the same potential as the body layer 13. Therefore, a superjunction structure is formed in which a depletion layer extends from the second p-type region 42 to the second n-type region n2.

[0021] FIG. 2 shows the semiconductor device 1 in a state in which the depletion layer DL1 has expanded. A first pn junction is formed between the upper surface of the first p-type region 41 and the first n-type region n1. A second pn junction is formed between the lower surface of the first p-type region 41 and the second n-type region n2. A third pn junction is formed between the upper surface of the second p-type region 42 and the second n-type region n2. Built-in potentials cause depletion layers to expand from each of these three pn junctions and connect them to each other. This forms a depletion layer DL1 that covers the entire first n-type region n1, the first p-type region 41, and the second n-type region n2.

[0022] The impurity distribution may be set in consideration of charge balance (a state in which depletion is easily caused) in the four layers of the first n-type region n1, the first p-type region 41, the second n-type region n2, and the second p-type region 42. The impurity concentrations of the first n-type region n1 and the second n-type region n2 are offset by the first p-type region 41 and the second p-type region 42, resulting in a lower concentration, which promotes depletion directly below the bottom surface 20b. Even if the impurity concentrations of the first n-type region n1 and the second n-type region n2 decrease, the on-resistance of the semiconductor device 1 does not deteriorate. This is because, as shown in FIG. 2, the current path CP is formed on the side of the first n-type region n1 and the second n-type region n2. Furthermore, almost no current flows through the first n-type region n1 and the second n-type region n2.

[0023] (assignment) The problem will be explained using a semiconductor device 100 of a comparative example in Fig. 3. Unlike the semiconductor device 1 of this embodiment (Fig. 1), the semiconductor device 100 of the comparative example does not include a first p-type region 41. In the semiconductor device 100 of the comparative example, the depletion layer DL100 extending upward from the second p-type region 42 does not reach the bottom surface 20b of the trench 20. Therefore, a non-depleted drift layer 12 exists below the bottom surface 20b of the trench 20.

[0024] The semiconductor device 100 has a gate-drain capacitance Cgd (also called feedback capacitance). The gate-drain capacitance Cgd includes an oxide film capacitance Cox and a MOS capacitance Cm. The oxide film capacitance Cox is a parasitic capacitance due to the gate insulating film 22 disposed on the bottom surface 20b. The MOS capacitance Cm is a parasitic capacitance due to the MOS structure (trench gate electrode 23, gate insulating film 22, and drift layer 12) directly below the bottom surface 20b. The magnitude of the MOS capacitance Cm is determined by the distance d100 in the depth direction of the depletion layer DL100. Since the distance d100 corresponds to the distance between the electrodes of the capacitance, the MOS capacitance Cm increases as the distance d100 decreases.

[0025] One method for achieving low on-resistance in the semiconductor device 100 is to increase the impurity concentration in the drift layer 12, which serves as the current path. This reduces the resistance of the drift layer 12 and allows for an increase in current. However, this makes it difficult for the depletion layer DL100 to expand, reducing the distance d100 and increasing the MOS capacitance Cm. As a result, the gate-drain capacitance Cgd increases. As the gate-drain capacitance Cgd increases, the rise time of the gate voltage on (time constant t = Cgd × gate resistance Rg) increases. This increases losses during transient turn-on. From the above, it can be seen that there is a trade-off between reducing on-resistance and reducing on-loss, and it is difficult to simultaneously improve both.

[0026] (effect) In the semiconductor device 1 of this embodiment (FIG. 2), a depletion layer DL1 can be formed that entirely covers the first n-type region n1, the first p-type region 41, and the second n-type region n2. Therefore, the depth distance d1 of the depletion layer DL1 can be made larger than the distance d100 of the depletion layer DL100 in the comparative example (FIG. 3). This reduces the MOS capacitance Cm, thereby enabling the gate-drain capacitance Cgd to be reduced. The rise time of the gate voltage ON can be shortened, thereby reducing ON-state loss. Furthermore, the gate-drain capacitance Cgd can be reduced while maintaining a high impurity concentration in the drift layer 12, thereby maintaining a low ON-state resistance. Therefore, it is possible to simultaneously achieve reduced ON-state resistance and ON-state loss.

[0027] The thickness GT1 of the gate insulating film 22 disposed on the bottom surface 20b corresponds to the inter-electrode distance of the oxide film capacitance Cox, and therefore, the larger the thickness GT1, the smaller the oxide film capacitance Cox. In the semiconductor device 1 of this embodiment, the thickness GT1 at the bottom surface 20b is made thicker than the thickness GT2 at the side surface 20s. This reduces the oxide film capacitance Cox, and therefore the gate-drain capacitance Cgd.

[0028] (Simulation results (part 1)) FIG. 4 shows the simulation results of the turn-on loss E and the on-resistance Ron when the depth of the first p-type region 41 is changed. FIG. 4(A) shows an enlarged view of a part of the cross-sectional structure. Since it is symmetrical with respect to the center line CL of the trench 20, only the right half is shown. The simulation was performed under the following conditions. The trench width Wg of the bottom surface 20b of the trench 20 was set to 0.25 μm. The width Wp of the first p-type region 41 was set to 0.35 μm. In other words, the ratio of the width Wp to the trench width Wg (Wp / Wg) was set to 1.4. The impurity concentration ICn of the first n-type region n1 was set to 1.2×10 17 (cm -3 ) was decided.

[0029] The distance from the bottom surface 20b to the upper surface of the first p-type region 41 is defined as the first distance Dp. The distance from the bottom surface 20b to the upper surface of the second p-type region 42 is defined as the second distance Tepi. The ratio of the first distance Dp to the second distance Tepi (Dp / Tepi) was changed to five levels from 0.1 to 0.8, and the turn-on loss E (FIG. 4(B)) and the on-resistance Ron (FIG. 4(C)) were obtained. Note that Dp / Tepi of "0.1" indicates a state in which the first p-type region 41 is in contact with the bottom surface 20b. Furthermore, Dp / Tepi of "1" indicates a state in which the first p-type region 41 is not present. Each of the graphs G1 to G4 shows the impurity concentration ICp of the first p-type region 41 at 1.5×10 17 (cm -3 ), 2×10 17 (cm -3 ), 3×10 17 (cm -3 ), 3.5×10 17 (cm -3 ) is shown.

[0030] As shown in Figure 4(B), when Dp / Tepi is 0.7 or less, the turn-on loss E is significantly reduced. Also, as shown in Figure 4(C), when Dp / Tepi is 0.2 or more, the on-resistance Ron is significantly reduced. From the above, it can be seen that the preferable range SR1 of Dp / Tepi is 0.2 to 0.7.

[0031] As shown in Figure 4(B), the impurity concentration ICp is 3.5 × 10 17 (cm -3 ), there is a region where the turn-on loss E becomes extremely large (see region R1). Therefore, the impurity concentration ICp is 3.0×10 17 (cm -3 ) or less. That is, the ratio (ICp / ICn) of the impurity concentration ICp of the first p-type region n1 to the impurity concentration ICn of the first n-type region n1 is preferably within the range of 1 to 2.5.

[0032] (Simulation results (part 2)) Figure 5 shows the simulation results of the turn-on loss E and the on-resistance Ron when the width Wp of the first p-type region 41 is changed. The content of Figure 5 is the same as Figure 4, so a detailed explanation will be omitted. The simulation was performed under the following conditions: Dp / Tepi was fixed at 0.5; and the trench width Wg in the x-direction of the bottom surface 20b was set to 0.25 µm.

[0033] The ratio of the width Wp to the trench width Wg (Wp / Wg) was changed from 0 to 1.6, and the turn-on loss E (FIG. 5(B)) and the on-resistance Ron (FIG. 5(C)) were obtained. Note that Wp / Wg being "0" indicates a state in which the first p-type region 41 does not exist.

[0034] As shown in Fig. 5(B), it can be seen that the turn-on loss E is significantly reduced when Wp / Wg is equal to or greater than 1. From the above, it can be seen that the preferable range SR2 of Wp / Wg is 1 to 1.6.

[0035] (Simulation results (part 3)) Figure 6 shows the simulation results of the turn-on loss E and the on-resistance Ron when the width Wp2 of the second p-type region 42 is changed. Since the content of Figure 6 is the same as Figures 4 and 5, a detailed description will be omitted. The simulation was performed under the following conditions: Dp / Tepi was fixed at 0.5; the trench width Wg of the bottom surface 20b and the width Wp of the first p-type region 41 were set to 0.25 µm.

[0036] The ratio of the width Wp2 to the trench width Wg (Wp2 / Wg) was changed from 0 to 1.6, and the turn-on loss E (FIG. 6(B)) and the on-resistance Ron (FIG. 6(C)) were obtained. Note that Wp2 / Wg being "0" indicates a state in which the second p-type region 42 is not present.

[0037] As shown in Fig. 6(B), it can be seen that the turn-on loss E becomes significantly smaller when Wp2 / Wg is equal to or greater than 1. From the above, it can be seen that the preferable range SR3 of Wp2 / Wg is 1 to 1.6.

[0038] (Method of manufacturing semiconductor device 1) First, an SiC substrate 10 is prepared, in which a drift layer 12 and a body layer 13 are formed by epitaxial growth on a drain layer 11. Next, ion implantation is performed from a surface 10s of the SiC substrate 10 to form a source region 14 and a body contact region 15. After that, a mask having openings corresponding to trenches 20 is formed on the surface 10s. The trenches 20 are formed by dry etching through the mask.

[0039] Next, using the mask as it is, p-type impurity ions are implanted into trench 20 to form first p-type region 41, second p-type region 42, and third p-type region 43. At this time, by adjusting the ion implantation time and implantation strength (for example, the acceleration energy given to the ions), first p-type region 41 to third p-type region 43 can be formed. Furthermore, by performing oblique ion implantation, width Wp of first p-type region 41 and width Wp2 of second p-type region 42 can be made larger than trench width Wg at bottom surface 20b of trench 20.

[0040] Thereafter, the gate insulating film 22, the trench gate electrode 23, the interlayer insulating film 24, the source electrode 30, and the drain electrode 31 are formed, completing the semiconductor device 1 shown in FIG.

[0041] Although specific examples of the present technology have been described in detail above, these are merely examples and do not limit the scope of the claims. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings can achieve multiple objectives simultaneously, and achieving one of these objectives itself has technical utility.

[0042] (Variation) Although the semiconductor material is SiC in the above description, it is not limited to this, and various materials such as Si, GaN, and Ga2O3 can also be used.

[0043] The impurity concentration of the second p-type region 42 may be equal to or lower than the impurity concentration of the first p-type region 41 as long as charge balance is achieved. [Explanation of symbols]

[0044] 1: semiconductor device 12: drift layer 13: body layer 14: source region 20: trench 20b: bottom surface 22: gate insulating film 23: trench gate electrode 41: first p-type region 42: second p-type region n1: first n-type region n2: second n-type region

Claims

1. an n-type drift layer; a p-type body layer in contact with an upper surface of the drift layer; an n-type source region disposed on the body layer; a trench extending from an upper surface of the source region through the body layer to reach the drift layer; a gate electrode disposed in the trench via a gate insulating film; A semiconductor device comprising: a first p-type region disposed in the drift layer below a bottom surface of the trench and spaced apart from the bottom surface of the trench; a second p-type region disposed in the drift layer below a lower surface of the first p-type region and spaced apart from the lower surface of the first p-type region; a third p-type region disposed in the drift layer below a lower surface of the second p-type region and in contact with the lower surface of the second p-type region; Equipped with The semiconductor device, wherein the second p-type region has a higher impurity concentration than the third p-type region.

2. a first n-type region is located between a bottom surface of the trench and the first p-type region; a second n-type region is located between the first p-type region and the second p-type region; 2. The semiconductor device according to claim 1, wherein a depletion layer extending from each pn junction interface covers the entire first n-type region, the first p-type region, and the second n-type region.

3. the second p-type region is connected to the body layer; 3. The semiconductor device according to claim 1, wherein the impurity concentration of said second p-type region is higher than the impurity concentration of said first p-type region.

4. 4. The semiconductor device according to claim 1, wherein the thickness of said second p-type region in the depth direction is greater than the thickness of said first p-type region in the depth direction.

5. 5. The semiconductor device according to claim 1, wherein when a distance from a bottom surface of the trench to an upper surface of the first p-type region is a first distance and a distance from the bottom surface of the trench to an upper surface of the second p-type region is a second distance, the ratio of the first distance to the second distance is within a range of 0.2 to 0.

7.

6. a first n-type region is located between a bottom surface of the trench and the first p-type region; 6. The semiconductor device according to claim 1, wherein a ratio of an impurity concentration of said first p-type region to an impurity concentration of said first n-type region is within a range of 1 to 2.

5.

7. 7. The semiconductor device according to claim 1, wherein when the width of the bottom surface of the trench in a direction parallel to the surface of the semiconductor substrate is defined as a trench width and the width of the first p-type region in a direction parallel to the surface of the semiconductor substrate is defined as a first width, the ratio of the first width to the trench width is within a range of 1 to 1.

6.

8. 8. The semiconductor device according to claim 1, wherein when the width of the bottom surface of the trench in a direction parallel to the surface of the semiconductor substrate is defined as a trench width and the width of the second p-type region in a direction parallel to the surface of the semiconductor substrate is defined as a second width, the ratio of the second width to the trench width is within the range of 1 to 1.6.

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