Jitter Cancellation Circuit

Abstract

To reduce clock jitter in a clock supply destination circuit.SOLUTION: A jitter cancellation circuit 100a includes a clock buffer 110, and a current control portion 120, and the clock buffer 110 receives a clock CLKIN output from a clock propagation element 50 driven by a power supply voltage VDD. The clock buffer 110 outputs the clock CLKOUT by adding a delay time to the input clock CLKIN, which decreases as the operating current Iop increases and increases as the operating current Iop decreases. The current control unit 120 is configured to increase or decrease the operating current Iop of the clock buffer 110 with the opposite phase of the fluctuation component of the power supply voltage VDD.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to techniques for suppressing clock jitter. [Background technology]

[0002] It is known that constant-frequency clocks have minute fluctuations in their clock cycles called jitter. If the jitter is large, there is a concern that it could cause discrepancies in the operation timing of circuits that operate based on the clock supply, so technology to suppress clock jitter is needed.

[0003] For example, the following non-patent document 1 describes a configuration for suppressing jitter that occurs due to the influence of noise components (AC components) of the power supply voltage (DC) in a clock generating oscillator placed inside an ADPLL (All-Digital Phase-Locked Loop).

[0004] Specifically, the current (I OSC ) is copied using a current mirror, and the AC component extracted from the copied current is applied to the above current (I OSC ) to suppress the variation in delay time that occurs in the oscillator. [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] "A supply-noise-rejection technique in ADPLL with noise-cancelling current source", Y Niki et al.,2013 Proceedings ESSCIRC, October 2013 Summary of the Invention [Problem to be solved by the invention]

[0006] In actual circuits, clocks generated by PLLs or other devices are transmitted to destination circuits using clock propagation elements such as CTS (Clock Tree Synthesis) or repeaters. However, even these clock propagation elements can superimpose jitter onto the clocks passing through them due to the influence of noise components in the power supply voltage.

[0007] Therefore, even if the jitter of the clock output from a PLL or the like is sufficiently suppressed by Non-Patent Document 1 or the like, there is a concern that it may be difficult to reduce the jitter of the clock actually input to the destination circuit.

[0008] The present disclosure is intended to solve the above-mentioned problems, and provides a jitter cancellation circuit that can reduce clock jitter in a circuit to which the clock is supplied by compensating for jitter that occurs in a clock output from a PLL or the like due to power supply noise.

[0009] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0010] A jitter cancellation circuit according to one embodiment includes a clock buffer and a current control unit. The clock buffer receives a clock output from a clock generation circuit or a clock propagation element driven by a power supply voltage. The clock buffer further provides the input clock with a delay time that decreases as the operating current increases and increases as the operating current decreases, and outputs the clock. The current control unit is configured to increase or decrease the operating current of the clock buffer in antiphase with a fluctuation component of the power supply voltage. [Effects of the Invention]

[0011] According to the above embodiment, it is possible to compensate for jitter caused by power supply noise and reduce clock jitter in the circuit to which the clock is supplied. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a conceptual diagram for explaining a general clock supply format. [Figure 2] FIG. 10 is a conceptual waveform diagram illustrating jitter caused by power supply noise. [Figure 3] FIG. 1 is a conceptual diagram illustrating the distribution of jitter. [Figure 4] 1 is a block diagram illustrating a configuration of a jitter cancellation circuit according to a first embodiment. [Figure 5] FIG. 5 is a circuit diagram illustrating the basic configuration of an amplifier unit shown in FIG. [Figure 6] 6 is a conceptual diagram illustrating the input / output characteristics of the amplifier shown in FIG. 5. [Figure 7] 1 is a circuit diagram illustrating a configuration example of a jitter cancellation circuit according to a first embodiment. [Figure 8] 8 is a conceptual waveform diagram illustrating the operation of the jitter cancellation circuit shown in FIG. 7. FIG. [Figure 9] FIG. 10 is a block diagram illustrating a configuration of a jitter cancellation circuit according to a modification of the first embodiment. [Figure 10] FIG. 10 is a circuit diagram illustrating a configuration example of the jitter cancellation circuit shown in FIG. 9. [Figure 11] FIG. 10 is a block diagram illustrating the configuration of a jitter cancellation circuit according to a second embodiment. [Figure 12] 12 is a circuit diagram illustrating an example of the configuration of the jitter cancellation circuit shown in FIG. 11. FIG. [Figure 13] 10 is a flowchart illustrating an example of the operation of a feedback control unit. [Figure 14] FIG. 13 is a circuit diagram illustrating a configuration example of the TDC circuit shown in FIG. 12. [Figure 15] FIG. 13 is a block diagram illustrating an example of the configuration of a control calculation unit shown in FIG. 12. [Figure 16] 16 is a waveform diagram illustrating an example of the operation of the control calculation unit shown in FIG. 15. [Figure 17]FIG. 11 is a block diagram illustrating an example of the arrangement of a jitter cancellation circuit according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, each embodiment will be described in detail with reference to the drawings. The same or corresponding parts will be denoted by the same reference characters and description thereof will not be repeated.

[0014] First Embodiment (Clock jitter due to power supply noise) Before describing this embodiment, clock jitter caused by power supply noise will be described.

[0015] FIG. 1 shows a conceptual diagram for explaining a general clock supply format. 1, clock generation circuit 10 is typically configured with a PLL (Phase-Locked Loop) and generates a constant frequency clock CLK1. As will become clear from the following description, the jitter cancellation circuit according to this embodiment can be applied to suppressing jitter in a clock generated by clock generation circuit 10 of any configuration.

[0016] For example, a clock generation circuit 10 includes an internal oscillator 11 that generates a clock CLK1, and a jitter suppression circuit 12 that suppresses jitter in the clock CLK1. As described above, in Non-Patent Document 1, the jitter suppression circuit 12 is provided with a configuration for suppressing AC components in the current supplied to the internal oscillator 11. This suppresses jitter in the clock CLK1 output from the clock generation circuit 10.

[0017] A clock propagation element 50 driven by a power supply voltage is arranged in the propagation path of the clock CLK1 from the clock generation circuit 10 to the clock destination circuit 20. The clock propagation element 50 refers to a circuit element that is driven by a power supply voltage and inputs and outputs a clock, including a repeater, a buffer (clock buffer) included in a CTS (Clock Tree Synthesis), an inverter, etc. Therefore, in addition to an inverter, logic circuits such as a NAND (Negative AND) gate are also included in the clock propagation element 50 if they input or output a clock.

[0018] The power supply voltage of the clock propagation element 50 is ideally a constant DC voltage, but in reality, AC noise components are superimposed on it. As a result, jitter occurs in the clock due to power supply noise that causes the power supply voltage to rise and fall, as shown in FIG.

[0019] 2, the power supply voltage VDD of the clock propagation element 50 has a fluctuating component (power supply noise) relative to the average value Vm. The delay time that occurs between the input and output of the clock propagation element 50 fluctuates depending on the power supply voltage VDD. This is because the operating current when the clock propagation element 50 drives an output signal increases or decreases depending on the level of the power supply voltage VDD.

[0020] 2 shows an example in which the rising edge of clock CLK1 is input to the clock propagation element 50 at each of times t1 to t4. At this time, the clock propagation element 50 is given delay times Td1 to Td4 according to the power supply voltage VDD. When the power supply voltage VDD is high, the operating current of the clock propagation element 50 increases, thereby shortening the delay time. Conversely, when the power supply voltage VDD is low, the operating current of the clock propagation element 50 decreases, thereby lengthening the delay time.

[0021] 2, at time t2 when the power supply voltage VDD is Vm (average value), the clock propagation element 50 imparts a delay time Td2 between the rising edges of the clocks CLK1 and CLK2. On the other hand, at times t1 and t4 when the power supply voltage VDD is higher than Vm, the delay times Td1 and Td4 caused by the clock propagation element 50 are shorter than the delay time Td2 at time t2.

[0022] In contrast, at time t3 when the power supply voltage VDD is lower than Vm, the delay time Td3 caused by the clock propagation element 50 is longer than the delay time Td2 at time t2.

[0023] 3, even if a clock CLK1 with a constant period is input to the clock propagation element 50, at the time when the edge of the clock CLK2 rises, a distribution like that shown in histogram 30 occurs depending on the level of the power supply voltage VDD at that time. As a result, even if the clock CLK1 is a clean clock with a constant period, as shown in FIG. 1, jitter occurs in the clock CLK2 that is output from the clock propagation element 50 and supplied to the destination circuit 20.

[0024] In this embodiment, a technique for canceling jitter superimposed on a clock output from a clock generating circuit (PLL) 10 along a propagation path of the clock to its destination will be described.

[0025] (Jitter Cancellation Circuit According to First Embodiment) FIG. 4 is a block diagram illustrating the configuration of the jitter cancellation circuit according to the first embodiment.

[0026] 4, the jitter cancellation circuit 100a according to the first embodiment includes a clock buffer 110 and a current control unit 120. The clock CLKIN output from the clock propagation element 50 is input to the clock buffer 110. Hereinafter, the clock CLKIN will also be referred to as the input clock CLKIN.

[0027] The clock propagation element 50 receives the clock CLK1 and outputs the input clock CLKIN, which corresponds to the clock CLK2 in Fig. 1. If a fluctuation component (power supply noise) exists in the power supply voltage VDD, even if the clock CLK1 is clean, jitter caused by the power supply noise will be superimposed on the input clock CLKIN.

[0028] Current control unit 120 increases or decreases operating current Iop of clock buffer 110 in the opposite phase to the fluctuation component of power supply voltage VDD. For example, current control unit 120 includes an amplifier unit 130 that inverts and amplifies the fluctuation component of power supply voltage VDD, and a variable current source circuit 140 that supplies operating current Iop to clock buffer 110. The output current of variable current source circuit 140 is increased or decreased according to the output of amplifier unit 130.

[0029] FIG. 5 shows a basic configuration diagram of the amplifier 130. As shown in FIG. 5, the amplifier unit 130 can be configured, for example, by an inverting amplifier using a transistor TR whose negative electrode is grounded. In the following, an example will be described in which the transistor TR is configured as a field effect transistor such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The source (negative electrode) of the transistor TR is connected to a ground line NL, and a power supply voltage VDD is input to the gate (control electrode). Furthermore, a resistor R is connected between the drain (positive electrode) of the transistor TR and a power supply line PL. In the following, the electrical resistance value of the resistor R will also be represented as R.

[0030] The transistor TR may also be configured as a bipolar transistor having an emitter as a negative electrode, a collector as a positive electrode, and a base as a control electrode.

[0031] 5, a voltage signal VOUT shown in Fig. 6 is output from an output node No corresponding to the connection point between the drain (positive electrode) of the transistor TR and the resistance element R. The current I flowing through the transistor TR changes in response to an increase or decrease in the power supply voltage VDD.

[0032] As is well known, the gain G, which is the ratio of the fluctuation ΔVOUT of the voltage signal VOUT to the fluctuation ΔVDD of the power supply voltage VDD, of the amplifier 130 shown in FIG. 5, is given by the following equation (1).

[0033] G=ΔVOUT / ΔVDD=ro·(1-gm·R) / (ro+R) …(1) In equation (1), ro is the output resistance of the amplifier unit 130, and gm is the transconductance of the transistor TR. From equation (1), to obtain an antiphase signal through inverting amplification when G<0, the electrical resistance value R (resistance element R) should be determined so that 1-rm·R<0, that is, rm·R>1. It can also be seen that when G<0, the greater the electrical resistance value R, the greater the absolute value of the gain |G|.

[0034] As a result, as shown in Fig. 6, a voltage signal VOUT in which the fluctuation ΔVDD of the power supply voltage VDD has been inverted and amplified can be output from the amplifier 130. Specifically, for a power supply voltage VDD in which the fluctuation ΔVDD has been superimposed on an average value Vm (dotted line), a voltage signal VOUT in which the fluctuation ΔVOUT obtained by inverting and amplifying ΔVDD has been superimposed on the average value (dotted line) can be obtained. The difference in average values ​​(DC component) between the power supply voltage VDD and the voltage signal VOUT corresponds to I·R.

[0035] FIG. 7 shows a circuit diagram illustrating an example of the configuration of a jitter cancellation circuit according to the first embodiment.

[0036] 7, clock buffer 110 has N inverters IV1-IVN (N: an integer of 2 or more) connected in series. An input clock CLKIN from clock propagation element 50 is input to first-stage inverter IV1, and a final-stage inverter IVN generates an output clock CLKOUT of jitter cancellation circuit 100a. The number N of inverters IV1-IVN is usually an even number, but N can also be an odd number in order to obtain a clock with an opposite phase.

[0037] The variable current source circuit 140 has P-type transistors TP0 to TPN and N-type transistors TN0 to TNN. The P-type transistor TP0 and the N-type transistor TN0 are connected in series between the power supply wiring PL (VDD) and the ground wiring NL (VSS). The P-type transistor TP0 is diode-connected. The voltage signal VOUT output from the amplifier 130 is input to the gate of the N-type transistor TN0.

[0038] The P-type transistors TP1 to TPN are connected between the power supply wiring PL and the inverters IV1 to IVN, respectively. Similarly, the N-type transistors TN1 to TNN are connected between the ground wiring NL and the inverters IV1 to IVN, respectively. The gates of the P-type transistors TP1 to TPN are connected to the gate of the P-type transistor TP0. The gates of the N-type transistors TN1 to TNN are connected to the gate of the N-type transistor TN0. The operating current Iop of the inverters IV1 to IVN is supplied by the N pairs of P-type transistors (TP1 to TPN) and N-type transistors (TN1 to TNN), respectively.

[0039] In the variable current source circuit 140, the current Iv flowing through the series-connected P-type transistor TP0 and N-type transistor TN0 varies according to the voltage signal VOUT from the amplifier unit 130. Specifically, when the potential of the voltage signal VOUT rises, the current Iv increases, and conversely, when the potential of the voltage signal VOUT drops, the current Iv decreases.

[0040] The P-type transistors TP1 to TPN form a current mirror with the P-type transistor TP0, and the N-type transistors TN1 to TNN form a current mirror with the N-type transistor TN0. Therefore, the operating current Iop of the inverters IV1 to IVN is proportional to the current Iv that changes in response to the voltage signal VOUT. Typically, the operating current Iop and the current Iv have a 1:1 ratio.

[0041] 7, the amplifier 130 is configured to further include a voltage divider circuit 132 in addition to the basic configuration described in FIG. 5. Specifically, the amplifier 130 is configured to include resistance elements 133, 134, and 136, and a transistor 135.

[0042] Resistance elements 133 (electrical resistance value R0) and 134 (electrical resistance value R1) are connected in series between the power supply wiring PL (VDD) and the ground wiring NL (VSS) to form a voltage dividing circuit 132. The transistor 135 corresponds to the transistor TR in FIG. 5, and the resistance element 136 (electrical resistance value R2) corresponds to the resistance element R in FIG. 5.

[0043] The voltage divider circuit 132 divides the power supply voltage VDD by a voltage division ratio R0 / (R0+R1) and inputs the divided voltage to the gate (control electrode) of the transistor 135. Therefore, as the electrical resistance value R1 increases, the voltage division ratio decreases and the input voltage to the gate of the transistor 135 also decreases.

[0044] 7, the amplification characteristic of the amplifier 130, specifically, the characteristic of the fluctuation component ΔVOUT of the voltage signal VOUT relative to the fluctuation component ΔVDD of the power supply voltage VDD, can be obtained by replacing the electrical resistance value R with R2 in equation (1). That is, the electrical resistance value R2 of the resistive element 136 is determined so that the gain G of equation (1) becomes G<0.

[0045] The DC operating point of the amplifier unit 130 can be adjusted by the voltage divider circuit 132. As shown in Fig. 6, when the electrical resistance value R2 of the resistive element 136 is increased in order to increase the inverting amplification gain in the amplifier unit 130, the voltage drop (I·R in Fig. 6) of the voltage signal VOUT relative to the power supply voltage VDD increases, and the level of the voltage signal VOUT decreases. Therefore, by adjusting the voltage division ratio of the voltage divider circuit 132 in conjunction with changes in the electrical resistance value R2, the DC operating point of the amplifier unit 130 can be maintained constant even when the gain is changed.

[0046] Even in the configuration example of FIG. 7, the voltage signal VOUT is generated so as to invert and amplify the fluctuation component ΔVDD (power supply noise) of the power supply voltage VDD by having the fluctuation component ΔVOUT according to Equation (1). Therefore, the operating current Iop supplied to each of the inverters IV1 to IVN by the variable current source circuit 140 decreases as the power supply voltage VDD increases, while increasing as the power supply voltage VDD decreases. That is, the operating current Iop is controlled so as to increase and decrease in a phase opposite to the fluctuation component of the power supply voltage VDD.

[0047] As a result, the jitter cancellation circuit operates as shown in FIG. 8, thereby suppressing the jitter of the output clock CLKOUT.

[0048] FIG. 8 shows the delay times imparted by the clock propagation element 50 and the jitter cancellation circuit 100a under the same power supply voltage VDD waveform as in FIG. 2.

[0049] The clock CLK1 is shown as a clean waveform as in FIG. 2, and the input clock CLKIN corresponds to the clock CLK2 in FIG. 2. That is, with respect to the rising edges of the clock CLK1 at times t1 to t3, the delay times Td1 to Td3 imparted by the clock propagation element 50 are the same as in FIG. 2. Specifically, the delay time Td1 at time t1 when VDD > Vm is shorter than the delay time Td2 at time t2 when the power supply voltage VDD is the average value Vm. And the delay time Td3 at time t3 when VDD < Vm is longer than Td2. As a result, jitter indicated by the clock period histogram 31 occurs in the input clock CLKIN.

[0050] On the other hand, in the jitter cancellation circuit 100a, the operating current Iop of the clock buffer 110 at time t1 when VDD > Vm is controlled to be smaller than at time t2 when VDD = Vm by the amplifier 130 and the variable current source circuit 140 that constitute the current control unit 120. As a result, in the clock buffer 110, the delay time Td1x added between the input clock CLKIN and the output clock CLKOUT becomes longer than the delay time Td2x of the clock buffer 110 at time t2.

[0051] On the contrary, the operating current Iop of the clock buffer 110 at time t3 when VDD < Vm is controlled to be larger than that at time t2 when VDD = Vm. As a result, the delay time Td3x caused by the clock buffer 110 at time t3 becomes shorter than the delay time Td2x of the clock buffer 110 at time t2.

[0052] For each rising edge of the output clock CLKOUT of the jitter cancellation circuit 100a, the sum of the delay time by the clock propagation element 50 and the delay time by the jitter cancellation circuit 100a acts on the clock CLK1. As a result, the delay times generated between the clock CLK1 and the output clock CLKOUT at times t1 to t3 shown in FIG. 8 are T1 = Td1 + Td1x, T2 = Td2 + Td2x, and T3 = Td3 + Td3x. It is understood that the difference between these delay times T1 to T3 is smaller than the difference between the delay times Td1 to Td3 by the clock propagation element 50 from the magnitude relationship of the above-described delay times Td1 to Td3 and the magnitude relationship of the delay times Td1x to Tdx3.

[0053] As a result, the jitter of the output clock CLKOUT indicated by the histogram 32 can be made smaller than the jitter of the input clock CLKIN indicated by the histogram 31.

[0054] Thus, according to the jitter cancellation circuit 100a according to the first embodiment, it is possible to control the increase and decrease of the operating current Iop of the clock buffer 110 with the opposite phase of the fluctuation component of the power supply voltage VDD that drives the clock propagation element 50. Thereby, it is possible to impart a delay time corresponding to the increase and decrease of the power supply voltage VDD with characteristics opposite to those of the clock propagation element 50 to the input clock CLKIN output from the clock propagation element 50. As a result, it is possible to compensate for the jitter generated due to power supply noise and reduce the clock jitter in the clock supply destination circuit.

[0055] 7 according to the first embodiment, the resistive element 134 corresponds to an example of a "first resistive element," and the electrical resistance value R1 corresponds to a "first electrical resistance value." Similarly, the resistive element 136 corresponds to an example of a "second resistive element," and the electrical resistance value R2 corresponds to a "second electrical resistance value."

[0056] <Modification of the first embodiment> As described above, the jitter compensation characteristics in the jitter cancellation circuit depend on the input / output characteristics (amplification characteristics) of the voltage signal VOUT relative to the power supply voltage VDD in the amplifier unit 130. Therefore, in a modification of the first embodiment, a configuration example will be described that makes it possible to easily adjust the amplification characteristics of the amplifier unit 130.

[0057] FIG. 9 is a block diagram illustrating the configuration of a jitter cancellation circuit according to a modification of the first embodiment.

[0058] 9, a jitter cancellation circuit 100b according to a modification of the first embodiment differs from the jitter cancellation circuit 100a according to the first embodiment (FIG. 4) in that it further includes a register 150. The register 150 receives an input signal DIN for adjusting the amplification characteristics of the amplifier section 130. The register 150 is arranged so that the input signal DIN can be input from outside the jitter cancellation circuit 100b.

[0059] The input signal DIN is stored in the register 150 and is input to the amplifier unit 130 as control signals S1 and S2 for the amplifier unit 130. For example, some bits of the multi-bit input signal DIN are output from the register 150 as the control signals S1 and S2 and input to the amplifier unit 130.

[0060] FIG. 10 shows a circuit diagram illustrating an example of the configuration of the jitter cancellation circuit 100b shown in FIG.

[0061] 10, the modification of the first embodiment differs from the first embodiment (FIG. 7) in that the resistance elements 134 and 136 of the amplifier unit 130 are configured as variable resistance elements. The electrical resistance value R1 of the resistance element 134 is variably set by a control signal S1. Similarly, the electrical resistance value R2 of the resistance element 136 is variably set by a control signal S2. The configuration of other parts in FIG. 10 is the same as in FIG. 7, and therefore detailed description will not be repeated.

[0062] As a result, in the jitter cancellation circuit 100b according to the modification of the first embodiment, the electrical resistance values ​​R1 and R2 that determine the amplification characteristics of the amplification section 130 can be variably adjusted by the input signal DIN input to 150 from outside the jitter cancellation circuit 100b. Except for this point, the configuration and operation of the jitter cancellation circuit 100b according to the modification of the first embodiment are similar to those of the jitter cancellation circuit 100a according to the first embodiment, and therefore detailed description will not be repeated.

[0063] This allows the amplification characteristics of the amplifier 130, i.e., the characteristics of how the operating current Iop increases or decreases in response to fluctuations in the power supply voltage VDD, to be changed as desired by the input signal DIN. The input signal DIN to the register 150 can be given different values ​​from outside the jitter cancellation circuit 100b, making it possible to easily adjust such characteristics through testing. In this way, the input signal DIN corresponds to an embodiment of an "adjustment signal," and the register 150 corresponds to an embodiment of an "adjustment input section."

[0064] Therefore, according to the modification of the first embodiment, in addition to the effects described in the first embodiment, it becomes easier to adjust the characteristics of the amplifier unit 130 to operate the jitter cancellation circuit at the optimum point. More specifically, it becomes possible to easily search for the optimum values ​​of the electrical resistance values ​​R1 and R2 for adjusting the inverting amplification gain and DC operating point of the amplifier unit 130 by analysis while changing the input signal DIN.

[0065] <Second embodiment> In the second embodiment, the output feedback control of the jitter cancellation circuit will be further explained.

[0066] FIG. 11 is a block diagram illustrating the configuration of a jitter cancellation circuit according to the second embodiment.

[0067] 11, the jitter cancellation circuit 100c according to the second embodiment differs from the jitter cancellation circuit 100a according to the first embodiment (FIG. 4) in that it further includes a feedback control section 160. The feedback control section 160 generates control signals S1 and S2 similar to those in the modification of the first embodiment, based on the output clock CLKOUT from the jitter cancellation circuit 100c.

[0068] FIG. 12 shows a circuit diagram illustrating an example of the configuration of the jitter cancellation circuit 100c shown in FIG.

[0069] 12, in a jitter cancellation circuit 100c according to the second embodiment, in the amplification section 130, similarly to the modification of the first embodiment (FIG. 10), each of the resistance element 134 (electrical resistance value R1) and the resistance element 136 (electrical resistance value R2) is configured with a variable resistance element. In the second embodiment, the control signals S1 and S2 for the electrical resistance values ​​R1 and R2 are generated by a feedback control section 160.

[0070] The feedback control unit 160 has a TDC (Time to Digital Converter) circuit 170 for measuring the period of the output clock CLKOUT, an average value calculation unit 180, and a control operation unit 200. As will be described later, the control operation unit 200 functions as a constant controller for the analog elements that make up the amplifier unit 130, in this case, a controller for the electrical resistance value R1 of the resistor element 134 and the electrical resistance value R2 of the resistor element 136, using feedback of the output clock CLKOUT.

[0071] FIG. 13 shows a flowchart illustrating an example of the operation of the feedback control unit 160.

[0072] 13, feedback control section 160 obtains a measured value of the period of output clock CLKOUT in step (hereinafter simply referred to as "S") 110. The process of S110 is implemented by TDC circuit 170 in FIG.

[0073] 14 shows an example of the configuration of the TDC circuit 170. The TDC circuit 170 has a delay element 172, M delay elements DL1 to DLM (M: an integer of 2 or more), and M flip-flops FF1 to FFM.

[0074] The delay element 172 and the delay elements DL1 to DLM are connected in series. The delay element 172 provides a predetermined delay time Tx corresponding to one cycle (standard value) of the output clock CLKOUT. In contrast, each of the delay elements DL1 to DLM provides a delay time τ.

[0075] The output clock CLKOUT is input to the delay element 172, and the output clock CLKOUT' delayed by one cycle is input to the M first-stage delay elements DL1. A delay time τ is sequentially applied to this CLKOUT' by each of the delay elements DL1 to DLM.

[0076] The inputs of delay elements DL1 to DLM are input to the D terminals of flip-flops FF1 to FFM, respectively. On the other hand, the output clock CLKOUT is input to the CLK terminal of each of flip-flops FF1 to FFM. The outputs (Q terminals) of flip-flops FF1 to FFM are input to decoder 175.

[0077] With this configuration, the M flip-flops FF1 to FFM output to the decoder 175 an M-bit digital value DTc obtained by measuring the time difference between the output clock CLKOUT and the delayed CLKOUT′ with the delay time τ as a resolution.

[0078] For example, if Tx is the sum of one cycle of the output clock CLKOUT and τ·(M / 2), the time difference between each rising edge of the output clock CLKOUT and the next rising edge one cycle later can be measured within the range of 0±τ·(M / 2). In this way, the decoder 175 can output a measured cycle value Tc of the output clock CLKOUT based on the digital value DTc for each rising edge input.

[0079] 13 again, in S120, feedback control unit 160 calculates a period mean value Tmean, which is the average value of period measurement values ​​Tc from TDC circuit 170. For example, in S120, a moving average of a predetermined number H (H: an integer of 2 or more) of period measurement values ​​Tc is calculated. Mean value calculation unit 180 in FIG. 12 can be configured to perform the above-mentioned moving average calculation using, as input, period measurement value Tc calculated for each period of output clock CLKOUT.

[0080] Next, in S130, the feedback control unit 160 calculates a clock period deviation ΔTc (ΔTc=Tc−Tmean) corresponding to the difference between the period average value Tmean calculated in S120 and the period measurement value Tc obtained in S110. Furthermore, in S140, the feedback control unit 160 generates control signals S1 and S2 for the amplifier unit 130 by control calculation to bring the clock period deviation ΔTc closer to zero. This realizes feedback control that adjusts the amplification characteristics of the amplifier unit 130, i.e., the characteristics of increase and decrease of the operating current Iop in response to fluctuations in the power supply voltage VDD, based on the period measurement value of the output clock CLKOUT.

[0081] FIG. 15 shows an example of the configuration of the control and calculation unit 200 in FIG. 12 for implementing the processes of S130 and S140 in FIG.

[0082] As shown in FIG. 15, the control calculation section 200 has a deviation calculation section 201, an absolute value calculation section 202, a unit changeover switch 205, a calculation unit 210 that generates a control signal S1, and a calculation unit 220 that generates a control signal S2.

[0083] The deviation calculation unit 201 subtracts the period average value Tmean of the average calculation unit 180 from the period measurement value Tc of the TDC circuit 170 to output the clock period deviation ΔTc for each period of the output clock CLKOUT. The clock period deviation ΔTc is input to each of the integral control units 191 and 192. The absolute value calculation unit 202 outputs the absolute value |ΔTc| of the clock period deviation ΔTc calculated by the deviation calculation unit 201. The unit changeover switch 205 connects the output side of the absolute value calculation unit 202 to the input side (ph1) of the calculation unit 210 or the input side (ph2) of the calculation unit 220. For example, the connection to the ph1 side and the connection to the ph2 side are switched every predetermined number of periods of the output clock CLKOUT. As a result, the absolute value |ΔTc| of the clock period deviation for those multiple periods is input alternately to the calculation units 210 and 220.

[0084] The arithmetic unit 210 has a multiplication unit 211, an addition unit 212, a z-transform delay element 213, a sign control unit 214, and a sign setting unit 215. The multiplication unit 211 multiplies the absolute value |ΔTc| of the clock period deviation transmitted by the unit changeover switch 205 by an adjustment coefficient ku1 to which a sign sgn1 is assigned, the sign sgn1 being set to "+ (positive)" or "- (negative)" by the sign setting unit 215. That is, the multiplication unit 211 outputs ku1·|ΔTc| or -ku1·|ΔTc| in accordance with the sign sgn1.

[0085] The output value (±ku1·|ΔTc|) of the multiplication unit 211 is integrated by the delay element 213 and the adder 212 to calculate the integral value val1. In other words, +ku1 and -ku1 correspond to the integral gains of the integral control by the delay element 213 and the adder 212. The sign control unit 214 sets the sign sgn1 based on the absolute value |ΔTc| of the clock period deviation and the behavior (direction of change) of the integral value val1. The decoder 217 converts the integral value val1 into a control signal S1 in accordance with predetermined decoding conditions.

[0086] Similarly, the arithmetic unit 220 has a multiplication unit 221, an addition unit 222, a z-transform delay element 223, a sign control unit 224, and a sign setting unit 225. The multiplication unit 221 multiplies the absolute value |ΔTc| of the clock period deviation transmitted by the unit changeover switch 205 by an adjustment coefficient ku2 to which a sign sgn2 is assigned, the sign sgn2 being set to "+ (positive)" or "- (negative)" by the sign setting unit 225. That is, the multiplication unit 221 outputs ku2·|ΔTc| or -ku2·|ΔTc| in accordance with the sign sgn2.

[0087] The delay element 223 and the adder 222 integrate the output value (±ku2·|ΔTc|) of the multiplier 221 to calculate the integral value val2. In other words, +ku2 and −ku2 correspond to the integral gains of the integral control by the delay element 223 and the adder 222. The sign control unit 224 sets the sign sgn2 based on the absolute value |ΔTc| of the clock period deviation and the behavior (direction of change) of the integral value val2. The decoder 227 converts the integral value val2 into a control signal S2 according to predetermined decoding conditions. For example, the decoding conditions of the decoders 217 and 227 can be set so that the electrical resistance values ​​R1 and R2 increase as the integral values ​​val1 and val2 increase, and conversely, the electrical resistance values ​​R1 and R2 decrease as the integral values ​​val1 and val2 decrease. As a result, the values ​​of the electrical resistance values ​​R1 and R2 in the amplifier 130 change in response to the integral values ​​val1 and val2.

[0088] Next, an example of the operation of the control calculation unit 200 shown in FIG. 15 will be described with reference to FIG. 15, the time length of each of the periods TT1 to TT11 corresponds to L (L: an integer equal to or greater than 2) periods of the output clock CLKOUT. The output destination of the unit changeover switch 205 is switched for each of the above periods. For example, in periods TT1, TT3, TT5, TT7, TT9, and TT11 (odd-numbered periods), the unit changeover switch 205 is controlled to the ph1 side (FIG. 15), and the absolute value |ΔTc| of the clock period deviation is input to the arithmetic unit 210 in each period of the output clock CLKOUT. On the other hand, in these periods, the absolute value |ΔTc| of the clock period deviation output from the absolute value calculation unit 202 is not transmitted to the arithmetic unit 220.

[0089] Conversely, during periods TT2, TT4, TT6, TT8, and TT10 (even-numbered periods), the unit changeover switch 205 is controlled to the ph2 side (FIG. 15), and the absolute value |ΔTc| of the clock period deviation is input to the arithmetic unit 220 at each period of the output clock CLKOUT. On the other hand, during these periods, the absolute value |ΔTc| of the clock period deviation output from the absolute value calculation section 202 is not transmitted to the arithmetic unit 210.

[0090] In the arithmetic unit 210, the sign control unit 214 sets the sign sgn1 for the next period depending on the direction of change of the absolute value |ΔTc| of the clock period deviation input from the unit changeover switch 205. Specifically, if the absolute value |ΔTc| of the clock period deviation is decreasing within the period, it recognizes that the current direction of change of the integral value val1, i.e., the current setting of the sign sgn1, is correct, and maintains the setting of the sign sgn1. Conversely, if the absolute value |ΔTc| of the clock period deviation is increasing within the period, it recognizes that the current direction of change of the integral value val1, i.e., the current setting of the sign sgn1, is incorrect, and reverses the setting of the sign sgn1.

[0091] For example, in the example of FIG. 16, during period TT1, the integral value val1 is increasing, and the absolute value |ΔTc| of the clock period deviation is increasing with the sign sgn1 set to "+". Therefore, during period TT3, which follows period TT1 and in which the absolute value |ΔTc| of the clock period deviation is input to the arithmetic unit 210, the sign sgn1 is set to "-" inverted from the sign during period TT1 to reverse the direction of change of the integral value val1. As a result, the integral value val1, which was increasing during period TT1, begins to decrease during period TT3. Note that during each of the periods in which |ΔTc| is not input to the arithmetic unit 210 (periods TT2, TT4, TT6, TT8, and TT10 in FIG. 16), the integral value val1 does not change, and the setting of the sign sgn1 is maintained the same as during the immediately preceding period.

[0092] In the following periods TT3, TT5, TT7, TT9, and TT11, the absolute value of the clock period deviation |ΔTc| decreases. Therefore, the setting of the sign sgn1 is maintained at "-", and under this condition, |ΔTc| decreases toward zero.

[0093] Similarly, in the arithmetic unit 220, the sign control unit 224 sets the sign sgn2 for the next period according to the direction of change of the absolute value |ΔTc| of the clock period deviation input from the unit changeover switch 205. That is, when the absolute value |ΔT| of the clock period deviation is decreasing within a certain period, the setting of sign sgn2 is maintained in order to maintain the current direction of change of the integral value val2, while when |ΔTc| is increasing, the setting of sign sgn2 for the next period is reversed in order to reverse the current direction of change of the integral value val2.

[0094] For example, in the example of FIG. 16 , during period TT2, the integral value val2 is increasing, and with the sign sgn2 set to "+", the absolute value |ΔTc| of the clock period deviation is decreasing. Therefore, during period TT4, when |ΔTc| is next input to the arithmetic unit 220, the sign sgn2 is maintained at "+" as in period TT2 to maintain the direction of change of the integral value val2. However, during period TT4, with the sign sgn2 set to "+", the absolute value |ΔTc| of the clock period deviation increases. Therefore, during period TT6, when |ΔTc| is next input to the arithmetic unit 220, the sign sgn2 is set to "-", opposite to period TT4, to reverse the direction of change of the integral value val2.

[0095] In period TT6, the absolute value of the clock period deviation |ΔTc| decreases with sign sgn2 at "-", so in period TT8, sign sgn2 is maintained at "-". However, in period TT8, the absolute value of the clock period deviation |ΔTc| increases with sign sgn2 set to "-". Therefore, in period TT10, sign sgn2 is inverted to "+" to reverse the direction of change in integral value val2.

[0096] Furthermore, during each period in which |ΔTc| is not input to the calculation unit 220 (periods TT1, TT3, TT5, TT7, TT9, and TT11 in FIG. 16), the integral value val1 does not change, and the setting of the code sgn2 is maintained the same as in the immediately preceding period.

[0097] In this way, in the arithmetic units 210 and 220, by monitoring whether the absolute value |ΔTc| of the clock period deviation is decreasing and switching the signs sgn1 and sgn2, the sign of the gain is switched (positive / negative) and integral control is performed. As a result, the integral value val1 of the arithmetic unit 210 and the integral value val2 of the arithmetic unit 220 can be converged to steady-state values ​​Val1* and Val2* that make the absolute value |ΔTc| of the clock period deviation zero. It can be understood that these steady-state values ​​Val1* and Val2* correspond to the characteristics of the amplifier unit 130 that make the clock period deviation ΔTc (|ΔTc|) zero, specifically, the electrical resistance values ​​R1 and R2.

[0098] In this way, the feedback control unit 160 can appropriately set the amplification characteristics of the amplifier unit 130, specifically, the inverting amplification gain that depends on the electrical resistance value R2, and the electrical resistance value R1 for maintaining a constant DC operating point, so as to bring the clock deviation ΔTc closer to zero.

[0099] For example, the feedback control unit 160 can be configured using digital calculation elements. Furthermore, the functions of the average value calculation unit 180 and the control calculation unit 200 can also be realized by software. The configuration of the control calculation unit 200 shown in Fig. 15 is just one example, and the control calculation unit 200 can be configured according to any control calculation for bringing the clock period deviation ΔTc closer to zero.

[0100] As described above, according to the second embodiment, in addition to the effects described in the first embodiment, the characteristics of the amplifier unit 130 can be automatically adjusted by feedback control of the output clock CLKOUT to operate the jitter cancellation circuit at an optimum point, thereby further enhancing the clock jitter suppression effect.

[0101] It is also possible to combine the modified example of embodiment 1 with embodiment 2. In this case, in a system equipped with a jitter cancellation circuit, the characteristics of the amplifier unit 130 are adjusted using the register 150 while offline to determine the reference values ​​(default values) of the electrical resistance values ​​R1 and R2, and then the feedback control unit 160 can be configured to automatically variably adjust the electrical resistance values ​​R1 and R2 while online.

[0102] 14 and 15 described in the second embodiment, TDC 170 corresponds to an example of the "first calculation unit." Similarly, deviation calculation unit 201 and absolute value calculation unit 202 (FIG. 15) correspond to an example of the "second calculation unit." Furthermore, calculation unit 210 (FIG. 15) corresponds to an example of the "third calculation unit," with integral value val1 corresponding to the "first integral value," and the product of adjustment coefficient kc1 and sign sgn1 corresponding to the "gain of first integral control." Similarly, calculation unit 220 (FIG. 15) corresponds to an example of the "fourth calculation unit," with integral value val2 corresponding to the "second integral value," and the product of adjustment coefficient kc2 and sign sgn2 corresponding to the "gain of second integral control." Furthermore, each of the periods TT1, TT3, TT5, TT7, TT9, and TT11 in FIG. 16 corresponds to an example of a "first period," and each of the periods TT2, TT4, TT6, TT8, and TT10 corresponds to an example of a "second period."

[0103] <Third embodiment> In the third embodiment, an example of the arrangement of the jitter cancellation circuits described in the first and second embodiments will be described.

[0104] FIG. 17 is a block diagram illustrating an example of the arrangement of a jitter cancellation circuit according to the third embodiment.

[0105] 17, a clock CLK1 output from a clock generation circuit (PLL) 10 is supplied to a clock destination circuit 20, for example, a module constituting a physical layer (PHY), via a clock propagation path in which clock propagation elements 50 are arranged. The clock generation circuit 10 and the multiple clock propagation elements 50 operate by receiving a common power supply voltage VDD from a power supply line PL.

[0106] The jitter cancellation circuit 100 in FIG. 17 includes the jitter cancellation circuits 100a to 100c described in the first embodiment and its modifications, as well as the second embodiment.

[0107] For example, the jitter cancellation circuit 100 can be configured so that it is supplied with the same power supply voltage VDD as the clock generation circuit 10, and so that the clock CLK1 from the clock generation circuit 10 is input as CLKIN. In this way, even if the configuration for suppressing jitter caused by power supply noise inside the clock generation circuit 10 is omitted or simplified, it is expected that the jitter superimposed on the clock CLK1 can be compensated for and the clock can be cleaned.

[0108] Alternatively, the jitter cancellation circuit 100 can be arranged so that the output clock CLKOUT of the jitter cancellation circuit 100 is supplied to the clock destination circuit 20. The jitter cancellation circuit 100 is supplied with the same power supply voltage VDD as the clock propagation element 50. In this way, the destination circuit 20 can operate using a clean clock with suppressed jitter.

[0109] In this way, the jitter cancellation circuit 100 according to this embodiment can be placed at any location in the clock propagation path between the clock generation circuit 10 and any destination circuit 20, and in any number, as long as it receives the same power supply voltage VDD as the clock generation circuit 10 or the clock propagation element 50.

[0110] Regarding the multiple embodiments described above, we would like to confirm that it was intended from the beginning of the application to appropriately combine the configurations described in each embodiment, including combinations not mentioned in the specification, within the scope that does not result in inconsistencies or contradictions.

[0111] The present disclosure has been specifically described above based on the embodiments, but it goes without saying that the present disclosure is not limited to the embodiments and can be modified in various ways without departing from the spirit of the present disclosure. [Explanation of symbols]

[0112] 10 clock generation circuit, 11 internal oscillator, 12 jitter suppression circuit, 20 supply destination circuit, 30-32 histogram, 50 clock propagation element, 100, 100a-100c jitter cancellation circuit, 110 clock buffer, 120 current control section, 130 amplifier section, 132 voltage divider circuit, 133, 134, 136, R resistor element, 135, TR transistor, 140 variable current source circuit, 150 register, 160 feedback control section, 170 circuit, 172, 195, DL1, DLM delay element, 175, 217, 227 decoder, 180 average value calculation section, 200 control calculation section, 201 deviation calculation section, 202 absolute value calculation section, 205 unit changeover switch, 210, 220 calculation unit, 211, 221 Multiplication unit, 212, 222 addition unit, 213, 223 delay element (z conversion), 214, 224 sign control unit, 215, 225 sign setting unit, CLK, CLK1, CLK2, CLKIN clock, CLKIN input clock, CLKOUT output clock, DIN input signal, DTc digital value, IV1 to IVN inverter, Iop operating current, NL ground wiring, No output node, PL power supply wiring, S1, S2 control signal, Td1 to Td4, Td1x to Td3x delay time, TN0, TN1 to TNN N-type transistor, TP0, TP1 to TPN P-type transistor, Tc period measurement value, Tmean period average value, VDD power supply voltage, Vm average value, ku1, ku2 adjustment coefficient, val1, val2 integral value.

Claims

1. a clock buffer that receives a clock output from a clock generating circuit or a clock propagation element that is driven by a power supply voltage; a current control unit that increases or decreases an operating current of the clock buffer in an antiphase with a fluctuation component of the power supply voltage, the clock buffer applies a delay time to the input clock that decreases in response to an increase in the operating current and increases in response to a decrease in the operating current, and outputs the clock; The jitter cancellation circuit further comprises a feedback control section that adjusts the increase / decrease characteristic of the operating current in response to the fluctuation component in the current control section based on a measured value of the period of the output clock from the clock buffer.

2. 2. The jitter cancellation circuit according to claim 1, further comprising an adjustment input section for inputting, from outside said jitter cancellation circuit, an adjustment signal for adjusting the characteristics of said operating current increase / decrease in said current control section in response to said fluctuation component.

3. 2. The jitter cancellation circuit according to claim 1, wherein the feedback control section adjusts the characteristics of the current control section so that a deviation between each of the period measurement values ​​and an average value of a plurality of past period measurement values ​​approaches zero.

4. The current control unit an amplifier that outputs a voltage signal obtained by inverting and amplifying the fluctuation component of the input power supply voltage; a variable current source circuit that supplies an output current that is increased or decreased in response to the voltage signal to the clock buffer as the operating current, 2. The jitter cancellation circuit according to claim 1, wherein said variable current source circuit is configured so that the output current increases as the voltage of said voltage signal increases.

5. 5. The jitter cancellation circuit according to claim 4, further comprising an adjustment input section for inputting, from outside said jitter cancellation circuit, an adjustment signal for adjusting the amplification characteristic of said voltage signal with respect to said fluctuation component in said amplifier section.

6. A clock buffer that receives a clock output from a clock generation circuit or a clock propagation element driven by a power supply voltage; a current control unit that increases or decreases an operating current of the clock buffer in an antiphase with a fluctuation component of the power supply voltage, the clock buffer applies a delay time to the input clock that decreases in response to an increase in the operating current and increases in response to a decrease in the operating current, and outputs the clock; The current control unit an amplifier that outputs a voltage signal obtained by inverting and amplifying the fluctuation component of the input power supply voltage; a variable current source circuit that supplies an output current that is increased or decreased in response to the voltage signal to the clock buffer as the operating current, the variable current source circuit is configured so that the output current increases as the voltage of the voltage signal increases; The jitter cancellation circuit further comprises a feedback control section that adjusts the amplification characteristics of the voltage signal with respect to the fluctuation component in the amplifier section based on a measured value of the period of the output clock from the clock buffer.

7. 7. The jitter cancellation circuit according to claim 6, wherein the feedback control section adjusts the amplification characteristics of the amplifier section so that a deviation between each of the period measurement values ​​and an average value of a plurality of past period measurement values ​​approaches zero.

8. A clock buffer that receives a clock output from a clock generation circuit or a clock propagation element driven by a power supply voltage; a current control unit that increases or decreases an operating current of the clock buffer in an antiphase with a fluctuation component of the power supply voltage, the clock buffer applies a delay time to the input clock that decreases in response to an increase in the operating current and increases in response to a decrease in the operating current, and outputs the clock; The current control unit an amplifier that outputs a voltage signal obtained by inverting and amplifying the fluctuation component of the input power supply voltage; a variable current source circuit that supplies an output current that is increased or decreased in response to the voltage signal to the clock buffer as the operating current, the variable current source circuit is configured so that the output current increases as the voltage of the voltage signal increases; The amplifier unit a voltage dividing circuit configured to divide the power supply voltage, the voltage dividing circuit including a first resistor element; a transistor having a negative electrode grounded and a control electrode receiving the output voltage of the voltage divider circuit; a second resistive element connected between the supply node of the power supply voltage and the positive electrode of the transistor;

9. the first resistance element and the second resistance element are configured by variable resistance elements, 9. The jitter cancellation circuit according to claim 8, further comprising an adjustment input section for inputting an adjustment signal for adjusting the first electrical resistance value of the first resistance element and the second electrical resistance value of the second resistance element from outside the jitter cancellation circuit.

10. the first resistance element and the second resistance element are configured by variable resistance elements, 9. The jitter cancellation circuit according to claim 8, further comprising a feedback control section that adjusts the first electrical resistance value of the first resistor element and the second electrical resistance value of the second resistor element of the amplifier section based on a period measurement value of the output clock from the clock buffer.

11. The feedback control unit a first calculation unit that calculates an average value of a plurality of past period measurement values; a second calculation unit that calculates an absolute value of a deviation of each of the period measurement values ​​from the average value; a third calculation unit that generates a first control signal to adjust the first electrical resistance value based on a first integral value of the absolute value of the deviation obtained by first integral control so as to bring the deviation closer to zero; and a fourth calculation unit that generates a second control signal for adjusting the second electrical resistance value based on a second integral value of the absolute value of the deviation by second integral control so as to bring the deviation closer to zero.

12. the feedback control unit operates to alternately provide a first period during which the first integral value is updated in accordance with the absolute value of the deviation from the second calculation unit while the second integral value is maintained, and a second period during which the second integral value is updated in accordance with the absolute value of the deviation from the second calculation unit while the first integral value is maintained, the third calculation unit is configured to switch between positive and negative values ​​of a gain of the first integral control when an absolute value of the deviation increases during the first period; 12. The jitter cancellation circuit according to claim 11, wherein the fourth calculation unit is configured to switch the gain of the second integral control between positive and negative when the absolute value of the deviation increases in the second period.

13. the clock propagation element is connected in a path between the clock generation circuit and a destination of the clock; 13. The jitter cancellation circuit according to claim 1, wherein the jitter cancellation circuit operates by receiving the power supply voltage common to the clock propagation element or the clock generation circuit.

Images