Voltage-controlled oscillator and sub-sampling phase-locked loop

Abstract

The invention discloses a voltage-controlled oscillator and a sub-sampling phase-locked loop, and relates to the technical field of phase-locked loops. The voltage-controlled oscillator comprises two negative resistance transistors and a three-layer coil structure; the three layers of coil structures are respectively a drain coil, a grid coil and a source coil from outside to inside; the gate coil and the drain coil are both of an octagonal structure, and the source coil is of a splayed structure; the drain coil, the source coil and the grid coil are all provided with center taps, the center tap of the source coil is connected with a power voltage module, the center tap of the drain coil is grounded, and the connection point of the center tap of the source coil and the power voltage module and the connection point of the center tap of the drain coil and the ground are located on the same side of the drain coil. And the two negative resistance transistors are positioned on the other side of the drain coil. According to the invention, automatic alignment of second harmonics in a wide frequency range is realized. And meanwhile, an extra chip area is not increased.

Description

Technical Field

[0001] This invention relates to the field of phase-locked loop technology, and in particular to a voltage-controlled oscillator and a subsampling phase-locked loop. Background Technology

[0002] With the rapid development of wireless and wired communication systems, providing carrier signals with ultra-low jitter (<50fs) and fast-locking phase-locked loops (PLLs) has become a research hotspot. Phase noise is the main source of jitter, and various PLL architectures have emerged to continuously optimize jitter performance. Charge pump type II PLLs, as the mainstream architecture, primarily rely on in-band loop noise and out-of-band voltage-controlled oscillator (VCO) noise. Harmonic shaping techniques can reduce out-of-band noise caused by the VCO without increasing power consumption. However, in traditional PLLs, the noise from the frequency and phase detectors, charge pump, and frequency divider is amplified N² times by a division ratio N before being transmitted to the output, severely limiting in-band noise performance, especially under high division ratio N conditions.

[0003] Sub-Sampling Phase Locked Loop (SSPLL) directly samples the VCO output through a reference signal, eliminating the need for a frequency divider and utilizing high phase detection gain. K PD It effectively suppresses the noise of the charge pump and phase detector, thus achieving excellent in-band phase noise performance, making it more suitable for generating high-frequency, wide-tuning-range, and low-jitter clock signals. However, its disadvantages cannot be ignored: direct sampling of the VCO output voltage with the reference clock can introduce significant reference spurious signals due to factors such as periodic disturbances of the load capacitor, clock feedthrough, and charge injection; at the same time, the SSPLL phase detection range is relatively narrow, its ability to cope with frequency offset is weak, and the subsampling loop is prone to loss of lock, resulting in a long lock-in time.

[0004] In recent years, various solutions have been proposed by the academic community to address the poor reference spurious performance of SSPLLs. Xiang Gao et al. systematically analyzed the generation mechanism of reference spuriousness. For reference spuriousness caused by the binary frequency shift keying (BFSK) effect, they increased the virtual sampling capacitor to maintain a constant VCO load and used a delay phase-locked loop (SSDLL) to adjust the duty cycle to suppress the BFSK effect. However, this solution cannot completely eliminate the process mismatch between the sampling capacitor and the virtual sampling capacitor, and reducing the sampling capacitor introduces additional noise. Using an SSDLL to align the non-sampling edge with the VCO zero-crossing point can reduce reference spuriousness caused by charge injection and charge sharing, but this sacrifices chip area and increases power consumption. Furthermore, Zunsong Yang et al. proposed gate-isolated sampling technology to increase the isolation between the VCO and the SSPD; however, low noise usually requires a larger transistor size, and changes in its gate capacitance still modulate the VCO load and exacerbate clock feedthrough and charge injection effects.

[0005] To accelerate the loop locking speed of PLLs, Wen Chen et al. proposed an automatic dead-time control technique based on orthogonal subsampling phase detectors to reduce the dead time of traditional frequency-locked loops (FLLs). However, this requires a four-phase clock from the VCO, placing higher demands on the design of the LC-VCO. Haoran Li et al. used an adaptive frequency calibrator (AFC) to quickly adjust the VCO control word by comparing the frequency-division signal with the reference clock, but the accuracy of the AFC cannot be guaranteed, and search errors will prolong the loop locking time.

[0006] To reduce the phase noise of the VCO, traditional methods add a tail-end secondary resonator to suppress flicker noise upconversion. However, the secondary resonator not only increases the chip area but also, due to its narrow-band characteristics, makes it difficult to effectively suppress low-frequency noise upconversion over a wide tuning range. To reduce chip area and achieve broadband second harmonic alignment, David Murphy et al. proposed an implicit common-mode resonant oscillator scheme, using a single transformer resonator to combine differential-mode and common-mode oscillations. However, this requires manual adjustment of the differential and single-ended capacitors to achieve differential-mode and common-mode impedance alignment, increasing the complexity of frequency tuning. To solve the problem of manual harmonic alignment adjustment, Hao Guo et al. proposed an improved scheme, adding a secondary resonator to the drain inductor L of the transformer feedback oscillator. D The center tap integrates a head resonant cavity to flatten the second harmonic impedance. However, the asymmetrical structure of the head resonant cavity leads to drain voltage imbalance and occupies additional chip area. Furthermore, the power supply voltage being far from the ground plane causes common-mode current to return to a long path, and at high frequencies, the parasitic inductance of the decoupling capacitor can render second harmonic shaping techniques ineffective.

[0007] In summary, voltage-controlled oscillators (VCOs) in subsampling phase-locked loops (PLLs) struggle to achieve wideband second harmonic auto-alignment within a small area, and the long common-mode current return path is significantly affected by parasitic common-mode inductance. Furthermore, existing AFCs, when encountering erroneous control words, cause the VCO tuning voltage to remain unstable for extended periods, thus increasing the loop lockout time. Summary of the Invention

[0008] In view of the defects of the existing technology, the present invention provides a voltage-controlled oscillator and a subsampling phase-locked loop, which solves the existing problems.

[0009] The present invention adopts the following technical solution: In a first aspect, the present invention provides a voltage-controlled oscillator, comprising two negative resistance transistors and a three-layer coil structure; the three-layer coil structure consists of a drain coil, a gate coil, and a source coil from the outside to the inside; the gate coil and the drain coil are both octagonal structures, and the source coil is a figure-eight structure. The two ends of the source coil are respectively connected to the source of the two negative resistance transistors, the two ends of the gate coil are respectively connected to the gate of the two negative resistance transistors, and the drain coil is respectively connected to the drain of the two negative resistance transistors. The drain coil, source coil, and gate coil are all equipped with center taps. The center tap of the source coil is connected to the power supply voltage module, the center tap of the drain coil is grounded, and the center tap of the gate coil is connected to a fixed voltage module. The connection point between the center tap of the source coil and the power supply voltage module and the connection point between the center tap of the drain coil and ground are located on the same side of the drain coil, and the two negative resistance transistors are located on the other side of the drain coil.

[0010] Preferably, the system further includes a switched capacitor array, which includes two gate capacitors, two variable capacitors, and two source capacitors. One end of each of the two gate capacitors is connected to the gate of one of the two negative resistance transistors, and the other end is connected to each other. One end of each of the two variable capacitors is connected to the gate of one of the two negative resistance transistors, and the other end is connected to each other. One end of each of the two source capacitors is connected to the source of one of the two negative resistance transistors, and the other end is grounded.

[0011] In a second aspect, the present invention provides a subsampling phase-locked loop, comprising a subsampling loop, a frequency-locked loop, a lockout detector, and an adaptive frequency calibrator; the subsampling loop includes the voltage-controlled oscillator described above. The frequency-locked loop includes a frequency divider, the input of which is connected to the output of the voltage-controlled oscillator. The frequency divider is used to reduce the frequency of the output signal of the voltage-controlled oscillator to obtain a frequency-divided signal. The input of the adaptive frequency calibrator is connected to the output of the frequency divider, and the output is connected to the input of the voltage-controlled oscillator. The adaptive frequency calibrator is used to output a corresponding control word to the voltage-controlled oscillator according to the phase difference between the frequency divider signal and the reference signal, and to calibrate the frequency of the output signal of the voltage-controlled oscillator to the frequency band closest to the target frequency based on the control word. The unlock detector is used to detect whether the frequency band is correct. If the frequency band is incorrect, the control voltage is adjusted through the subsampling loop and the frequency locking loop. The control voltage controls the voltage-controlled oscillator and locks the frequency of the output signal.

[0012] Preferably, the subsampling loop further includes a reference clock buffer, a subsampling phase detector, a main charge pump, and a low-pass filter; The reference clock buffer is used to convert the crystal oscillator signal into two clock signals CLK1 and CLK2, wherein the reference signal is CLK1; The input terminal of the subsampling phase detector is connected to the output terminal of the reference clock buffer and the output terminal of the voltage-controlled oscillator, and is used to sample two sinusoidal signals to obtain two sampled voltages; wherein, the clock signal is used to control the on and off of the sampling switch of the subsampling phase detector; The input terminal of the main charge pump is connected to the output terminal of the subsampling phase detector, and is used to generate a first current based on the magnitude relationship between the two sampling voltages. The input terminal of the low-pass filter is connected to the output terminal of the main charge pump via a second switch, and the output terminal is connected to the voltage-controlled oscillator (VCO). It is used to generate a control voltage based on the first current and to calibrate the frequency of the output signal of the VCO using the control voltage.

[0013] Preferably, the frequency-locked loop further includes a frequency and phase detector and an auxiliary charge pump; The input terminal of the frequency and phase detector is connected to the output terminal of the frequency divider and the output terminal of the reference clock buffer, and is used to detect the phase difference between the reference signal and the frequency divider signal. The input terminal of the auxiliary charge pump is connected to the output terminal of the frequency and phase detector, and is used to output a second current when the phase difference is greater than the dead zone range. The input terminal of the low-pass filter is connected to the output terminal of the auxiliary charge pump through a second switch. The low-pass filter is also used to generate a control voltage based on the sum of the first current and the second current, and to calibrate the frequency of the output signal of the voltage-controlled oscillator through the control voltage.

[0014] Preferably, the input terminal of the low-pass filter is connected to the initial voltage module via a first switch. The initial voltage module is used to generate an initial voltage and input it to the low-pass filter to generate a control voltage.

[0015] Preferably, the output of the adaptive frequency calibrator is also used to generate an LK signal for the opening and closing of the first and second switches.

[0016] Compared with the prior art, the above-mentioned at least one technical solution adopted by the present invention can achieve the following beneficial effects: The voltage-controlled oscillator of this invention comprises a three-layer coil structure; the three-layer coil structure, from the outside in, consists of a drain coil, a gate coil, and a source coil; the gate coil and drain coil are both octagonal structures, and the source coil is a figure-eight structure. In differential mode, the source coil L of this invention... S The generated induced magnetic field cancels itself out, and the VCO's resonant cavity operates in a Class F VCO mode similar to a two-coil transformer, reducing output phase noise. In common-mode, the drain coil L... D and source coil L S The generated induced magnetic fields superimpose and enhance each other, and the gate coil L G The generated induced magnetic field self-cancels, and in this state, the common-mode impedance of the VCO is flattened, achieving automatic alignment of the second harmonic over a wide frequency range. This is achieved without increasing additional chip area. The connection point between the source coil center tap and the power supply voltage module is located on the same side of the drain coil as the connection point between the drain coil center tap and ground, shortening the common-mode current recirculation path on the layout. The subsampling PLL of this invention incorporates a separate unlock detector in the adaptive frequency calibrator, ensuring adaptability by monitoring the VCO tuning voltage and reducing lock-in time. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the overall structure of the subsampling phase-locked loop of the present invention; Figure 2 This is a schematic diagram of the broadband harmonic shaping compact VCO of the present invention; Figure 3 The current flow direction and equivalent topology of the three-coil transformer of the present invention under different operating modes; in, Figure 3 (a): Differential mode operation, Figure 3 (b): Common mode operation; Figure 4 The simulation results of the common-mode impedance of the VCO of this invention under different coefficients are shown. in, Figure 4 (a): Adjustment K 2, Figure 4 (b): Adjustment C S ; Figure 5 This is the layout of the broadband harmonic shaping compact VCO of the present invention; Figure 6 This is the schematic diagram of different outputs of the gate terminal and source terminal of the VCO of the present invention; Among them, Figure 6 (a): Output waveform, Figure 6 (b): Output frequency; Figure 7 This is the post - simulation result of the VCO of the present invention; Among them, Figure 7 (a): Phase noise, Figure 7 (b): FoM value; Figure 8 This is the structural block diagram of the connection between the adaptive frequency calibrator and the VCO of the present invention; Figure 9 This is the out - of - lock detector of the present invention; Among them, Figure 9 (a): Circuit schematic diagram, Figure 9 (b): Judgment logic schematic diagram; Figure 10 This is the working flow chart of the adaptive frequency calibrator and the out - of - lock detector of the present invention; Figure 11 This is the simulation result of the adaptive frequency calibrator of the present invention; Among them, Figure 11 (a): Frequency change, Figure 11 (b): Initial phase change, Figure 11 (c): T res Change, Figure 11 (d): f SC Change; Figure 12 This is the simulation result of triggering out - of - lock of the present invention; Figure 13 This is the phase noise curve of the output signal of the phase - locked loop of the present invention; Figure 14 This is the spectrogram of the output signal of the present invention; Figure 15 This is the pie chart of the power consumption decomposition of the phase - locked loop of the present invention; Figure 16 This is the curve of the control voltage of the phase - locked loop changing with time of the present invention; Figure 17 This is the layout of the core circuit part of the phase - locked loop of the present invention; Figure 18 This is a schematic diagram of the overall layout and simulated power consumption of the phase-locked loop of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] To avoid manual second harmonic alignment of the harmonic shaping VCO, existing technologies combine common-mode oscillation with a Class F VCO in the VCO design to achieve broadband harmonic alignment. This is achieved by adding an additional head resonator that resonates with the main resonator to flatten the common-mode impedance near 0°. However, this head resonator has an asymmetrical structure, resulting in an unbalanced drain voltage swing between the oscillating transistors and consuming additional chip area. Furthermore, the large distance between the power supply voltage VDD and the ground plane GND of this broadband harmonic shaping VCO causes the parasitic inductance of the decoupling capacitor to significantly affect the harmonic impedance flattening effect of the head resonator. In addition, the lack of effective isolation between the phase-locked loop and the VCO resonator leads to poor reference spurious performance.

[0021] To address the aforementioned problems, this invention first proposes a voltage-controlled oscillator, the schematic diagram of which is attached. Figure 2 As shown, this achieves three major objectives: broadband harmonic alignment, common-mode current return to the short path, and source-to-output isolation. It includes a switched capacitor array, two negative-resistance transistors M1 and M2, and a three-layer coil structure. The three-layer coil structure, from the outside in, consists of a drain coil L... D , gate coil L G and source coil L S Drain coil L D , gate coil L G All are octagonal structures, with source coil L S It has a figure-eight structure. The two ends of the source coil are connected to the sources of the two negative resistance transistors, the two ends of the gate coil are connected to the gates of the two negative resistance transistors, and the drain coil is connected to the drains of the two negative resistance transistors.

[0022] The drain, source, and gate coils are all equipped with center taps. The center tap of the source coil is connected to the power supply voltage module, the center tap of the drain coil is grounded, and the center tap of the gate coil is connected to a fixed voltage module. The power supply voltage module is used to provide the power supply voltage V. DD The voltage V of the fixed voltage module BSetting it to 0 will improve the conduction state of transistors M1 and M2, making it easier for the VCO to start oscillating.

[0023] The connection point between the source coil center tap and the power supply voltage module and the connection point between the drain coil center tap and ground are located on the same side of the drain coil, while the two negative resistance transistors are located on the other side of the drain coil.

[0024] The switched capacitor array includes the gate capacitor C. G Variable capacitor C V Source capacitor C S and drain capacitance C D Drain capacitance C D Including fixed capacitor C DD Switched capacitor arrays are an existing structure and will not be discussed in detail here.

[0025] Broadband harmonic alignment: The transformer of the VCO of this invention includes 3 coils (drain coil L) D , gate coil L G Source coil L S Each coil is a symmetrical inductor, as shown in the attached diagram. Figure 3 As shown, in differential mode, the source coil L S The generated induced magnetic field cancels itself out, and the VCO's resonant cavity operates in a Class F VCO mode similar to a two-coil transformer, reducing output phase noise. In common-mode, the drain coil L... D and source coil L S The generated induced magnetic fields superimpose and enhance each other, and the gate coil L G The generated induced magnetic field cancels itself out. In this state, the common-mode impedance of the VCO is flattened, achieving automatic alignment of the second harmonic over a wide frequency range, as shown in the attached figure. Figure 4 As shown, by adjusting L D and L S The coupling coefficient K2 (not labeled in the figure) and the source capacitance C between them S The value can flatten the common-mode resonant impedance peak.

[0026] Common-mode current returns to short path: L of the VCO of this invention D Together with the center tap of the Ls coil, it extends from the top, as shown in the attached diagram. Figure 5 As shown, connect the ground plane G respectively. ND With power supply voltage V DD This shortens the common-mode current return path on the layout.

[0027] Source-to-output isolation: VCO source-to-output signal V S+ and V S-The sampled signal is supplied to the next stage subsampling phase detector, enhancing the isolation between the resonant cavity and the sampling loop. To demonstrate the superiority of source-end output isolation, additional... Figure 6 The output waveforms and frequency variations at the gate and source terminals of the VCO of this invention are shown. When sampling from the gate terminal, the VCO frequency variation is 1290MHz, while when sampling from the source terminal, the frequency variation is reduced to 61MHz. Source terminal sampling exhibits better isolation, significantly reducing reference spurious emissions caused by the BFSK effect. Through the above innovative circuit structure design, the VCO of this invention achieves good phase noise and FoM performance over a wide bandwidth. Figure 7 The simulation results of phase noise and FoM for the VCO of this invention are presented. In the frequency range of 13.5 to 14.9 GHz, the phase noise at a frequency offset of 100 kHz is -87.5 to -97.7 dBc / Hz, the phase noise at a frequency offset of 1 MHz is -110.8 to -112.8 dBc / Hz, and the phase noise at a frequency offset of 10 MHz is -131.3 to -132.9 dBc / Hz. The corresponding FoM values ​​are 185.4 to 188.8 dBc / Hz, 188.6 to 189.8 dBc / Hz, and 189.1 to 190 dBc / Hz, respectively.

[0028] To accelerate the loop locking speed of subsampling phase-locked loops (PLLs), existing technologies incorporate Automatic Current-Focused (AFC) technology, enabling rapid searching for a suitable VCO control word and thus shortening the loop locking time. However, existing AFC structures lack an external monitoring circuit to ensure accurate operation. If the AFC searches for an incorrect control word, the VCO tuning voltage will remain unstable for an extended period, thereby increasing the loop locking time.

[0029] The phase-locked loop of this invention includes a reference clock buffer, a gate-isolated subsampling phase detector, a main charge pump, a low-pass filter, a broadband harmonic shaping compact VCO, a lock-out detector, an adaptive frequency calibrator, a frequency and phase detector with dead time, an auxiliary charge pump, and a frequency divider, as shown in the appendix. Figure 1 As shown. The phase-locked loop of this invention is mainly divided into two loops: the first loop is a sub-sampling loop (SSL) consisting of a reference clock buffer, a gate-isolated sub-sampling phase detector, a main charge pump, a low-pass filter, and a broadband harmonic shaping compact VCO; the second loop is a frequency-locked loop (FLL) consisting of a frequency-locked phase detector with dead time, an auxiliary charge pump, and a frequency divider.

[0030] The reference clock buffer is used to convert the crystal oscillator signal into a square wave signal, that is, to generate non-overlapping clock signals CLK1 and CLK2, where CLK1 is the reference signal REF.

[0031] initial voltage V The low-pass filter and the main charge pump are connected via a first switch, and the low-pass filter is connected via a second switch. An adaptive frequency calibrator generates an LK signal to control the first and second switches before the low-pass filter. Only one switch can be closed at a time; when one is closed, the other is open. The LK signal is initially 0, with the first switch closed and the second switch open. When the phase difference between the reference signal and the divided frequency signal is less than a set threshold, the LK signal changes from 0 to 1. The second switch closes and the first switch opens. When the first switch is closed and the second switch is open, the low-pass filter and the initial voltage... V When the first switch is open and the second switch is closed, the SSL and FLL loops are connected to the low-pass filter and VCO. In this embodiment, the initial voltage... V 0 is 350mV.

[0032] Specific working principle: In the initial stage of SSPLL operation, the control voltage V of the VCO is... CTRL The voltage is 350mV. The subsampling loop (SSL) and frequency-locked loop (FLL) are disconnected from the broadband harmonic shaping compact VCO; only the VCO and the frequency divider are functioning normally. The frequency divider down-converts the two sinusoidal signals output from the VCO to obtain the divided signal DIV. The divided signal DIV, along with the reference signal REF, enters the adaptive frequency calibrator. This calibrator uses these two signals to continuously search for the control word K of the VCO's switched capacitor array until a suitable control word is found, causing the VCO oscillation frequency to be in the band closest to 14GHz (the target signal frequency). The unlock detector is used to detect whether the adaptive frequency calibrator has detected the correct band. If the adaptive frequency calibrator detects an incorrect band, the VCO oscillation frequency will be far from 14GHz, causing the VCO's V... CTRL The voltage rises or falls until it exceeds the specified range. At this point, the unlock detector activates, causing the adaptive frequency calibrator to re-search for a suitable control word. In this case, the frequency-locked loop helps the subsampling loop achieve rapid rises or falls in the control voltage. Then, the SSL and FLL are connected to the VCO to form a path. The charge pumps of the SSL and FLL loops are connected to the low-pass filter, making the entire PLL a closed loop. Next, the subsampling loop SSL will gradually adjust the VCO's VCTRL until the loop is finally locked at 14 GHz. The control word is coarse adjustment, and the control voltage V... CTRL For fine-tuning.

[0033] In this embodiment, when the control voltage is high, the tuning gain of the VCO will decrease significantly. When the control voltage varies around 350mV, the tuning gain of the VCO changes less, and its average value is closer to the initial design value.

[0034] The specific function of SSL is: a gate-isolated subsampling phase detector samples two sinusoidal signals output from the VCO, obtaining two sampled voltages (V... SP and V SN ) is transferred to the main charge pump, if V SP and V SN If they are equal, no current is output; otherwise, current is output to the low-pass filter to generate a real-time V. CTRL The FLL controls the frequency of the VCO's output sine wave signal, thus achieving phase locking of the PLL. If the frequency of the output sine wave signal differs from 14GHz by more than 25MHz, the FLL assists the SSL in quickly adjusting the VCO's V. CTRL The auxiliary SSL allows the output frequency to approach 14GHz more quickly, ultimately enabling the loop to be precisely locked at 14GHz.

[0035] The working principle of FLL is similar to that of SSL, but its phase detection module is a frequency-frequency phase detector with a dead time. This phase detector detects the phase difference between REF and DIV. When the phase difference becomes too large to exceed the dead time range, FLL will start, and the auxiliary charge pump of FLL will output current. This current is combined with the output current of the subsampling loop to form I. CP Entering the low-pass filter to form V CTRL When the phase difference between REF and DIV is adjusted to a small value, that is, after entering the dead zone, FLL will be turned off, and the remaining work will be handed over to SSL to achieve the final frequency and phase locking of PLL.

[0036] The adaptive frequency calibrator in this invention searches for a suitable control word for the VCO, and its structural block diagram connected to the VCO is shown below. Figure 8 As shown, the adaptive frequency calibrator outputs a corresponding 6-bit VCO control word based on the phase difference between the input REF and DIV. If the DIV signal lags behind REF by too much, the output control word will cause the VCO to oscillate in a higher frequency band. If the DIV signal leads REF or the phase difference between them is too small, the output control word will cause the VCO to oscillate in a lower frequency band, ultimately stabilizing the VCO control word state and ensuring that the phase difference between REF and DIV is within the resolution range of TDC. Once the adaptive frequency calibrator finds a control word for the VCO, it stops working. The unlock detector monitors in real time whether the VCO tuning voltage exceeds a preset voltage threshold range. If it exceeds the range, it means that the adaptive frequency calibrator has not found a suitable control word, the loop will lose lock, and the adaptive frequency calibrator will restart to search for the VCO control word again.

[0037] The schematic diagram and judgment logic diagram of the unlock detector are attached. Figure 9As shown. Its detection module is a low-power comparator composed of two five-transistor units, used to detect the control voltage of the VCO. V CTRL To determine whether the voltage is within the specified range VTH+ to VTH-, this comparator and subsampling charge pump are cascaded in one module to configure the reference voltage of the tail current source transistor. The comparator's output is fed into the unlock detector; if the VCO control voltage exceeds 32 reference signal cycles... T ref If the loop is consistently outside the control voltage range VTH+ to VTH- specified by the designer within a certain time period, the loss-of-lock detector will determine that the loop is out of lock. At this time, it will output the signal RLKN to wake up the AFC and restart it in order to find a suitable VCO control word.

[0038] The workflow diagrams for the adaptive frequency calibrator and the unlock detector are attached. Figure 10 As shown. First, the AFC detects whether the phase difference between the REF and DIV signals is within the resolution range of the TDC; then, the AFC searches for a suitable VCO band control word; finally, the AFC fixes the VCO control word, disconnects the VCO from the initial 350mV level, connects to the PLL loop, and begins the normal PLL operation. The loss-of-lock detector monitors the VCO control voltage in real time. V CTRL The value is used to determine the locking status of the loop. Once the unlock detector determines that the loop is unlocked, AFC restarts the process.

[0039] Appendix Figure 11 Simulation results of the locking behavior of the adaptive frequency calibrator of this invention under different frequencies, initial phases, TDC resolutions (Tres), and VCO band spacing (fSC) are presented. From an output frequency of 13.5 to 14.5 GHz and an initial phase difference of 0 to 360°, the band search time is less than 60 ns (15 Tref) in the worst case. Even with Tres and fSC deviating from the ideal value by ±50%, the stability of the locking behavior remains unaffected. Furthermore, the difference between the maximum and minimum locking times is within 40 ns (10 Tref), demonstrating the good robustness of the designed adaptive frequency calibrator. (Appendix) Figure 12 The simulation results of the unlocking process are shown. When the VCO control voltage exceeds the threshold range at 100ns, the unlocking is triggered. The adaptive frequency calibrator can re-search for the band control word within 12ns and enter the locked state.

[0040] The phase noise curve of the output signal is as follows Figure 13 As shown, integrating the phase noise curve over a frequency offset range from 1 kHz to 100 MHz yields a root mean square jitter of 28.2 fs. The spectrum of the output signal is shown below. Figure 14As shown, the reference spurious signal at 250MHz is -101.8dBc. A pie chart showing the power consumption breakdown of the phase-locked loop is attached. Figure 15 As shown in the attached figure, the control voltage changes over time. Figure 16 When the control voltage remains constant, it indicates that the phase-locked loop (PLL) is locked, thus the PLL locking time of this invention is 360ns. The top-level layout of the core circuit of this invention's PLL is shown below. Figure 17 As shown. The overall layout and simulated power consumption are as follows. Figure 18 As shown in the figure. Among them, the power consumption of the voltage-controlled oscillator is 3.75mW, the power consumption of the subsampling phase detector and charge pump is 0.76mW, the power consumption of the frequency-locked loop is 1.72mW, the power consumption of the adaptive frequency calibrator is 0.16mW, the power consumption of the reference clock buffer is 0.55mW, and the power consumption of the loop filter is 0, for a total of 6.94mW.

[0041] Compared to the closest existing technology, this invention features lower jitter, lower reference spurious emissions, faster lock-in time, lower power consumption, and a higher factor of quality (FOM). JIT value.

[0042] The phase-locked loop (PLL) of this invention exhibits superior performance and can provide a core clock source for next-generation 5G / 6G millimeter-wave base stations, terminals, and military data links, replacing solutions with poor jitter, spurious emissions, and slow loop locking speeds. This invention can be used in high-speed wired communication systems, such as providing a low-jitter clock for SerDes, meeting stringent requirements for timing accuracy and power consumption, and possessing a huge market potential. Simultaneously, this invention can be licensed as an IP core to other chip design companies, generating profits. Furthermore, this invention helps break the monopoly of foreign companies in the field of high-performance clocks, achieving domestic substitution, ensuring supply chain security, and possessing significant strategic and economic value.

[0043] The phase-locked loop of this invention integrates a broadband harmonic shaping VCO, achieving automatic second harmonic alignment without increasing chip area. The common-mode current of the broadband harmonic shaping VCO of this invention returns to the short path. The VCO of this invention uses the source-side output signal to sample the subsampling phase detector, increasing the isolation between the sampling capacitor and the VCO resonant cavity. This invention designs a separate unlock detector in the adaptive frequency calibrator, ensuring the normal operation of the adaptive frequency calibrator by monitoring the VCO tuning voltage.

[0044] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0045] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A voltage controlled oscillator characterized by, The application relates to a voltage-controlled oscillator, which comprises two negative resistance transistors and a three-layer coil structure; the three-layer coil structure comprises a drain coil, a gate coil and a source coil from outside to inside; the gate coil and the drain coil are octagonal structures, and the source coil is an eight-shaped structure; two ends of the source coil are connected with sources of the two negative resistance transistors, two ends of the gate coil are connected with gates of the two negative resistance transistors, and the drain coil is connected with drains of the two negative resistance transistors; the drain coil, the source coil and the gate coil are all provided with center taps, the center tap of the source coil is connected with a power voltage module, the center tap of the drain coil is grounded, and the center tap of the gate coil is connected with a fixed voltage module; a connecting point of the source coil center tap and the power voltage module and a connecting point of the drain coil center tap and the ground are located on the same side of the drain coil, and the two negative resistance transistors are located on the other side of the drain coil.

2. The voltage controlled oscillator of claim 1, wherein, The application further comprises a switched capacitor array, the switched capacitor array comprises two gate capacitors, two variable capacitors and two source capacitors, one end of each of the two gate capacitors is connected with a gate of the two negative resistance transistors, and the other end of each of the two gate capacitors is connected with each other, one end of each of the two variable capacitors is connected with a gate of the two negative resistance transistors, and the other end of each of the two variable capacitors is connected with each other, one end of each of the two source capacitors is connected with a source of the two negative resistance transistors, and the other end of each of the two source capacitors is grounded.

3. A sub-sampling phase-locked loop, characterized by, The application relates to a voltage-controlled oscillator, which comprises a sub-sampling loop, a frequency-locked loop, a lock-loss detector and an adaptive frequency calibrator; the sub-sampling loop comprises the voltage-controlled oscillator according to any one of claims 1-2; the frequency-locked loop comprises a frequency divider, an input end of the frequency divider is connected with an output end of the voltage-controlled oscillator, and the frequency divider is used for frequency reduction of an output signal of the voltage-controlled oscillator to obtain a frequency-divided signal; an input end of the adaptive frequency calibrator is connected with an output end of the frequency divider, an output end of the adaptive frequency calibrator is connected with an input end of the voltage-controlled oscillator, the adaptive frequency calibrator is used for outputting a corresponding control word to the voltage-controlled oscillator according to a phase difference between the frequency-divided signal and a reference signal, and the frequency of the output signal of the voltage-controlled oscillator is calibrated to a frequency band closest to a target frequency based on the control word; the lock-loss detector is used for detecting whether the frequency band is correct, if the frequency band is incorrect, then the control voltage is adjusted through the sub-sampling loop and the frequency-locked loop, the voltage-controlled oscillator is controlled through the control voltage, and the frequency of the output signal is locked.

4. A sub-sampling phase locked loop as claimed in claim 3, characterized in that, the sub-sampling loop further comprises a reference clock buffer, a sub-sampling phase detector, a main charge pump and a low-pass filter; the reference clock buffer is used for converting a crystal oscillator signal into two clock signals CLK1 and CLK2, and the reference signal is CLK1; an input end of the sub-sampling phase detector is connected with an output end of the reference clock buffer and an output end of the voltage-controlled oscillator, and the sub-sampling phase detector is used for sampling two sinusoidal signals to obtain two sampling voltages; wherein, the clock signal is used for controlling the on-off of a sampling switch of the sub-sampling phase detector; an input end of the main charge pump is connected with an output end of the sub-sampling phase detector, and the main charge pump is used for generating a first current according to the size relationship of the two sampling voltages; The input end of the low-pass filter is connected with the output end of the main charge pump through a second switch, and the output end is connected with a voltage-controlled oscillator, for generating a control voltage according to the first current, and calibrating the frequency of the output signal of the voltage-controlled oscillator through the control voltage.

5. A subsampled phase-locked loop as recited in claim 3, wherein, The frequency-locked loop further comprises a phase-frequency detector and an auxiliary charge pump; The input end of the phase-frequency detector is connected with the output end of the frequency divider and the output end of a reference clock buffer, for detecting the phase difference between the reference signal and the frequency-divided signal; The input end of the auxiliary charge pump is connected with the output end of the phase-frequency detector, for outputting a second current when the phase difference is greater than a dead zone range; The input end of the low-pass filter is connected with the output end of the auxiliary charge pump through a second switch, and the low-pass filter is further used for generating a control voltage according to the sum of the first current and the second current, and calibrating the frequency of the output signal of the voltage-controlled oscillator through the control voltage.

6. A subsampled phase-locked loop as recited in claim 4, wherein, The input end of the low-pass filter is connected with an initial voltage module through a first switch, and the initial voltage module is used for generating an initial voltage and inputting the initial voltage to the low-pass filter to generate a control voltage.

7. A subsampled phase-locked loop as claimed in claim 6, characterized in that The output end of the adaptive frequency calibrator is further used for generating an LK signal for opening and closing the first switch and the second switch.

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