Circular Bond Finger Pads

Abstract

Examples of integrated circuit (IC) packages are disclosed. Each IC package may include a flip chip (FC) die on a substrate, a wire bond die above the FC die, wire bonds connected to the wire bond die, and a mold on the substrate and encapsulating the FC die, the wire bond die, and the wire bonds. The substrate may include at least a first metallization layer comprising a first substrate layer, traces on the first substrate layer and routed within the first metallization layer to electrically couple with one or more interconnects of the FC die, and bond finger pads formed on the traces. The bond finger pads may be circular. The wire bonds may be electrically connected to the traces such that the wire bond die is electrically coupled with the FC die through the wire bonds, the bond finger pads, and the traces.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This patent application claims the benefit of U.S. Non-Provisional Application No. 17 / 161,105, entitled "CIRCULAR BOND FINGER PAD," filed January 28, 2021, which is assigned to the assignee of the present application and is expressly incorporated herein by reference in its entirety.

[0002] The present disclosure relates generally to integrated circuit (IC) packages, and more particularly to circular bond finger pads, for example but not limited to, for 5G devices. [Background technology]

[0003] Integrated circuit technology has achieved great advances in increasing computing power by miniaturizing active components. Packaged devices can be found in many electronic devices, including processors, servers, radio frequency (RF) integrated circuits, etc. Packaging techniques have become cost-effective for high pin count devices and / or high production volume parts.

[0004] An exemplary conventional IC package includes a flip-chip (FC) die, such as a baseband modem, in contact with a substrate. A memory die is above the baseband modem, with a die attach between them. A mold encapsulates the baseband modem and memory die in contact with and on the substrate. The substrate includes a metallization layer in which traces are routed to electrically couple with solder bumps on the baseband modem. Wire bonds (e.g., formed of gold (Au), silver (Ag), copper (Cu), etc.) are used within the mold to electrically couple the memory die to the baseband modem through the traces. The wire bonds connect to the traces through bond finger pads in contact with the traces. Typically, the pads are nickel / gold (Ni / Au) plated surfaces. This means that the traces are formed from an electroplating process; that is, the traces are plated traces. Therefore, the plated traces extend to the edge of the substrate. The traces at the edge are connected to plated lines that electrically connect to all of the bond finger pads, which will be used for electroplating the top of the bond finger pads.

[0005] The bond finger pads (e.g., made from Cu) are typically rectangular or oval in shape because they are non-solder mask defined (NSMD), where the pad is defined by the metal and the solder mask opening is wider than the pad, meaning that there is clearance between the solder mask opening and the pad, exposing the entire Cu pad.

[0006] Solder mask openings can move in any direction. This means that NSMD bond finger pads, due to Ni / Au plating, typically require loose design rules for spacing. Unfortunately, this results in a lower Cu density in the bond finger area. Also, the bond fingers are located near the edge of the substrate in conventional packaging to make routing the plated traces easier. This means that long wire bonds are required to connect the memory die to the bond fingers. This increases the electrical resistance of the wire bonds. Long wire bonds are also more difficult to achieve. Summary of the Invention [Problem to be solved by the invention]

[0007] Therefore, there is a need for systems, devices, and methods that overcome the shortcomings of conventional packaging, including the methods, systems, and devices provided herein. [Means for solving the problem]

[0008] The following presents a simplified summary of one or more aspects and / or examples related to the apparatus and methods disclosed herein. As such, the following summary should not be considered an extensive overview of all contemplated aspects and / or examples, nor should it be considered to identify key or critical elements of all contemplated aspects and / or examples or to delineate the scope associated with any particular aspect and / or example. As such, the following summary is solely intended to present certain concepts related to one or more aspects and / or examples related to the apparatus and methods disclosed herein in a simplified form prior to the detailed description presented below.

[0009] An exemplary integrated circuit (IC) package is disclosed. The IC package may include a substrate, a flip-chip (FC) die, a wirebond die disposed above the FC die, wirebonds connected to the wirebond die, and a mold in contact with the substrate. The mold may encapsulate the FC die, the wirebond die, and the wirebonds. The substrate may include one or more metallization layers, including a first metallization layer. The first metallization layer may include a first substrate layer, traces, and bond finger pads. The traces may be formed in contact with the first substrate layer and routed within the first metallization layer to electrically couple with one or more FC interconnects of the FC die. The bond finger pads may be formed in contact with the traces. The bond finger pads may be substantially circular in shape. The wirebonds may be electrically connected to the bond finger pads such that the wirebond die is electrically coupled to the FC die through the wirebonds, the bond finger pads, and the traces.

[0010] A method for fabricating an integrated circuit (IC) package is disclosed. The method may include forming a substrate. The method may also include disposing a flip-chip (FC) die on the substrate. The method may further include disposing a wirebond die above the FC die. The method may also include forming wirebonds connected to the wirebond die. The method may also further include forming a mold on the substrate, the mold encapsulating the FC die, the wirebond die, and the wirebonds. The substrate may be formed to include one or more metallization layers, including a first metallization layer. The first metallization layer may include a first substrate layer, traces, and bond finger pads. The traces may be formed on the first substrate layer and routed within the first metallization layer to electrically couple with one or more FC interconnects of the FC die. The bond finger pads may be formed on the traces. The bond finger pads may be substantially circular in shape. Wirebonds can be formed to electrically connect to the bond finger pads such that the wirebond die is electrically coupled with the FC die through the wirebonds, bond finger pads, and traces.

[0011] Other features and advantages associated with the apparatus and methods disclosed herein will become apparent to one skilled in the art upon review of the accompanying drawings and detailed description.

[0012] A more complete appreciation of the same will be readily obtained as the aspects of the present disclosure and many of its attendant advantages become better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings, which are presented merely to illustrate and not to limit the disclosure, and in which: [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a diagram showing an example of a conventional integrated circuit (IC) package. [Figure 2]FIG. 1 illustrates bond finger pads of a conventional IC package. [Figure 3] FIG. 1 illustrates an example of an IC package, according to one or more aspects of the present disclosure. [Figure 4] 1 illustrates bond finger pads of an IC package according to one or more embodiments of the present disclosure. [Figure 5] 1A-1C illustrate further examples of IC packages according to one or more embodiments of the present disclosure. [Figure 6] 1A-1C illustrate further examples of IC packages according to one or more embodiments of the present disclosure. [Figure 7] 1 is a process flow of various stages of fabricating a substrate for an IC package according to one or more embodiments of the present disclosure. [Figure 8] 1 is a process flow of various stages of assembling an IC package according to one or more embodiments of the present disclosure. [Figure 9] 1 is a flowchart of an exemplary method for manufacturing an IC package according to one or more embodiments of the present disclosure. [Figure 10] 1A-1C illustrate various electronic devices that may utilize one or more aspects of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0014] Other objects and advantages associated with the aspects disclosed herein will become apparent to those skilled in the art based on the accompanying drawings and detailed description. According to common practice, features illustrated by the drawings may not be drawn to scale. Accordingly, dimensions of illustrated features may be arbitrarily increased or decreased for clarity. According to common practice, some of the drawings have been simplified for clarity. Accordingly, the drawings may not depict all components of a particular apparatus or method. Furthermore, like reference numerals refer to like features throughout the specification and figures.

[0015] Aspects of the present disclosure are illustrated in the following description and related drawings directed to specific embodiments. Alternative aspects or embodiments may be devised without departing from the scope of the teachings herein. Additionally, well-known elements of the exemplary embodiments herein may not be described in detail or may be omitted so as not to obscure the relevant details of the teachings in the present disclosure.

[0016] In some described exemplary implementations, instances are identified where portions of the structure and operation of various components may be derived from known conventional techniques and configured in accordance with one or more exemplary embodiments. In such instances, some internal details of the structure and / or operation of known conventional components may be omitted to help avoid potentially obscuring the concepts illustrated in the exemplary aspects disclosed herein.

[0017] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context dictates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including," as used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0018]

[0006] Various aspects of the present disclosure are proposed to address problems associated with conventional IC packages. For background purposes, an example of a conventional IC package is shown in FIG. 1. The conventional IC package 100 includes a baseband modem 110 on a three-layer substrate, which is a flip-chip (FC) die. A memory die 120 is above the baseband modem 110 with a die attach 130 therebetween. A mold 140 encapsulates the baseband modem 110 and the memory die 120 on and above the substrate.

[0019] The three-layer substrate includes metallization layers M1, M2, and M3. The M1 layer includes a first substrate layer 170, the M2 layer includes a second substrate layer 180, and the M3 layer includes a third substrate layer 190. Traces 172 are routed within the metallization layer M1 to electrically couple with solder bumps 115 of the baseband modem 110. Also within the metallization layer M1, solder resist (SR) 178 is formed adjacent to the traces 172 and adjacent to the first substrate 170. Bond finger pads 150 (which will be discussed further below) are formed within openings in the solder resist 178 adjacent to the traces 172. Solder balls 165 are formed adjacent to the underside of the third substrate layer 190.

[0020] Within mold 140, wire bonds 160 (formed, for example, of gold (Au), silver (Ag), copper (Cu), etc.) are used to electrically couple memory die 120 to baseband modem 110 through traces 172. Wire bonds 160 electrically connect to traces 172 through bond finger pads 150.

[0021] Typically, bond finger pads 150 are nickel / gold (Ni / Au) plated onto the surface of traces 172. Thus, traces 172 may also be referred to as plated traces. Plated traces 172 extend to the edges of the substrate. Plated traces 172 at the edges are connected to one or more plated lines (not shown) that electrically connect to bond finger pads 150 and that will be used for electroplating the top of bond finger pads 150.

[0022] 1, the vicinity of bond finger pad 150 is highlighted by a dashed circle. Note that bond finger pad 150 is formed within an opening in solder resist 178. Note also that on either side of bond finger pad 150, there is a gap between bond finger pad 150 and solder resist 178. That is, the opening in solder resist 178, also referred to as a solder resist opening (SRO), is wider than bond finger pad 150.

[0023] A top view of the M1 layer near the bond finger pads is shown in FIG. 2. Here, two bond finger pads 150 are shown formed within SRO, which is the area of ​​trace 172 not covered by solder resist 178. As can be seen, the shape of bond finger pads 150 (e.g., formed from Ni / Au plating) is typically rectangular or oval. For example, the dimensions of each bond finger pad 150 may be 100 μm (e.g., horizontally in FIG. 2) by 50 μm (e.g., vertically in FIG. 2).

[0024] Bond finger pad 150 is an example of a non-solder mask defined (NSMD) pad. As shown, SRO is wider than bond finger pad 150. This means that the shape of bond finger pad 150 is not defined by solder resist 178 (also called solder mask). Rather, bond finger pad 150 is defined by the metal.

[0025] Because the SRO is wider than the bond finger pad 150, the entire bond finger pad 150 is exposed by the gap between the SRO and the bond finger pad 150. The SRO can move in any direction. This means that the bond finger pad 150 requires a loose design rule for spacing due to Ni / Au plating. This is because any metal exposed in the SRO, including any traces 172, can be plated when the bond finger pad 150 is formed. This means that the traces 172 can be thick. As a result, adjacent traces 172 can short out. A loose spacing design means that sufficient spacing is provided between adjacent bond finger pads 150 to prevent problems such as undesirable shorts. The spacing between adjacent bond finger pads 150 can be large, for example, 25 μm or more. Unfortunately, the loose spacing results in a low Cu density in the SRO region. In printed circuit boards (PCBs), areas of low Cu density can lead to undesirable issues such as warpage (e.g., 2 mm or more), which can be especially true for prepreg PCBs.

[0026] Another problem is the following: Referring again to FIG. 1, the NSMD bond finger pads 150 are located near the edge of the substrate to make it easier to route the plated traces to the edge of the substrate. This means that the wire bonds 160 must be very long. Unfortunately, long wire bonds are associated with electrical problems (e.g., high resistance) and process problems (e.g., wire shorts).

[0027] According to various aspects disclosed herein, to address problems associated with conventional IC packages, it is proposed to provide circular bond finger pads that are solder mask defined (SMD). In SMD pads, the solder mask is smaller than the actual metal that makes up the bond finger pad. This implies that when an electroplating process is performed, only the opening, i.e., the solder mask opening (SMO), is plated to form the bond finger pad. The traces are not plated. As a result, the spacing between adjacent bond finger pads can be reduced, for example, to 15 μm or less, without concern for short circuiting. This means that metal density (e.g., Cu density) can be increased, which leads to reduced or even eliminated warpage.

[0028] Another advantage of the proposed SMD bond finger pads is that they can be found anywhere. Recall that the location of conventional NSMD bond finger pads 150 is limited to near the edge of the substrate. However, the proposed SMD bond finger pads can be placed anywhere on the substrate. For example, the proposed SMD bond finger pads can be placed near the memory die. As a result, wire bonds can be made shorter, which reduces electrical resistance and also reduces the possibility of wire shorts.

[0029] An example of an IC package according to one or more embodiments of the present disclosure is shown in FIG. 3. The exemplary IC package 300 may include a flip-chip (FC) die 310. A baseband modem die may be an example of the FC die 310. The FC die 310 may be in contact with a substrate including one or more metallization layers (described further below). A wirebond die 320 (e.g., a memory die) may be disposed above the FC die 310, with a die attach 330 therebetween. A mold 340 may be in contact with and over the substrate and encapsulate the FC die 310 and the wirebond die 320.

[0030] In FIG. 3 , a substrate is shown with three metallization layers M1, M2, and M3. This is by way of example only. The actual number of metallization layers is not so limited. That is, a substrate may include one or more metallization layers. Each metallization layer may include a substrate layer. For example, the M1 metallization layer (or first metallization layer) may include a first substrate layer 370. Similarly, the M2 metallization layer (or second metallization layer) may include a second substrate layer 380, the M3 metallization layer (or third metallization layer) may include a third substrate layer 390, and so on. The substrate layers 370, 380, 390 may each be an insulating layer.

[0031] In one, some, or all of the metallization layers, traces may be routed to electrically couple with the FC interconnects 315 (e.g., bumps) of the FC die 310. For example, in FIG. 3 , in the first metallization layer M1, traces 372 may be formed on the first substrate layer 370 and routed to electrically couple with the FC interconnects 315. The traces 372 may be formed from a conductive metal such as Cu, aluminum (Al), or the like.

[0032] Also within the first metallization layer M1, a solder mask (SM) 378 (e.g., solder resist) may be formed adjacent the traces 372 as well as adjacent the first substrate layer 370. Bond finger pads 350 may be formed adjacent the traces 372 within solder mask openings (SM0, which are discussed further below) in the solder mask 378. External interconnects 365 (e.g., solder balls) may be formed adjacent the bottom surface of the substrate. In this case, the external interconnects 365 may be formed adjacent the bottom surface of the substrate, which in this case is substrate layer 390.

[0033] Within mold 340, wirebonds 360 may be formed to electrically couple wirebond die 320 to FC die 310. For example, ends of wirebonds 360 may be connected to wirebond die 320 and bond finger pads 350. Thus, wirebond die 320 may be electrically coupled to FC die 310 through wirebonds 360, bond finger pads 350, and traces 372. Wirebonds 360 may be formed from a metal such as gold (Au), silver (Ag), copper (Cu), or the like.

[0034] It should be noted that although not shown, in practice there would likely be multiple wirebonds 360, multiple bond finger pads 350, and multiple traces 372. However, for ease of description and explanation, only one wirebond 360 and one corresponding bond finger pad 350 are shown.

[0035] Bond finger pad 350 may be a metal (e.g., nickel / gold (Ni / Au)) plated onto the surface of trace 372. Trace 372 may extend from bond finger pad 350 to the edge of the substrate within first metallization layer M1 such that trace 372 at the edge of the substrate is electrically coupled to bond finger pad 350. Thus, trace 372 may be connected to one or more plating lines (not shown) at the edge of the substrate for electroplating of bond finger pad 350.

[0036] 3, the vicinity of bond finger pad 350 is highlighted by a dashed circle. Bond finger pad 350 may be formed within an opening in solder mask 378, i.e., within a solder mask opening (SMO). However, unlike bond finger pad 150 in conventional IC package 100, there is no gap between bond finger pad 350 and solder mask 378. That is, SMO is not wider than bond finger pad 350.

[0037] A top view of the M1 layer near the bond finger pads is shown in FIG. 4, where a single bond finger pad 350 is shown as being formed in the SMO. The SMO may be defined as the area above the first substrate layer 370 and traces 372 that is not covered by solder mask 378. Note that the first substrate layer 370 and traces 372 are not visible in this top view because they are completely covered by solder mask 378 and bond finger pad 350, at least in the vicinity of bond finger pad 350.

[0038] Unlike conventional bond finger pads 150, bond finger pads 350 (e.g., formed metal (e.g., Ni / Au) plating) may be circular or substantially circular in shape. Also, the dimensions or size of bond finger pads 350 may be small. For example, bond finger pads 350 may be 50 μm or less in diameter, which means that the SMO may also be 50 μm or less. Bond finger pads 350 are an example of solder mask defined (MSD) pads. In other words, the characteristics (e.g., size, shape, etc.) of bond finger pads 350 may be defined, at least in part, by solder mask 378.

[0039] Recall from above that conventional IC package 100 requires a relaxed spacing design. However, for SMD bond finger pad 350, the spacing may be narrower because trace 372 is covered by solder mask 378, i.e., trace 372 is not exposed. More specifically, trace 372 is not exposed except for the portion of trace 372 where bond finger pad 350 is formed, i.e., the portion of trace 372 corresponding to the SMD.

[0040] Therefore, even when traces 372 are used in the electroplating process to form bond finger pads 350, traces 372 themselves are not plated. Therefore, the size of traces 372 does not change, at least not significantly, during plating. This means that the possibility of short circuits occurring between traces 372 is greatly reduced. As a result, the spacing between bond finger pads 350 can be reduced to, for example, 15 μm or less.

[0041] Because the spacing between traces 372 can be reduced, this suggests that the density of traces 372 can be increased accordingly. In other words, the metal density (e.g., Cu density) can be increased with SMD bond finger pads 350. This is advantageous in that warpage can be reduced (e.g., less than 2 mm) or even eliminated.

[0042] Referring again to FIG. 3 , note that bond finger pad 350 is located near wire bond die 320. In fact, it can be said that bond finger pad 350 may be positioned such that the die-to-pad distance, which may be defined as the distance from wire bond die 320 to bond finger pad 350, is less than the edge-to-pad distance, which may be defined as the distance from the edge of the substrate to bond finger pad 350. This is contrary to conventional IC packages, where the die-to-pad distance is much longer than the edge-to-pad distance. The shorter die-to-pad distance allows for correspondingly shorter wire bonds 360. As a result, electrical characteristics can be improved (e.g., lower resistance) and process issues can be reduced (e.g., lower likelihood of wire shorts).

[0043] Also, wirebond 360 may be a reverse wirebond, i.e., one end of wirebond 360 may be ball-bonded to bond finger pad 350 and the other end may be stitch-bonded to wirebond die 320. Although not shown, there may be multiple wirebond dies 320 above FC die 310, and all wirebond dies 320 and FC die 310 may be encapsulated by mold 340. Also, each of multiple wirebond dies 320 may be electrically coupled to FC die 310 through a corresponding wirebond 360 and bond finger pad 350.

[0044] 5 shows another example of an IC package 500 according to one or more embodiments of the present disclosure. The IC package 500 may include a flip-chip (FC) die 510 (e.g., a baseband modem) in contact with a substrate, a wirebond die 520 (e.g., a memory die) disposed above the FC die 510 with a die adhesive 530 between the FC die 510, and a mold 540 in contact with and above the substrate that encapsulates the FC die 510 and the wirebond die 520. The substrate may include one or more metallization layers (e.g., M1, M2, M3, etc.), and each metallization layer may include a corresponding substrate layer (e.g., a first substrate layer 570, a second substrate layer 580, a third substrate layer 590, etc.).

[0045] Within one, some, or all of the metallization layers, traces may be routed to electrically couple with FC interconnects 515 (e.g., bumps) of FC die 510. For example, in FIG. 5, within first metallization layer M1, trace 572-1 may be formed against first substrate layer 570 and routed to electrically couple with FC interconnect 515. For reasons discussed below, trace 572-1 may also be referred to as first layer 1 trace 572-1.

[0046] Also within the first metallization layer M1, a solder mask (SM) 578 (e.g., solder resist) may be formed on the first layer 1 traces 572-1 and on the first substrate layer 570. Bond finger pads 550 may be formed within the SM1 on the first layer 1 traces 572-1. External interconnects 565 (e.g., solder balls) may be formed on the underside of the substrate (e.g., on the underside of the third substrate layer 590, the bottom layer of the substrate).

[0047] Within mold 540, wirebonds 560 may be formed to electrically couple wirebond die 520 to FC die 510. For example, ends of wirebonds 560 may be connected to wirebond die 520 and bond finger pads 550. Thus, wirebond die 520 may be electrically coupled to FC die 510 through wirebonds 560, bond finger pads 550, and first layer 1 traces 572-1. Wirebonds 560 may be formed from a metal such as gold (Au), silver (Ag), copper (Cu), or the like.

[0048] The IC package 500 of Figure 5 is similar to the IC package 300 of Figure 3. One major difference between IC packages 500 and 300 is in the routing of the traces. Recall that in Figure 3, the traces 372 may extend entirely within the first metallization layer M1 from the bond finger pads 350 to the edge of the substrate. A plating line (not shown) may be electrically coupled to the traces 372 in the first metallization layer M1 for electroplating.

[0049] 5, the electrical coupling to the plating lines for plating bond finger pads 550 also occurs in the first metallization layer M1. However, it may be difficult or even impossible to simply extend traces from bond finger pads 550 to the edge of the substrate within the first metallization layer M1. For example, there may be multiple traces that need to be routed within the first metallization layer M1, and extending the traces from bond finger pads 550 to the edge may make it difficult to route other traces within the first metallization layer M1.

[0050] However, if trace routing for plating can be achieved through other metallization layers, the trace routing as a whole may be more optimized. As seen in FIG. 5 , in addition to the first layer-1 trace 572-1, the first metallization layer M1 may also include a second layer-1 trace 572-2, a first layer-1 via 574-1, and a second layer-1 via 574-2. The second layer-1 trace 572-2 may be formed on the first substrate layer 570. The first layer-1 via 574-1 and the second layer-1 via 574-2 may be formed through the first substrate layer 570 from the first layer-1 trace 572-1 and the second layer-1 trace 572-2, respectively, to the bottom surface of the first metallization layer M1. Each of the first and second layer 1 traces 572-1 and 572-2 and the first and second layer 1 vias 574-1 and 574-2 may be formed from a conductive metal such as Cu, Al, or the like.

[0051] The second metallization layer M2 may include a layer 2 trace 582 formed in contact with the second substrate layer 580. The layer 2 trace 582 may also be formed from a conductive metal such as Cu, Al, etc. As can be seen, the wiring for plating from the bond finger pad 550 to the edge of the substrate may pass, in order, through the first layer 1 trace 572-1, the first layer 1 via 574-1, the layer 2 trace 582, the second layer 1 via 574-2, and the second layer 1 trace 572-2.

[0052] The second layer 1 traces 572-2 may extend from within the first metallization layer M1 to the edge of the substrate such that the second layer 1 traces 572-2 at the edge of the substrate are electrically coupled to the bond finger pads 550. In this manner, the second layer 1 traces 572-2 may be connected to one or more plating lines (not shown) at the edge of the substrate for electroplating of the bond finger pads 550.

[0053] When there are multiple metallization layers, it is not necessary for a plating line to always join with a trace (e.g., trace 372, second layer 1 trace 572-2, etc.) in the first metallization layer M1. For example, with respect to FIG. 5, it may be an option to extend layer 2 trace 582 to the edge of the substrate (not shown). Layer 2 trace 582 may then be connected to one or more plating lines for electroplating of bond finger pad 550.

[0054] 6 illustrates an exemplary IC package 600 according to one or more aspects of the disclosure. The IC package 600 may include a flip-chip (FC) die 610 (e.g., a baseband modem) in contact with a substrate, a wirebond die 620 (e.g., a memory die) disposed above the FC die 610 with a die attach adhesive 630 between the FC die 610, and a mold 640 in contact with and above the substrate that encapsulates the FC die 610 and the wirebond die 620. The substrate may include one or more metallization layers (e.g., M1, M2, M3, etc.), and each metallization layer may include a corresponding substrate layer (e.g., a first substrate layer 670, a second substrate layer 680, a third substrate layer 690, etc.).

[0055] Traces may be routed within one, some, or all of the metallization layers to electrically couple with FC interconnects 615 (e.g., bumps) of FC die 610. For example, in FIG. 6 , within first metallization layer M1, layer 1 traces 672 may be formed against first substrate layer 670 and routed to electrically couple with FC interconnects 615.

[0056] Also within the first metallization layer M1, a solder mask (SM) 678 (e.g., solder resist) may be formed on the layer 1 traces 672, as well as on the first substrate layer 670. Bond finger pads 650 may be formed within the SM1 on the layer 1 traces 672-1. External interconnects 665 (e.g., solder balls) may be formed on the underside of the substrate (e.g., on the underside of the third substrate layer 690, the bottom layer of the substrate).

[0057] Within mold 640, wirebonds 660 may be formed to electrically couple wirebond die 620 to FC die 610. For example, ends of wirebonds 660 may be connected to wirebond die 620 and bond finger pads 650. Thus, wirebond die 620 may be electrically coupled to FC die 610 through wirebonds 660, bond finger pads 650, and layer 1 traces 672. Wirebonds 660 may be formed from a metal such as gold (Au), silver (Ag), copper (Cu), etc.

[0058] The IC package 600 of Figure 6 is similar to the IC packages 300 and 500 of Figures 3 and 5. One major difference is that plating lines (not shown) for electroplating of bond finger pads 650 may be electrically coupled to traces in metallization layers other than the first metallization layer M1.

[0059] 6 , the first metallization layer M1 may include layer 1 vias 674 in addition to layer 1 traces 672. The layer 1 vias 674 may be formed through the first substrate layer 370. The second metallization layer M2 may include layer 2 traces 682 and layer 2 vias 684. The layer 2 traces 682 may be formed on the second substrate layer 680, and the layer 2 vias 684 may be formed through the second substrate layer 680. The third metallization layer M3 may include layer 3 formed on the third substrate layer 690. Each of the layer 1 traces 672, layer 1 vias 674, layer 2 traces 682, layer 2 vias 684, and layer 3 traces 692 may be formed from a conductive metal, such as Cu, Al, etc.

[0060] As can be seen, routing for plating from bond finger pad 650 to the edge of the substrate may pass, in order, through layer 1 trace 672, layer 1 via 674, layer 2 trace 682, layer 2 via 684, and layer 3 trace 692. Layer 3 trace 692 may extend from within third metallization layer M3 to the edge of the substrate such that layer 3 trace 692 at the edge of the substrate is electrically coupled with bond finger pad 650. In this manner, layer 3 trace 692 may be connected to one or more plating lines (not shown) at the edge of the substrate for electroplating of bond finger pad 650.

[0061] 7 shows a process flow 700 of various stages of fabricating a substrate for an IC package. At block 705, solder resist may be applied. At block 710, plasma etching may be performed. At block 715, dry film resist (DFR) lamination may be performed, followed by exposure at block 720 and development at block 725. At block 730, Ni / Au plating may be performed (e.g., to form bond finger pads 350, 550, 650). At block 735, the substrate may be stripped.

[0062] Another DFR lamination may be performed in block 740, followed by exposure in block 745 and another development in block 750. A plating bar etch may then be performed in block 755, followed by stripping in block 760 and strip wiring in block 765. A protective material such as an organic solderability preservative (OSP) may be applied in block 770. The substrate may be packaged in block 775.

[0063] 8 shows a process flow 800 of various stages of assembling an IC package 300, 500, 600. In block 805, dicing may be performed. In block 810, a flip-chip (FC) die 310, 510, 610 may be bonded to a substrate. In block 815, a die attach material 330, 530, 630 may be disposed on the FC die 310, 510, 610. In block 820, a wirebond die 320, 520, 620 may be attached to the FC die 310, 510, 610 through the die attach material 330, 530, 630.

[0064] Reflow may be performed at block 825, followed by a flux clean at block 830. Reverse wire bonding may be performed at block 835 to form wire bonds 360, 560, 660 connecting the bond finger pads 350, 550, 650 and the wire bond die 320, 520, 620. At block 840, a mold 340, 540, 640 may be formed to encapsulate the FC die 310, 510, 610, the wire bond die 320, 520, 620, and the wire bonds 360, 560, 660.

[0065] Laser marking may be performed in block 845, followed by ball mounting in block 850 and substrate cutting in block 855. FT O / S may be performed in block 860. The IC packages 300, 500, 600 may be inspected in block 865 and shipped in block 870.

[0066] 9 shows a flowchart of an exemplary method 900 of fabricating an IC package, such as any of IC packages 300, 500, 600. At block 910, a substrate may be formed.

[0067] In block 920, a flip chip (FC) die (eg, FC die 310, 510, 610) may be disposed on a substrate.

[0068] At block 930, a wirebond die (e.g., wirebond die 320, 520, 620) may be disposed above the FC die. For example, a die attach (e.g., die attach 330, 530, 630) may be used.

[0069] At block 940, wirebonds (eg, wirebonds 360, 560, 660) may be formed to connect to the wirebond die.

[0070] At block 950, a mold may be formed on the substrate to encapsulate the FC die, the wirebond die, and the wirebonds.

[0071] In an embodiment, a substrate may be formed in block 910 to include one or more metallization layers, including a first metallization layer (M1) (e.g., metallization layer M1). The first metallization layer may include a first substrate layer (e.g., first substrate layer 370, 570, 670), traces (e.g., trace 372, first layer 1 trace 572-1, layer 1 trace 672) formed on the first substrate layer and routed within the first metallization layer to electrically couple with one or more FC interconnects (e.g., FC interconnects 315, 515, 615), and bond finger pads (e.g., bond finger pads 350, 550, 650) formed on the traces. The bond finger pads may be circular or substantially circular in shape. Wirebonds can be formed to electrically connect to the bond finger pads such that the wirebond die is electrically coupled with the FC die through the wirebonds, bond finger pads, and traces.

[0072] The first metallization layer may further include a solder mask (e.g., solder masks 378, 578, 678) formed on the traces and the first substrate layer. Bond finger pads may be formed in the SMO.

[0073] In one embodiment, traces (eg, trace 372) can extend from the bond finger pads in the first metallization layer to the edge of the substrate (see, eg, FIG. 3).

[0074] In another aspect, the trace may be a first layer 1 trace (e.g., first layer 1 trace 572-1), and the first metallization layer may further include a second layer 1 trace (e.g., second layer 1 trace 572-2) formed on the first substrate layer (e.g., first substrate layer 570) and routed within the first metallization layer. The second layer 1 trace may be electrically coupled to the first layer 1 trace and extend within the first metallization layer from within the substrate to the edge of the substrate (see, e.g., FIG. 5).

[0075] In yet another embodiment, the trace may be a layer 1 trace (e.g., layer 1 672), and the substrate further comprises an additional metallization layer (e.g., third metallization layer M3) below the first metallization layer (M1). The additional metallization layer may comprise an additional substrate layer (e.g., third substrate layer 690) and an additional trace (e.g., layer 3 trace 692) formed on the additional substrate layer and routed within the additional metallization layer. The additional trace may be electrically coupled to the layer 1 trace (672) and may extend within the additional metallization layer from within the substrate to the edge of the substrate (see, e.g., FIG. 6).

[0076] 10 illustrates various electronic devices that may be integrated with any of the above-described integrated circuit packages 300, 500, 600, according to various examples of the present disclosure. For example, a mobile phone device 1002, a laptop computer device 1004, and a fixed location terminal device 1006 may each be generally considered user equipment (UE) and may include an apparatus 1000 incorporating an IC package 300, 500, 600 as described herein. The devices 1002, 1004, 1006 illustrated in FIG. 10 are examples only. Other electronic devices may also include IC packages 300, 500, 600, including, but not limited to, mobile devices, handheld personal communications system (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communications devices, smartphones, tablet computers, computers, wearable devices, servers, routers, electronic devices implemented in automotive vehicles, Internet of Things (IoT) devices, or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0077] The devices and functions disclosed above may be designed and configured into computer files (e.g., RTL, GDSII, GERBER, etc.) stored on a computer-readable medium. Some or all of such files may be provided to a fabricator who fabricates devices based on such files. The resulting product may include a semiconductor wafer that is then cut into semiconductor dies and packaged as described herein.

[0078] The following provides a summary of an embodiment of the present disclosure.

[0079] Example 1: An integrated circuit (IC) package comprising a substrate, a flip chip (FC) die disposed on the substrate, a wire bond die disposed above the FC die, wire bonds connected to the wire bond die, and a mold on the substrate that encapsulates the FC die, the wire bond die, and the wire bonds, wherein the substrate comprises one or more metallization layers including a first metallization layer, the first metallization layer comprising a first substrate layer, traces formed on the first substrate layer and routed within the first metallization layer to electrically couple with one or more FC interconnects of the FC die, and bond finger pads formed on the traces, the bond finger pads being substantially circular in shape, and the wire bonds electrically connecting to the bond finger pads so that the wire bond die is electrically coupled to the FC die through the wire bonds, bond finger pads, and traces.

[0080] Example 2: The IC package of Example 1, wherein the first metallization layer further comprises a solder mask formed in contact with the traces and the first substrate layer, and the bond finger pads are formed within solder mask openings (SMOs) that define areas above the first substrate layer that are not covered by the solder mask.

[0081] Example 3: The IC package of Example 2 with no gap between the bond finger pads and the solder mask.

[0082] Example 4: The IC package of any of Examples 1-3, wherein the traces extend from the bond finger pads within the first metallization layer to the edges of the substrate.

[0083] Example 5: The IC package of any of Examples 1 to 3, wherein the trace is a first layer 1 trace, the first metallization layer further comprising a second layer 1 trace formed in contact with the first substrate layer and routed within the first metallization layer, the second layer 1 trace being electrically coupled to the first layer 1 trace and extending within the first metallization layer from inside the substrate to the edge of the substrate.

[0084] Example 6: The IC package of Example 5, wherein the first metallization layer further comprises a first layer 1 via formed through the first substrate layer from the first layer 1 trace to a lower surface of the first metallization layer and a second layer 1 via formed through the first substrate layer from the second layer 1 trace to a lower surface of the first metallization layer, the substrate further comprising a second metallization layer below the first metallization layer, the second metallization layer comprising a second substrate layer and a layer 2 trace, the layer 2 trace formed on the second substrate layer and routed within the second metallization layer to electrically couple with the first layer 1 via and the second layer 1 via, such that the second layer 1 trace and the bond finger pad are electrically coupled through, in order, the first layer 1 trace, the first layer 1 via, the layer 2 trace, and the second layer 1 via.

[0085] Example 7: The IC package of any of Examples 1 to 3, wherein the trace is a layer 1 trace, and the substrate further comprises an additional metallization layer below the first metallization layer, the additional metallization layer comprising an additional substrate layer and an additional trace formed in contact with the additional substrate layer and routed within the additional metallization layer, the additional trace being electrically coupled to the layer 1 trace and extending within the additional metallization layer from within the substrate to an edge of the substrate.

[0086] Example 8: The IC package of Example 7, wherein the additional metallization layer is a third metallization layer, the additional substrate layer is a third substrate layer, the additional trace is a layer 3 trace, the substrate further comprises a second metallization layer between the first metallization layer and the third metallization layer, the first metallization layer further comprises a layer 1 via formed through the first substrate layer from the layer 1 trace to a lower surface of the first metallization layer, the second metallization layer comprises a second substrate layer, a layer 2 trace formed on the second substrate layer and routed within the second metallization layer, and a layer 2 via formed through the second substrate layer from the layer 2 trace to a lower surface of the second metallization layer, and the bond finger pad is electrically coupled to the layer 3 trace through, in order, the layer 1 trace, the layer 1 via, the layer 2 trace, and the layer 2 via.

[0087] Example 9: The IC package of any of Examples 1 to 8, wherein the die-to-pad distance is less than the edge-to-pad distance, the die-to-pad distance being the distance from the wirebond die to the bond finger pad, and the edge-to-pad distance being the distance from the edge of the substrate to the bond finger pad.

[0088] Example 10: The IC package of any of Examples 1 to 9, wherein the IC package comprises a plurality of wirebond dies above the FC die, each of the plurality of wirebond dies being electrically coupled to the FC die through a corresponding wirebond and bond finger pad.

[0089] Example 11: The IC package of any of Examples 1 to 10, wherein the traces are formed from copper (Cu) or aluminum (Al).

[0090] Example 12: The IC package of any of Examples 1 to 11, wherein the bond finger pads are plated metal.

[0091] Example 13: The IC package of Example 12, wherein the plated metal comprises plated nickel or gold or both.

[0092] Example 14: The IC package of any of Examples 1 to 13, wherein the wirebond is a reverse wirebond such that one end is ball bonded to the bond finger pad and the other end is stitch bonded to the wirebond die.

[0093] Example 15: The IC package of any of Examples 1 to 14, wherein the FC die is a baseband modem die.

[0094] Example 16: The IC package of any of Examples 1 to 15, wherein the wire-bond die is a memory die.

[0095] Example 17: The IC package of any of Examples 1 to 16, wherein the IC package is incorporated into a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, and a device in an automotive vehicle.

[0096] Example 18: A method for fabricating an integrated circuit (IC) package, comprising the steps of forming a substrate, disposing a flip chip (FC) die on the substrate, disposing a wire bond die above the FC die, forming wire bonds connected to the wire bond die, and forming a mold on the substrate, wherein the mold encapsulates the FC die, the wire bond die, and the wire bonds, and the substrate is formed to have one or more metallization layers including a first metallization layer, the first metallization layer comprising a first substrate layer, traces formed on the first substrate layer and routed within the first metallization layer to electrically couple with one or more FC interconnects of the FC die, and bond finger pads formed on the traces, the bond finger pads being substantially circular in shape, and the wire bonds being formed to electrically connect to the bond finger pads so that the wire bond die is electrically coupled to the FC die through the wire bonds, bond finger pads, and traces.

[0097] Example 19: The method of Example 18, wherein the substrate is formed such that the first metallization layer further comprises a solder mask formed in contact with the traces and the first substrate layer, and the bond finger pads are formed in solder mask openings (SMOs) that define areas above the first substrate layer that are not covered by the solder mask.

[0098] Example 20: The method of Example 19, wherein there is no gap between the bond finger pad and the solder mask.

[0099] Example 21: The method of any of Examples 18-20, wherein the substrate is formed such that traces extend from the bond finger pads within the first metallization layer to an edge of the substrate.

[0100] Example 22: The method of any of Examples 18 to 20, wherein the trace is a first layer 1 trace, and the substrate is formed such that the first metallization layer further comprises a second layer 1 trace formed in contact with the first substrate layer and routed within the first metallization layer, the second layer 1 trace being electrically coupled to the first layer 1 trace and extending within the first metallization layer from within the substrate to an edge of the substrate.

[0101] Example 23: The method of Example 22, wherein the substrate is formed so that the first metallization layer further comprises a first layer 1 via formed through the first substrate layer from the first layer 1 trace to a lower surface of the first metallization layer and a second layer 1 via formed through the first substrate layer from the second layer 1 trace to a lower surface of the first metallization layer, and the substrate is formed so that the substrate further comprises a second metallization layer below the first metallization layer, the second metallization layer comprising the second substrate layer and a layer 2 trace, the layer 2 trace being formed on the second substrate layer and routed within the second metallization layer to electrically couple with the first layer 1 via and the second layer 1 via, such that the second layer 1 trace and the bond finger pad are electrically coupled through, in order, the first layer 1 trace, the first layer 1 via, the layer 2 trace, and the second layer 1 via.

[0102] Example 24: The method of any of Examples 18 to 20, wherein the trace is a layer 1 trace, and the substrate is formed to further include an additional metallization layer below the first metallization layer, the additional metallization layer including an additional substrate layer and an additional trace formed in contact with the additional substrate layer and routed within the additional metallization layer, the additional trace being electrically coupled to the layer 1 trace and extending within the additional metallization layer from within the substrate to an edge of the substrate.

[0103] Example 25: The method of Example 24, wherein the additional metallization layer is a third metallization layer, the additional substrate layer is a third substrate layer, the additional trace is a layer 3 trace, the substrate is formed further comprising a second metallization layer between the first metallization layer and the third metallization layer, the substrate is formed such that the first metallization layer further comprises a layer 1 via formed through the first substrate layer from the layer 1 trace to a lower surface of the first metallization layer, the second metallization layer is formed such that the second substrate layer comprises a second substrate layer, a layer 2 trace formed on the second substrate layer and routed within the second metallization layer, and a layer 2 via formed through the second substrate layer from the layer 2 trace to a lower surface of the second metallization layer, and the bond finger pad is formed to electrically couple to the layer 3 trace through, in order, the layer 1 trace, the layer 1 via, the layer 2 trace, and the layer 2 via.

[0104] Example 26: The method of any of Examples 18 to 25, wherein the die-to-pad distance is less than the edge-to-pad distance, the die-to-pad distance being the distance from the wirebond die to the bond finger pad, and the edge-to-pad distance being the distance from the edge of the substrate to the bond finger pad.

[0105] Example 27: The method of any of Examples 18 to 26, wherein a plurality of wirebond dies are formed above the FC die, and each of the plurality of wirebond dies is electrically coupled to the FC die through a corresponding wirebond and bond finger pad.

[0106] Example 28: The method of any of Examples 18 to 27, wherein the wire bond is formed as a reverse wire bond such that one end is ball bonded to the bond finger pad and the other end is stitch bonded to the wire bond die.

[0107] As used herein, terms such as “user equipment” (or “UE”), “user device,” “user terminal,” “client device,” “communication device,” “wireless device,” “wireless communication device,” “handheld device,” “mobile device,” “mobile terminal,” “mobile station,” “handset,” “access terminal,” “subscriber device,” “subscriber terminal,” “subscriber station,” “terminal,” and the like may interchangeably refer to any suitable mobile or fixed device capable of receiving wireless communication and / or navigation signals. These terms include, but are not limited to, music players, video players, entertainment units, navigation devices, communication devices, smartphones, personal digital assistants, fixed location terminals, tablet computers, computers, wearable devices, laptop computers, servers, automotive devices in automotive vehicles, and / or other types of portable electronic devices that are typically carried by a person and / or have communication capabilities (e.g., wireless, cellular, infrared, short-range radio, etc.). These terms are also intended to include a device that communicates with another device that can receive wireless communication and / or navigation signals via a short-range wireless connection, an infrared connection, a wired connection, or other connection, etc., regardless of whether the satellite signal reception, assistance data reception, and / or location-related processing occurs on that device or on another device. Furthermore, these terms are intended to include all devices, including wireless and wired communication devices, that can communicate with a core network via a radio access network (RAN) through which the UE can connect to external networks such as the Internet and to other UEs. Of course, other mechanisms for connecting to a core network and / or the Internet are also possible for a UE, such as via a wired access network, a wireless local area network (WLAN) (e.g., based on IEEE 802.11, etc.), etc.A UE may be embodied by any of several types of devices, including, but not limited to, a printed circuit (PC) card, a compact flash device, an external or internal modem, a wireless or wired phone, a smartphone, a tablet, a tracking device, an asset tag, etc. A communication link through which a UE can transmit signals to a RAN is called an uplink channel (e.g., a reverse traffic channel, a reverse control channel, an access channel, etc.). A communication link through which a RAN can transmit signals to a UE is called a downlink channel or a forward link channel (e.g., a paging channel, a control channel, a broadcast channel, a forward traffic channel, etc.). As used herein, the term traffic channel (TCH) can refer to either an uplink / reverse traffic channel or a downlink / forward traffic channel.

[0108] Wireless communication between electronic devices may be based on various technologies, such as code division multiple access (CDMA), W-CDMA, time division multiple access (TDMA), frequency division multiple access (FDMA), orthogonal frequency division multiplexing (OFDM), Global System for Mobile Communications (GSM), 3GPP® Long Term Evolution (LTE), 5G New Radio, Bluetooth (BT), Bluetooth Low Energy (BLE), IEEE 802.11 (WiFi), and IEEE 802.15.4 (Zigbee / Thread), or other protocols that may be used within wireless or data communication networks. Bluetooth Low Energy (also known as Bluetooth LE, BLE, and Bluetooth Smart) is a wireless personal area network technology designed and marketed by the Bluetooth Special Interest Group that aims to significantly reduce power consumption and cost while maintaining a similar communication range. BLE was integrated into the main Bluetooth standard in 2010 by adopting Bluetooth Core Specification Version 4.0 and updated in Bluetooth 5.

[0109] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any detail described herein as "exemplary" should not be construed as advantageous over other examples. Likewise, the term "example" does not imply that all examples include the described feature, advantage or mode of operation. Furthermore, particular features and / or structures may be combined with one or more other features and / or structures. Moreover, at least a portion of the apparatuses described herein may be configured to perform at least a portion of the methods described herein.

[0110] It should be noted that the terms "connected" and "coupled," or any variation thereof, mean any direct or indirect connection or coupling between elements unless the connection is expressly disclosed as being directly connected, and may encompass the presence of intermediate elements between two elements that are "connected" or "coupled" together through intermediary elements.

[0111] Any reference herein to an element using a designation such as "first," "second," etc. is not intended to limit the quantity and / or order of those elements. Rather, these designations are used as a convenient method of distinguishing between two or more elements and / or instances of an element. Also, unless otherwise stated, a set of elements can comprise one or more elements.

[0112] Those skilled in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, the data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0113] Nothing described, illustrated, or shown in this application is intended to publicly disclose any element, act, feature, benefit, advantage, or equivalent, whether or not that element, act, feature, benefit, advantage, or equivalent is claimed.

[0114] In the above detailed description, it will be seen that various features are grouped together in the examples. This method of disclosure should not be interpreted as a claimed example having more features than are expressly recited in each claim. Rather, the present disclosure may include fewer features than all of the individual disclosed examples. Accordingly, the following claims are hereby considered incorporated into this description, with each claim standing alone as a separate example. While each claim may stand alone as a separate example, it should be noted that a dependent claim may refer to a specific combination with one or more claims within its scope, while other examples may encompass or include a combination of the dependent claim with the subject matter of any other dependent claim, or a combination of any feature with other dependent and independent claims. Such combinations are suggested herein unless it is expressly stated that a specific combination is not intended. Furthermore, it is also intended that features of a claim may be included in any other independent claim, even if that claim is not directly dependent on that independent claim.

[0115] It is further noted that the methods, systems, and apparatuses disclosed in this description or claims may be implemented by a device comprising means for performing each act and / or function of the disclosed method.

[0116] Furthermore, in some examples, an individual act may be subdivided into or include one or more sub-acts, and such sub-acts may be included in and become part of the disclosure of the individual act.

[0117] While the above disclosure illustrates examples of the present disclosure, it should be noted that various modifications and variations can be made herein without departing from the scope of the present disclosure, as defined by the appended claims. The functions and / or actions of the method claims according to the examples of the present disclosure described herein need not be performed in any particular order. Additionally, well-known elements may not be described in detail or may be omitted so as not to obscure the relevant details of the aspects and examples disclosed herein. Furthermore, although elements of the present disclosure may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated. [Explanation of symbols]

[0118] 100 Conventional IC package 110 Baseband Modem 115 Solder Bumps 120 memory dies 130 Die Adhesive 140 Mold 150 Bond Finger Pads 160 Wirebond 165 solder balls 170 first substrate layer 172 Trace 178 Solder Resist 180 Second substrate layer 190 Third substrate layer 300 IC packages 310 FC die 315 FC Interconnect 320 Wirebond Die 330 Die Adhesive 340 Mold 350 Bond Finger Pad 360 Wirebond 365 External Interconnect 370 first substrate layer 372 Trace 378 Solder Mask 380 Second substrate layer 390 Third Substrate Layer 500 IC packages 510 FC die 515 FC Interconnect 520 Wirebond Die 530 Die Adhesive 540 Mold 550 Bond Finger Pad 560 Wirebond 565 External Interconnect 570 First substrate layer 572 Trace 574 Layer 1 vias 578 Solder Mask 580 Second substrate layer 582 Trace 590 Third Substrate Layer 600 IC packages 610 FC die 615 FC Interconnect 620 Wirebond Die 630 Die Adhesive 640 Mold 650 Bond Finger Pad 660 Wirebond 665 External Interconnect 670 First substrate layer 672 Layer 1 Traces 674 Layer 1 vias 678 Solder Mask 680 Second substrate layer 682 Layer 2 Traces 684 Layer 2 Vias 690 Third Substrate Layer 692 Layer 3 Traces 1000 devices 1002 mobile phone devices 1004 laptop computer device 1006 Fixed Location Terminal Device

Claims

1. 1. An integrated circuit (IC) package comprising: A substrate; a flip chip (FC) die disposed on the substrate; a wire bond die disposed above the FC die; a wire bond connected to the wire bond die; a mold in contact with the substrate and encapsulating the FC die, the wire bond die, and the wire bonds; The substrate comprises one or more metallization layers, including a first metallization layer, the first metallization layer comprising: a first substrate layer; traces formed on the first substrate layer and routed within the first metallization layer to electrically couple to one or more FC interconnects of the FC die; a bond finger pad formed adjacent to the trace, the bond finger pad being substantially circular in shape; Equipped with the wirebonds electrically connect to the bond finger pads such that the wirebond die is electrically coupled to the FC die through the wirebonds, the bond finger pads, and the traces; the first metallization layer further comprising: a solder mask formed on the traces and the first substrate layer; The IC package, wherein the bond finger pads are solder mask defined (SMD) pads formed within solder mask openings (SMO) that define areas above the first substrate layer that are not covered by the solder mask.

2. 2. The IC package of claim 1, wherein there are no gaps between said bond finger pads and said solder mask.

3. 2. The IC package of claim 1, wherein the traces extend from the bond finger pads within the first metallization layer to an edge of the substrate.

4. the trace is a first layer 1 trace; the first metallization layer further comprising: a second layer 1 trace formed on the first substrate layer and routed within the first metallization layer, the second layer 1 trace electrically coupled to the first layer 1 trace and extending within the first metallization layer from within the substrate to an edge of the substrate; a first layer 1 via formed through the first substrate layer from the first layer 1 trace to a lower surface of the first metallization layer; a second layer 1 via formed through the first substrate layer from the second layer 1 trace to the bottom surface of the first metallization layer; Equipped with The substrate further comprises a second metallization layer below the first metallization layer, the second metallization layer comprising: a second substrate layer; and 2. The IC package of claim 1, further comprising: a layer 2 trace formed on the second substrate layer and routed within the second metallization layer to electrically couple to the first layer 1 via and the second layer 1 via, such that the second layer 1 trace and the bond finger pad are electrically coupled through, in order, the first layer 1 trace, the first layer 1 via, the layer 2 trace, and the second layer 1 via.

5. the trace is a layer 1 trace; The substrate further comprises an additional metallization layer below the first metallization layer, the additional metallization layer comprising: an additional substrate layer; an additional trace formed on the additional substrate layer and routed within the additional metallization layer, the additional trace electrically coupled to the layer 1 trace and extending within the additional metallization layer from within the substrate to an edge of the substrate; the additional metallization layer is a third metallization layer, the additional substrate layer is a third substrate layer, and the additional trace is a layer 3 trace; the substrate further comprising a second metallization layer between the first metallization layer and the third metallization layer; the first metallization layer further comprising: a layer 1 via formed through the first substrate layer from the layer 1 trace to a lower surface of the first metallization layer; the second metallization layer comprising: a second substrate layer; and Layer 2 traces formed on the second substrate layer and routed within the second metallization layer; a layer 2 via formed through the second substrate layer from the layer 2 trace to the underside of the second metallization layer; Equipped with 2. The IC package of claim 1, wherein said bond finger pad is electrically coupled to said layer 3 trace through, in order, said layer 1 trace, said layer 1 via, said layer 2 trace, and said layer 2 via.

6. 2. The IC package of claim 1, wherein a die-to-pad distance is less than an edge-to-pad distance, the die-to-pad distance being the distance from the wirebond die to the bond finger pad, and the edge-to-pad distance being the distance from the edge of the substrate to the bond finger pad.

7. 2. The IC package of claim 1, wherein the IC package comprises a plurality of wirebond dies above the FC die, each of the plurality of wirebond dies being electrically coupled to the FC die through a corresponding wirebond and bond finger pad.

8. 2. The IC package of claim 1, wherein the traces are formed from copper (Cu) or aluminum (Al).

9. the bond finger pads are plated metal; 10. The IC package of claim 1, wherein the plated metal comprises plated nickel or gold or both.

10. 2. The IC package of claim 1, wherein the wirebonds are reverse wirebonds such that one end is ball bonded to the bond finger pad and the other end is stitch bonded to the wirebond die.

11. the FC die is a baseband modem die; 10. The IC package of claim 1, wherein the wirebond die is a memory die.

12. 10. The IC package of claim 1, wherein the IC package is incorporated into a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, and a device in an automotive vehicle.

13. 1. A method of fabricating an integrated circuit (IC) package, comprising: forming a substrate; disposing a flip chip (FC) die on the substrate; disposing a wirebond die above the FC die; forming a wire bond connected to the wire bond die; forming a mold in contact with the substrate, the mold encapsulating the FC die, the wirebond die, and the wirebonds; The substrate is formed with one or more metallization layers, including a first metallization layer, the first metallization layer comprising: a first substrate layer; traces formed on the first substrate layer and routed within the first metallization layer to electrically couple to one or more FC interconnects of the FC die; a bond finger pad formed adjacent to the trace, the bond finger pad being substantially circular in shape; Equipped with the wirebonds are formed to electrically connect to the bond finger pads such that the wirebond die is electrically coupled to the FC die through the wirebonds, the bond finger pads, and the traces; the first metallization layer further comprising: the substrate is formed with a solder mask formed on the traces and the first substrate layer; The method, wherein the bond finger pads are solder mask defined (SMD) pads formed within solder mask openings (SMO) that define areas above the first substrate layer that are not covered by the solder mask.

14. the trace is a first layer 1 trace; the first metallization layer further comprising: a second layer 1 trace formed on the first substrate layer and routed within the first metallization layer, the second layer 1 trace electrically coupled to the first layer 1 trace and extending within the first metallization layer from within the substrate to an edge of the substrate; a first layer 1 via formed through the first substrate layer from the first layer 1 trace to a lower surface of the first metallization layer; a second layer 1 via formed through the first substrate layer from the second layer 1 trace to the bottom surface of the first metallization layer; Equipped with The substrate is formed to further include a second metallization layer below the first metallization layer, the second metallization layer comprising: a second substrate layer; and 14. The method of claim 13, further comprising: a layer 2 trace formed on the second substrate layer and routed within the second metallization layer to electrically couple to the first layer 1 via and the second layer 1 via, such that the second layer 1 trace and the bond finger pad are electrically coupled through, in order, the first layer 1 trace, the first layer 1 via, the layer 2 trace, and the second layer 1 via.

15. the trace is a layer 1 trace; The substrate is formed to further include an additional metallization layer below the first metallization layer, the additional metallization layer comprising: an additional substrate layer; an additional trace formed on the additional substrate layer and routed within the additional metallization layer, the additional trace electrically coupled to the layer 1 trace and extending within the additional metallization layer from within the substrate to an edge of the substrate; the additional metallization layer is a third metallization layer, the additional substrate layer is a third substrate layer, and the additional trace is a layer 3 trace; the substrate is formed to further include a second metallization layer between the first metallization layer and the third metallization layer; the first metallization layer further comprising: a layer 1 via formed through the first substrate layer from the layer 1 trace to the underside of the first metallization layer; the substrate is formed to comprise the second metallization layer comprising: a second substrate layer; and Layer 2 traces formed on the second substrate layer and routed within the second metallization layer; a layer 2 via formed through the second substrate layer from the layer 2 trace to the underside of the second metallization layer; the substrate is formed to comprise 14. The method of claim 13, wherein the bond finger pad is formed to electrically couple to the layer 3 trace through, in order, the layer 1 trace, the layer 1 via, the layer 2 trace, and the layer 2 via.

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