Semiconductor device and manufacturing method

Abstract

To provide a semiconductor device with a bonded transistor structure that eliminates a factor that inhibits a current flowing through a channel, and a manufacturing method thereof.SOLUTION: A semiconductor device 301 according to the present invention includes a vertical trench structure in which a wide gap semiconductor layer 2 and a silicon semiconductor layer 3 are bonded, and a trench 0 is formed from the silicon semiconductor layer 3 to the wide gap semiconductor layer 2 by penetrating the junction surface between the wide gap semiconductor layer 2 and the silicon semiconductor layer 3, and an insulating film 5 formed on the inner wall of the trench 0 is thicker at the silicon semiconductor layer 3 part by X nm (X is 1 or more and 15 or less) than the film thickness at the wide gap semiconductor layer 2 part.SELECTED DRAWING: Figure 32

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device having a transistor structure in which a silicon (Si) semiconductor and a wide-gap semiconductor such as silicon carbide (SiC) are bonded together, and a method for manufacturing the same. [Background technology]

[0002] A MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) has been disclosed in which a Si semiconductor layer and a wide-gap semiconductor layer are stacked and a trench gate is formed (see, for example, Patent Documents 1 and 2 and Non-Patent Document 1). Wide-gap semiconductors include gallium oxide, gallium nitride, zinc oxide, and the like, in addition to silicon carbide. In the following explanation, silicon carbide will be used as a representative wide-gap semiconductor, but the same applies to other wide-gap semiconductors. Note that a transistor in which a Si layer and a SiC layer are stacked and a trench gate is formed is sometimes referred to as a "Si / SiC bonded transistor."

[0003] 1 to 4 are diagrams illustrating the manufacturing process of such a MOSFET. n + a p-type SiC semiconductor layer 3; an n-type SiC semiconductor layer 1; an n-type SiC semiconductor layer 2 having a lower impurity concentration than that of the n-type SiC semiconductor layer 1; + A silicon semiconductor layer 4 is laminated in this order (Fig. 1). A trench 0 is formed from the semiconductor layer 4 side to the semiconductor layer 2 (Fig. 2). A gate insulating film 5 is formed on the wall surface of the trench 0 (Fig. 3). A gate electrode 6 is formed in the trench with the gate insulating film 5 formed on it. A drain electrode 7 is formed on the surface of the semiconductor layer 1, and a source electrode 8 is formed on the surface of the semiconductor layer 4, to create a high-voltage field-effect transistor (Fig. 4). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-153893 [Patent Document 2] International Publication WO2019 / 239632 Brochure [Non-patent literature]

[0005] [Non-Patent Document 1] Baoxing Duan et.al, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 65, NO. 8, AUGUST 2018 Summary of the Invention [Problem to be solved by the invention]

[0006] To achieve the structure shown in Figure 4, after trench etching, a gate insulating film 5 is formed on the wall surface of trench 0 by thermal oxidation (155 minutes in an oxygen atmosphere at 1100°C). Figure 5 shows the results of a process simulation that explains the thickness of gate insulating film 5 due to this thermal oxidation. The results show that a step of about 35 nm is formed between the interface between SiC semiconductor layer 2 and insulating film 5 and the interface between Si semiconductor layer 3 and insulating film 5.

[0007] 6 shows the results of a device simulation that explains the current distribution due to the step. The results show that the current distribution changes at the interface between the Si semiconductor layer 3 and the SiC semiconductor layer 2, and the current (drain current in the case of a MOSFET) flowing through the channel (Si semiconductor layer 3) is blocked.

[0008] 5, if the thickness of the insulating film 5 on the Si semiconductor layer 3 side is greater than the thickness of the insulating film 5 on the SiC semiconductor layer 2, the threshold voltage will increase. This phenomenon also becomes a factor that inhibits the current flowing through the channel.

[0009] As mentioned above, a bonded transistor in which a Si semiconductor layer and a wide-gap semiconductor layer are stacked and a trench gate is formed has the problem that there is a factor that inhibits the current flowing through the channel. Therefore, in order to solve the first problem, an object of the present invention is to provide a semiconductor device with a bonded transistor structure that eliminates factors that hinder current flowing through the channel, and a method for manufacturing the same. [Means for solving the problem]

[0010] In order to achieve the above object, the semiconductor device according to the present invention controls the size of the step between the wide-gap semiconductor layer and the Si semiconductor layer formed on the trench wall surface in a process after trench formation.

[0011] Specifically, the semiconductor device according to the present invention is a semiconductor device having a vertical trench structure in which a wide gap semiconductor layer and a silicon semiconductor layer are bonded together, and a trench is formed from the silicon semiconductor layer through a junction surface between the wide gap semiconductor layer and the silicon semiconductor layer to reach the wide gap semiconductor layer, The insulating film formed on the inner wall of the trench is characterized in that the film thickness of the silicon semiconductor layer portion is X nm (X is 1 to 15) thicker than the film thickness of the wide gap semiconductor layer portion.

[0012] A manufacturing method according to the present invention is a method for manufacturing a semiconductor device having a vertical trench structure, comprising the steps of: bonding a wide-gap semiconductor layer to a silicon semiconductor layer; forming a trench extending from the silicon semiconductor layer through a junction surface between the wide gap semiconductor layer and the silicon semiconductor layer to the wide gap semiconductor layer; removing a damaged layer on the inner wall of the trench caused by the formation of the trench so that the surface of the silicon semiconductor layer is recessed by X nm (X is 1 or more and 15 or less) from the surface of the wide-gap semiconductor layer on the inner wall of the trench; and forming an insulating film of a desired thickness on the inner wall of the trench by chemical vapor deposition; Do the following.

[0013] By setting the step between the wide-gap semiconductor layer and the Si semiconductor layer formed on the trench wall surface to X nm, the current flowing through the channel can be increased compared to a structure in which the step is zero. Therefore, the present invention can provide a semiconductor device with a bonded transistor structure that eliminates factors that inhibit the current flowing through the channel, and a manufacturing method thereof.

[0014] When trenches in a bonded transistor are formed by dry etching, the walls of the trench become rough, increasing the interface state density at the interface between the insulating film and each semiconductor layer. Figure 7 shows the results of a simulation that explains the relationship between the interface state density at the interface between the oxide film and SiC semiconductor and the breakdown voltage (drain voltage). The results show that the interface state density at the interface between the oxide film and SiC semiconductor is 2 x 10 12 cm -2 It can be seen that when the temperature exceeds this value, the breakdown voltage drops drastically.

[0015] Therefore, in order to maintain the breakdown voltage of the bonded transistor at a desired value (for example, 600 V), when removing the damaged layer, After forming the insulating film, The interface state density at the interface between the silicon semiconductor layer and the insulating film is 1×10 11 cm -2 below, The interface state density at the interface between the wide-gap semiconductor layer and the insulating film is 2×10 12 cm -2 The following, and a difference between the interface state density at the interface between the silicon semiconductor layer and the insulating film and the interface state density at the interface between the wide gap semiconductor layer and the insulating film of 1.9×10 12 cm -2 The damaged layer is removed so as to:

[0016] Here, it is preferable to remove the damaged layer by sacrificial oxidation and oxide film removal, or wet etching, which allows adjustment of the step height and interface state density by the processing time.

[0017] For example, the semiconductor device is a field effect transistor in which the wide gap semiconductor layer side serves as a drain, the silicon semiconductor layer side serves as a source, and polycrystalline silicon filled in the trench via the insulating film serves as a gate.

[0018] For example, the semiconductor device is an insulated gate bipolar transistor having the wide-gap semiconductor layer side as a collector, the silicon semiconductor layer side as an emitter, and polycrystalline silicon filled in the trench via the insulating film as a gate.

[0019] The above inventions can be combined as much as possible. [Effects of the Invention]

[0020] The present invention can provide a semiconductor device with a laminated transistor structure that eliminates factors that inhibit current flowing through the channel, and a method for manufacturing the same. [Brief explanation of the drawings]

[0021] [Figure 1] 1A to 1C are diagrams illustrating the manufacturing process of a MOSFET. [Figure 2] 1A to 1C are diagrams illustrating the manufacturing process of a MOSFET. [Figure 3] 1A to 1C are diagrams illustrating the manufacturing process of a MOSFET. [Figure 4] 1A to 1C are diagrams illustrating the manufacturing process of a MOSFET. [Figure 5] 10 is a cross-sectional view showing the results of a process simulation illustrating the thickness of a gate insulating film due to thermal oxidation. [Figure 6] This is the result of a device simulation that explains the current distribution due to the step formed at the interface between the Si semiconductor layer and the SiC semiconductor layer. [Figure 7] 10 shows the results of a simulation that explains the relationship between the interface state density at the interface between an oxide film and a SiC semiconductor and the drain voltage. [Figure 8]10 shows the results of a device simulation illustrating IDVG characteristics in vertical trench MOS devices having a structure of a comparative example (film thickness difference: 0 nm) and a structure of the present invention (film thickness difference: 3 nm). [Figure 9] FIG. 10 is a diagram illustrating the relationship between the film thickness difference and the drain current value (VD=1V, VG=15V) of a vertical trench MOS structure. [Figure 10] 10 is a device simulation result illustrating the drain current density distribution in the structure of the comparative example. [Figure 11] 10 is a device simulation result illustrating the drain current density distribution in the structure of the present invention. [Figure 12] FIG. 2 is a diagram illustrating a band diagram at the interface between a SiC semiconductor layer and an insulating film (comparative example). [Figure 13] FIG. 2 is a diagram illustrating a band diagram at the interface between a SiC semiconductor layer and an insulating film (comparative example). [Figure 14] FIG. 2 is a diagram illustrating a band diagram at the interface between a SiC semiconductor layer and an insulating film (comparative example). [Figure 15] FIG. 2 is a diagram illustrating a band diagram at the interface between a SiC semiconductor layer and an insulating film in the present invention. [Figure 16] FIG. 2 is a diagram illustrating a band diagram at the interface between a SiC semiconductor layer and an insulating film in the present invention. [Figure 17] FIG. 2 is a diagram illustrating a band diagram at the interface between a SiC semiconductor layer and an insulating film in the present invention. [Figure 18] FIG. 10 is a diagram illustrating the potential distribution in a vertical trench MOS structure of the comparative example (IDVG characteristics VD=1V, VG=15V). [Figure 19] FIG. 1 is a diagram illustrating the potential distribution in a vertical trench MOS structure according to the present invention (IDVG characteristics VD=1V, VG=15V). [Figure 20] FIG. 10 is a diagram illustrating the electric field strength distribution of a vertical trench MOS structure of a comparative example (IDVG characteristics VD=1V, VG=15V). [Figure 21] FIG. 1 is a diagram illustrating the electric field strength distribution of a vertical trench MOS structure according to the present invention (IDVG characteristics VD=1V, VG=15V). [Figure 22] FIG. 10 is a schematic diagram showing a model of the on-resistance component of a vertical trench MOS structure of a comparative example. [Figure 23] 1 is a schematic diagram showing a model of the on-resistance component of a vertical trench MOS structure according to the present invention. FIG. [Figure 24] 1A to 1C are diagrams illustrating a substrate forming step in the manufacturing method of a semiconductor device according to the present invention. [Figure 25] 1A to 1C are diagrams illustrating a trench forming step in the method for manufacturing a semiconductor device according to the present invention. [Figure 26] 1A to 1C are diagrams illustrating a sacrificial oxidation step in the manufacturing method of a semiconductor device according to the present invention. [Figure 27] 1A to 1C are diagrams illustrating a reoxidation step in the method for manufacturing a semiconductor device according to the present invention. [Figure 28] 1A to 1C are diagrams illustrating a gate insulating film forming step in the manufacturing method of a semiconductor device according to the present invention. [Figure 29] 1A to 1C are diagrams illustrating a gate electrode forming step in the manufacturing method of a semiconductor device according to the present invention. [Figure 30] 3A to 3C are diagrams illustrating a well layer, a source layer, and a body layer forming step in the method for manufacturing a semiconductor device according to the present invention. [Figure 31] 1A to 1C are diagrams illustrating a gate electrode wiring layer and a source electrode / body electrode wiring layer forming step in a method for manufacturing a semiconductor device according to the present invention. [Figure 32] 1A to 1C are diagrams illustrating a drain electrode wiring layer forming step in the manufacturing method of a semiconductor device according to the present invention. [Figure 33] 1A to 1C are diagrams illustrating a substrate forming step in the manufacturing method of a semiconductor device according to the present invention. [Figure 34] 3A to 3C are diagrams illustrating a base layer, an emitter layer, and a p-base layer forming step in the method for manufacturing a semiconductor device according to the present invention. [Figure 35] 1A to 1C are diagrams illustrating a gate electrode wiring layer and an emitter electrode / base electrode wiring layer forming step in a method for manufacturing a semiconductor device according to the present invention. [Figure 36]1A to 1C are diagrams illustrating a collector electrode wiring layer forming step in the method for manufacturing a semiconductor device according to the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0022] The following description of the preferred embodiments of the present invention will be given with reference to the accompanying drawings. The preferred embodiments described below are examples of the present invention, and the present invention is not limited to the preferred embodiments. In this specification and the drawings, components having the same reference numerals are intended to represent the same components.

[0023] [Embodiment 1] FIG. 32 is a diagram illustrating a semiconductor device 301 according to this embodiment. The semiconductor device 301 includes: a vertical trench structure in which a wide-gap semiconductor layer 2 and a silicon semiconductor layer 3 are bonded together, and a trench 0 is formed from the silicon semiconductor layer 3 through a junction surface between the wide-gap semiconductor layer 2 and the silicon semiconductor layer 3 to reach the wide-gap semiconductor layer 2; The insulating film 5 formed on the inner wall of the trench 0 is characterized in that the thickness of the silicon semiconductor layer 3 portion is thicker than the thickness of the wide gap semiconductor layer 2 portion by X nm (X is 1 to 15).

[0024] More specifically, the semiconductor device 301 includes a first conductivity type (n-type in FIG. 32) SiC semiconductor layer 1, a first conductivity type (n-type in FIG. 32) SiC semiconductor layer 2 having a lower impurity concentration than the first conductivity type (n-type in FIG. 32), a substrate of a second conductivity type (p-type in FIG. 32) Si semiconductor layer 3, a well layer 9, a source layer 10, a body layer 11, a gate insulating film 5, and a gate electrode 6. In the semiconductor device 301, the difference in thickness between the insulating film 5 in the channel (SiC semiconductor layer 2) portion and the insulating film 5 in the drift (Si semiconductor layer 3) portion on the inner wall of the trench 0 is set to 1 to 15 nm. The insulating film 5 is, for example, an oxide film.

[0025] Furthermore, the semiconductor device 301 reduces the interface state density at the interface between the insulating film 5 and the SiC semiconductor layer 2. Specifically, on the inner wall of the trench 0, The interface state density at the interface between the silicon semiconductor layer 3 and the insulating film 5 is 1×1011 cm -2 That is: The interface state density at the interface between the wide-gap semiconductor layer 2 and the insulating film 5 is 2×10 12 cm -2 and The difference between the interface state density at the interface between the silicon semiconductor layer 3 and the insulating film 5 and the interface state density at the interface between the wide-gap semiconductor layer 2 and the insulating film 5 is 1.9×10 12 cm -2 That is: It is characterized by:

[0026] The semiconductor device 301 is a vertical trench field effect transistor in which the wide gap semiconductor layer 2 side is the drain (drain electrode wiring layer 19), the silicon semiconductor layer 3 side is the source (source electrode 18), and polycrystalline silicon filled in the trench 0 via the insulating film 5 is the gate electrode 6 (gate electrode wiring layer 17).

[0027] 24 to 32 are diagrams illustrating a manufacturing method of the semiconductor device 301. The manufacturing method includes the following steps: Bonding the wide-gap semiconductor layer 2 and the silicon semiconductor layer 3 (FIG. 24); forming a trench 0 extending from the silicon semiconductor layer 3 through the junction surface between the wide gap semiconductor layer 2 and the silicon semiconductor layer 3 to the wide gap semiconductor layer 2 (FIG. 25); Removing a damaged layer on the inner wall of the trench 0 caused by the formation of the trench 0 so that the surface of the silicon semiconductor layer 3 is recessed by X nm (X is 1 or more and 15 or less) from the surface of the wide-gap semiconductor layer 2 on the inner wall of the trench 0 (FIGS. 26 to 27); and Forming an insulating film 5 of a desired thickness on the inner wall of the trench 0 by chemical vapor deposition (FIG. 28). Do the following.

[0028] In this embodiment, the wide-gap semiconductor is described as a SiC semiconductor. The conductivity type (n-type / p-type) of each semiconductor layer in this embodiment is an example and can be determined arbitrarily depending on the specifications of the transistor. A first conductivity type (n+ type) SiC semiconductor layer 1, a first conductivity type (n type) SiC semiconductor layer 2 having a lower impurity concentration than the first conductivity type (n type), and a second conductivity type (p type) Si semiconductor layer 3 are laminated in this order (FIG. 24). A trench 0 is formed from the surface of the Si semiconductor layer 3 to a part of the SiC semiconductor layer 2 (FIG. 25).

[0029] During trench formation, etching causes surface roughness (etching roughness) on the inner walls of the trench. This rough surface is called the "damaged layer." The damaged layer is removed by sacrificial oxidation and oxide film removal, or by wet etching using tetramethylammonium hydroxide or the like.

[0030] 26 and 27 are diagrams illustrating a method for removing a damaged layer by sacrificial oxidation and oxide film removal. An oxide film 5a for sacrificial oxidation is formed on the surface of the Si semiconductor layer 3 and the surface of the SiC semiconductor layer 2 on the inner wall of the trench 0 (FIG. 26). This oxidation process causes the interface between the Si semiconductor layer 3 and the oxide film 5a to recede from the interface between the SiC semiconductor layer 2 and the oxide film 5a (toward the positive X-direction in FIG. 26), creating a step. The oxide film 5a is then removed with hydrofluoric acid, thereby removing the damaged layer. The inner wall of the trench 0 from which the damaged layer has been removed is then reoxidized to form an oxide film 5b on the surface of the Si semiconductor layer 3 and the surface of the SiC semiconductor layer 2 (FIG. 27).

[0031] An insulating film (oxide film) is further deposited by chemical vapor deposition (CVD), and recovery annealing is performed to combine it with oxide film 5b to form insulating film 5 (FIG. 28). Note that FIGS. 26 to 28 are the results of a process simulation.

[0032] Polycrystalline silicon containing n-type impurities is deposited by chemical vapor deposition (CVD) into the trench 0 with the insulating film 5 formed therein to form the gate electrode 6 (Figure 29). A p-type impurity layer that will become the well layer 9 is formed by photolithography and ion implantation techniques. An n+ type impurity layer that will become the source layer 10 is formed by photolithography and ion implantation techniques. A p+ type impurity layer that will become the body layer 11 is formed by photolithography and ion implantation techniques. Activation is performed by annealing (Figure 30).

[0033] An interlayer insulating film 31 is deposited on the surface of the Si semiconductor layer 3 (on the well layer 9 and the source layer 10). Contact holes are opened in the interlayer insulating film 31, and a gate electrode wiring layer 17 and a source electrode / body electrode wiring layer 18 are formed by sputtering or the like (FIG. 31). A drain electrode wiring layer 19 is formed on the surface of the SiC semiconductor layer 1, completing a vertical trench MOS transistor (FIG. 32).

[0034] [Embodiment 2] 36 is a diagram illustrating a semiconductor device 302 of this embodiment. The semiconductor device 302 also has the vertical trench structure described in embodiment 1, and is characterized in that the insulating film 5 formed on the inner wall of the trench 0 has a thickness of the silicon semiconductor layer 3 portion that is thicker by X nm (X is 1 to 15) than the thickness of the wide gap semiconductor layer 2 portion.

[0035] More specifically, the semiconductor device 302 includes a second conductivity type (p-type in FIG. 36) SiC semiconductor layer 20, a first conductivity type (n-type in FIG. 36) SiC semiconductor layer 2 having a lower impurity concentration than the second conductivity type (p-type in FIG. 36), a substrate of the second conductivity type (p-type in FIG. 36) Si semiconductor layer 3, a base layer 12, an emitter layer 13, a p-base layer 14, a gate insulating film 5, a gate electrode 6, an emitter electrode / p-base electrode 21, and a collector electrode 22. The semiconductor device 302 also has a difference in thickness between the channel (SiC semiconductor layer 2) portion and the drift (Si semiconductor layer 3) portion on the inner wall of the trench 0 of 1 to 15 nm. The insulating film 5 is, for example, an oxide film.

[0036] That is, the semiconductor device 302 is a vertical trench insulated gate bipolar transistor (IGBT) in which the wide gap semiconductor layer 2 side is the collector (collector electrode 22), the silicon semiconductor layer 2 side is the emitter (emitter electrode and p-base electrode 21), and polycrystalline silicon filled in the trench 0 via the insulating film 5 is the gate electrode 6 (gate electrode wiring layer 17).

[0037] The semiconductor device 302 has the same interface state density as the semiconductor device 301 (the interface state density at the interface between the insulating film 5 and the SiC semiconductor layer 2 and the interface between the insulating film 5 and the Si semiconductor layer 3).

[0038] 33 to 36 are diagrams illustrating a manufacturing method of the semiconductor device 302. The manufacturing method includes the following steps: Bonding the wide-gap semiconductor layer 2 and the silicon semiconductor layer 3 (FIG. 33); Forming a trench 0 that extends from the silicon semiconductor layer 3 through the junction surface between the wide gap semiconductor layer 2 and the silicon semiconductor layer 3 and reaches the wide gap semiconductor layer 2 (similar to the description of FIG. 25 ); Removing a damaged layer on the inner wall of the trench 0 caused by the formation of the trench 0 so that the surface of the silicon semiconductor layer 3 is recessed by X nm (X is 1 or more and 15 or less) from the surface of the wide gap semiconductor layer 2 on the inner wall of the trench 0 (similar to the description of FIGS. 26 and 27 ); Forming an insulating film 5 of a desired thickness on the inner wall of the trench 0 by chemical vapor deposition (similar to the description of FIG. 28). Do the following.

[0039] In this embodiment, the wide-gap semiconductor is also described as a SiC semiconductor. The conductivity type (n-type / p-type) of each semiconductor layer in this embodiment is an example and can be determined arbitrarily depending on the specifications of the transistor. A second conductivity type (p+ type) SiC semiconductor layer 20, a first conductivity type (n type) SiC semiconductor layer 2 having a lower impurity concentration than the second conductivity type (p+ type), and a first conductivity type (n type) Si semiconductor layer 3 are laminated in this order (FIG. 33). As described in FIG. 25, a trench 0 is formed from the surface of the Si semiconductor layer 3 to a part of the SiC semiconductor layer 2.

[0040] As described with reference to FIGS. 26 to 29 , in the process of removing the damaged layer caused by trench etching, the surface of the Si semiconductor layer 3 is recessed from the surface of the SiC semiconductor layer 2 (recessed toward the positive side in the X direction in FIG. 26 ) to form a step, and an insulating film 5 is formed on the inner wall of the trench 0, which is then filled with a gate electrode 6.

[0041] Using photolithography and ion implantation techniques, a p-type impurity layer that will become base layer 12 is formed. Using photolithography and ion implantation techniques, an n+ type impurity layer that will become emitter layer 13 is formed. Using photolithography and ion implantation techniques, a p+ type impurity layer that will become p-base layer 14 is formed. Activation is performed by annealing (Figure 34).

[0042] An interlayer insulating film 31 is deposited on the surface of the Si semiconductor layer 3 (on the emitter layer 13 and p-base layer 14). Contact holes are opened in the interlayer insulating film 31, and a gate electrode wiring layer 17 and an emitter electrode / p-base electrode wiring layer 21 are formed by sputtering or the like (FIG. 35). A collector electrode wiring layer 22 is formed on the surface of the p+ type SiC semiconductor layer 20, completing the vertical trench IGBT (FIG. 36).

[0043] [effect] The effect of the step between the Si semiconductor layer 3 and the SiC semiconductor layer 2 on the inner wall of the trench 0, which is a feature of the semiconductor device (301, 302), will be described. To confirm this effect, we performed a simulation (VD=1V, VG=15V) of IDVG characteristics for two types of vertical trench MOS structures (the structure with a thickness difference of 0 nm in FIG. 4 and the structure with a thickness difference of 3 nm in FIG. 32 or FIG. 36) in which the insulating film 5 of the SiC semiconductor layer 2 in the channel portion was set to 100 nm and the insulating film 5 of the Si semiconductor layer 3 in the channel portion was set to 100 nm or 103 nm. FIG. 8 is a diagram illustrating the results of the IDVG characteristics. Note that the interface state density between the Si semiconductor layer 3 and the insulating film (oxide film) 5 was set to 1×10 11 cm -2 , the interface state density between the SiC semiconductor layer 2 and the insulating film (oxide film) 5 is set to 2×10 12 cm -2 As shown in the results of Fig. 8, it can be seen that more current flows in the structure of the example with a film thickness difference of 3 nm than in the structure of the comparative example with a film thickness difference of 0 nm.

[0044] Next, to confirm the effect of structures with other thickness differences, we similarly simulated the IDVG characteristics for several vertical trench MOS structures with different thickness differences. The results are shown in Figure 9. Figure 9 is a graph in which the horizontal axis represents thickness difference and the vertical axis represents the drain current value (VD=1V, VG=15V) of the vertical trench MOS structure corresponding to each thickness difference. The drain current value peaks at a thickness difference of 3 nm, and the drain current value increases compared to the comparative example structure when the thickness difference is in the range of 1 to 15 nm.

[0045] 10 shows the simulation results of the current density distribution of the IDVG characteristics (VD=1V, VG=15V) of the structure of the comparative example. The current decreases from the Si semiconductor layer 3 to the SiC semiconductor layer 2. The cause of this current decrease is that the current flowing from Si to SiC tunnels through a heterobarrier caused by the energy difference between the electron affinity of Si, 4.05 eV, and the electron affinity of SiC, 3.6 eV.

[0046] Fig. 11 shows the simulation results of the current density distribution of the IDVG characteristics (VD=1V, VG=15V) of the structure of the example (film thickness difference 3 nm). The current decreases from the Si semiconductor layer 3 to the SiC semiconductor layer 2, but the current density increases compared to the comparative example of Fig. 10. The area where the current density is high on the SiC semiconductor layer 3 side is not in the Si channel direction but along the oxide film.

[0047] To analyze this phenomenon, we consider the band diagram of SiC in a plane (XZ plane) shifted by D nm from the interface between the Si semiconductor layer 3 and the SiC semiconductor layer 2 toward the SiC semiconductor layer 2, based on the current density distribution results (comparison example) in Figure 10. Figure 12 shows the band diagram for D = 1 nm, Figure 13 shows the band diagram for D = 12 nm, and Figure 14 shows the band diagram for D = 13 nm. From Figure 12, it can be seen that the Fermi level at the location of D = 1 nm is lower than the conduction band, so the accumulation state is not established, i.e., it is difficult for current to flow. From Figure 13, it can be seen that the Fermi level at the location of D = 12 nm is also lower than the conduction band, so it is not established. From Figure 14, it can be seen that the conduction band at the location of D = 13 nm is lower than the Fermi level, so the accumulation state is established, i.e., it is easy for current to flow (low resistance).

[0048] Next, considering the current density distribution results (Example) of FIG. 11, we consider the band diagram of SiC in a plane (XZ plane) shifted parallel by D nm from the interface between the Si semiconductor layer 3 and the SiC semiconductor layer 2 toward the SiC semiconductor layer 2. FIG. 15 shows the band diagram for D=1 nm, FIG. 16 shows the band diagram for D=12 nm, and FIG. 17 shows the band diagram for D=13 nm. From FIG. 15, it can be seen that the area where D=1 nm is in an accumulation state near the interface with the insulating film 5 because the Fermi level is lower than the conduction band, but that accumulation is not observed further to the side (positive side of the X direction). From FIG. 16, it can be seen that the area where D=12 nm is in an accumulation state because the Fermi level is lower than the conduction band. From FIG. 17, it can be seen that the area where D=13 nm is also in an accumulation state because the conduction band is lower than the Fermi level. These results indicate that in the structure of the Example (film thickness difference of 3 nm), the area with high current density is in an accumulation state, and therefore a larger current can flow than the structure of the Comparative Example.

[0049] Next, for further analysis, FIG. 18 shows the simulation results of the potential distribution of the IDVG characteristics (VD=1V, VG=15V) of the structure of the comparative example, and FIG. 19 shows the simulation results of the potential distribution of the IDVG characteristics (VD=1V, VG=15V) of the structure of the example (film thickness difference of 3 nm). In the structure of the comparative example, the potential distribution is disturbed near the interface with the insulating film 5, and the potential of the SiC semiconductor layer 2 is higher than that of the Si semiconductor layer 3. This is presumably due to a heterobarrier. On the other hand, it can be seen that the potential distribution is more uniform in the structure of the example than in the structure of the comparative example.

[0050] Next, for further analysis, FIG. 20 shows the simulation results of the electric field strength distribution of the IDVG characteristics (VD=1V, VG=15V) of the comparative example structure, and FIG. 21 shows the simulation results of the electric field strength of the IDVG characteristics (VD=1V, VG=15V) of the example structure (thickness difference 3 nm). In the comparative example structure, the electric field strength applied to the insulating film 5 on the Si semiconductor layer 3 side is different from that applied to the insulating film 5 on the SiC semiconductor layer 2 side. Furthermore, there are areas where the electric field strength is concentrated and high on the insulating film 5 on the Si semiconductor layer 3 side and on the SiC semiconductor layer 2 side. This is presumably due to the difference in the potential distribution in FIG. 18 and the smaller dielectric constant of SiC compared to Si. On the other hand, in the example structure, the electric field strength applied to the insulating film 5 on the Si semiconductor layer 3 side is equal to that applied to the insulating film 5 on the SiC semiconductor layer 2 side. Furthermore, the areas where the electric field strength is concentrated are smaller than those in the comparative example structure. This is presumably due to the electric field relaxation caused by the difference in thickness between the insulating film 5 on the Si semiconductor layer 3 side and the insulating film 5 on the SiC semiconductor layer 2 side.

[0051] FIG. 22 is a schematic diagram (contact resistance omitted) modeling the on-resistance component of a vertical trench MOS structure with a thickness difference of 0 nm, which is a comparative example. Here, it is assumed that the resistance portion without accumulation state described in FIGS. 12 and 13 and the low-resistance portion with accumulation state described in FIG. 14 are connected in series. FIG. 23 is a schematic diagram (contact resistance omitted) modeling the on-resistance component of a vertical trench MOS structure with a thickness difference of 3 nm, which is an example. The low-resistance portion with accumulation state described in FIGS. 15 to 17 and the resistance portion without accumulation state are connected in series, but the resistance portion without accumulation state has a lateral (X-direction) path from the low-resistance portion to the channel of the Si semiconductor layer 3. Therefore, it can be assumed that the lateral distance of the resistance portion in the example (approximately 3 nm or less) is shorter than the distance of the resistance portion without accumulation state in the comparative example (approximately 13 nm) (the resistance value of the example structure is lower than that of the comparative example structure), allowing a larger current to flow.

[0052] As described above, in a vertical trench MOS device made of a wide-gap semiconductor and a Si semiconductor with different electron affinities, the drain current (collector current) can be increased by using a structure in which the difference in film thickness between the SiC semiconductor 2 and the insulating film 5 in the channel portion and the Si semiconductor 3 and the insulating film 5 in the channel portion is 1 to 15 nm. Furthermore, as described above, a step difference can be tolerated between the SiC semiconductor layer 2 and the insulating film 5 in the channel portion, and between the Si semiconductor layer 3 and the insulating film 5 in the channel portion. Therefore, by adjusting the treatment time using sacrificial oxidation or etching solution, it is possible to reduce the interface state density at the interface between the oxide film on the inner wall of the trench and the wide gap semiconductor layer, thereby preventing a decrease in breakdown voltage.

[0053] In this embodiment, a structure has been described in which the lower region (bottom) of trench 0 directly faces SiC semiconductor layer 2, but the present invention is not limited to this structure. For example, before forming trench insulating film 5, a high-resistance region may be formed in the region of SiC semiconductor layer 2 corresponding to the bottom of trench 0 by photolithography and ion implantation technology. Also, a p-type layer may be embedded in this region of SiC semiconductor layer 2 in advance. By adopting such a structure, the application of a high electric field to the insulating film near the bottom of trench 0 during off operation is alleviated, thereby further improving reliability. [Industrial Applicability]

[0054] The semiconductor device of the present invention can be applied to high-voltage power devices having high withstand voltage and high channel mobility, particularly semiconductor devices using gate insulating films such as MOSFET or IGBT circuits. [Explanation of symbols]

[0055] 0: Trench 1: First conductivity type (n+ type) SiC semiconductor layer 2: First conductivity type (n-type) SiC semiconductor layer 3: Second conductivity type (p-type) Si semiconductor layer 4: n+ type Si semiconductor layer 5: Insulating film (gate insulating film) 5a, 5b: Oxide film 6: Gate electrode 7: Drain electrode 8: Source electrode 9: Well layer 10: Source layer 11: Body layer 12: Base layer 13: Emitter layer 14:p base layer 15: Emitter electrode and p-base electrode 16: Collector electrode 17: Gate electrode wiring layer 18: Source electrode / body electrode wiring layer 19: Drain electrode wiring layer 20: p+ type SiC semiconductor layer 21: Emitter electrode / p-base electrode wiring layer 22: Collector electrode wiring layer

Claims

1. A semiconductor device having a vertical trench structure in which a wide-gap semiconductor layer and a silicon semiconductor layer are bonded together, and a trench is formed from the silicon semiconductor layer through a junction surface between the wide-gap semiconductor layer and the silicon semiconductor layer to reach the wide-gap semiconductor layer, The insulating film formed on the inner wall of the trench has a thickness of the silicon semiconductor layer portion that is X nm (X is 1 or more and 15 or less) thicker than a thickness of the wide-gap semiconductor layer portion.

2. On the inner wall of the trench, The interface state density at the interface between the silicon semiconductor layer and the insulating film is 1×10 １１ cm －２ That is: The interface state density at the interface between the wide-gap semiconductor layer and the insulating film is 2×10 １２ cm －２ and a difference between an interface state density at the interface between the silicon semiconductor layer and the insulating film and an interface state density at the interface between the wide gap semiconductor layer and the insulating film of 1.9×10 １２ cm －２ That is:

2. The semiconductor device according to claim 1, wherein:

3. The semiconductor device includes:

3. The semiconductor device according to claim 1, wherein the semiconductor device is a field effect transistor having a drain on the wide band gap semiconductor layer side, a source on the silicon semiconductor layer side, and a gate made of polycrystalline silicon filled in the trench via the insulating film.

4. The semiconductor device includes:

3. The semiconductor device according to claim 1, wherein the semiconductor device is an insulated gate bipolar transistor having a collector on the wide-gap semiconductor layer side, an emitter on the silicon semiconductor layer side, and a gate made of polycrystalline silicon filled in the trench via the insulating film.

5. A method for manufacturing a semiconductor device having a vertical trench structure, comprising: bonding a wide-gap semiconductor layer to a silicon semiconductor layer; forming a trench extending from the silicon semiconductor layer through a junction surface between the wide gap semiconductor layer and the silicon semiconductor layer to the wide gap semiconductor layer; removing a damaged layer on the inner wall of the trench caused by the formation of the trench so that the surface of the silicon semiconductor layer is recessed by X nm (X is 1 or more and 15 or less) from the surface of the wide-gap semiconductor layer on the inner wall of the trench; and forming an insulating film of a desired thickness on the inner wall of the trench by chemical vapor deposition; A manufacturing method that performs the above.

6. When removing the damaged layer, After forming the insulating film, The interface state density at the interface between the silicon semiconductor layer and the insulating film is 1×10 １１ cm －２ below, The interface state density at the interface between the wide-gap semiconductor layer and the insulating film is 2×10 １２ cm －２ The following, and a difference between an interface state density at the interface between the silicon semiconductor layer and the insulating film and an interface state density at the interface between the wide gap semiconductor layer and the insulating film of 1.9×10 １２ cm －２ below 6. The manufacturing method according to claim 5, wherein the damaged layer is removed so that

7. 7. The manufacturing method according to claim 5, wherein the damaged layer is removed by sacrificial oxidation and oxide film removal.

8. 7. The manufacturing method according to claim 5, wherein the damaged layer is removed by wet etching.

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